Integrated circuit, information processing device, routing control method, and program

Abstract

To provide an integrated circuit, a routing control method and a program which can efficiently use a network of buses on a circuit.SOLUTION: An integrated circuit 100 according to an embodiment comprises: a net-like bus B which connects a plurality of processor cores C and a plurality of memories M together; and a plurality of routers R which is provided at intersection points of nets in the bus B, and determines the memory M which transfers data outputted from the processor core C. At least one of the routers R, in a predetermined argument of a physical address about a destination of the data, executes processing which replaces at least the least significant bit with the other bit, and newly generates a memory number of a transfer destination by using the predetermined argument subjected to the processing, and the memory number of the transfer destination of the data included in the physical address.SELECTED DRAWING: Figure 1B

Description

Technical Field

[0001] The present invention relates to an integrated circuit, a routing control method, and a program.

Background Art

[0002] In an apparatus having a memory, techniques for efficiently using the memory have been studied. For example, when sequential access is made to a plurality of memories each having a plurality of banks, there is a problem that bank conflict may occur. In Reference Citation 1, a memory control method for suppressing the occurrence of such an event has been proposed.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] In recent years, the technology of a network-on-chip (NoC) having a mesh-structured bus has been evolving. In this network-on-chip, a state where data is input and output from a plurality of processor cores to a plurality of memories is assumed. Here, when the memory number specified by the original physical address is directly used as the data transfer destination, the following problems may occur. When a plurality of processor cores simultaneously request data stored in memories indicated by adjacent memory numbers, a situation where accesses concentrate on memory pairs facing each other in the bus network is likely to occur. In this situation, congestion occurs because the communication paths of the requests of each processor core overlap on the bus between the memory pairs where accesses concentrate, and the communication bandwidth reaches its peak on that bus, which may prevent other buses from being effectively used. Therefore, as a result, there is a problem that the overall bandwidth on the network-on-chip cannot be effectively utilized.

[0005] The purpose of this disclosure is to provide an integrated circuit, a routing control method, and a program that enable efficient use of a bus network on a circuit. [Means for solving the problem]

[0006] An integrated circuit according to one aspect of the present disclosure includes a network bus connecting a plurality of processor cores and a plurality of memories to each other, and a plurality of routers provided at the intersections of the network on the bus, which determine the memory to which data output from the processor cores is transferred, wherein at least one of the plurality of routers performs a process of swapping at least the least significant bit of a predetermined argument of a physical address relating to the destination of the data with another bit, and generates a new destination memory number using the predetermined argument from which the process has been performed and the memory number of the destination of the data included in the physical address.

[0007] A routing control method according to one aspect of the present disclosure is an integrated circuit comprising a network bus connecting a plurality of processor cores and a plurality of memories to each other, and a plurality of routers provided at the intersections of the network on the bus, which determine the memory to which data output from the processor cores is transferred, wherein at least one of the plurality of routers performs a process of swapping at least the least significant bit of a predetermined argument of the physical address relating to the destination of the data with another bit, and generates a new destination memory number using the predetermined argument from which the process has been performed and the memory number of the destination of the data included in the physical address.

[0008] A program according to one aspect of the present disclosure is an integrated circuit comprising a network bus connecting a plurality of processor cores and a plurality of memories to each other, and a plurality of routers provided at the intersections of the network in the bus, which determine the memory to which data output from the processor cores is transferred, wherein at least one of the plurality of routers is made to perform a process of swapping at least the least significant bit of a predetermined argument of a physical address relating to the destination of the data with another bit, and a process of generating a new destination memory number using the predetermined argument from which the process has been performed and the memory number of the destination of the data included in the physical address. [Effects of the Invention]

[0009] According to this disclosure, it is possible to provide an integrated circuit, a routing control method, and a program that can efficiently utilize a bus network on a circuit. [Brief explanation of the drawing]

[0010] [Figure 1A] This is a block diagram showing a minimum set of components of the integrated circuit according to Embodiment 1. [Figure 1B] A block diagram showing an example of an integrated circuit according to Embodiment 1. [Figure 2] This flowchart shows an example of a process performed by the integrated circuit according to Embodiment 1. [Figure 3] This is a block diagram showing an example of a multicore processor device according to Embodiment 2. [Figure 4] This figure shows an example of a method for calculating the memory number of the access destination according to Embodiment 2. [Figure 5A] This is a block diagram showing an example of the network-on-chip configuration according to Embodiment 3. [Figure 5B] This is a block diagram showing an example of the network-on-chip configuration according to Embodiment 3. [Modes for carrying out the invention]

[0011] Embodiment 1 Embodiments of the present invention will be described below with reference to the drawings.

[0012] Figure 1A is a block diagram showing a minimal example of the components of an integrated circuit according to Embodiment 1. The integrated circuit 100 is applicable to any information processing device (computer) and comprises a network bus B and a plurality of routers R.

[0013] Figure 1B is a block diagram that shows the configuration of the integrated circuit 100 shown in Figure 1A, as well as the processor core C (hereinafter simply referred to as "core") and memory M related to bus B and router R. The following explanation will refer to Figure 1B to describe each component.

[0014] Bus B forms a network by connecting multiple cores C and multiple memory Ms to each other. This configuration allows cores C to transfer data to memory M, and cores C can also access memory M to retrieve data stored in memory M.

[0015] Multiple routers R are located at network intersections on bus B and determine which memory M to transfer data output from core C to. For example, data output from core C0 can be transferred to any memory M via at least router R0. Each router R is also connected to other adjacent routers R on bus B. In the example in Figure 2, each memory M is connected to the outermost router R located in the vertical and horizontal directions in Figure 1B.

[0016] In this example, nine cores C from C0 to C8 and nine memories M from M0 to M8 are provided respectively. However, any number of cores C and memories M may be provided. For example, the number of cores C and memories M may be the same or different. In FIG. 1B, the number of cores C in the vertical and horizontal directions is equal, but they may be different numbers. The same applies to the number of memories M in the vertical and horizontal directions. Similarly, in this example, routers R0 to R8 are connected to each of cores C0 to C8, but any number of routers R can be provided. Also, the number of cores C and routers R may be the same or different. Furthermore, the number of paths connected to each core C, router R, and memory M may be appropriately changed.

[0017] At least one of the core C and the memory M may be provided in the integrated circuit 100, or both may be provided as components separate from the integrated circuit 100. Also, the memory number of the memory M is assigned by the core C.

[0018] The processor provided in the core C reads and executes software (computer program) from the memory M or a memory not shown. As an example of the processor, one of a CPU (Central Processing Unit), MPU (Micro Processing Unit), FPGA (Field-Programmable Gate Array), DSP (Demand-Side Platform), and ASIC (Application Specific Integrated Circuit) may be used, or a plurality of them may be used in parallel.

[0019] The memory M is composed of a volatile memory, a non-volatile memory, or a combination thereof. The volatile memory may be, for example, a RAM (Random Access Memory) such as a DRAM (Dynamic Random Access Memory) or an SRAM (Static Random Access Memory). The non-volatile memory may be, for example, a ROM (Random Only Memory) such as a PROM (Programmable Random Only Memory) or an EPROM (Erasable Programmable Read Only Memory), a flash memory, or an SSD (Solid State Drive).

[0020] FIG. 2 is a flowchart showing an example of a typical process executed by at least one of the plurality of routers R. Hereinafter, the process executed by the router R will be described while referring to FIG. 2.

[0021] First, the router R executes a process of swapping at least the position of the least significant bit with other bits in a predetermined argument of the physical address regarding the destination of the data output from the connected core C (step S11). This predetermined argument is an argument for generating the memory number of the transfer destination of the new data.

[0022] Next, the router R uses the predetermined argument processed in step S11 and the memory number of the transfer destination of the data included in the physical address to newly generate the memory number of the transfer destination (step S12). The router R can use any function as a method for generating a new memory number. For example, any hash function may be used, or any pseudo-random number generation method may be used. This specific example will be described in Embodiment 2.

[0023] As described above, router R can change the destination memory number by using the physical address data related to the destination of the data output from core C. At this time, since the least significant bit of the predetermined argument is swapped, the memory numbers of the memory M that store each data become non-contiguous and not biased towards any particular pattern. As a result, even if data is stored in memory M indicated by a memory number adjacent to core C in the integrated circuit 100, and multiple cores C simultaneously request that data, it is possible to suppress the concentration of access to opposing memory pairs on bus B. Therefore, congestion is less likely to occur, and the bus network on the circuit can be used efficiently.

[0024] Embodiment 2 Embodiment 2 of the present invention will now be described with reference to the drawings. Embodiment 2 further discloses details of the integrated circuit 100 described in Embodiment 1.

[0025] Figure 3 is a block diagram showing an example of a multicore processor device according to Embodiment 2. The multicore processor device 200 is an information processing device and comprises a plurality of cores 201, a plurality of memories 202, and a network-on-chip 203. As described later, the multicore processor device 200 operates as a routing device for the network-on-chip 203 in order to control access to the plurality of installed memories 202. That is, the multicore processor device 200 controls the memory 202 to which a data request is made when a data request is made from each core 201.

[0026] Core 201 corresponds to Core C in Embodiment 1 and is connected to Memory 202 via Network-on-Chip 203. Memory 202 corresponds to Memory M in Embodiment 1 and is connected to Core 201 via Network-on-Chip 203. In Figure 4, Cores 201A to 201D are shown as examples of multiple Cores 201, and Memory 202A to 202D are shown as examples of multiple Memory 202.

[0027] The network-on-chip 203 has the configuration of the integrated circuit 100 shown in Figure 1B. Therefore, the network-on-chip 203 has a bus network and is configured to connect any core 201 and any memory 202 via the bus and routers. Furthermore, the network-on-chip 203 forms a mesh network in which, even if one path becomes unavailable, the routers can forward the data to another path, thereby transferring the data to the destination memory.

[0028] In Embodiment 2, when data is output from the connected core C(201), each router R generates a new memory number to be designated as the access destination using the initially specified memory number, as follows:

[0029] Figure 4 shows an example of how the memory number of the access destination is calculated. The following explanation of the router R's processing will refer to Figure 4.

[0030] Router R refers to the physical address information indicating the destination of the received data. The physical address is the address that indicates where the data is stored in memory M(202), and is specified by the program running on the processor core. Consecutive data output from core C is stored at consecutive addresses on the physical address system.

[0031] The physical address information includes the higher-order address, the initially designated memory number (hereinafter also referred to as the raw memory number), the hash argument, and the in-line address information. The raw memory number has enough bits to represent all the memories M connected to the network-on-chip 203, and specifies one of the memories M as the access target. The hash argument is the target of processing by the hash function and corresponds to the predetermined argument in Embodiment 1. This argument consists of the same number of bits as the raw memory number.

[0032] When router R receives data from core C, it extracts hash argument information from the physical address information. In this example, as shown in Figure 4(1), router R generates intermediate data by left-rotating the bits of the hash argument by the number of bits in the hash argument minus 1 (i.e., right-rotating by +1). This rotation process is an example of a hash function. In the configuration of the two-dimensional integrated circuit shown in Figure 1B, there are 12 memories connected to each other on the plane on which each router R and each memory M are located, so the minimum number of bits required to identify a memory is 4 bits. Therefore, left-rotating by 4-1=3 bits is most effective in ensuring that the newly generated memory numbers are discontinuous and not biased towards any particular pattern. However, rotation can be performed in other ways as long as the least significant bit of the hash argument is swapped with other bits.

[0033] Then, as shown in Figure 4 (2), Router R calculates the bitwise exclusive OR (or negative exclusive OR) of the generated "intermediate data" and the "raw memory number" contained in the physical address, and uses the resulting bit sequence as the new destination memory number. Router R then transfers the data to memory 202, which is indicated by this generated memory number.

[0034] Furthermore, if the hash argument is used directly as intermediate data without rotation in (1) to generate a new memory number, many patterns will occur where consecutive data on the physical address are stored in consecutive memory numbers. Therefore, it is expected that congestion will occur frequently on the mesh network.

[0035] In multi-core processor devices interconnected by a network-on-chip, the physical addresses assigned to multiple memory locations did not take into account the data access congestion caused by the network-on-chip configuration and routing. As a result, local memory accesses that occur in typical programs frequently caused congestion on the network-on-chip, preventing effective utilization of the overall network-on-chip bandwidth. For example, in Figure 1B, it is conceivable that congestion occurs due to frequent access to opposing memory M paths, such as the path between memory M3 and M4, and the path between memory M5 and M6.

[0036] In contrast, in the multi-core processor device 200 according to Embodiment 2, intermediate data is generated by swapping the position of the least significant bit in the hash argument of the physical address, and a new memory number is generated from this intermediate data. As a result of this process, even when continuous data is output from core 201 (i.e., when physical addresses are continuous in multiple data), the newly generated memory number for each data will be non-contiguous and not biased towards any particular pattern. As a result, even when each core accesses a continuous physical memory address from the perspective of the core, the proportion of accesses that end up in the same memory or on the network-on-chip is significantly reduced. In other words, it is possible to suppress congestion caused by load concentration on specific paths on the network-on-chip and improve the memory bandwidth for the entire network-on-chip. This is expected to improve memory access throughput.

[0037] Furthermore, the multicore processor device 200 may generate a new memory number by calculating an exclusive OR or negative exclusive OR for each bit of the hash argument with the least significant bit swapped and the raw memory number. This logical calculation suppresses bias in the newly generated memory numbers, thus reducing congestion during access.

[0038] Furthermore, the multicore processor device 200 may perform a process of swapping the least significant bit with another bit by rotating each bit in the hash argument. Since the processing performed by the router is relatively simple, the router configuration can be simplified.

[0039] In particular, as a process of swapping the least significant bit with other bits, each bit in the hash argument may be left-rotated by a number of bits obtained by subtracting 1 from the minimum number of bits required to represent the number of memories connected to the router R on the plane where the router R and memory M are located in the integrated circuit. This maximizes the effect of ensuring that the newly generated memory numbers are discontinuous and not biased towards any particular pattern.

[0040] Embodiment 3 Embodiment 3 of the present invention will now be described with reference to the drawings. In Embodiment 2, a two-dimensional configuration was shown as an example of a mesh network configuration. However, the number of dimensions of the mesh network is not limited to two.

[0041] Figures 5A and 5B are block diagrams showing examples of the configuration of a mesh network according to Embodiment 3. This mesh network 300 is a circuit structure having a three-dimensional mesh structure. Figure 5A is a block diagram showing a two-dimensional network in the xy-plane at a certain height z1 of the mesh network 300. Figure 5B is a block diagram showing a two-dimensional network in the xy-plane at a height z2 different from height z1 of the mesh network 300. In other words, Figures 5A and 5B show integrated circuits formed in different layers of the three-dimensional mesh network 300.

[0042] Both Figures 5A and 5B have networks similar to the two-dimensional network shown in Figure 1B. Specifically, the circuit configuration shown in Figure 5A has cores C10-C18, routers R10-R18, and memory M12-M23. On the other hand, the circuit configuration shown in Figure 5B has different components from those in Figure 5A: cores C19-C27, routers R19-R27, and memory M24-M35. Here, routers R10 and R19, R11 and R20, R12 and R21, R13 and R22, R14 and R23, R15 and R24, R16 and R25, R17 and R26, and R18 and R27, which are located in overlapping positions in the stacked structure, are connected by buses B that extend in the height direction (z-axis direction), thereby forming a three-dimensional network. For example, in Figure 5A, core C10 can access memory M28 via routers R10, R19, and R21.

[0043] In the three-dimensional mesh structure described above, each router R can perform the same processing as described in Embodiment 2. As a result, even when continuous data is output from core C, the memory numbers M that store each piece of data will be discontinuous and not biased towards any particular pattern. In this three-dimensional mesh structure, any amount can be applied to the left rotation of the hash argument when generating a new memory number. The amount of rotation may be the same as the amount of rotation in the two-dimensional integrated circuit configuration shown in Figure 1B, or it may be a different amount. For example, in the three-dimensional integrated circuit configuration shown in Figures 5A and 5B, there are 12 memories connected to router R in each xy plane of Figures 5A and 5B. Therefore, the minimum number of bits required for each router R to identify a memory is 4 bits in both Figures 5A and 5B. Thus, when 4-1=3 bits are left rotated, the effect of generating discontinuous and not biased towards any particular pattern is maximized. However, rotation can be performed by other methods, as long as the least significant bit of the hash argument is swapped with other bits. In this way, the amount of left rotation of the hash argument can be appropriately changed according to changes in the mesh structure.

[0044] It should be noted that the present invention is not limited to the embodiments described above, and can be modified as appropriate without departing from the spirit of the invention. For example, the assignment of memory numbers is not limited to those shown in each embodiment.

[0045] The amount by which the hash argument is rotated is not limited to the amount shown in the embodiment described above, but can be set to any amount. Even in this case, the position of the least significant bit of the hash argument is swapped with the position of the other bits, thus producing the same effect as described in Embodiment 2. Furthermore, the process does not have to be rotation; it may simply be a matter of swapping the position of the least significant bit of the hash argument with the position of the other bits of the hash argument.

[0046] In each of the embodiments described above, the router R is equipped with a processor, which reads and executes software (computer programs) from memory (not shown) to perform the processing described in the embodiments described above. Here, memory is used to store one or more instructions, and the one or more instructions are stored in memory as a group of software modules. The processor of the router R can perform the processing described in the embodiments described above by reading and executing these groups of software modules from memory. Specific examples of these processors and memories are shown in Embodiment 1. Note that the router R is not limited to software, and may perform the processing described in the embodiments described above by using any algorithm for routing. For example, the processing described in the embodiments described above may be performed by applying sequential circuits or combinational circuits implemented as hardware to the router R.

[0047] As described above, the one or more processors in each of the above embodiments execute one or more programs that include a set of instructions for causing a computer to perform the algorithm described with reference to the drawings. This process enables the signal processing method described in each embodiment.

[0048] The program, when loaded into a computer, includes a set of instructions (or software code) for causing the computer to perform one or more of the functions described in the embodiments. The program may be stored on a non-temporary computer-readable medium or a physical storage medium. Examples, but not limited to, include random-access memory (RAM), read-only memory (ROM), flash memory, solid-state drive (SSD) or other memory technologies, CD-ROM, digital versatile disk (DVD), Blu-ray® disc or other optical disk storage, magnetic cassette, magnetic tape, magnetic disk storage or other magnetic storage devices. The program may be transmitted over a temporary computer-readable medium or a communication medium. Examples, but not limited to, include temporary computer-readable medium or a communication medium that includes electrical, optical, acoustic or other forms of propagating signals.

[0049] While the present disclosure has been described above with reference to embodiments, the present disclosure is not limited thereto. Various modifications to the structure and details of the present disclosure may be made that can be understood by those skilled in the art within the scope of the disclosure. [Explanation of Symbols]

[0050] 100 Integrated Circuits B Bus R Router C Processor Core M Memory 200 Multicore Processor Device 201 processor cores, 202 memory 203 Network-on-a-chip 300 Mesh Network

Claims

1. A network bus that connects multiple processor cores and multiple memory modules to each other, The bus comprises a plurality of routers located at the intersections of the network, which determine the memory to which the data output from the processor core is transferred. At least one of the plurality of routers performs a process in which at least the least significant bit of a predetermined argument of the physical address relating to the destination of the data is swapped with another bit, and generates a new memory number for the destination using the predetermined argument from which the process has been performed and the memory number of the destination of the data included in the physical address. Integrated circuit.

2. At least one of the plurality of routers performs a process to swap at least the least significant bit of a hash argument, which is included in the physical address relating to the destination of the data and is used to generate a new memory number for the destination of the data, in order to avoid network congestion, and generates a new memory number for the destination of the data using the hash argument from which the process has been performed and the memory number for the destination of the data included in the physical address. The integrated circuit according to claim 1.

3. At least one of the plurality of routers generates a new destination memory number by calculating an exclusive OR or negative exclusive OR for each bit of the predetermined argument on which the processing has been performed and the memory number of the destination of the data contained in the physical address. The integrated circuit according to claim 1 or 2.

4. At least one of the plurality of routers performs a process of swapping the least significant bit with another bit by rotating each bit in the predetermined argument. The integrated circuit according to any one of claims 1 to 3.

5. At least one of the plurality of routers performs a process of swapping the least significant bit with another bit by left-rotating each bit in the predetermined argument by a number of bits obtained by subtracting 1 from the minimum number of bits required to represent the number of memories connected to the at least one router on the plane on which the at least one router and the plurality of memories are provided by the integrated circuit. The integrated circuit according to claim 4.

6. The aforementioned network of buses constitutes a three-dimensional network. The integrated circuit according to any one of claims 1 to 5.

7. An information processing apparatus comprising an integrated circuit according to any one of claims 1 to 6.

8. A network bus that connects multiple processor cores and multiple memory modules to each other, An integrated circuit comprising: a plurality of routers provided at the intersections of the bus network, which determine the memory to which data output from the processor core is transferred; At least one of the aforementioned multiple routers is In a predetermined argument of the physical address relating to the destination of the aforementioned data, perform a process in which at least the least significant bit is swapped with another bit. Using the predetermined arguments after the above processing and the memory number of the destination where the data included in the physical address is transferred, a new memory number for the transfer destination is generated. Routing control method.

9. A network bus that connects multiple processor cores and multiple memory modules to each other, An integrated circuit comprising: a plurality of routers provided at the intersections of the bus network, which determine the memory to which data output from the processor core is transferred; At least one of the aforementioned multiple routers, A process of swapping at least the least significant bit of a predetermined argument of the physical address relating to the destination of the aforementioned data with another bit, A process to generate a new memory number for the transfer destination using the predetermined arguments from which the above processing has been performed and the memory number of the data transfer destination included in the physical address, A program that executes the command.

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