Multilayer ceramic capacitor

Abstract

The present invention provides a multilayer ceramic capacitor which is capable of suppressing or preventing the occurrence of a tombstone phenomenon and has high mounting reliability.　A multilayer ceramic capacitor 1 is provided with: a multilayer body 2 that comprises an inner layer part 11 in which a plurality of dielectric layers 14 and a plurality of internal electrode layers 15 are alternately stacked, the multilayer body 2 having a first main surface and a second main surface that are opposite to each other in the stacking direction; and a plurality of external electrodes that are arranged on two end faces C or two lateral surfaces B of the multilayer body 2, while being connected to the internal electrode layers 15. In a cross-section obtained by cutting the multilayer body 2 at a plane that is perpendicular to the length direction L at a position where the external electrodes are not arranged, the distance T1 between the first lateral surface Ba-side end of an internal electrode layer 15 which is closest to the first main surface and the first lateral surface Ba-side end of an internal electrode layer 15 which is closest to the second main surface is longer than the distance T2 between the second lateral surface Bb-side end of the internal electrode layer 15 which is closest to the first main surface and the second lateral surface Bb-side end of the internal electrode layer 15 which is closest to the second main surface.

Description

Technical Field

[0001] The present invention relates to a multilayer ceramic capacitor.

Background Art

[0002] In recent years, multilayer ceramic capacitors widely used in electronic devices such as mobile phones have been developed to be further miniaturized and lightened as the electronic devices are miniaturized.

[0003] On the other hand, when mounting a multilayer ceramic capacitor, an external electrode is attached onto a solder paste applied on a land of a substrate, and the entire substrate on which electronic components such as the multilayer ceramic capacitor are fixed is heated to melt the solder paste and then cured, whereby the electronic components are mounted on the substrate. At this time, if the balance of solder melting on the land is lost and solder wraps around under one of the external electrodes of the multilayer ceramic capacitor to form a fillet, a so-called tombstone phenomenon occurs in which a chip such as the multilayer ceramic capacitor rises due to the surface tension during solder melting. In particular, as the multilayer ceramic capacitor is miniaturized and its self-weight becomes smaller, the tombstone phenomenon tends to occur more easily.

[0004] Therefore, there is a need for a multilayer ceramic capacitor having a structure in which the tombstone phenomenon hardly occurs for the purpose of reliably mounting a miniaturized multilayer ceramic capacitor.

Prior Art Documents

Patent Documents

[0005]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0006] The present invention aims to provide a highly reliable multilayer ceramic capacitor that can more reliably suppress and prevent the occurrence of the tombstone phenomenon than conventional multilayer ceramic capacitors. [Means for solving the problem]

[0007] The inventors have discovered that in an inner layer where dielectric layers and internal electrode layers are alternately stacked, by making the distance T1 between the first side surface end of the internal electrode layer located closest to the first main surface and the first side surface end of the internal electrode layer located closest to the second main surface longer than the distance T2 between the second side surface end of the internal electrode layer located closest to the first main surface and the second side surface end of the internal electrode layer located closest to the second main surface, the center of gravity of the multilayer ceramic capacitor can be shifted to the first side surface, and by mounting the first side surface toward the substrate, the occurrence of the tombstone phenomenon can be suppressed and prevented, thus completing the present invention.

[0008] In other words, the present invention includes an inner layer portion in which a plurality of dielectric layers and internal electrode layers are alternately stacked, and a laminate that forms a first main surface and a second main surface facing each other in the stacking direction, a first end surface and a second end surface facing each other in the length direction intersecting the stacking direction, and a first side surface and a second side surface facing each other in the width direction intersecting the stacking direction and the width direction, A plurality of external electrodes are arranged on either of the two end faces and the two side faces of the laminate and connected to the internal electrode layer, A multilayer ceramic capacitor equipped with, When the laminate is cut in a plane perpendicular to the longitudinal direction at a position where the external electrodes are not arranged, This is a multilayer ceramic capacitor in which the distance T1 between the first side surface end of the internal electrode layer located closest to the first main surface and the first side surface end of the internal electrode layer located closest to the second main surface is longer than the distance T2 between the second side surface end of the internal electrode layer located closest to the first main surface and the second side surface end of the internal electrode layer located closest to the second main surface. [Effects of the Invention]

[0009] According to the present invention, it is possible to suppress and prevent the occurrence of the tombstone phenomenon during mounting, and to provide a multilayer ceramic capacitor with high mounting reliability. [Brief explanation of the drawing]

[0010] [Figure 1] This is a schematic perspective view of the multilayer ceramic capacitor 1 (first embodiment). [Figure 2] This is a cross-sectional view of the multilayer ceramic capacitor 1 (first embodiment) taken along the line II-II shown in Figure 1. [Figure 3] This is a cross-sectional view of the multilayer ceramic capacitor 1 (first embodiment) taken along the line III-III shown in Figure 1. [Figure 4] This is an exploded perspective view illustrating the stacking state of the inner layer portion 11 of the multilayer ceramic capacitor 1 (first embodiment). [Figure 5] This is a flowchart illustrating the manufacturing method of the multilayer ceramic capacitor 1 (first embodiment). [Figure 6] This is a perspective view of a material sheet 203 on which an internal electrode layer pattern 103, which will become the internal electrode layer 15 of a multilayer ceramic capacitor 1 (first embodiment), is printed on the surface of a ceramic green sheet 101. [Figure 7] This is a perspective view showing the ceramic paste 102 placed on the material sheet 203. [Figure 8] This is a partial cross-sectional view of Figure 7. [Figure 9] This diagram illustrates the layering state of material sheet 203. [Figure 10] This figure shows the mounting state of the multilayer ceramic capacitor 1 (first embodiment). [Figure 11] This is a schematic perspective view of the multilayer ceramic capacitor 300 (second embodiment). [Figure 12] This is an exploded perspective view illustrating the state of the internal electrode layer 15 in the inner layer portion 11 of the multilayer ceramic capacitor 300 (second embodiment). [Figure 13]It is an exploded perspective view for explaining the arrangement of ceramic pastes 102A and 102B in the inner layer portion 11 of the multilayer ceramic capacitor 300 (second embodiment).

Mode for Carrying Out the Invention

[0011] Hereinafter, regarding the multilayer ceramic capacitor of the present invention, a two-terminal type ceramic capacitor will be described as the first embodiment, and a three-terminal type multilayer ceramic capacitor will be described as the second embodiment. FIG. 1 is a schematic perspective view of the multilayer ceramic capacitor 1 of the first embodiment. FIG. 2 is a cross-sectional view of the multilayer ceramic capacitor 1 of the first embodiment taken along line II-II shown in FIG. 1. FIG. 3 is a cross-sectional view of the multilayer ceramic capacitor 1 of the first embodiment taken along line III-III shown in FIG. 1.

[0012] The embodiments exemplarily show the embodiments of the present invention, and the present invention is not limited to the contents of the embodiments. Also, it is possible to combine and implement the contents described in different embodiments, and the implementation contents in that case are also included in the present invention. Further, the drawings are for assisting in understanding the specification, and may be drawn schematically, and the ratio of the drawn components or the dimensions between the components may not match the ratio of those dimensions described in the specification. Also, there are cases where the components described in the specification are omitted in the drawings or the number is omitted in the drawing.

[0013] (Multilayer Ceramic Capacitor 1) The multilayer ceramic capacitor 1 is a two-terminal type multilayer ceramic capacitor (first embodiment). The multilayer ceramic capacitor 1 includes a multilayer body 2 and a pair of end face external electrodes 3 provided at both ends of the multilayer body 2. The multilayer body 2 includes an inner layer portion 11 including a plurality of sets of dielectric layers 14 and internal electrode layers 15, and an outer layer portion 12. The dimensions of the multilayer ceramic capacitor 1 are not particularly limited, but it is preferable that the dimension in the length direction L is 0.6 mm or more and 3.2 mm or less, the dimension in the width direction W is 0.3 mm or more and 2.5 mm or less, and the dimension in the stacking direction T is 0.3 mm or more and 2.5 mm or less.

[0014] In the following description, as terms representing the orientation of the multilayer ceramic capacitor 1, in the multilayer ceramic capacitor 1, the direction in which the dielectric layer 14 and the internal electrode layer 15 are laminated is defined as the lamination direction T. In the multilayer ceramic capacitor 1, the direction intersecting the lamination direction T and in which the pair of end face external electrodes 3 are provided is defined as the length direction L. The direction intersecting both the length direction L and the lamination direction T is defined as the width direction W. In the embodiment, the lamination direction T, the length direction L, and the width direction W are orthogonal to each other. Also, FIG. 2 is an LT cross-section passing through the length direction L and the lamination direction T obtained by cutting the multilayer ceramic capacitor 1 with a plane perpendicular to the width direction W, and FIG. 3 is a WT cross-section passing through the width direction W and the lamination direction T obtained by cutting the multilayer ceramic capacitor 1 with a plane perpendicular to the length direction L.

[0015] Furthermore, in the following description, among the six outer surfaces of the laminate 2, the pair of outer surfaces facing each other in the lamination direction T are defined as the first main surface Aa and the second main surface Ab, the pair of outer surfaces facing each other in the width direction W are defined as the first side surface Ba and the second side surface Bb, and the pair of outer surfaces facing each other in the length direction L are defined as the first end surface Ca and the second end surface Cb. When there is no need to particularly distinguish and describe the first main surface Aa and the second main surface Ab, they are collectively referred to as the main surface A. When there is no need to particularly distinguish and describe the first side surface Ba and the second side surface Bb, they are collectively referred to as the side surface B. When there is no need to particularly distinguish and describe the first end surface Ca and the second end surface Cb, they are collectively referred to as the end surface C for description.

[0016] (Laminate 2) The laminate 2 includes an inner layer portion 11 and outer layer portions 12 disposed on both sides of the inner layer portion 11 in the lamination direction T. The dimensions of the laminate 2 are not particularly limited, but it is preferable that the dimension in the length direction L is 0.6 mm or more and 3.2 mm or less, the dimension in the width direction W is 0.3 mm or more and 2.5 mm or less, and the dimension in the lamination direction T is 0.3 mm or more and 2.5 mm or less.

[0017] (Inner layer portion 11) The inner layer 11 includes multiple sets of dielectric layers 14 and internal electrode layers 15 that are alternately stacked along the stacking direction T.

[0018] (Internal electrode layer 15) The internal electrode layer 15 comprises a plurality of first internal electrode layers 15A and a plurality of second internal electrode layers 15B. The first internal electrode layers 15A and the second internal electrode layers 15B are arranged alternately. When there is no need to specifically distinguish between the first internal electrode layers 15A and the second internal electrode layers 15B, they will be described together as the internal electrode layer 15.

[0019] The internal electrode layer 15 is preferably formed from a metallic material such as Ni, Cu, Ag, Pd, Ag-Pd alloy, or Au. The thickness of the internal electrode layer 15 in the stacking direction T is preferably 0.25 μm or more and 0.60 μm or less, and particularly preferably 0.3 μm or more and 0.5 μm or less. The number of internal electrode layers 15 is preferably 14 or more and 1000 or less.

[0020] The internal electrode layer 15 has an opposing portion 15a and a lead-out portion 15b that extends from the opposing portion 15a to the end face C and is connected to the end face external electrode 3.

[0021] (Dielectric layer 14) The dielectric layer 14 is manufactured from a ceramic material. As the ceramic material, for example, a dielectric ceramic mainly composed of BaTiO3 can be used. Alternatively, a ceramic material may be used in which at least one of the minor components such as Mn compounds, Fe compounds, Cr compounds, Co compounds, and Ni compounds is added to these main components. The thickness of the dielectric layer 14 in the stacking direction T is preferably 0.3 μm or more and 1.5 μm or less, and particularly preferably 0.5 μm or more and 1.0 μm or less. Furthermore, the number of dielectric layers 14, including the upper outer layer portion 12a and the lower outer layer portion 12b, is preferably 14 or more and 1000 or less.

[0022] Figure 4 is an exploded perspective view illustrating the stacking state of the inner layer 11. As will be described in detail later, during the manufacturing of the multilayer ceramic capacitor 1, ceramic paste 102 is printed on the area where the internal electrode layer pattern 103, which will become the internal electrode layer 15, is not located on the material sheet 203, which has the internal electrode layer pattern 103 printed on the ceramic green sheet 101, which will become the dielectric layer 14. Furthermore, the ceramic paste 102 overlaps one side of the internal electrode layer 15 on the first side surface Ba by a certain width. The inner layer 11 is formed by stacking the material sheet 203, on which the internal electrode layer pattern 103 and ceramic paste 102 are printed, on the ceramic green sheet 101.

[0023] Since the ceramic paste 102 overlaps one side of the internal electrode layer 15 on the first side surface Ba by a certain width, as shown in Figure 3, the spacing in the stacking direction T becomes wider at the end of the internal electrode layer 15 on the first side surface Ba. In a laminate 2 in which multiple such internal electrode layers 15 are stacked, the distance T1 between the end of the first side surface Ba of the uppermost internal electrode layer 15, which is located closest to the first main surface Aa, and the end of the first side surface Ba of the lowest internal electrode layer 15, which is located closest to the second main surface Ab, is longer than the distance T2 between the end of the second side surface Bb of the uppermost internal electrode layer 15, which is located closest to the first main surface Aa, and the end of the second side surface Bb of the lowest internal electrode layer 15, which is located closest to the second main surface Ab. Here, the distance T1 between the end of the first side surface Ba of the uppermost internal electrode layer 15, which is located on the first main surface Aa side, and the end of the first side surface Ba of the lowermost internal electrode layer 15, which is located on the second main surface Ab side, and the distance T2 between the end of the second side surface Bb of the uppermost internal electrode layer 15, which is located on the first main surface Aa side, and the end of the second side surface Bb of the lowermost internal electrode layer 15, which is located on the second main surface Ab side, can be measured using a scanning electron microscope (SEM) or a metallurgical microscope on a cross-section obtained by cross-polishing the multilayer ceramic capacitor 1 to a position that is half the length dimension of the multilayer ceramic capacitor 1, so that the cross-section is perpendicular to the length direction.

[0024] The difference in length between distance T1 and distance T2 corresponds to the difference in thickness in the stacking direction T between the first side surface Ba and the second side surface Bb in the laminate 2. As shown in Figure 1, a raised portion M is formed along the length direction L on the surface of the first side surface Ba on the first main surface Aa and the second main surface Ab of the multilayer ceramic capacitor 1.

[0025] Furthermore, when the internal electrode layer 15 is divided into a central region including the central part, a first side region located on the first side Ba side of the central region, and a second side region located on the second side Bb side of the central region, it is preferable that the distance t1 in the stacking direction at any position in the first side region is longer than the distance t2 in the stacking direction at any position in the second side region. Here, the distance t1 in the stacking direction at any position in the first side region and the distance t2 in the stacking direction at any position in the second side region can be measured using a scanning electron microscope (SEM) or a metallurgical microscope on a cross-section obtained by polishing the multilayer ceramic capacitor 1 to a position that is perpendicular to the length of the stack, up to half the length dimension of the stack.

[0026] The volume of the laminate 2 constituting the multilayer ceramic capacitor 1 is larger on the first side surface Ba than on the second side surface Bb, and the weight is greater on the first side surface Ba side. Therefore, the center of gravity of the laminate 2 is located on the first side surface Ba side rather than the center of the laminate 2. Consequently, as shown in Figure 10, by mounting the multilayer ceramic capacitor 1 with the first side surface Ba facing the substrate, the center of gravity of the multilayer ceramic capacitor 1 can be brought closer to the substrate with minimal weight increase, thereby effectively suppressing and preventing the occurrence of the tombstone phenomenon during mounting.

[0027] To ensure that the first side surface Ba is positioned toward the substrate during mounting, it is preferable that the first side surface Ba and / or the second side surface Bb of the laminate 2 be provided with identification means for identifying the orientation of placement. The identification means are not particularly limited, but examples include printing, engraving, or coloring the second side surface Bb.

[0028] Furthermore, since the first side surface Ba is positioned toward the substrate, it is preferable to provide identification means for identifying the direction in which the end face external electrode 3 is positioned. The identification means is not particularly limited, but examples include making the shape and length of the second side surface Bb side of the end face external electrode 3 different from the shape of the first side surface Ba.

[0029] (Outer layer part 12) The outer layer 12 comprises an upper outer layer 12a located on one side of the inner layer 11 and a lower outer layer 12b located on the other side of the inner layer 11 in the stacking direction T. Unless it is necessary to explain the upper outer layer 12a and the lower outer layer 12b separately, they are described together as the outer layer 12.

[0030] The outer layer 12 is manufactured from the same material as the dielectric layer 14 of the inner layer 11. The thickness of the outer layer 12 is, for example, 20 μm or less, and more preferably 10 μm or less. The upper outer layer 12a and the lower outer layer 12b are arranged on both sides of the inner layer in the stacking direction, each with a predetermined thickness. In this embodiment, they have the same thickness, but are not limited to this and may be different.

[0031] (End surface external electrode 3) The end of the lead portion 15b of the first internal electrode layer 15A is exposed to the first end face Ca and is electrically connected to the first end face external electrode 3A. The end of the lead portion 15b of the second internal electrode layer 15B is exposed to the second end face Cb and is electrically connected to the second end face external electrode 3B. As a result, the structure between the first end face external electrode 3A and the second end face external electrode 3B is such that multiple capacitor elements are electrically connected in parallel. Furthermore, the end-face external electrode 3 covers not only the end face C, but also a portion of the main surface A and side surface B on the end face C side, and also covers the raised portion M of the laminate 2.

[0032] Both the end-face external electrode 3 and the side-face external electrode 4 provided in the second embodiment described later can have a structure comprising a base electrode layer and a plating layer disposed on the base electrode layer.

[0033] The base electrode layer includes at least one layer selected from a baked layer, a conductive resin layer, a direct plating layer, etc., as described below.

[0034] (Baked layer) The baked layer is formed by applying a conductive paste containing glass and metal to the laminate and baking it. It may be baked simultaneously with the internal electrodes, or baked after the internal electrodes have been baked. The baking temperature is preferably 700 to 900°C.

[0035] The glass component includes at least one selected from B, Si, Ba, Mg, Al, Li, etc. The metal component also includes at least one selected from, for example, Cu, Ni, Ag, Pd, Ag-Pd alloy, Au, etc.

[0036] The thickness of the baked layer is preferably, for example, 3 μm to 70 μm. The baked layer may also consist of multiple layers.

[0037] (Conductive resin layer) The conductive resin layer is formed on the surface of the baked layer or directly on the surface of the laminate. The conductive resin layer may consist of multiple layers.

[0038] The method for forming the conductive resin layer involves applying a conductive resin paste containing a thermosetting resin and metal components onto a baked layer or laminate, and then heat-treating it at a temperature of 250 to 550°C or higher to heat-cur the resin and form the conductive resin layer. The atmosphere during this heat treatment is preferably an N2 atmosphere. Furthermore, to prevent resin scattering and oxidation of various metal components, the oxygen concentration is preferably kept below 100 ppm.

[0039] The thickness of the conductive resin layer in the central part of the end face C is preferably, for example, 10 μm or more and 150 μm or less.

[0040] As the resin for the conductive resin layer, various known thermosetting resins such as epoxy resin, phenolic resin, urethane resin, silicone resin, and polyimide resin can be used. Among these, epoxy resin, which has excellent heat resistance, moisture resistance, and adhesion, is one of the most suitable resins. Preferably, the resin contained in the conductive resin layer is present in an amount of 25 vol% to 65 vol% of the total volume of the conductive resin.

[0041] Furthermore, it is preferable that the conductive resin layer contains a curing agent along with the thermosetting resin. When epoxy resin is used as the base resin, various known compounds such as phenolic, amine, acid anhydride, and imidazole compounds can be used as curing agents for the epoxy resin.

[0042] Because the conductive resin layer contains a thermosetting resin, it is more flexible than conductive layers made of, for example, a plated film or a fired conductive paste. Therefore, even if the ceramic electronic component is subjected to physical shock or shock caused by thermal cycling, the conductive resin layer functions as a buffer layer, preventing cracks in the ceramic electronic component.

[0043] The metals that can be included in the conductive resin layer are Ag, Cu, or alloys thereof. Alternatively, metal powder with an Ag coating on its surface can be used. When using metal powder with an Ag coating on its surface, it is preferable to use Cu or Ni as the metal powder. Furthermore, Cu treated with an anti-oxidation treatment can also be used.

[0044] The reason for using Ag conductive metal powder as a conductive metal is that Ag has a relatively low resistivity among metals, making it suitable for electrode materials, and because Ag is a noble metal, it does not oxidize and has high stability. The reason for using Ag-coated metal is that it allows for the use of an inexpensive base metal while maintaining the above-mentioned properties of Ag.

[0045] Preferably, the metal contained in the conductive resin layer is present in an amount of 35 vol% to 75 vol% relative to the total volume of the conductive resin.

[0046] The shape of the metal contained in the conductive resin layer is not particularly limited. The conductive filler may be spherical, flattened, or the like. The average particle size of the metal contained in the conductive resin layer is not particularly limited, but can be, for example, 0.3 μm to 10 μm.

[0047] The metals contained in the conductive resin layer are primarily responsible for the conductivity of the conductive resin layer. Specifically, conductive fillers come into contact with each other, forming an electrical pathway within the conductive resin layer.

[0048] (Plating layer) The plating layer may be directly applied to the end face where the internal electrodes of the laminate are exposed. In other words, the multilayer ceramic capacitor may have a structure that includes a plating layer that is electrically directly connected to the internal electrode layer and the surface electrode layer. In such a case, the plating layer may be formed directly after a catalyst is placed on the surface of the laminate as a pretreatment.

[0049] The plating layer preferably contains at least one metal selected from, for example, Cu, Ni, Sn, Pb, Au, Ag, Pd, Bi, or Zn, or an alloy containing such metal. For example, when the first and second internal electrode layers are formed using Ni, the direct plating layer is preferably formed using Cu, which has good bonding properties with Ni.

[0050] The thickness of each plating layer is preferably 2 μm to 15 μm. The plating layer is preferably free of glass. The metal content per unit volume of the plating layer is preferably 99% by volume or more.

[0051] When performing the plating process, either electrolytic plating or electroless plating may be used. However, electroless plating requires pretreatment with catalysts or other means to improve the plating deposition rate, which has the disadvantage of complicating the process. Therefore, electrolytic plating is generally preferred. As for the plating method, barrel plating is preferred. If necessary, the upper plating electrode formed on the surface of the lower plating electrode may be formed in the same manner.

[0052] When the underlying electrode layer is a thin film layer, the thin film layer is formed by a thin film formation method such as sputtering or vapor deposition, and is a layer of 1 μm or less in thickness on which metal particles are deposited.

[0053] The plating layer placed on the underlying electrode layer includes, for example, at least one selected from Cu, Ni, Ag, Pd, Ag-Pd alloy, Au, etc.

[0054] The plating layer may be formed by multiple layers. Preferably, it is a two-layer structure of Ni plating and Sn plating. The Ni plating layer can prevent the underlying electrode layer from being eroded by the solder when mounting ceramic electronic components, and the Sn plating layer improves the wettability of the solder when mounting ceramic electronic components, making mounting easier. The thickness of each plating layer is preferably 2 μm or more and 15 μm or less.

[0055] (Method for manufacturing a multilayer ceramic capacitor 1) Next, an example of a manufacturing method for the multilayer ceramic capacitor 1 of the embodiment will be described. Figure 5 is a flowchart illustrating the manufacturing method for the multilayer ceramic capacitor 1.

[0056] (Internal electrode layer pattern formation process S1) First, an internal electrode layer pattern 103, which will become the internal electrode layer 15, is formed on the ceramic green sheet 101, which will become the dielectric layer 14, using a conductive paste. Figure 6 is a perspective view of the material sheet 203 on which the internal electrode layer pattern 103, which will become the internal electrode layer 15, is printed on the surface of the ceramic green sheet 101.

[0057] (Ceramic Green Sheet 101) The ceramic green sheet 101 is a strip-shaped sheet formed on a carrier film using a die coater, gravure coater, microgravure coater, etc., from a ceramic slurry containing ceramic powder, a binder, and a solvent.

[0058] (Internal electrode layer pattern 103) The internal electrode layer pattern 103 is formed by printing, for example, screen printing, gravure printing, or letterpress printing.

[0059] Here, the internal electrode layer pattern 103 forms a step 104 on the ceramic green sheet 101 due to its thickness. In this embodiment, the step 104 is an inclined surface.

[0060] (Overlap dielectric arrangement process S2) Next, a ceramic paste 102 is placed on the material sheet 203 to fill the step 104 caused by the thickness of the internal electrode layer pattern 103 and to form a dielectric layer, overlapping by a certain width with one side of the first side surface Ba of the internal electrode layer pattern 103. Alternatively, the ceramic paste 102 for forming the dielectric layer may be placed on the outer periphery where the internal electrode layer pattern 103 is to be formed first, and then the internal electrodes may be placed later so as to overlap by a certain width with one side of the first side surface Ba of the internal electrode layer pattern 103. Figure 7 is a perspective view showing the ceramic paste 102 placed on the material sheet 203. Figure 8 is a cross-sectional view along line VIII-VIII in Figure 7. The ceramic paste 102 is applied by printing, for example, screen printing, gravure printing, or letterpress printing. The ceramic paste 102 may have a different component ratio from the dielectric material of the ceramic green sheet 101, or it may have the same component ratio, or it may contain different components.

[0061] The ceramic paste 102 is applied to one side of the first side surface Ba of the internal electrode layer 15 so as to overlap by a certain width. The width of the overlap is preferably less than 33% of the width dimension of the internal electrode layer 15, and preferably between 2% and 25%. Furthermore, as shown in Figure 8, since the step 104 of the internal electrode layer pattern 103 is an inclined surface, the ceramic paste 102 gradually rides up onto the internal electrode layer pattern 103. Therefore, the upper surface of the ceramic paste 102 becomes smooth. The thickness of the ceramic paste 102 is preferably 0.4 times or more and 0.8 times or less the thickness of the ceramic green sheet 101.

[0062] (Lamination process S3) Figure 9 illustrates the stacking state of the material sheet 203. As shown in Figure 9, the material sheet 203 is arranged such that adjacent internal electrode layer patterns 103 in the stacking direction T are alternately offset in the length direction L.

[0063] Furthermore, on one side of the multiple stacked material sheets 203, a ceramic green sheet 212 for the upper outer layer, which will become the upper outer layer 12a, is stacked, and on the other side, a ceramic green sheet 213 for the lower outer layer, which will become the lower outer layer 12b, is stacked.

[0064] (Mother block formation process S4) Next, the ceramic green sheet 212 for the upper outer layer, the stacked material sheets 203, and the ceramic green sheet 213 for the lower outer layer are heat-pressed together to form the mother block.

[0065] (Mother block splitting process S5) Next, the mother block is cut at position Z shown in Figure 9. Although only the cutting position Z in the length direction L is shown, the laminate 2 is also cut at predetermined cutting positions in the width direction W, which are perpendicular to the position Z in the width direction, and multiple rectangular laminates 2 are manufactured.

[0066] (Firing process S6) In the firing process, the laminated chip is subjected to a binder removal treatment and firing treatment to form the base body. The firing treatment causes the conductive paste layer and the green sheet for the dielectric layer to co-sinter, forming the internal electrode layer 15 and the dielectric layer 14, respectively. The conditions for the binder removal treatment should be determined according to the type of organic binder contained in the green sheet and the conductive paste layer. The firing treatment should be performed at a temperature at which the laminated chip becomes sufficiently densified. The firing temperature depends on the materials of the dielectric and the internal electrode layer, but is preferably between 900°C and 1400°C.

[0067] (External electrode formation step S7) In the external electrode formation process, end-face external electrodes 3 are formed on the laminate 2 to form a multilayer ceramic capacitor 1. The end-face external electrodes 3 can be formed by known methods. The side external electrodes 4 provided in the second embodiment, described later, can also be formed in the same way as the end-face external electrodes 3. For example, a base electrode layer, a conductive resin layer, or a direct plating layer is formed on the end face C exposed by pulling out the internal electrode layer 15 of the laminate 2, and a plating layer is further provided as needed. In this embodiment, a Ni plating layer and a Sn plating layer were formed on the baked layer. The Ni plating layer and the Sn plating layer are formed sequentially, for example, by a barrel plating method. In this way, a multilayer ceramic capacitor can be obtained.

[0068] (Multilayer ceramic capacitor 300) The multilayer ceramic capacitor 300 is a three-terminal multilayer ceramic capacitor (second embodiment). Since the dielectric layer, internal electrode layer, external electrodes, etc. that constitute the three-terminal multilayer ceramic capacitor are often the same as those of a two-terminal multilayer ceramic capacitor, the following description will focus on the configurations that differ from those of a two-terminal multilayer ceramic capacitor.

[0069] Figures 11 to 13 show the shape and structure of the multilayer ceramic capacitor 300. Figure 11 is an external view of the three-terminal multilayer ceramic capacitor 300. Figure 12 is an exploded perspective view illustrating the state of the internal electrode layer 15 in the inner layer portion 11 of the multilayer ceramic capacitor 300. Figure 13 is an exploded perspective view illustrating the arrangement of ceramic pastes 102A and 102B in the inner layer portion 11 of the multilayer ceramic capacitor 300. The stacking direction is defined as the stacking direction T for the dielectric layer and the internal electrode layer, and the structure of the multilayer ceramic capacitor 300 is described using the length direction L, which is perpendicular to the stacking direction T, and the width direction W, which is perpendicular to both the stacking direction T and the length direction L. In this embodiment, the width direction W, the length direction L, and the stacking direction T are perpendicular to each other, but they are not necessarily perpendicular to each other and may intersect with each other.

[0070] A first end-face external electrode 3A, a second end-face external electrode 3B, and a side-face external electrode 4 are formed on the surface of the laminate 2.

[0071] The first end face external electrode 3A is formed on the first end face Ca of the laminate 2. The first end face external electrode 3A is formed in a cap shape, with its edge portion extending from the first end face Ca of the laminate 2 to the first main surface Aa, the second main surface Ab, the first side surface Ba, and the second side surface Bb.

[0072] The second end face external electrode 3B is formed on the second end face Cb of the laminate 2. The second end face external electrode 3B is formed in a cap shape, with its edge extending from the second end face Cb of the laminate 2 to the first main surface Aa, the second main surface Ab, the first side surface Ba, and the second side surface Bb.

[0073] The side external electrodes 4 can be formed on either the left or right side of the laminate 2, but Figure 11 shows a configuration in which the first side external electrode 4A and the second side external electrode 4B are formed on the first side Ba and second side Bb of the laminate 2, respectively. The side external electrodes 4 are also formed extending to the first main surface Aa and the second main surface Ab.

[0074] Figure 11 schematically shows the internal electrode layer 15 and dielectric layer 14 of the multilayer ceramic capacitor 300.

[0075] The internal electrode layer 15 is composed of a first internal electrode layer 15A and a second internal electrode layer 15B. The first internal electrode layer 15A and the second internal electrode layer 15B are each placed on top of the dielectric layer 14.

[0076] The first internal electrode layer 15A penetrates the interior of the laminate 2 in the width direction W, connects to the side external electrode 4, and forms an electrostatic capacitance with the second internal electrode layer 15B. In this embodiment, both ends of the first internal electrode layer 15A are drawn out to the side B of the laminate 2 and connected to the side external electrode 4, while they are not drawn out to the end face C of the laminate 2 and do not connect to the end face external electrode 3. The first internal electrode layer 15A can be in a roughly cross shape as shown in Figure 12, but is not limited to this, and any shape can be adopted as long as it connects to the side external electrode 4 and does not connect to the end face external electrode 3.

[0077] In the embodiment shown in Figure 12, the first internal electrode layer 15A includes a first opposing portion 15Aa facing the second internal electrode layer 15B via the dielectric layer 14, a first side-side lead portion 15Ab1 extending from the first opposing portion 15Aa and leading out to the first side surface Ba of the laminate 2, and a second side-side lead portion 15Ab2 extending from the first opposing portion 15Aa and leading out to the second side surface Bb of the laminate 2. However, if either of the lead portions is present, for example, the first side-side lead portion 15Ab1, it can function as a three-terminal multilayer ceramic capacitor.

[0078] The second internal electrode layer 15B penetrates the interior of the laminate 2 in the longitudinal direction L and connects to the end face external electrode 3. The second internal electrode layer 15B is shaped such that both ends are drawn out to the end face C of the laminate and connected to the end face external electrode 3, while it is not drawn out to the side B of the laminate and does not connect to the side external electrode 4.

[0079] In this embodiment, the second internal electrode layer 15B is rectangular as shown in Figure 12, but it is not limited to this. The second internal electrode layer 15B may have a second opposing portion 15Ba that faces the first internal electrode layer 15A via the dielectric layer 14, a first pull-out portion 15Bb1 that extends from the second opposing portion 15Ba and is pulled out to one of the two side surfaces B or two end surfaces C of the laminate 2, at a position different from the first side surface pull-out portion 15Ab1 when the laminate 2 is viewed in plan from the stacking direction T, and a second pull-out portion 15Bb2 that extends from the second opposing portion 15Ba and is pulled out to one of the two side surfaces B or two end surfaces C of the laminate 2, at a position different from the first side surface pull-out portion 15Ab1, the second side surface pull-out portion 15Ab2, and the first pull-out portion 15Bb1 when the laminate 2 is viewed in plan from the stacking direction T. The external electrodes can be arranged according to the positions of the first pull-out portion 15Bb1 and the second pull-out portion 15Bb2.

[0080] A multilayer ceramic capacitor 300, in which the first internal electrode layer 15A is connected to the side external electrode 4 and the second internal electrode layer 15B is connected to the first end face external electrode 3A and the second end face external electrode 3B, can be used as a three-terminal capacitor. That is, the multilayer ceramic capacitor 300 can be used as a three-terminal capacitor by interrupting a power line or signal line in a circuit, connecting the first end face external electrode 3A to one side of the interruption, connecting the second end face external electrode 3B to the other side of the interruption, and connecting the side external electrode 4 to ground. In this case, the second internal electrode layer 15B becomes a through electrode, and the first internal electrode layer 15A becomes a ground electrode.

[0081] Figure 13 schematically shows the areas of ceramic paste 102A and 102B applied to the inner layer 11 of the multilayer ceramic capacitor 300 during manufacturing. During the manufacturing of the multilayer ceramic capacitor 300, ceramic paste 102A is printed on the area where the internal electrode layer pattern 103A, which will become the first internal electrode layer 15A, is not located on the material sheet 203A, which has the internal electrode layer pattern 103A, which will become the first internal electrode layer 15A, printed on the ceramic green sheet 101A, which will become the dielectric layer 14. Furthermore, ceramic paste 102A covers the first side side lead-out portion 15Ab1 that extends from the first opposing portion 15Aa of the first internal electrode layer 15A to the first side external electrode 4A on the first side Ba side. In addition, ceramic paste 102A covers the internal electrode layer pattern 103A at a position corresponding to one side of the first opposing portion 15Aa of the first internal electrode layer 15A on the first side Ba side with a certain width. Similarly, ceramic paste 102B is printed on a material sheet 203B on which an internal electrode layer pattern 103B, which will become the second internal electrode layer 15B, is printed, in areas where the internal electrode layer pattern 103B is not present. Furthermore, the ceramic paste 102B covers the internal electrode layer pattern 103B at a position corresponding to one side of the second internal electrode layer 15B on the first side surface Ba with a certain width.

[0082] Since the ceramic pastes 102A and 102B overlap one side of the internal electrode layer 15 on the first side Ba side by a certain width, the spacing in the stacking direction T becomes wider at the end of the internal electrode layer 15 on the first side Ba side. In a laminate 2 in which multiple such internal electrode layers 15 are stacked, when the laminate 2 is cut by a plane perpendicular to the length direction L at a position where no side external electrodes 4 are placed, the distance T1 between the end of the uppermost internal electrode layer 15 on the first side Ba side and the end of the lowermost internal electrode layer 15 on the first side Ba side is longer than the distance T2 between the end of the uppermost internal electrode layer 15 on the second side Bb side and the end of the lowermost internal electrode layer 15 on the second side Bb side.

[0083] The volume of the laminate 2 constituting the multilayer ceramic capacitor 300 is larger on the first side than on the second side, and therefore the weight is greater on the first side. Consequently, the center of gravity of the laminate 2 is located on the first side Ba side rather than the center of the laminate 2. Therefore, by mounting the multilayer ceramic capacitor 300 with the first side Ba facing the substrate, the center of gravity of the multilayer ceramic capacitor 1 can be brought closer to the substrate with minimal weight increase, thereby effectively suppressing and preventing the occurrence of the tombstone phenomenon during mounting.

[0084] Although embodiments of the present invention have been described above, the present invention is not limited to these embodiments and can be implemented in various forms without departing from the spirit of the invention. The present invention includes the following combinations.

[0085] <1> A laminate comprising an inner layer in which a plurality of dielectric layers and internal electrode layers are alternately stacked, having a first main surface and a second main surface facing each other in the stacking direction, a first end surface and a second end surface facing each other in the length direction intersecting the stacking direction, and a first side surface and a second side surface facing each other in the width direction intersecting the stacking direction and the length direction, A plurality of external electrodes are arranged on either of the two end faces and two side faces of the laminate and connected to the internal electrode layer, A multilayer ceramic capacitor equipped with, When the laminate is cut in a plane perpendicular to the longitudinal direction at a position where the external electrodes are not arranged, A multilayer ceramic capacitor in which the distance T1 between the first side surface end of the internal electrode layer located closest to the first main surface and the first side surface end of the internal electrode layer located closest to the second main surface is longer than the distance T2 between the second side surface end of the internal electrode layer located closest to the first main surface and the second side surface end of the internal electrode layer located closest to the second main surface.

[0086] <2> When the internal electrode layer is divided into a central region including the central part, a first side region located on the first side side of the central region, and a second side region located on the second side side of the central region, The distance between two adjacent internal electrode layers, The distance t1 in the stacking direction of the first side region is longer than the distance t2 in the stacking direction of the second side region. <1> The multilayer ceramic capacitors described.

[0087] <3> The laminate is provided with identification means for identifying the orientation in which it is arranged on the first and / or second side surfaces. <1> or <2> The multilayer ceramic capacitors described.

[0088] <4> The external electrode is provided with an identification means for identifying the direction in which it is placed. <1> ~ <3> A multilayer ceramic capacitor as described in any of the following.

[0089] <5> The plurality of internal electrode layers comprises a plurality of first internal electrode layers drawn out to the first end face and a plurality of second internal electrode layers drawn out to the second end face, and external electrodes are provided on the first end face and the second end face. <1> ~ <4> A multilayer ceramic capacitor as described in any of the following.

[0090] <6> The plurality of internal electrode layers comprises a first internal electrode layer and a second internal electrode layer, The first internal electrode layer has a first opposing portion that faces the second internal electrode layer via the dielectric layer, and a first side-side withdrawal portion that extends from the first opposing portion and is drawn out to the first side surface of the laminate. The second internal electrode layer has a second opposing portion that faces the first internal electrode layer via the dielectric layer, a first pull-out portion that extends from the second opposing portion and is pulled out to one of the two sides or two end faces of the laminate at a position different from the first side pull-out portion when the laminate is viewed in plan from the stacking direction, and a second pull-out portion that extends from the second opposing portion and is pulled out to one of the two sides or two end faces of the laminate at a position different from the first side pull-out portion and the first pull-out portion when the laminate is viewed in plan from the stacking direction. The plurality of external electrodes include a first side external electrode connected to the first side extension portion, a first external electrode connected to the first extension portion, and a second external electrode connected to the second extension portion. <1> ~ <4> A multilayer ceramic capacitor as described in any of the following. [Explanation of Symbols]

[0091] A Main surface Aa First main face Ab Second main plane B side Ba, first side Bb 2nd side C end face Ca 1st end surface Cb 2nd end face M Excitement Section T Stacking direction W (width direction) L (Length direction) 1. Multilayer ceramic capacitor 2 Laminate 3 Edge external electrode 4 Side external electrode 11 Inner layer 12 Outer layer 14 Dielectric layer 15 Internal electrode layer 15a Opposite part 15b Drawer section 101 Ceramic Green Sheet 102 Ceramic Paste 103 Internal electrode layer pattern 104 steps 203 Material Sheet 300 Multilayer Ceramic Capacitors

Claims

1. A laminate comprising an inner layer in which a plurality of dielectric layers and internal electrode layers are alternately stacked, having a first main surface and a second main surface facing each other in the stacking direction, a first end surface and a second end surface facing each other in the length direction intersecting the stacking direction, and a first side surface and a second side surface facing each other in the width direction intersecting the stacking direction and the length direction, A plurality of external electrodes are arranged on either of the two end faces and two side faces of the laminate and connected to the internal electrode layer, A multilayer ceramic capacitor equipped with, When the laminate is cut in a plane perpendicular to the longitudinal direction at a position where the external electrodes are not arranged, A multilayer ceramic capacitor in which the distance T1 between the first side surface end of the internal electrode layer located closest to the first main surface and the first side surface end of the internal electrode layer located closest to the second main surface is longer than the distance T2 between the second side surface end of the internal electrode layer located closest to the first main surface and the second side surface end of the internal electrode layer located closest to the second main surface.

2. When the internal electrode layer is divided into a central region including the central part, a first side region located on the first side side of the central region, and a second side region located on the second side side of the central region, The distance between two adjacent internal electrode layers, The multilayer ceramic capacitor according to claim 1, wherein the distance t1 in the stacking direction of the first side region is longer than the distance t2 in the stacking direction of the second side region.

3. The multilayer ceramic capacitor according to claim 1 or 2, further comprising identification means for identifying the orientation in which the laminate is arranged on the first side surface and / or the second side surface.

4. The multilayer ceramic capacitor according to claim 1 or 2, further comprising identification means for identifying the direction in which the external electrodes are arranged.

5. The multilayer ceramic capacitor according to claim 1 or 2, wherein the plurality of internal electrode layers comprises a plurality of first internal electrode layers drawn out to the first end face and a plurality of second internal electrode layers drawn out to the second end face, and the external electrodes are provided on the first end face and the second end face.

6. The plurality of internal electrode layers comprises a first internal electrode layer and a second internal electrode layer, The first internal electrode layer has a first opposing portion that faces the second internal electrode layer via the dielectric layer, and a first side-side withdrawal portion that extends from the first opposing portion and is drawn out to the first side surface of the laminate. The second internal electrode layer has a second opposing portion that faces the first internal electrode layer via the dielectric layer, a first pull-out portion that extends from the second opposing portion and is pulled out to one of the two sides or two end faces of the laminate at a position different from the first side pull-out portion when the laminate is viewed in plan from the stacking direction, and a second pull-out portion that extends from the second opposing portion and is pulled out to one of the two sides or two end faces of the laminate at a position different from the first side pull-out portion and the first pull-out portion when the laminate is viewed in plan from the stacking direction. The multilayer ceramic capacitor according to claim 1 or 2, wherein the plurality of external electrodes include a first side external electrode connected to the first side lead portion, a first external electrode connected to the first lead portion, and a second external electrode connected to the second lead portion.

7. A laminate comprising an inner layer in which a plurality of dielectric layers and internal electrode layers are stacked, the laminate having a first main surface and a second main surface facing each other in the stacking direction, a first end surface and a second end surface facing each other in the length direction intersecting the stacking direction, and a first side surface and a second side surface facing each other in the width direction intersecting the stacking direction and the length direction, A plurality of external electrodes are arranged on either of the two end faces and two side faces of the laminate and connected to the internal electrode layer, A multilayer ceramic capacitor equipped with, When the laminate is cut in a plane perpendicular to the longitudinal direction at a position where the external electrodes are not arranged, The internal electrode layer is The central region including the central part, The first side region located on the first side side of the central region, The second side region located on the second side side of the central region, Equipped with, The distance between two adjacent internal electrode layers, A multilayer ceramic capacitor in which the distance t1 in the stacking direction in the first side region is longer than the distance t2 in the stacking direction in the second side region.

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