Semiconductor equipment

Abstract

To provide a semiconductor device capable of switching drive speeds.SOLUTION: The semiconductor device includes a first buffer circuit and a second buffer circuit, each of which outputs a control signal to one control line on the basis of input from a signal output circuit, and an element that receives the control signals transmitted through the one control line. At least one of the first buffer circuit and the second buffer circuit is capable of switching between electrical connection and disconnection with the one control line.SELECTED DRAWING: Figure 3

Description

Technical Field

[0001] The present invention relates to a semiconductor device.

Background Art

[0002] Patent Document 1 discloses an imaging device having a buffer circuit that outputs control signals to a plurality of pixels arranged in the same row and an auxiliary drive circuit that assists in driving the buffer circuit. By providing the auxiliary drive circuit, the difference in the timing at which the control signal reaches the pixels is reduced.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] Patent Document 1 discloses that the driving of elements is accelerated by an auxiliary drive circuit. However, Patent Document 1 does not disclose switching of the driving speed.

[0005] Therefore, an object of the present invention is to provide a semiconductor device capable of switching the driving speed.

Means for Solving the Problems

[0006] According to one disclosure of this specification, the device comprises a first buffer circuit and a second buffer circuit, each outputting a control signal to a control line based on an input from a signal output circuit, and an element that receives the control signal transmitted through the control line, wherein the second buffer circuit is switchable between electrical connection and disconnection with the control line, and the device is switchable between a first mode in which the first buffer circuit supplies current to the control line with a first drive capability, and a second mode in which both the first buffer circuit and the second buffer circuit are connected to the control line, thereby supplying current to the control line with a second drive capability greater than the first drive capability. Therefore, the driving capability of the first buffer circuit and the driving capability of the second buffer circuit are different from each other. A semiconductor device characterized by the above is provided. According to one disclosure of this specification, a semiconductor device is provided comprising: a first buffer circuit and a second buffer circuit, each outputting a control signal to a control line based on an input from a signal output circuit; and an element that receives the control signal transmitted through the control line, wherein the second buffer circuit is switchable between electrical connection and disconnection with the control line, and is switchable between a first mode in which the first buffer circuit supplies current to the control line with a first drive capability and a second mode in which both the first buffer circuit and the second buffer circuit are connected to the control line to supply current to the control line with a second drive capability greater than the first drive capability, wherein the second buffer circuit includes a first MOS transistor of a first conductivity type, and the first main electrode of the first MOS transistor is electrically connected to the control line. According to one disclosure of this specification, a semiconductor device is provided comprising: a first buffer circuit and a second buffer circuit, each outputting a control signal to a control line based on an input from a signal output circuit; and an element that receives the control signal transmitted through the control line, wherein the second buffer circuit is switchable between electrical connection and disconnection with the control line, and is switchable between a first mode in which the first buffer circuit supplies current to the control line with a first drive capability and a second mode in which both the first buffer circuit and the second buffer circuit are connected to the control line to supply current to the control line with a second drive capability greater than the first drive capability, and having a plurality of such elements, the control line being commonly connected to the plurality of such elements, and the first buffer circuit and the second buffer circuit being arranged to sandwich the plurality of such elements. [Effects of the Invention]

[0007] According to the present invention, it is possible to provide a semiconductor device that can switch the drive speed. [Brief explanation of the drawing]

[0008] [Figure 1] This block diagram shows a schematic configuration of the photoelectric conversion device according to the first embodiment. [Figure 2] This is a circuit diagram of a pixel according to the first embodiment. [Figure 3] This is a circuit diagram showing a more detailed configuration of the buffer circuit group according to the first embodiment. [Figure 4] This is a timing chart showing the operation of the photoelectric converter according to the first embodiment. [Figure 5] This is a timing chart showing the operation of the photoelectric converter according to the first embodiment. [Figure 6] This figure shows the configuration and operation of the buffer circuit group according to the second embodiment. [Figure 7] This figure shows the configuration and operation of the buffer circuit group according to the third embodiment. [Figure 8] This figure shows the configuration and operation of the buffer circuit group according to the fourth embodiment. [Figure 9] This figure shows the configuration and operation of the buffer circuit group according to the fifth embodiment. [Figure 10] This figure shows the configuration of the buffer circuit group according to the sixth embodiment. [Figure 11] This is a circuit diagram of a pixel according to the sixth embodiment. [Figure 12] This is a block diagram of the equipment according to the seventh embodiment. [Figure 13] This is a block diagram of the equipment according to the eighth embodiment. [Modes for carrying out the invention]

[0009] Embodiments of the present invention will be described below with reference to the drawings. Elements identical or corresponding to each other across multiple drawings are denoted by the same reference numerals, and their descriptions may be omitted or simplified.

[0010] In the first to fifth embodiments described below, the imaging device will be described as an example of a photoelectric conversion device. However, the photoelectric conversion device in each embodiment is not limited to an imaging device and can be applied to other photodetection devices based on photoelectric conversion. Examples of other photodetection devices include distance measuring devices and photometric devices. Distance measuring devices may be, for example, focus detection devices or distance measuring devices using TOF (Time-Of-Flight). Photometric devices may be devices that measure the amount of light incident on the device. Furthermore, photoelectric conversion devices are sometimes more generally called semiconductor devices.

[0011] [First Embodiment] Figure 1 is a block diagram showing the schematic configuration of a photoelectric converter according to this embodiment. The photoelectric converter of this embodiment includes a pixel array 10, a vertical scanning circuit 20, a buffer circuit group 30, a readout circuit 50, a horizontal scanning circuit 52, an output circuit 54, and a control circuit 60. The circuits constituting the photoelectric converter can be formed on one or more semiconductor substrates.

[0012] The pixel array 10 has a plurality of pixels 11 arranged over a plurality of rows and a plurality of columns. Each of the plurality of pixels 11 is an element that photoelectrically converts incident light to generate charges and outputs a signal corresponding to the incident light. A microlens and a color filter may be arranged on the pixel 11. In FIG. 1, only three rows and three columns of the plurality of pixels 11 are shown, but actually, there may be thousands of rows and thousands of columns.

[0013] In each row of the pixel array 10, a plurality of control lines CL are arranged extending in a first direction (the horizontal direction in FIG. 1). Each of the plurality of control lines CL is connected to the pixels 11 arranged in the first direction respectively, forming a common signal line for these pixels 11. The first direction in which the control line CL extends is sometimes called the row direction or the horizontal direction. The control line CL is connected to the buffer circuit group 30.

[0014] In each column of the pixel array 10, a vertical signal line VL is arranged extending in a second direction (the vertical direction in FIG. 1) intersecting the first direction. Each of the vertical signal lines VL is connected to the pixels 11 arranged in the second direction respectively, forming a common signal line for these pixels 11. The second direction in which the vertical signal line VL extends is sometimes called the column direction or the vertical direction. Each of the vertical signal lines VL is connected to the readout circuit 50 and a current source 12 described later in FIG. 2.

[0015] The control circuit 60 outputs control signals such as a vertical synchronization signal, a horizontal synchronization signal, and a clock signal to the vertical scanning circuit 20, the buffer circuit group 30, the readout circuit 50, and the horizontal scanning circuit 52. Thereby, the control circuit 60 controls the operations of these circuits.

[0016] The vertical scanning circuit 20 is a signal output circuit including logic circuits such as a shift register and a gate circuit. The vertical scanning circuit 20 outputs a control signal to the pixel 11 via the buffer circuit group 30 and the control line CL based on a vertical synchronization signal, a horizontal synchronization signal, a clock signal, etc., and performs a scan to sequentially output signals from the pixel 11 row by row. Also, the vertical scanning circuit 20 controls the charge accumulation period in the pixel 11.

[0017] The buffer circuit group 30 includes multiple buffer circuits that buffer the control signals output from the vertical scanning circuit 20 and output them to the control line CL. The detailed configuration of the buffer circuit group 30 will be described later.

[0018] The signal generated by pixel 11 is output to the readout circuit 50 via the corresponding column's vertical signal line VL. The readout circuit 50 has a column circuit corresponding to each column. The column circuit includes an analog memory, an amplification circuit, an analog-to-digital conversion circuit (AD conversion circuit), a digital memory, etc. The column circuit processes the signal input via the vertical signal line VL, such as amplification and AD conversion, and stores the processed signal for each column.

[0019] The horizontal scanning circuit 52 is a scanning circuit that includes logic circuits such as a shift register, gate circuit, and buffer circuit. The horizontal scanning circuit 52 sequentially selects multiple column circuits of the readout circuit 50. As a result, each of the multiple column circuits sequentially outputs the signal it holds to the output circuit 54. The output circuit 54 outputs the signal to the outside of the photoelectric converter in a predetermined format.

[0020] Figure 2 is a circuit diagram of a pixel 11 according to this embodiment. Figure 2 shows one pixel 11 extracted from the pixel array 10. In the following description, when a subscript in the form of "VL[0]" is appended to the end of a reference numeral, this subscript indicates the row number or column number. Subscripts in this form may be appended to reference numerals when it is necessary to distinguish between rows and columns, and subscripts may be omitted when it is not necessary to distinguish between rows and columns. The pixel 11 shown in Figure 2 is assumed to be the pixel 11 of the 0th row and 0th column.

[0021] In the following explanation, it is assumed that the charge accumulated in the photoelectric conversion unit within pixel 11 is electrons. Furthermore, it is assumed that all transistors in pixel 11 are n-channel type MOS transistors (hereinafter abbreviated as nMOS transistors). However, the charge accumulated in the photoelectric conversion unit may also be holes, in which case the transistors in pixel 11 may be p-channel type MOS transistors (hereinafter abbreviated as pMOS transistors). In other words, the conductivity type of transistors, etc., can be appropriately changed depending on the polarity of the charge treated as a signal. In addition, one of the n-channel type and the p-channel type may be called the first conductivity type, and the other the second conductivity type.

[0022] Pixel 11 includes a photoelectric converter PD, a transfer transistor M1, a reset transistor M2, an amplification transistor M3, and a selection transistor M4. The photoelectric converter PD is, for example, a photodiode. The anode of the photoelectric converter PD is connected to the ground node, and the cathode of the photoelectric converter PD is connected to the source of the transfer transistor M1. The drain of the transfer transistor M1 is connected to the source of the reset transistor M2 and the gate of the amplification transistor M3. The node to which the drain of the transfer transistor M1, the source of the reset transistor M2, and the gate of the amplification transistor M3 are connected is a stray diffusion section FD. The stray diffusion section FD includes a capacitive component (stray diffusion capacitance) and functions as a charge holder. The stray diffusion capacitance includes the parasitic capacitance of the electrical path from the transfer transistor M1 through the stray diffusion section FD to the amplification transistor M3.

[0023] The drains of reset transistor M2 and amplifier transistor M3 are connected to a power supply voltage node to which voltage VDD is supplied. The source of amplifier transistor M3 is connected to the drain of selection transistor M4. The source of selection transistor M4 is connected to the vertical signal line VL.

[0024] A current source 12 is connected to the vertical signal line VL. The current source 12 may be a current source with a switchable current value, or a constant current source with a constant current value.

[0025] The control line CL[0] of the 0th row includes the control line Tx[0] connected to the gate of the transfer transistor M1, the control line Res[0] connected to the gate of the reset transistor M2, and the control line sel[0] connected to the gate of the selection transistor M4. The gate of the transfer transistor M1 is supplied with a control signal ΦTx from the vertical scanning circuit 20 via the buffer circuit group 30. The gate of the reset transistor M2 is supplied with a control signal ΦRes from the vertical scanning circuit 20 via the buffer circuit group 30. The gate of the selection transistor M4 is supplied with a control signal Φsel from the vertical scanning circuit 20 via the buffer circuit group 30. Multiple pixels 11 in the same row are connected to a common control line and are controlled simultaneously by a common control signal.

[0026] In this embodiment, each transistor constituting the pixel 11 is assumed to be an n-channel MOS transistor. Therefore, when a high-level control signal is supplied from the vertical scanning circuit 20, the corresponding transistor turns on. Conversely, when a low-level control signal is supplied from the vertical scanning circuit 20, the corresponding transistor turns off. Furthermore, the names of the source and drain of a MOS transistor may differ depending on the conductivity type of the transistor or the function of interest. Some or all of the source and drain names used in this embodiment may also be referred to by the reverse names.

[0027] The photoelectric conversion unit PD converts incident light into an amount of charge corresponding to the amount of light (photoelectric conversion). When the transfer transistor M1 is turned on, it transfers the charge held by the photoelectric conversion unit PD to the floating diffusion unit FD. The charge transferred from the photoelectric conversion unit PD is held in the capacitance (floating diffusion capacitance) of the floating diffusion unit FD. As a result, the floating diffusion unit FD reaches a potential corresponding to the amount of charge transferred from the photoelectric conversion unit PD through charge-voltage conversion by the floating diffusion capacitance.

[0028] When the select transistor M4 is turned on, it connects the amplifier transistor M3 to the vertical signal line VL. The amplifier transistor M3 is configured such that a voltage VDD is supplied to its drain and a bias current is supplied to its source from the current source 12 via the select transistor M4, forming an amplification section (source follower circuit) with its gate as the input node. As a result, the amplifier transistor M3 outputs a signal based on the potential of the floating diffusion section FD to the vertical signal line VL via the select transistor M4. In this sense, the amplifier transistor M3 and the select transistor M4 are output sections that output a pixel signal corresponding to the amount of charge held in the floating diffusion section FD.

[0029] The reset transistor M2 has the function of resetting the floating diffusion section FD by controlling the supply of voltage (voltage VDD) to the floating diffusion section FD. When the reset transistor M2 is turned on, it resets the floating diffusion section FD to a voltage corresponding to voltage VDD.

[0030] In Figure 2, a configuration is shown in which a signal is output to the corresponding vertical signal line VL via a single selection transistor M4. However, the configuration of the selection transistor M4 and the vertical signal line VL is not limited to this. For example, in a configuration in which multiple selection transistors M4 and multiple vertical signal lines VL are arranged for a single pixel 11, a configuration may be adopted in which the vertical signal line VL that outputs the signal can be selected by individually controlling the multiple selection transistors M4.

[0031] Figure 3 is a circuit diagram showing a more detailed configuration of the buffer circuit group 30 according to this embodiment. Figure 3 shows the pixel array 10, vertical scanning circuit 20, and readout circuit 50 as peripheral circuits to the buffer circuit group 30, while other elements are omitted. Also, in Figure 3, three rows and three columns, from row 0 to row 2 and from column 0 to column 2, are extracted and shown. In addition, in Figure 3, only the control line sel of the control line CL is shown, and the control line Tx and control line Res are omitted from the illustration. Between the vertical scanning circuit 20 and the buffer circuit group 30, control lines selp[0], selp[1], and selp[2], which transmit control signals for controlling the selection transistor M4, are arranged corresponding to each row.

[0032] The buffer circuit group 30 includes a plurality of first buffer circuits 31, a plurality of second buffer circuits 32, and an inverter circuit INV2. Each of the first buffer circuits 31 and the second buffer circuits 32 is arranged corresponding to each row of the pixel array 10. One first buffer circuit 31 and one second buffer circuit 32 are connected to a corresponding control line sel[n] (where n is a non-negative integer).

[0033] The first buffer circuit 31 and the second buffer circuit 32 in row 0 will be described. The first and second rows are the same as row 0, so their explanation will be omitted. The first buffer circuit 31 includes a pMOS transistor M5 (second MOS transistor), an nMOS transistor M6 (third MOS transistor), and an inverter circuit INV1. The second buffer circuit 32 includes a pMOS transistor M7 (first MOS transistor) and a NAND circuit NA1.

[0034] The control line selp[0] is connected to the input terminal of inverter circuit INV1. The output terminals of inverter circuit INV1 are connected to the gate of pMOS transistor M5 and the gate of nMOS transistor M6. The source (second main electrode) of pMOS transistor M5 is connected to the power supply voltage node to which voltage VDD is supplied. The source (second main electrode) of nMOS transistor M6 is connected to the ground node. The drain (first main electrode) of pMOS transistor M5 and the drain (first main electrode) of nMOS transistor M6 are connected to the control line sel[0].

[0035] The control line selp[0] is connected to the first input terminal of the NAND circuit NA1. The input terminal of the inverter circuit INV2 receives the register value r_DebugLH_en from the control circuit 60. The output terminal of the inverter circuit INV2 is connected to the second input terminal of the NAND circuit NA1. The output terminal of the NAND circuit NA1 is connected to the gate of the pMOS transistor M7. The source (second main electrode) of the pMOS transistor M7 is connected to the power supply voltage node to which the voltage VDD is supplied. The drain (first main electrode) of the pMOS transistor M7 is connected to the control line sel[0]. The control line sel[0] is connected to multiple pixels 11 located in row 0.

[0036] In Figure 3, the symbols "x1," "x15," and "x16" shown near each transistor indicate the ratio of each transistor's drive capability to a reference value for drive capability. Drive capability is the magnitude of the ability of each transistor to supply current to the control line for transmitting control signals. Drive capability varies depending on the design of the transistor, such as its channel width.

[0037] The reference value for drive capability refers to the drive capability of a pMOS transistor and an nMOS transistor in an inverter circuit composed of a pMOS transistor and an nMOS transistor such that the duty cycles of the input pulse and the output pulse are the same. The channel width of the pMOS transistor at the reference value is 2 to 3 times the channel width of the nMOS transistor at the reference value. This is because the carrier mobility in the channel portion of the pMOS transistor is 1 / 3 to 1 / 2 of the carrier mobility in the channel portion of the nMOS transistor. This means that if the pMOS transistor and the nMOS transistor are the same size, the drive capability of the pMOS transistor is 1 / 3 to 1 / 2 of the drive capability of the nMOS transistor. In this way, by appropriately designing the channel width, etc., taking into account the difference in carrier mobility, it is possible to design the drive capability of each transistor to a predetermined value.

[0038] As shown in Figure 3, the driving capability of pMOS transistor M5 is 1x the reference value, i.e., it is the same as the reference value. The driving capability of nMOS transistor M6 is 16 times the reference value. The driving capability of pMOS transistor M7 is 15 times the reference value. Because the driving capabilities of pMOS transistor M5 and pMOS transistor M7 are different in this way, the amount of change in driving capability due to the switching of driving capabilities, as described later, can be made large.

[0039] When the register value r_DebugLH_en is low level (second mode), the input signal to the second input terminal of the NAND circuit NA1 is high level, so the NAND circuit NA1 functions as an inverter circuit that takes the first input terminal as its input. In this case, both pMOS transistors M5 and M7 operate in parallel, and their combined driving capability (second driving capability) becomes 16 times the reference value, resulting in a configuration that is balanced with the driving capability of the nMOS transistor M6.

[0040] In contrast, when the register value r_DebugLH_en is high (first mode), the input signal to the second input terminal of the NAND circuit NA1 is low, so the output signal of the NAND circuit NA1 is fixed at a high level. As a result, the pMOS transistor M7 is always off. In this case, the pMOS transistor M7 does not supply current to the control line sel[0], so the driving capability when the potential of the control line sel[0] changes from low to high is lower compared to when the register value r_DebugLH_en is low. More specifically, the driving capability at this time (first driving capability) is 1 times the reference value. Thus, the electrical connection and disconnection of the pMOS transistor M7 in the second buffer circuit and the control line sel[0] can be switched according to the level of the register value r_DebugLH_en, and this changes the driving capability.

[0041] Figures 4 and 5 are timing charts showing the operation of the photoelectric converter according to this embodiment. Figure 4 is the timing chart when the register value r_DebugLH_en is at a low level, and Figure 5 is the timing chart when the register value r_DebugLH_en is at a high level.

[0042] Figures 4 and 5 show the timing of the operation of the control signal Φselp[0] from row 0, the control signals Φselp[1], Φsel[1], ΦRes[1], and ΦTx[1] from row 1, and the control signal Φselp[2] from row 2. Here, the control signals Φselp[0], Φselp[1], and Φselp[2] represent the signals output from the vertical scanning circuit 20 to the control lines selp[0], selp[1], and selp[2], respectively. In Figures 4 and 5, "ADC" indicates the timing of AD conversion performed in the readout circuit 50. The boxes labeled "ADC[0]", "ADC[1]", and "ADC[2]" represent the AD conversion periods of the output signals from row 0, row 1, and row 2, respectively.

[0043] First, referring to Figure 4, we will explain the operation of the photoelectric converter when the register value r_DebugLH_en is at a low level.

[0044] At time t0, the control signal Φselp[0] changes from a low level to a high level. This turns on the selection transistor M4 of pixel 11 in row 0, thus selecting row 0.

[0045] During the period from time t0 to t1, the pixel signals from the 0th row of pixels 11 are output to the readout circuit 50 via the vertical signal lines VL[0], VL[1], and VL[2]. These pixel signals are held in the analog memory within the readout circuit 50.

[0046] At time t1, the control signal Φselp[0] changes from a high level to a low level. This turns off the selection transistor M4 of pixel 11 in row 0, thereby deselecting row 0.

[0047] At time t2, the AD conversion circuit in the readout circuit 50 starts the AD conversion of the pixel signals of the 0th row held in the analog memory.

[0048] At time t3, the control signal Φselp[1] changes from a low level to a high level. The buffer circuit group 30 buffers the control signal Φselp[1] and outputs it as Φsel[1], so Φsel[1] also changes from a low level to a high level. As a result, the selection transistor M4 of the first row pixel 11 turns on, and the first row is selected.

[0049] At time t3, the control signal ΦRes[1] is at a high level, and the reset transistor M2 is on. Also, the control signal ΦTx[1] is at a low level, and the transfer transistor M1 is off. Therefore, at time t3, the floating diffuser FD of the first row of pixels 11 is in a reset state.

[0050] At time t4, the AD conversion circuit in the readout circuit 50 completes the AD conversion of the pixel signals of the 0th row held in the analog memory. The converted digital data is held in the digital memory within the readout circuit 50.

[0051] At time t5, the control signal ΦRes[1] changes from a high level to a low level. This turns off the reset transistor M2, and the reset of the floating diffuser FD of pixel 11 is released, putting it into a floating state.

[0052] At time t6, the control signal ΦTx[1] changes from a low level to a high level. This turns on the transfer transistor M1. Then, at time t7, ΦTx[1] changes from a high level to a low level. This turns off the transfer transistor M1. These operations result in the transfer of the charge accumulated in the pixel 11 to the floating diffusion unit FD during the period from time t6 to time t7.

[0053] At time t8, the control signal ΦRes[1] changes from a low level to a high level, and the reset transistor M2 turns on. As a result, from time t8 onward, the potential of the floating diffuser FD is reset to a potential corresponding to the voltage VDD.

[0054] Furthermore, at time t8, the control signal Φselp[1] changes from a high level to a low level. The buffer circuit group 30 buffers the control signal Φselp[1] and outputs it as Φsel[1], so Φsel[1] also changes from a high level to a low level. As a result, the selection transistor M4 of the first row pixel 11 is turned off, and the selection of the first row is deselected.

[0055] During the period from time t7 to t8, the pixel signals from the first row's pixels 11 are output to the readout circuit 50 via the vertical signal lines VL[0], VL[1], and VL[2]. These pixel signals are held in the analog memory within the readout circuit 50. The subsequent steps are similar except for the difference in the row in which the operation is performed, so further explanation is omitted.

[0056] The timing chart in Figure 4 shows an example of operation when the register value r_DebugLH_en is at a low level, i.e., when the drive capability of the buffer circuit group 30 is relatively large. In contrast, referring to Figure 5, the operation of the photoelectric converter when the register value r_DebugLH_en is at a high level, i.e., when the drive capability of the buffer circuit group 30 is smaller than in the example in Figure 4, will be explained.

[0057] In Figure 5, everything is the same as in Figure 4 except for the level of the register value r_DebugLH_en and the control signal Φsel[1]. However, due to the low driving capability of the buffer circuit group 30, in Figure 5, the potential transition speed when the control signal Φsel[1] transitions from a low level to a high level is slow. Time t3 is the time when the AD conversion of the pixel signal of the 0th row is in progress. If the potential of the control signal Φsel[1] transitions rapidly during AD conversion, noise due to fluctuations in the power supply potential may affect the accuracy of the AD conversion. In contrast, in the example in Figure 5, the potential transition speed of the control signal Φsel[1] is reduced at time t3, so the fluctuations in the power supply potential are smaller. Therefore, by setting the register value r_DebugLH_en to a high level and reducing the driving capability of the buffer circuit group 30, the influence of fluctuations in the power supply potential on the accuracy of the AD conversion can be reduced.

[0058] On the other hand, if the potential transition speed when the control signal Φsel[1] transitions from a low level to a high level is reduced, the pixel signal readout speed may decrease. For this reason, when high-speed readout of pixel signals is required, it is desirable to set the register value r_DebugLH_en to a low level to increase the transition speed of the control signal Φsel[1]. On the other hand, when readout of pixel signals with low noise is required, it is desirable to set the register value r_DebugLH_en to a high level to decrease the transition speed of the control signal Φsel[1]. In this way, by changing the level of the register value r_DebugLH_en according to the performance required of the photoelectric converter, the driving capability of the buffer circuit group 30 can be switched to select an appropriate transition speed. Therefore, according to this embodiment, a photoelectric converter capable of switching the driving speed is provided.

[0059] Furthermore, the drive speed switching in this embodiment can be applied to applications other than those described above. One example of such an application is enhanced shipping testing of photoelectric converters. In shipping testing of photoelectric converters after manufacturing, it is desirable to test the photoelectric converter with the register value r_DebugLH_en set to a high level. In this case, because the drive capability is low and the drive speed is low, abnormalities in the control line sel can be detected more clearly. Examples of abnormalities in the control line sel that can be detected by this method include high-resistance shorts between the control line sel and other wiring, and high resistance due to the control line sel becoming too thin due to manufacturing variations. The effects of abnormalities that include such high-resistance parts become more pronounced as the drive capability decreases, so more accurate abnormality detection is possible by performing the test with a low drive capability. In this way, enhanced shipping testing can be performed by setting the register value r_DebugLH_en to a high level. Furthermore, by introducing such enhanced shipping testing, process abnormalities in the mass production process of photoelectric converters can be detected early. On the other hand, when a user uses the photoelectric converter after it has been shipped, setting the register value r_DebugLH_en to a low level can speed up the reading of pixel signals.

[0060] Another application of switching the drive speed is for analyzing the cause of defects in defective products that occur after shipment. For example, consider a case where a defect occurs in which the signal output from a specific row shows an abnormal value when light is shone on only a portion of the pixel array 10. In this case, if the defect becomes more pronounced when the register value r_DebugLH_en is set to a high level compared to when it is set to a low level, it can be determined that the cause of the defect is likely due to the control line sel.

[0061] The buffer circuit group 30 in this embodiment is configured to allow switching of the drive capability of the control line sel, but is not limited to this, and may also be configured to allow switching of the drive capability of the control line Res or the control line Tx. However, since the selection transistor M4 often occupies a small area on the substrate, and the wiring related to the selection transistor M4 is prone to abnormalities such as high-resistance short circuits, it is desirable to have a configuration in which the drive capability of the control line sel can be switched.

[0062] In this embodiment, the sources of both pMOS transistor M5 and pMOS transistor M7 are connected to a power supply voltage node to which voltage VDD is supplied. That is, the sources of pMOS transistor M5 and pMOS transistor M7 are electrically connected, and pMOS transistors M5 and M7 are not cascode connected. Therefore, pMOS transistors M5 and M7 can provide a large driving capability to the control line sel with a small footprint.

[0063] In this embodiment, an example is shown in which the drive capability can be switched between two values, 1x and 16x the reference value. However, the two drive capability values ​​are not limited to this example, and the effects of this embodiment can be obtained as long as the two values ​​are different from each other. Nevertheless, in order to obtain sufficient effects in applications such as noise reduction in AD conversion, enhanced shipping tests, and failure cause analysis, it is desirable that the ratio of the two drive capability values ​​be 10 times or more.

[0064] [Second Embodiment] The photoelectric converter according to this embodiment will now be described. Components similar to those in the first embodiment are denoted by the same reference numerals, and their descriptions may be omitted or simplified.

[0065] Figure 6(a) is a circuit diagram showing the configuration of the buffer circuit group 30 according to this embodiment. In Figure 6(a), the pixel array 10 is shown as a peripheral circuit of the buffer circuit group 30, and other elements are omitted. Also, in Figure 6(a), the configuration of the 0th row is mainly extracted and shown, and the other rows are omitted or simplified.

[0066] The buffer circuit group 30 includes a first buffer circuit 33, a second buffer circuit 32, and inverter circuits INV2 and INV3 as elements corresponding to the 0th row. The first buffer circuit 33 includes a pMOS transistor M5, an nMOS transistor M6, an inverter circuit INV1, and a NAND circuit NA2. The second buffer circuit 32 includes a pMOS transistor M7 and a NAND circuit NA1.

[0067] The control line selp[0] is connected to the input terminal of inverter circuit INV1 and the first input terminal of NAND circuit NA2. The output terminal of inverter circuit INV1 is connected to the gate of nMOS transistor M6. The input terminal of inverter circuit INV3 receives the register value r_DebugLH1_en from control circuit 60. The output terminal of inverter circuit INV3 is connected to the second input terminal of NAND circuit NA2. The output terminal of NAND circuit NA2 is connected to the gate of pMOS transistor M5. The source of pMOS transistor M5 is connected to the power supply voltage node to which voltage VDD is supplied. The source of nMOS transistor M6 is connected to the ground node. The drains of pMOS transistor M5 and nMOS transistor M6 are connected to the control line sel[0].

[0068] Furthermore, the control line selp[0] is also connected to the first input terminal of the NAND circuit NA1. The input terminal of the inverter circuit INV2 receives the register value r_DebugLH0_en from the control circuit 60. The output terminal of the inverter circuit INV2 is connected to the second input terminal of the NAND circuit NA1. The output terminal of the NAND circuit NA1 is connected to the gate of the pMOS transistor M7. The source of the pMOS transistor M7 is connected to the power supply voltage node to which the voltage VDD is supplied. The drain of the pMOS transistor M7 is connected to the control line sel[0]. The control line sel[0] is connected to multiple pixels 11 located in row 0.

[0069] As shown in Figure 6(a), the driving capability of pMOS transistor M5 is 1 times the reference value, i.e., it is the same as the reference value. The driving capability of nMOS transistor M6 is 16 times the reference value. The driving capability of pMOS transistor M7 is 15 times the reference value.

[0070] Figure 6(b) is a table showing the operating settings of the buffer circuit group 30 in this embodiment. Figure 6(b) shows the levels of the register values ​​r_DebugLH0_en and r_DebugLH1_en and the drive capability for three types of settings S11, S12, and S13. In the columns for register values ​​r_DebugLH0_en and r_DebugLH1_en, "0" indicates a low level, and "1" indicates a high level.

[0071] The setting S11 shown in Figure 6(b) is the default setting, where both register values ​​r_DebugLH0_en and r_DebugLH1_en are at a low level. Since the input signals to the second input terminals of NAND circuits NA1 and NA2 are both at a high level, NAND circuits NA1 and NA2 both function as inverter circuits that take the first input terminal as their input. In this case, both pMOS transistors M5 and M7 operate in parallel, and their combined driving capability becomes 16 times the reference value.

[0072] The setting S12 shown in Figure 6(b) is a setting where the drive capability is slightly lower than that of setting S11. In this case, the register value r_DebugLH0_en is low level, and the register value r_DebugLH1_en is high level. Since the input signal to the second input terminal of NAND circuit NA1 is high level, NAND circuit NA1 functions as an inverter circuit that takes the first input terminal as its input. Since the input signal to the second input terminal of NAND circuit NA2 is low level, the output signal of NAND circuit NA2 is fixed at a high level. In this case, the drive capability becomes 15 times the reference value because only the pMOS transistor M7 is operating.

[0073] The setting S13 shown in Figure 6(b) is the setting with the smallest drive capability. In this case, the register value r_DebugLH0_en is high level, and the register value r_DebugLH1_en is low level. Since the input signal to the second input terminal of NAND circuit NA1 is low level, the output signal of NAND circuit NA1 is fixed at a high level. Since the input signal to the second input terminal of NAND circuit NA2 is high level, NAND circuit NA2 functions as an inverter circuit that takes the first input terminal as its input. In this case, only the pMOS transistor M5 operates, and the drive capability becomes 1 times the reference value.

[0074] As described above, in this embodiment, three types of drive capabilities can be selected by combining the register values ​​r_DebugLH0_en and r_DebugLH1_en. Therefore, according to this embodiment, a photoelectric converter is provided in which the drive speed can be switched in three stages.

[0075] [Third Embodiment] The photoelectric converter according to this embodiment will now be described. Components similar to those in the first or second embodiment are denoted by the same reference numerals, and their descriptions may be omitted or simplified.

[0076] Figure 7(a) is a circuit diagram showing the configuration of the buffer circuit group 30 according to this embodiment. In Figure 7(a), the pixel array 10 is shown as a peripheral circuit of the buffer circuit group 30, and other elements are omitted. Also, in Figure 7(a), the configuration of the 0th row is mainly extracted and shown, and the other rows are omitted or simplified.

[0077] The buffer circuit group 30 includes a first buffer circuit 33, a second buffer circuit 32, a third buffer circuit 34, and inverter circuits INV2, INV3, and INV4 as elements corresponding to the 0th row. The configurations of the first buffer circuit 33 and the second buffer circuit 32 are the same as in the second embodiment, so their description is omitted. The inverter circuit INV2 is input with the register value r_DebugLH0_en, as in the second embodiment. The inverter circuit INV3 is input with the register value r_DebugLH2_en, unlike in the second embodiment.

[0078] The third buffer circuit 34 includes a pMOS transistor M8 and a NAND circuit NA3. The control line selp[0] is connected to the first input terminal of the NAND circuit NA3. The input terminal of the inverter circuit INV4 receives the register value r_DebugLH1_en from the control circuit 60. The output terminal of the inverter circuit INV4 is connected to the second input terminal of the NAND circuit NA3. The output terminal of the NAND circuit NA3 is connected to the gate of the pMOS transistor M8. The source of the pMOS transistor M8 is connected to the power supply voltage node to which the voltage VDD is supplied. The drain of the pMOS transistor M8 is connected to the control line sel[0].

[0079] As shown in Figure 7(a), the driving capability of pMOS transistor M5 is 1x the reference value, i.e., it is the same as the reference value. The driving capability of nMOS transistor M6 is 32x the reference value. The driving capability of pMOS transistor M7 is 24x the reference value. The driving capability of pMOS transistor M8 is 7x the reference value.

[0080] Figure 7(b) is a table showing the operating settings of the buffer circuit group 30 in this embodiment. Figure 7(b) shows the levels of the register values ​​r_DebugLH0_en, r_DebugLH1_en, and r_DebugLH2_en and their driving capabilities for the seven types of settings from settings S21 to S27. In the columns for register values ​​r_DebugLH0_en, r_DebugLH1_en, and r_DebugLH2_en, "0" indicates a low level, and "1" indicates a high level.

[0081] The operation in each setting is generally the same as that described in the second embodiment, so the explanation will be omitted. In the seven settings from S21 to S27, the driving capacity is 32 times, 31 times, 25 times, 24 times, 8 times, 7 times, and 1 time the reference value, respectively.

[0082] As described above, in this embodiment, seven types of drive capabilities can be selected by combining the register values ​​r_DebugLH0_en, r_DebugLH1_en, and r_DebugLH2_en. Therefore, according to this embodiment, a photoelectric converter is provided in which the drive speed can be switched in seven stages.

[0083] [Fourth Embodiment] The photoelectric converter according to this embodiment will now be described. Components similar to those in the first to third embodiments are denoted by the same reference numerals, and their descriptions may be omitted or simplified.

[0084] Figure 8(a) is a circuit diagram showing the configuration of the buffer circuit group 30 according to this embodiment. In Figure 8(a), the pixel array 10 is shown as a peripheral circuit of the buffer circuit group 30, and other elements are omitted. Also, in Figure 8(a), the configuration of the 0th row is mainly extracted and shown, and the other rows are omitted or simplified.

[0085] The buffer circuit group 30 includes a first buffer circuit 31, a second buffer circuit 35, and an inverter circuit INV2 as elements corresponding to the 0th row. The configuration of the first buffer circuit 31 is the same as in the first embodiment, so its description is omitted.

[0086] The second buffer circuit 35 includes a pMOS transistor M7, an nMOS transistor M9 (the fourth MOS transistor), a NAND circuit NA1, and a NOR circuit NO1. The control line selp[0] is connected to the first input terminal of the NAND circuit NA1 and the first input terminal of the NOR circuit NO1. The input terminal of the inverter circuit INV2 receives the register value r_DebugLH_en from the control circuit 60. The output terminal of the inverter circuit INV2 is connected to the second input terminal of the NAND circuit NA1. The output terminal of the NAND circuit NA1 is connected to the gate of the pMOS transistor M7. The source of the pMOS transistor M7 is connected to the power supply voltage node to which the voltage VDD is supplied. The second input terminal of the NOR circuit NO1 receives the register value r_DebugHL_en from the control circuit 60. The output terminal of the NOR circuit NO1 is connected to the gate of the nMOS transistor M9. The drain (first main electrode) of the pMOS transistor M7 and the drain of the nMOS transistor M9 are connected to the control line sel[0]. The source of the nMOS transistor M9 is connected to the ground node.

[0087] Figure 8(b) is a table showing the operating settings of the buffer circuit group 30 in this embodiment. Figure 8(b) shows the levels of the register values ​​r_DebugLH_en and r_DebugHL_en and the potential transition speed for the four types of settings S31 to S34. In the columns for register values ​​r_DebugLH_en and r_DebugHL_en, "0" indicates a low level, and "1" indicates a high level. The "L→H" column shows the potential transition speed when the control signal Φsel transitions from a low level to a high level. The "H→L" column shows the potential transition speed when the potential of the control signal Φsel transitions from a high level to a low level.

[0088] The setting S31 shown in Figure 8(b) is the default setting, where both register values ​​r_DebugLH_en and r_DebugHL_en are at a low level. Since the input signal to the second input terminal of NAND circuit NA1 is high level, NAND circuit NA1 functions as an inverter circuit that takes the first input terminal as its input. Since the input signal to the second input terminal of NOR circuit NO1 is low level, NOR circuit NO1 functions as an inverter circuit that takes the first input terminal as its input. In this case, because both pMOS transistors M5 and M7 operate in parallel, the potential transition speed when the potential of the control signal Φsel transitions from a low level to a high level is fast. Also, because both nMOS transistors M6 and M9 operate in parallel, the potential transition speed when the potential of the control signal Φsel transitions from a high level to a low level is fast.

[0089] The setting S32 shown in Figure 8(b) is a setting that slows down the transition speed from low level to high level. In this case, the register value r_DebugLH_en is high level and the register value r_DebugHL_en is low level. Since the input signal to the second input terminal of NAND circuit NA1 is low level, the output signal of NAND circuit NA1 is fixed at high level. Since the input signal to the second input terminal of NOR circuit NO1 is low level, NOR circuit NO1 functions as an inverter circuit that takes the first input terminal as its input. In this case, since the pMOS transistor M7 does not contribute to the driving capability, the transition speed of the potential when the potential of the control signal Φsel transitions from low level to high level is slow. On the other hand, because both nMOS transistors M6 and M9 operate in parallel, the transition speed of the potential when the potential of the control signal Φsel transitions from high level to low level is fast.

[0090] The setting S33 shown in Figure 8(b) is a setting that slows down the transition speed from high level to low level. In this case, the register value r_DebugLH_en is low level and the register value r_DebugHL_en is high level. Since the input signal to the second input terminal of NAND circuit NA1 is high level, NAND circuit NA1 functions as an inverter circuit that takes the first input terminal as its input. Since the input signal to the second input terminal of NOR circuit NO1 is high level, the output signal of NOR circuit NO1 is fixed at a low level. In this case, because both pMOS transistors M5 and M7 operate in parallel, the transition speed of the potential when the potential of the control signal Φsel transitions from low level to high level is fast. On the other hand, since nMOS transistor M9 does not contribute to the driving capability, the transition speed of the potential when the potential of the control signal Φsel transitions from high level to low level is slow.

[0091] The setting S34 shown in Figure 8(b) slows down both the transition speed from low level to high level and the transition speed from high level to low level. In this case, both register values ​​r_DebugLH_en and r_DebugHL_en are at a high level. Since the input signal to the second input terminal of NAND circuit NA1 is low level, the output signal of NAND circuit NA1 is fixed at a high level. Since the input signal to the second input terminal of NOR circuit NO1 is high level, the output signal of NOR circuit NO1 is fixed at a low level. In this case, neither pMOS transistor M7 nor nMOS transistor M9 contributes to the driving capability, so the potential transition speed of the control signal Φsel is slow in both the case of transitioning from low level to high level and from high level to low level.

[0092] As described above, in this embodiment, the pMOS transistor M7 and the nMOS transistor M9 can be controlled individually by the combination of register values ​​r_DebugLH_en and r_DebugHL_en. Therefore, according to this embodiment, a photoelectric converter is provided that can switch not only the transition speed when the potential of the control signal Φsel transitions from a low level to a high level, but also the transition speed when it transitions from a high level to a low level.

[0093] [Fifth Embodiment] The photoelectric converter according to this embodiment will now be described. Components similar to those in the first to fourth embodiments are denoted by the same reference numerals, and their descriptions may be omitted or simplified.

[0094] The photoelectric converter of this embodiment has two buffer circuit groups 30a and 30b. Figure 9(a) is a circuit diagram showing the configuration of the buffer circuit groups 30a and 30b according to this embodiment. In Figure 9(a), the pixel array 10 is shown as a peripheral circuit to the buffer circuit groups 30a and 30b, and other elements are omitted. Also, in Figure 9(a), the configuration of the 0th row is mainly extracted and shown, and other rows are omitted or simplified.

[0095] In this embodiment, buffer circuit group 30a is located to the left of the pixel array 10, and buffer circuit group 30b is located to the right of the pixel array 10. In other words, buffer circuit groups 30a and 30b are located on both sides of the pixel array 10. Buffer circuit group 30a has a first buffer circuit 31, and buffer circuit group 30b has a second buffer circuit 35 and an inverter circuit INV2. The circuit configuration and connection relationships of the first buffer circuit 31, the second buffer circuit 35, and the inverter circuit INV2 are the same as in the fourth embodiment, except that they are located on both sides of the pixel array 10, so a detailed explanation is omitted.

[0096] Figure 9(b) is a table showing the operation settings of the buffer circuit groups 30a and 30b in this embodiment. The contents of Figure 9(b) are the same as those of Figure 8(b), so no explanation is given. According to this embodiment, similar to the fourth embodiment, a photoelectric converter is provided that can switch not only the transition speed when the potential of the control signal Φsel transitions from a low level to a high level, but also the transition speed when it transitions from a high level to a low level.

[0097] Furthermore, in the photoelectric converter of this embodiment, the two buffer circuit groups 30a and 30b are separated on both sides of the pixel array 10, which may allow for the detection of abnormalities during shipping tests. For example, if an abnormality is observed to the left of a certain pixel 11 in the pixel array in any of the settings S32, S33, or S34 in Figure 9(b), it is highly likely that an abnormality such as increased resistance has occurred near that pixel. In this way, the photoelectric converter of this embodiment can make the detection of abnormalities during shipping tests more effective.

[0098] [Sixth Embodiment] This embodiment describes an example in which the configuration of the buffer circuit group 30 described in the first embodiment is applied to a display device. The display device is typically an organic light-emitting display device using an organic light-emitting diode (OLED) containing a light-emitting organic material. However, the display device may also use an inorganic light-emitting diode. More generally, the display device is sometimes called a semiconductor device.

[0099] Figure 10 shows the configuration of the buffer circuit group 30 in the display device of the sixth embodiment. In Figure 10, the same reference numerals are used for components similar to those in Figure 3, and the descriptions of these components may be omitted or simplified.

[0100] The display device includes a pixel array 16, a vertical scanning circuit 20, a buffer circuit group 30, and a writing circuit 56. The display device may also include a control circuit (not shown) that controls the vertical scanning circuit 20, the buffer circuit group 30, and the writing circuit 56. Similar to the first embodiment, the buffer circuit group 30 includes a plurality of first buffer circuits 31, a plurality of second buffer circuits 32, and an inverter circuit INV2, as shown in Figure 3. The configuration of the vertical scanning circuit 20 and the buffer circuit group 30 is the same as in Figure 3, so a detailed explanation is omitted. The circuits constituting the display device can be formed on one or more semiconductor substrates.

[0101] The pixel array 16 has multiple pixels 17 arranged across multiple rows and multiple columns. Each of the multiple pixels 17 emits light with a brightness corresponding to the applied current. A color filter may be placed on the pixels 17. In Figure 10, only three rows and three columns of the multiple pixels 17 are shown, but in reality, there may be thousands of rows and thousands of columns.

[0102] The writing circuit 56 is a circuit that outputs a pixel signal corresponding to the brightness of each pixel to each of the multiple pixels 17. The writing circuit 56 has a column circuit corresponding to each column. The column circuit includes a digital-to-analog conversion circuit, a column drive circuit, etc.

[0103] Figure 11 is a circuit diagram of a pixel 17 according to this embodiment. Figure 11 shows one pixel 17 extracted from the pixel array 16. The pixel 17 shown in Figure 11 is assumed to be the pixel 17 of the 0th row and 0th column. Furthermore, all transistors in the pixel 17 are assumed to be pMOS transistors, but they may also be nMOS transistors.

[0104] Pixel 17 includes a light-emitting element LD, a drive transistor M11, a selection transistor M12, switching transistors M13 and M14, and capacitive elements C1 and C2. The light-emitting element LD is a light-emitting diode such as an OLED. The cathode of the light-emitting element LD is connected to the ground node, and the anode of the light-emitting element LD is connected to the drain of the drive transistor M11 and the source of the switching transistor M14. The drain of the switching transistor M14 is connected to the ground node.

[0105] The gate of the drive transistor M11 is connected to the drain of the selection transistor M12 and the first terminal of the capacitance element C1. The source of the selection transistor M12 is connected to the vertical signal line VL. The source of the drive transistor M11 is connected to the drain of the switching transistor M13, the second terminal of the capacitance element C1, and the first terminal of the capacitance element C2. The second terminal of the capacitance element C2 and the source of the switching transistor M13 are connected to the power supply voltage node to which voltage VDD is supplied.

[0106] Note that the names of the source and drain of a MOS transistor may differ depending on the transistor's conductivity type or the function being considered. Some or all of the source and drain names used in this embodiment may also be referred to by their reversed names.

[0107] The control line CL[0] includes the control line sel[0] connected to the gate of the selection transistor M12, the control line sc2[0] connected to the gate of the switching transistor M13, and the control line sc1[0] connected to the gate of the switching transistor M14. Control signals are supplied to the control lines sel[0], sc1[0], and sc2[0] from the vertical scanning circuit 20 via the buffer circuit group 30.

[0108] The drive transistor M11 supplies the current to be applied to the light-emitting LD. A signal to switch the light emission of the light-emitting LD is input to the gate of the switching transistor M13 from the control line sc2[0].

[0109] A control signal is input to the gate of the selection transistor M12 from the control line sel[0] to select the row on which the image signal will be written. This operation causes an image signal corresponding to the brightness information to be sampled from the vertical signal line VL[0] to the gate electrode of the drive transistor M11.

[0110] During the calibration period, a signal controlling the voltage of the anode of the light-emitting LD is input to the gate of the switching transistor M14 from the control line sc1[0]. During the calibration period, a reference voltage is sampled from the vertical signal line VL[0] to the gate electrode of the drive transistor M11. This makes it possible to correct the threshold voltage variation of each drive transistor M11 of multiple pixels 17, and to reduce the brightness variation between multiple pixels 17 caused by threshold voltage variation.

[0111] The display device of this embodiment, like the first embodiment, has a group of buffer circuits 30 that can switch the drive capability. Therefore, this embodiment provides a display device in which the drive speed can be switched. Switching the drive speed can be used for at least one of the applications described in the first embodiment. For example, as described in the first embodiment, an enhanced shipping test can be performed by setting the drive speed to a low speed during the shipping test of the display device, and process abnormalities in the mass production process of the display device can be detected early.

[0112] [Seventh Embodiment] The photoelectric conversion device in the above-described embodiment is applicable to various devices. Examples of such devices include digital still cameras, digital camcorders, camera heads, photocopiers, fax machines, mobile phones, in-vehicle cameras, observation satellites, and surveillance cameras. Figure 12 shows a block diagram of a digital still camera as an example of such a device.

[0113] The device 70 shown in Figure 12 includes a barrier 706, a lens 702, an aperture 704, and an imaging device 700 (an example of a photoelectric converter). The device 70 further includes a signal processing unit (processing unit) 708, a timing generation unit 720, an overall control / calculation unit 718 (control device), a memory unit 710 (storage device), a recording medium control I / F unit 716, a recording medium 714, and an external I / F unit 712. At least one of the barrier 706, lens 702, and aperture 704 is an optical device corresponding to the device. The barrier 706 protects the lens 702, and the lens 702 forms an optical image of the subject on the imaging device 700. The aperture 704 varies the amount of light passing through the lens 702. The imaging device 700 is configured as in the above-described embodiment and converts the optical image formed by the lens 702 into image data (image signal). The signal processing unit 708 performs various corrections, data compression, etc., on the imaging data output from the imaging device 700. The timing generation unit 720 outputs various timing signals to the imaging device 700 and the signal processing unit 708. The overall control / calculation unit 718 controls the entire digital still camera, and the memory unit 710 temporarily stores image data. The recording medium control I / F unit 716 is an interface for recording or reading image data to or from the recording medium 714, which is a removable recording medium such as a semiconductor memory for recording or reading imaging data. The external I / F unit 712 is an interface for communicating with an external computer or the like. Timing signals and the like may be input from outside the device. Furthermore, the device 70 may also include a display device (monitor, electronic viewfinder, etc.) that displays information obtained from the photoelectric converter. The device includes at least a photoelectric converter. Furthermore, the device 70 includes at least one of an optical device, a control device, a processing device, a display device, a storage device, and a mechanical device that operates based on information obtained from the photoelectric converter. The mechanical device is a movable part (for example, a robot arm) that operates in response to signals from the photoelectric converter.

[0114] Each pixel may include multiple photoelectric conversion units (a first photoelectric conversion unit and a second photoelectric conversion unit). The signal processing unit 708 may be configured to process a pixel signal based on the charge generated by the first photoelectric conversion unit and a pixel signal based on the charge generated by the second photoelectric conversion unit to acquire distance information from the imaging device 700 to the subject.

[0115] [Eighth Embodiment] Figures 13(a) and 13(b) are block diagrams of the equipment related to the in-vehicle camera in this embodiment. Equipment 80 includes an imaging device 800 (an example of a photoelectric converter) as described above, and a signal processing device (processing device) that processes signals from the imaging device 800. Equipment 80 includes an image processing unit 801 that performs image processing on a plurality of image data acquired by the imaging device 800, and a parallax calculation unit 802 that calculates parallax (phase difference of parallax images) from a plurality of image data acquired by Equipment 80. Equipment 80 also includes a distance measurement unit 803 that calculates the distance to an object based on the calculated parallax, and a collision determination unit 804 that determines whether or not there is a possibility of collision based on the calculated distance. Here, the parallax calculation unit 802 and the distance measurement unit 803 are examples of distance information acquisition means that acquire distance information to an object. That is, distance information is information related to parallax, defocus amount, distance to an object, etc. The collision determination unit 804 may use any of this distance information to determine the possibility of collision. The means for acquiring distance information may be implemented by specially designed hardware, or by a software module. It may also be implemented by an FPGA (Field Programmable Gate Array), an ASIC (Application Specific Integrated Circuit), or a combination thereof.

[0116] Device 80 is connected to a vehicle information acquisition device 810 and can acquire vehicle information such as vehicle speed, yaw rate, and steering angle. Device 80 is also connected to a control ECU 820, which is a control device that outputs a control signal to generate braking force on the vehicle based on the collision determination result of the collision determination unit 804. Furthermore, device 80 is connected to a warning device 830 that issues a warning to the driver based on the collision determination result of the collision determination unit 804. For example, if the collision determination result of the collision determination unit 804 indicates a high probability of collision, the control ECU 820 performs vehicle control to avoid a collision or mitigate damage by applying the brakes, releasing the accelerator, or suppressing engine output. The warning device 830 warns the user by sounding an alarm, displaying warning information on a screen such as a car navigation system, or vibrating the seatbelt or steering wheel. As described above, device 80 functions as a control means that controls the actions that control the vehicle.

[0117] In this embodiment, the equipment 80 images the area around the vehicle, for example, in front of or behind it. Figure 13(b) shows the equipment when imaging the area in front of the vehicle (imaging range 850). The vehicle information acquisition device 810, acting as an imaging control means, sends instructions to the equipment 80 or imaging device 800 to perform the imaging operation. This configuration allows for further improvement of the accuracy of distance measurement.

[0118] The above example described controlling a vehicle to avoid collisions with other vehicles, but it can also be applied to control systems that automatically follow other vehicles, or control systems that automatically stay within their lane. Furthermore, the equipment is not limited to vehicles such as automobiles, but can be applied to mobile objects (mobile devices) such as ships, aircraft, satellites, industrial robots, and consumer robots. In addition, it can be applied not only to mobile objects, but also to a wide range of devices that utilize object recognition or biometric recognition, such as intelligent transportation systems (ITS) and surveillance systems.

[0119] [Modified Embodiment] The present invention is not limited to the embodiments described above and can be modified in various ways. For example, an example in which a part of the configuration of one embodiment is added to another embodiment, or in which a part of the configuration of another embodiment is replaced, is also an embodiment of the present invention.

[0120] The disclosures in this specification include the complements of the concepts described herein. That is, if this specification contains a statement such as "A is B" (A=B), the specification shall be deemed to disclose or imply "A is not B" (A≠B) even if a statement such as "A is not B" is omitted. This is because the statement "A is B" presupposes that the case where "A is not B" is being considered.

[0121] The present invention can also be realized by supplying a program that implements one or more of the functions of the above-described embodiments to a system or device via a network or storage medium, and by a process in which one or more processors in the computer of that system or device read and execute the program. It can also be realized by a circuit (e.g., an ASIC) that implements one or more functions.

[0122] It should be noted that the embodiments described above are merely examples of how the present invention can be implemented, and the technical scope of the present invention should not be interpreted as being limited by them. In other words, the present invention can be implemented in various ways without departing from its technical concept or its main features. [Explanation of Symbols]

[0123] 10-pixel array 11 pixels 20 Vertical scanning circuit 30 Buffer Circuit Groups 31 First Buffer Circuit 32 Second Buffer Circuit 50 Readout Circuit sel control line

Claims

1. A first buffer circuit and a second buffer circuit each output a control signal to a single control line based on the input from the signal output circuit, An element that receives the control signal transmitted via the aforementioned control line, It has, The second buffer circuit is capable of switching between electrical connection and disconnection with the one control line. The first mode, in which the first buffer circuit supplies current to the one control line with a first drive capability, and the second mode, in which both the first buffer circuit and the second buffer circuit are connected to the one control line, thereby supplying current to the one control line with a second drive capability greater than the first drive capability, are switchable. The driving capabilities of the first buffer circuit and the driving capabilities of the second buffer circuit are different from each other. A semiconductor device characterized by the following features.

2. The first buffer circuit is capable of switching between electrical connection and disconnection with the one control line. The semiconductor device according to feature 1.

3. The second driving capacity is 10 times or more the first driving capacity. The semiconductor device according to claim 1 or 2.

4. In the shipment test of the semiconductor device, operation in the first mode is performed. The semiconductor device according to any one of claims 1 to 3.

5. The second buffer circuit includes a first MOS transistor of the first conductivity type, The first main electrode of the first MOS transistor is electrically connected to the one control line. A semiconductor device according to any one of claims 1 to 4.

6. A first buffer circuit and a second buffer circuit, each outputting a control signal to a single control line based on an input from a signal output circuit, An element that receives the control signal transmitted via the aforementioned control line, It has, The second buffer circuit is capable of switching between electrical connection and disconnection with the one control line. The first mode, in which the first buffer circuit supplies current to the one control line with a first drive capability, and the second mode, in which both the first buffer circuit and the second buffer circuit are connected to the one control line, thereby supplying current to the one control line with a second drive capability greater than the first drive capability, are switchable. The second buffer circuit includes a first MOS transistor of the first conductivity type, The first main electrode of the first MOS transistor is electrically connected to the one control line. A semiconductor device characterized by the following features.

7. The first buffer circuit includes a second MOS transistor of the first conductivity type and a third MOS transistor of the second conductivity type. The first main electrode of the second MOS transistor and the first main electrode of the third MOS transistor are electrically connected to the one control line. The semiconductor device according to claim 5 or 6.

8. The second main electrode of the first MOS transistor and the second main electrode of the second MOS transistor are electrically connected. The semiconductor device according to feature 7.

9. The second main electrode of the first MOS transistor and the second main electrode of the second MOS transistor are connected to a wiring that has a power supply voltage. The semiconductor device according to feature 8.

10. The second buffer circuit includes a fourth MOS transistor of the second conductivity type, The first main electrode of the fourth MOS transistor is electrically connected to the one control line. The semiconductor device according to any one of claims 5 to 9.

11. The system further includes a third buffer circuit that outputs the control signal to one of the control lines based on the input from the signal output circuit. The third buffer circuit is capable of switching between electrical connection and disconnection with the one control line. The semiconductor device according to any one of claims 1 to 10.

12. Having a plurality of the aforementioned elements, The aforementioned control line is connected in common to multiple of the aforementioned elements. A semiconductor device according to any one of claims 1 to 11.

13. The first buffer circuit and the second buffer circuit are arranged so as to sandwich a plurality of the elements between them. The semiconductor device according to feature 12.

14. A first buffer circuit and a second buffer circuit, each outputting a control signal to a single control line based on an input from a signal output circuit, An element that receives the control signal transmitted via the aforementioned control line, It has, The second buffer circuit is capable of switching between electrical connection and disconnection with the one control line. The first mode, in which the first buffer circuit supplies current to the one control line with a first drive capability, and the second mode, in which both the first buffer circuit and the second buffer circuit are connected to the one control line, thereby supplying current to the one control line with a second drive capability greater than the first drive capability, are switchable. Having a plurality of the aforementioned elements, The aforementioned control line is connected in common to multiple elements. The first buffer circuit and the second buffer circuit are arranged so as to sandwich a plurality of the elements between them. A semiconductor device characterized by the following features.

15. A photodetector comprising a semiconductor device according to any one of claims 1 to 14, The aforementioned element includes a photodiode. A light detection device characterized by the following features.

16. The light detection device according to claim 15, An optical device corresponding to the aforementioned light detection device, Control device for controlling the aforementioned light detection device, A processing device that processes the signal output from the aforementioned light detection device, A display device that displays information obtained by the aforementioned light detection device. A storage device for storing information obtained by the aforementioned light detection device, and The apparatus is characterized by comprising at least one of the following: a mechanical device that operates based on information obtained by the aforementioned light detection device.

17. The processing device processes the image signals generated by each of the multiple photoelectric conversion units and acquires distance information from the light detection device to the subject. The apparatus according to feature 16.

18. A display device comprising a semiconductor device according to any one of claims 1 to 14, The element includes a light-emitting diode. A display device characterized by the following features.

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