Display devices and electronic equipment

Abstract

Provided is a display device with low chromaticity change and high controllability of grayscale. The display device is able to turn on and turn off a light-emitting device with PAM and PWM control (pulse width control accompanying change of amplitude). This display device writes the same input signals (data potentials) to a first node and a second node and generates pulse signals in accordance with the potential of the second node while turning on the light-emitting device in accordance with the potential of the first node. The potential of the first node can be reset in response to the generated pulse signals. Therefore, the light-emitting device can be turned on at a desired period with a desired light-emission intensity.

Description

[Technical Field]

[0001] One aspect of the present invention relates to a display device.

[0002] Furthermore, one aspect of the present invention is not limited to the above-mentioned technical field. The technical field of one aspect of the invention disclosed herein relates to a product, method, or method of manufacture. Alternatively, one aspect of the present invention relates to a process, machine, manufacture, or composition of matter. More specifically, examples of the technical field of one aspect of the present invention disclosed herein include semiconductor devices, display devices, liquid crystal display devices, light-emitting devices, lighting devices, energy storage devices, memory devices, imaging devices, methods of operating them, or methods of manufacturing them.

[0003] In this specification, the term "semiconductor device" refers to any device that can function by utilizing semiconductor properties. Transistors and semiconductor circuits are examples of semiconductor devices. Furthermore, memory devices, display devices, imaging devices, and electronic devices may also contain semiconductor devices. [Background technology]

[0004] Display devices and lighting devices equipped with micro light-emitting diodes (hereinafter referred to as micro LEDs (LEDs: Light Emitting Diodes)) have been proposed (for example, Patent Document 1). Display devices equipped with micro LEDs are capable of high-brightness display, are highly reliable, and are promising as next-generation displays.

[0005] Furthermore, the technology of constructing transistors using metal oxides formed on a substrate is attracting attention. For example, the technology of using transistors made of zinc oxide or In-Ga-Zn oxide as switching elements for pixels in display devices is disclosed in Patent Documents 2 and 3. [Prior art documents] [Patent Documents]

[0006] [Patent Document 1] U.S. Patent Application Publication No. 2014 / 0367705 [Patent Document 2] Japanese Patent Publication No. 2007-123861 [Patent Document 3] Japanese Patent Publication No. 2007-96055 [Overview of the Initiative] [Problems that the invention aims to solve]

[0007] In display devices using light-emitting devices (also called light-emitting elements), the brightness can be changed by controlling the current flowing through the light-emitting device. However, LEDs, one type of light-emitting device, have the characteristic that their chromaticity changes easily depending on the current density.

[0008] Therefore, controlling the brightness of an LED using pulse amplitude modulation (PAM) can result in poor color reproduction. Consequently, it is preferable to use pulse width modulation (PWM) control, which controls brightness by the duty cycle, to drive the LED. PWM control allows for a constant current density, enabling brightness adjustment without causing chromaticity shifts.

[0009] On the other hand, due to the transistors driving the LEDs and the response characteristics of the LEDs themselves, there is a lower limit to the duty cycle that can be stably controlled. Therefore, PWM control of LEDs has the problem of being difficult to control at lower grayscale levels where the duty cycle becomes smaller.

[0010] Therefore, one aspect of the present invention aims to provide a display device with small chromaticity changes and high gradation controllability. Alternatively, one aspect aims to provide a display device having a pixel circuit that generates pulse signals. Alternatively, one aspect aims to provide a display device having a pixel circuit capable of PAM control and PWM control. Alternatively, one aspect aims to provide a display device with excellent display characteristics. Alternatively, one aspect aims to provide a narrow-bezel display device.

[0011] Alternatively, one of the objectives is to provide a low-power display device. Alternatively, one of the objectives is to provide a highly reliable display device. Alternatively, one of the objectives is to provide a novel display device, etc. Alternatively, one of the objectives is to provide an operating method for the above-mentioned display device. Alternatively, one of the objectives is to provide a novel semiconductor device, etc.

[0012] Furthermore, the description of these problems does not preclude the existence of other problems. Moreover, one aspect of the present invention does not need to solve all of these problems. Other problems will naturally become apparent from the description in the specification, drawings, and claims, and it is possible to extract other problems from the description in the specification, drawings, and claims. [Means for solving the problem]

[0013] One aspect of the present invention relates to a display device having a pixel circuit capable of PAM control and PWM control.

[0014] A first aspect of the present invention is a display device having a pulse signal generation unit, a light-emitting device, a first node, and a second node in a pixel, wherein the first node is electrically connected to the input of the pulse signal generation unit, the second node is electrically connected to the output of the pulse signal generation unit, the first node and the second node are electrically connected via a transistor, the pixel causes the light-emitting device to emit light in response to a data potential input to the second node, the pulse signal generation unit generates a pulse signal in response to a data potential input to the first node, and the pixel resets the potential of the second node and turns off the light-emitting device in response to the pulse signal.

[0015] A second aspect of the present invention is a display device having a pulse signal generation unit, a first node, a second node, a first transistor, a second transistor, a third transistor, a first capacitor, and a light-emitting device in a pixel, wherein one source or drain of the first transistor, one source or drain of the second transistor, and the input of the pulse signal generation unit are electrically connected to the first node, the other source or drain of the second transistor, the gate of the third transistor, one electrode of the first capacitor, and the output of the pulse signal generation unit are electrically connected to the second node, one source or drain of the second transistor is electrically connected to one electrode of the light-emitting device, and the other source or drain of the third transistor is electrically connected to the other electrode of the first capacitor.

[0016] The pulse signal generation unit includes fourth to ninth transistors and a second capacitor. The fourth transistor has a first gate and a second gate. The first gate of the fourth transistor and one of the source or drain of the fifth transistor are electrically connected to the first node. One of the source or drain of the fourth transistor is electrically connected to the gate of the sixth transistor and one of the source or drain of the seventh transistor. The second gate of the fourth transistor is electrically connected to one of the source or drain of the eighth transistor and one electrode of the second capacitor. The other electrode of the second capacitor is electrically connected to one of the source or drain of the ninth transistor. The other of the source or drain of the ninth transistor is electrically connected to the other of the source or drain of the fourth transistor. One of the source or drain of the sixth transistor can be electrically connected to the second node.

[0017] The source or the other of the drain of the fourth transistor can be input to the signal potential of a ramp waveform.

[0018] The first, second, fourth, fifth, eighth, and ninth transistors may each be n-channel transistors, while the third, sixth, and seventh transistors may each be p-channel transistors.

[0019] It is preferable that n-channel transistors have a metal oxide in the channel formation region, and p-channel transistors have silicon in the channel formation region.

[0020] In a second aspect of the present invention, the pixel causes a light-emitting device to emit light in response to a data potential input to a first node, the pulse signal generation unit generates a pulse signal in response to a data potential input to a second node, and the pixel resets the potential of the first node and turns off the light-emitting device in response to the pulse signal.

[0021] The light-emitting device is preferably a micro-LED. [Effects of the Invention]

[0022] By using one aspect of the present invention, a display device with small chromaticity changes and high gradation controllability can be provided. Alternatively, a display device having a pixel circuit that generates pulse signals can be provided. Alternatively, a display device having a pixel circuit capable of PAM control and PWM control can be provided. Alternatively, a display device having excellent display characteristics can be provided. Alternatively, a narrow-bezel display device can be provided.

[0023] Alternatively, a low-power display device can be provided. Alternatively, a highly reliable display device can be provided. Alternatively, a novel display device can be provided. Alternatively, a method for operating the above-mentioned display device can be provided. Alternatively, a novel semiconductor device can be provided. [Brief explanation of the drawing]

[0024] Figure 1 is a diagram illustrating the pixel circuit. Figure 2A is a diagram illustrating the pixel circuit. Figure 2B is a timing chart illustrating the operation of the pixel circuit. Figure 2C is a diagram illustrating the slope potential. Figure 2D is a diagram illustrating the transistor. Figures 3A and 3B illustrate the stacked structure of the display device. Figures 4A and 4B illustrate the operation of pixels. Figures 5A and 5B illustrate the operation of pixels. Figures 6A and 6B illustrate the operation of pixels. Figure 7 is a timing chart illustrating the operation of the pixels. Figures 8A and 8B illustrate the operation of pixels. Figures 9A and 9B illustrate the operation of pixels. Figure 10 is a timing chart illustrating the operation of the pixels. Figures 11A and 11B illustrate variations of pixels. Figures 12A and 12B illustrate variations in the pixel structure. Figure 13A is a diagram illustrating the pixel circuit. Figure 13B is a timing chart illustrating the operation of the pixel. Figures 14A and 14B illustrate the operation of pixels. Figures 15A and 15B illustrate the operation of pixels. Figure 16A shows the relationship between gray level and brightness. Figure 16B explains the operation in response to brightness using the light intensity and light emission time of the light-emitting device. Figures 17A and 17B illustrate the range of chromaticity shift. Figure 18 is a block diagram illustrating the display device. Figures 19A and 19B illustrate the display device. Figure 20 is a diagram illustrating a display device. Figure 21 is a diagram illustrating a display device. Figures 22A and 22B illustrate the display device. Figures 23A to 23D illustrate electronic devices. [Modes for carrying out the invention]

[0025] Embodiments will be described in detail with reference to the drawings. However, it will be readily apparent to those skilled in the art that the present invention is not limited to the following description, and that its form and details can be modified in various ways without departing from the spirit and scope of the invention. Therefore, the present invention is not to be interpreted as being limited to the descriptions of the embodiments shown below. In the configuration of the invention described below, the same reference numerals are used in common between different drawings for the same parts or parts having similar functions, and repeated descriptions may be omitted. In addition, hatching of the same elements constituting the figures may be omitted or changed as appropriate between different drawings.

[0026] Furthermore, even if an element is shown as a single element in a circuit diagram, it may be composed of multiple elements as long as there is no functional disadvantage. For example, multiple transistors that act as switches may be connected in series or parallel. Also, a capacitor may be divided and placed in multiple locations.

[0027] Furthermore, a single conductor may have multiple functions, such as wiring, electrodes, and terminals, and in this specification, multiple designations may be used for the same element. Also, even if elements are shown as directly connected in a circuit diagram, they may actually be connected via one or more conductors, and in this specification, such configurations are included in the category of direct connection.

[0028] (Embodiment 1) In this embodiment, a display device that is one aspect of the present invention will be described with reference to the drawings.

[0029] One aspect of the present invention is a display device that can turn a light-emitting device on and off using PAM+PWM control (pulse width control with amplitude change). The display device writes the same input signal (data potential) to a first node and a second node, turns on the light-emitting device according to the potential of the first node, and generates a pulse signal according to the potential of the second node. Then, it resets the potential of the first node according to the generated pulse signal. Therefore, the light-emitting device can be turned on at a desired light intensity for a desired period of time.

[0030] In this embodiment, PAM control refers to controlling brightness by keeping the light emission time (corresponding to the width of the pulse signal generated by the pixel) constant and changing the light emission intensity (corresponding to the current flowing through the light-emitting device). PWM control refers to controlling brightness by keeping the light emission intensity constant and changing the light emission time. PAM+PWM control refers to controlling brightness by changing both the light emission intensity and the light emission time.

[0031] LEDs, a type of light-emitting device, have the characteristic that their chromaticity changes depending on the current density, making PAM control unsuitable in some cases. On the other hand, PWM control has the problem of being difficult to control low gradation due to the influence of the response characteristics of the drive transistor and the LED. In one embodiment of the present invention, a display device can perform a display operation that combines PWM control and PAM control in order to mitigate these problems.

[0032] For example, the low- and high-gradation sides can be displayed using PAM control, while the intermediate tones can be displayed using PAM + PWM control. This operation reduces the amount of chromaticity change from intermediate to high gradation while improving the controllability of the low-gradation side. However, the display device according to one aspect of the present invention is not limited to this, and the LED light emission operation can be performed using only PAM control or only PWM control across a wide range of gradations.

[0033] Figure 1 is a circuit diagram of a pixel 10a in a display device according to one aspect of the present invention. The pixel 10a has a pulse signal generation unit 11, and nodes N and A for holding data potential VDATA.

[0034] The data potential VDATA is a potential based on image data, and the same data potential VDATA is supplied to both node N and node A. The light-emitting device 110 can be lit according to the data potential VDATA supplied to node A (PAM control). In addition, the input of the pulse signal generation unit 11 is electrically connected to node N, and the output of the pulse signal generation unit 11 is electrically connected to node A. Therefore, the potential of node A can be reset according to the pulse signal generated by the pulse signal generation unit 11, and the light-emitting device 110 can be turned off (PWM control).

[0035] Pixel 10a may include transistor 101, transistor 102, transistor 103, light-emitting device 110, capacitor 111, and pulse signal generation unit 11. It is preferable to use an LED (e.g., a micro-LED or mini-LED) for the light-emitting device 110. Alternatively, an organic EL element may be used for the light-emitting device 110.

[0036] Here, transistors 101 and 102 function as switches. Transistor 103 is a p-channel transistor and functions as a drive transistor for the light-emitting device 110. Capacitor 111 functions as a holding capacitance for node A. Although the example shows n-channel transistors for transistors 101 and 102, the transistors functioning as switches may also be p-channel transistors.

[0037] One source or drain of transistor 101 is electrically connected to one source or drain of transistor 102 and the input of the pulse signal generation unit 11. The other source or drain of transistor 102 is electrically connected to the output of the pulse signal generation unit 11, one electrode of capacitor 111, and the gate of transistor 103. One source or drain of transistor 103 is electrically connected to one electrode (anode) of light-emitting device 110. The other source or drain of transistor 103 is electrically connected to the other electrode of capacitor 111.

[0038] Here, node N is defined as the point (wiring or electrode, etc.) connecting one source or drain of transistor 101, one source or drain of transistor 102, and the input of the pulse signal generation unit 11. Node A is defined as the point (wiring or electrode, etc.) connecting the other source or drain of transistor 102, the output of the pulse signal generation unit 11, one electrode of capacitor 111, and the gate of transistor 103.

[0039] The connection relationships between each transistor and the wiring are as follows: The other source or drain of transistor 101 is electrically connected to wiring 121. The other source or drain of transistor 103 is electrically connected to wiring 125. The other electrode (cathode) of light-emitting device 110 is electrically connected to wiring 129. The gate of transistor 101 is electrically connected to wiring 131. The gate of transistor 102 is electrically connected to wiring 132.

[0040] Wiring 121 is a source wire for supplying the data potential VDATA. Wiring 121 can be electrically connected to the source driver. Wires 125 and 129 are power lines; wire 125 can be a high-potential power line, and wire 129 can be a low-potential power line. Wires 131 and 132 are gate wires for controlling the conduction of each transistor and can be electrically connected to the gate driver.

[0041] Figure 2A shows an example of a specific circuit configuration of the pulse signal generation unit 11. The pulse signal generation unit 11 may include transistors 104, 105, 106, 107, 108, 109, capacitors 112 and 113.

[0042] Here, transistor 104 is an n-channel transistor having a first gate and a second gate. The first gate acts as the front gate, and the second gate acts as the back gate. Transistors 106 and 107 can be p-channel transistors. Although Figure 2A shows an example where n-channel transistors are used for the other transistors, p-channel transistors may also be used.

[0043] The first gate of transistor 104 is electrically connected to node N, one of the source or drain of transistor 105, and one electrode of capacitor 112. That is, the wiring or electrodes connecting the first gate of transistor 104, one of the source or drain of transistor 105, and one electrode of capacitor 112 can be called the input section of the pulse signal generation unit 11. Alternatively, node N can be called the input section of the pulse signal generation unit 11.

[0044] Either the source or drain of transistor 104 is electrically connected to the gate of transistor 106 and either the source or drain of transistor 107.

[0045] Either the source or the drain of transistor 106 is electrically connected to node A. That is, the wiring or electrodes connecting either the source or the drain of transistor 106 to node A can be called the output of the pulse signal generation unit 11. Alternatively, node A can be called the output of the pulse signal generation unit 11.

[0046] The second gate of transistor 104 is electrically connected to either the source or drain of transistor 108 and to one electrode of capacitor 113.

[0047] The other electrode of capacitor 113 is electrically connected to the other source or drain of transistor 105, and to one source or drain of transistor 109.

[0048] Here, node W is defined as the point (wiring or electrode, etc.) connecting one source or drain of transistor 104, the gate of transistor 106, and one source or drain of transistor 107. Node BG is defined as the point (wiring or electrode, etc.) connecting the second gate of transistor 104, one source or drain of transistor 108, and one electrode of capacitor 113. Node BS is defined as the point (wiring or electrode, etc.) connecting the other electrode of capacitor 113, the other source or drain of transistor 105, and one source or drain of transistor 109.

[0049] The connections between each transistor and the wiring are as follows: The other source or drain of transistor 104 and the other source or drain of transistor 109 are electrically connected to wiring 122. The other source or drain of transistor 106 is electrically connected to wiring 124. The other source or drain of transistor 107 is electrically connected to wiring 123. The other source or drain of transistor 108 is electrically connected to wiring 128. The gate of transistor 105 is electrically connected to wiring 133. The gate of transistor 107 is electrically connected to wiring 134. The gate of transistor 108 is electrically connected to wiring 135. The gate of transistor 109 is electrically connected to wiring 136. The other electrode of capacitor 112 is electrically connected to wiring 127.

[0050] Wiring 122 is for supplying slope potential SLO. In this specification, slope potential refers to a type of signal potential of a ramp waveform, which has a period during which the potential changes from high to low or low to high, or a period during which the potential changes in such a way that it has a gradient with respect to the time axis.

[0051] Wiring 123 is for supplying the reset potential VRESW to node W. Wiring 124 is for supplying the reset potential VRESA to node A. Wiring 127 is a fixed potential line, which can be, for example, a GND wire or a low-potential power line. Wiring 128 is for supplying the potential VSBG to node BG. The potential VSBG is a fixed potential supplied as the initial back gate potential.

[0052] Here, the reset potential VRESW supplied to wiring 123 can be a high potential. The reset potential VRESA supplied to wiring 124 can be a high potential. The potential VSBG supplied to wiring 128 can be a low potential (e.g., a negative potential). Details of the slope potential SLO supplied to wiring 122 will be described later.

[0053] Transistors 106 and 107 function as switches. Transistors 104, 105, 108, and 109 have the function of determining the width of the pulse signal to be generated. Capacitor 112 functions as the holding capacitance of node N. Capacitor 113 functions as the holding capacitance of node BG.

[0054] In the pulse signal generation unit 11, under certain conditions, transistor 104 conducts, lowering the potential of node W and causing transistor 106 to conduct. The conduction of transistor 106 allows the potential of node A to be set to the reset potential VRESA. In other words, the pulse signal generation unit 11 generates a pulse signal and can control the period during which the data potential VDATA is held at node A according to the pulse signal.

[0055] The transistors 101 to 109 in the pixel 10a can be transistors having silicon in the channel formation region (hereinafter referred to as Si transistors) or transistors having metal oxide in the channel formation region (hereinafter referred to as OS transistors). Furthermore, both Si transistors and OS transistors can be used.

[0056] For example, in the circuit configuration shown in Figure 2A, it is preferable to use Si transistors for transistors 103, 106, and 107, and OS transistors for the other transistors. Since OS transistors can be provided in the wiring layer process on top of the Si transistors, the integration density can be increased.

[0057] Transistors 103, 106, and 107 are preferably Si transistors, which allow for easy formation of p-channel type transistors. Furthermore, since transistors 106 and 107 are preferably rapid chargers, they are preferably transistors with high transconductance (gm). Because Si transistors have relatively high mobility, they can be used as transistors with high gm.

[0058] Because OS transistors have a large energy gap in their semiconductor layer, they can exhibit extremely low off-current characteristics of a few yA / μm (current value per 1 μm channel width). This low off-current enhances the node's potential retention capability, allowing for proper image display even at lower frame frequencies. For example, by using a first frame frequency (e.g., 60 Hz or higher) for moving images and switching to a second frame frequency lower than the first (e.g., around 1 to 10 Hz) for still image displays, the display device can be made more power-efficient.

[0059] As the semiconductor material used in OS transistors, metal oxides with an energy gap of 2 eV or more, preferably 2.5 eV or more, and more preferably 3 eV or more, can be used. Typical examples include indium-containing oxide semiconductors, such as CAAC-OS or CAC-OS, which will be described later. CAAC-OS has stable atoms constituting the crystal, making it suitable for transistors where reliability is important. In addition, CAC-OS exhibits high mobility characteristics, making it suitable for transistors that require high-speed operation.

[0060] OS transistors have characteristics that differ from transistors with silicon in the channel formation region (hereinafter referred to as Si transistors), such as the absence of impact ionization, avalanche breakdown, and short-channel effects, and can form highly reliable circuits.

[0061] Examples of metal oxides that can be used in the semiconductor layer of an OS transistor include indium oxide, gallium oxide, and zinc oxide. Furthermore, it is preferable that the metal oxide contains two or three elements selected from indium, element M, and zinc. Element M is one or more elements selected from gallium, aluminum, silicon, boron, yttrium, tin, copper, vanadium, beryllium, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium. In particular, it is preferable that element M is one or more elements selected from aluminum, gallium, yttrium, and tin.

[0062] In particular, it is preferable to use an oxide containing indium (In), gallium (Ga), and zinc (Zn) (also written as IGZO) as the metal oxide used in the semiconductor layer. Alternatively, it is preferable to use an oxide containing indium, tin, and zinc (also written as ITZO). Alternatively, it is preferable to use an oxide containing indium, gallium, tin, and zinc. Alternatively, it is preferable to use an oxide containing indium (In), aluminum (Al), and zinc (Zn) (also written as IAZO). Alternatively, it is preferable to use an oxide containing indium (In), aluminum (Al), gallium (Ga), and zinc (Zn) (also written as IAGZO).

[0063] When the metal oxide used in the semiconductor layer is an In-M-Zn oxide, it is preferable that the atomic ratio of In in the In-M-Zn oxide is greater than or equal to the atomic ratio of M. Examples of such atomic ratios of metal elements in an In-M-Zn oxide include: In:M:Zn=1:1:1 or near that composition, In:M:Zn=1:1:1.2 or near that composition, In:M:Zn=1:3:2 or near that composition, In:M:Zn=1:3:4 or near that composition, In:M:Zn=2:1:3 or near that composition, In:M:Zn=3:1:2 or near that composition, In:M:Zn=4:2: Compositions include 3 or near 3, In:M:Zn=4:2:4.1 or near 4, In:M:Zn=5:1:3 or near 5, In:M:Zn=5:1:6 or near 5, In:M:Zn=5:1:7 or near 5, In:M:Zn=5:1:8 or near 5, In:M:Zn=6:1:6 or near 6, and In:M:Zn=5:2:5 or near 5. Note that "near 5" means within a range of ±30% of the desired atomic ratio.

[0064] For example, when describing a composition with an atomic ratio of In:Ga:Zn = 4:2:3 or a similar ratio, it includes cases where, when In is set to 4, Ga is between 1 and 3, and Zn is between 2 and 4. Also, when describing a composition with an atomic ratio of In:Ga:Zn = 5:1:6 or a similar ratio, it includes cases where, when In is set to 5, Ga is greater than 0.1 and 2 or less, and Zn is between 5 and 7. Furthermore, when describing a composition with an atomic ratio of In:Ga:Zn = 1:1:1 or a similar ratio, it includes cases where, when In is set to 1, Ga is greater than 0.1 and 2 or less, and Zn is greater than 0.1 and 2 or less.

[0065] Furthermore, the semiconductor layer may have two or more metal oxide layers with different compositions. For example, a laminated structure can be suitably used in which a first metal oxide layer has a composition of In:M:Zn=1:3:4 [atomic ratio] or close to that, and a second metal oxide layer provided on the first metal oxide layer has a composition of In:M:Zn=1:1:1 [atomic ratio] or close to that. In addition, it is particularly preferable to use gallium or aluminum as element M.

[0066] Alternatively, a layered structure may be used, for example, comprising one selected from indium oxide, indium gallium oxide, and IGZO, and one selected from IAZO, IAGZO, and ITZO®.

[0067] However, the invention is not limited to these examples, and an oxide semiconductor with an appropriate composition may be used depending on the semiconductor characteristics and electrical characteristics (field-effect mobility, threshold voltage, etc.) of the transistor required. Furthermore, in order to obtain the required semiconductor characteristics of the transistor, it is preferable to set the carrier concentration, impurity concentration, defect density, atomic ratio of metal elements to oxygen, interatomic distance, density, etc., of the semiconductor layer appropriately.

[0068] In oxide semiconductors that constitute a semiconductor layer, the presence of silicon or carbon, which are Group 14 elements, increases oxygen vacancies and causes n-type semiconductor formation. Therefore, the concentration of silicon or carbon in the semiconductor layer (concentration obtained by secondary ion mass spectrometry) is 2 × 10⁻¹⁰. 18 atoms / cm 3 The following is preferably 2 × 10 17 atoms / cm 3 The following applies:

[0069] Furthermore, alkali metals and alkaline earth metals can generate carriers when bonded with oxide semiconductors, which can increase the transistor's off-current. For this reason, the concentration of alkali metals or alkaline earth metals in the semiconductor layer (concentration obtained by secondary ion mass spectrometry) should be set to 1 × 10⁻⁶. 18 atoms / cm 3Hereinafter, it is preferably 2×10 16 atoms / cm 3 or less.

[0070] In addition, if nitrogen is contained in the oxide semiconductor constituting the semiconductor layer, electrons as carriers are generated, the carrier concentration increases, and it tends to be n-type. As a result, a transistor using an oxide semiconductor containing nitrogen tends to have normally-on characteristics. Therefore, the nitrogen concentration (concentration obtained by secondary ion mass spectrometry) in the semiconductor layer is preferably 5×10 18 atoms / cm 3 or less.

[0071] In addition, if hydrogen is contained in the oxide semiconductor constituting the semiconductor layer, it reacts with oxygen bonded to metal atoms to become water, and thus oxygen deficiency may be formed in the oxide semiconductor. If oxygen deficiency is contained in the channel formation region in the oxide semiconductor, the transistor may have normally-on characteristics. Furthermore, a defect in which hydrogen enters the oxygen deficiency may function as a donor, and electrons as carriers may be generated. Also, a part of hydrogen may bond with oxygen bonded to metal atoms to generate electrons as carriers. Therefore, a transistor using an oxide semiconductor containing a large amount of hydrogen tends to have normally-on characteristics.

[0072] A defect in which hydrogen enters the oxygen deficiency can function as a donor of the oxide semiconductor. However, it is difficult to quantitatively evaluate the defect. Therefore, in the oxide semiconductor, it may be evaluated by the carrier concentration instead of the donor concentration. Thus, in this specification and the like, as a parameter of the oxide semiconductor, the carrier concentration assuming a state where no electric field is applied may be used instead of the donor concentration. That is, the "carrier concentration" described in this specification and the like may be paraphrased as the "donor concentration" in some cases.

[0073] Therefore, it is preferable that the hydrogen content in the oxide semiconductor be reduced as much as possible. Specifically, in the oxide semiconductor, the hydrogen concentration obtained by secondary ion mass spectrometry (SIMS) should be 1 × 10⁻⁶. 20 atoms / cm 3 Less than 1 × 10 19 atoms / cm 3 Less than 5x10 18 atoms / cm 3 Less than 1 × 10 18 atoms / cm 3 It should be less than [amount missing]. By using an oxide semiconductor with sufficiently reduced impurities such as hydrogen in the channel formation region of a transistor, stable electrical characteristics can be provided.

[0074] Furthermore, the semiconductor layer may have a non-single-crystal structure, for example. Non-single-crystal structures include, for example, CAAC-OS (C-Axis Aligned Crystalline Oxide Semiconductor) having crystals oriented along the c axis, polycrystalline structures, microcrystalline structures, or amorphous structures. Among non-single-crystal structures, the amorphous structure has the highest defect level density, while CAAC-OS has the lowest defect level density.

[0075] An amorphous oxide semiconductor film, for example, has a disordered atomic arrangement and does not contain crystalline components. Alternatively, an amorphous oxide film, for example, has a completely amorphous structure and does not contain crystalline parts.

[0076] Furthermore, the semiconductor layer may be a mixed film having two or more regions from among amorphous, microcrystalline, polycrystalline, CAAC-OS, and single-crystal structures. The mixed film may have a single-layer structure or a stacked structure that includes, for example, two or more of the regions described above.

[0077] The following describes the configuration of CAC (Cloud-Aligned Composite)-OS, which is one form of a non-single-crystal semiconductor layer.

[0078] CAC-OS is a material composition in which the elements constituting the oxide semiconductor are unevenly distributed in sizes of 0.5 nm to 10 nm, preferably 1 nm to 2 nm, or close to that size. In the following, in an oxide semiconductor, a state in which one or more metal elements are unevenly distributed, and the regions containing the metal elements are mixed in sizes of 0.5 nm to 10 nm, preferably 1 nm to 2 nm, or close to that size, is also referred to as a mosaic or patchy state.

[0079] Furthermore, the oxide semiconductor preferably contains at least indium. It is particularly preferable that it contains indium and zinc. In addition, it may also contain one or more elements selected from aluminum, gallium, yttrium, copper, vanadium, beryllium, boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, or magnesium.

[0080] For example, CAC-OS in In-Ga-Zn oxide (In-Ga-Zn oxide within CAC-OS may be specifically called CAC-IGZO) refers to indium oxide (hereinafter, InO X1 (Let X1 be a real number greater than 0.) ) or indium zinc oxide (hereinafter, In X2 Zn Y2 O Z2 (Let X2, Y2, and Z2 be real numbers greater than 0.) and gallium oxide (hereinafter referred to as GaO X3 (Let X3 be a real number greater than 0.) or gallium zinc oxide (hereinafter referred to as Ga X4 Zn Y4 O Z4 (Let X4, Y4, and Z4 be real numbers greater than 0).) The material separates into mosaic-like structures, and the mosaic-like InO X1 , or In X2 Zn Y2 O Z2 However, it is a uniformly distributed structure within the membrane (hereinafter also referred to as a cloud-like structure).

[0081] In other words, CAC-OS is GaO X3 The region in which is the main component, and In X2 Zn Y2 O Z2 , or InO X1 This is a composite oxide semiconductor having a structure in which a region in which is the main component is mixed with another region. In this specification, for example, if the atomic ratio of In to element M in the first region is greater than the atomic ratio of In to element M in the second region, then the first region is considered to have a higher concentration of In compared to the second region.

[0082] Note that IGZO is a common name and can refer to a single compound composed of In, Ga, Zn, and O. A typical example is InGaO3(ZnO). m1 (m1 is a natural number), or In (1+x0) Ga (1-x0) O3(ZnO) m0 Examples include crystalline compounds represented by (-1 ≤ x0 ≤ 1, where m0 is any number).

[0083] The above-mentioned crystalline compounds have a single-crystal structure, a polycrystalline structure, or a CAAC structure. A CAAC structure is a crystalline structure in which multiple IGZO nanocrystals are c-axis oriented and linked together without orientation in the ab-plane.

[0084] On the other hand, CAC-OS refers to the material composition of oxide semiconductors. CAC-OS is a material composition containing In, Ga, Zn, and O, in which regions observed as nanoparticles mainly composed of Ga and regions observed as nanoparticles mainly composed of In are randomly dispersed in a mosaic-like manner. Therefore, in CAC-OS, the crystal structure is a secondary element.

[0085] Furthermore, CAC-OS does not include layered structures of two or more films with different compositions. For example, a structure consisting of two layers, one with In as the main component and the other with Ga as the main component, is not included.

[0086] Note that GaOX3 The region in which is the main component, and In X2 Zn Y2 O Z2 , or InO X1 In some cases, a clear boundary may not be observable in a region where [this component] is the main component.

[0087] Furthermore, if gallium is replaced with one or more elements selected from aluminum, yttrium, copper, vanadium, beryllium, boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, or magnesium, CAC-OS refers to a configuration in which regions observed as nanoparticles mainly composed of the said metal element and regions observed as nanoparticles mainly composed of In are randomly dispersed in a mosaic pattern.

[0088] CAC-OS can be formed by sputtering, for example, under conditions where the substrate is not intentionally heated. When forming CAC-OS by sputtering, one or more gases selected from inert gases (typically argon), oxygen gas, and nitrogen gas may be used as the deposition gas. Furthermore, a lower ratio of oxygen gas flow rate to the total deposition gas flow rate during film formation is preferable; for example, an oxygen gas flow rate ratio of 0% or more and less than 30%, preferably 0% or more and 10% or less, is preferable.

[0089] CAC-OS is characterized by the absence of a clear peak when measured using the θ / 2θ scan method, an out-of-plane X-ray diffraction (XRD) measurement technique. In other words, X-ray diffraction measurements indicate that no orientation in the ab-plane direction or the c-axis direction of the measurement region is observed.

[0090] Furthermore, in the electron diffraction pattern obtained by irradiating CAC-OS with an electron beam with a probe diameter of 1 nm (also called a nanobeam electron beam), a ring-shaped region of high brightness and multiple bright spots within this ring-shaped region are observed. Therefore, from the electron diffraction pattern, it can be seen that the crystal structure of CAC-OS has an nc (nano-crystal) structure that does not have orientation in the planar and cross-sectional directions.

[0091] Furthermore, for example, in CAC-OS in In-Ga-Zn oxide, EDX mapping obtained using energy dispersive X-ray spectroscopy (EDX) revealed that GaO X3 The region in which is the main component, and In X2 Zn Y2 O Z2 , or InO X1 It can be confirmed that the structure has regions in which the main component is unevenly distributed and mixed.

[0092] CAC-OS has a different structure from IGZO compounds in which metal elements are uniformly distributed, and therefore has different properties from IGZO compounds. In other words, CAC-OS is GaO X3 Regions where such are the main components, and In X2 Zn Y2 O Z2 , or InO X1 It has a mosaic-like structure consisting of regions where one element is the main component and regions where each element is the main component, with each region being in a separate phase from the others.

[0093] Here, In X2 Zn Y2 O Z2 , or InO X1 The region in which is the main component is GaO X3 Compared to regions where these are the main components, this region has high conductivity. In other words, In X2 Zn Y2 O Z2 , or InO X1 In the region where this is the main component, the flow of carriers causes conductivity as an oxide semiconductor to emerge. Therefore, InX2 Zn Y2 O Z2 , or InO X1 A high field-effect mobility (μ) can be achieved when regions with this as the main component are distributed in a cloud-like manner within the oxide semiconductor.

[0094] On the other hand, GaO X3 Regions in which these are the main components are, X2 Zn Y2 O Z2 , or InO X1 This region has higher insulating properties compared to the region where GaO is the main component. X3 Regions with these as the main components are distributed within the oxide semiconductor, which suppresses leakage current and enables good switching operation.

[0095] Therefore, when CAC-OS is used in semiconductor devices, GaO X3 Insulation caused by factors such as, X2 Zn Y2 O Z2 , or InO X1 The conductivity resulting from this works in a complementary manner, resulting in a high on-current (I on ), and high field-effect mobility (μ) can be achieved.

[0096] Furthermore, semiconductor devices using CAC-OS are highly reliable. Therefore, CAC-OS is suitable as a constituent material for various semiconductor devices.

[0097] Furthermore, one or more of transistors 102 to 105 may be formed as OS transistors. Alternatively, one or more of transistors 102 to 105 may be formed as transistors having silicon in the channel formation region (hereinafter referred to as Si transistors).

[0098] Amorphous silicon, microcrystalline silicon, polycrystalline silicon, and monocrystalline silicon can be used for the channel formation region of a Si transistor. When the transistor is mounted on an insulating surface such as a glass substrate, polycrystalline silicon is preferable.

[0099] High-quality polycrystalline silicon can be easily obtained by using processes such as laser crystallization. Alternatively, high-quality polycrystalline silicon can also be obtained by solid-phase growth, which involves adding a metal catalyst such as nickel or palladium to amorphous silicon and heating it. Furthermore, the crystallinity of polycrystalline silicon formed by solid-phase growth using a metal catalyst may be further enhanced by laser irradiation. Since the metal catalyst remains in the polycrystalline silicon and degrades the electrical properties of the transistor, it is preferable to create regions outside the channel formation area where phosphorus or a noble gas is added, thereby trapping the metal catalyst in these regions.

[0100] Furthermore, to obtain the effects of one aspect of the present invention, the configuration is not limited to those described above; all transistors in the pixel may be formed from Si transistors. Alternatively, one or more transistors in the pixel may be formed from p-channel transistors.

[0101] Figure 3A shows an example of a display device having a stacked structure, and Figure 3B is an unfolded view and a partially enlarged view thereof. A display device having a stacked structure can be configured by sequentially stacking a layer 310 having a silicon substrate, a layer 320 having wiring, and a layer 330 having a light-emitting device. In this stacked structure, circuits can be formed by overlapping, so the display device can have a narrow bezel.

[0102] Layer 310 may have Si transistors 311 and functional circuits 312, which are components of the pixel circuit. Note that Si transistors 311 can be placed in a region that does not interfere with the functional circuits 312. Si transistors 311 correspond, for example, to transistors 103, 106, and 107 in Figure 2A. Layer 320 may have OS transistors 321, which are components of the pixel circuit. Layer 330 may have an LED array 331.

[0103] The LED array 331 has a configuration in which LEDs are arranged in a matrix. As LEDs, for example, microLEDs formed with a diameter or side length of 50 μm or less, or miniLEDs formed with a diameter or side length greater than 50 μm and 200 μm or less can be used.

[0104] The functional circuit 312 may include, for example, one or more of the following: a source driver, a gate driver, a memory circuit, an arithmetic circuit, and a power supply circuit. Alternatively, the functional circuit 312 may include a pulse signal generation unit for the pixel 10a. Note that some or all of the gate driver and memory circuit may be formed from OS transistors. Details of the stacked configuration will be described in Embodiment 2.

[0105] Next, the operation of transistor 104 will be explained using Figures 2B to 2D. Transistor 104 has a first gate and a second gate, and by supplying an appropriate potential to the second gate, a threshold voltage (V) is generated. th ) can be shifted. Transistor 104 adjusts V in accordance with the data potential VDATA supplied as image data. th The voltage can be shifted, and the timing of conduction can be controlled by the slope potential SLO supplied to the source.

[0106] In other words, transistor 104 can change the timing of conduction according to the magnitude of the data potential VDATA. This operation allows, for example, switching between PAM control for low and high gradations and PAM+PWM control for intermediate gradations. The details of the effect of switching the control method depending on the gradation will be described later.

[0107] Figure 2B is a timing chart illustrating the potential (Vbg) applied to the second gate (node ​​BG) of transistor 104. Here, the slope potential SLO supplied to wiring 122 is the signal potential of a ramp waveform that changes from the upper end (SLO_H) to the lower end (SLO_L) over time, as shown in Figure 2C. The relationship between the data potential VDATA supplied to wiring 121 and the slope potential SLO is SLO_H > VDATA > SLO_L.

[0108] First, a high potential is supplied to wirings 131, 133, and 135 to cause the transistors to conduct, thereby making transistors 101, 105, and 108 conduct.

[0109] At this time, the potential of node BS is VDATA and the potential of node BG is VSBG. Also, wiring 122 is in a standby state supplying the potential SOL_H at the upper end of the slope potential SLO, and the second gate-source voltage (Vbgs) of transistor 104 is VSBG-SLO_H.

[0110] Next, transistors 101, 105, and 108 are de-conducted, and a high potential is supplied to the wiring 136 to make transistor 109 conduct.

[0111] When the supply of slope potential SLO is started at this timing, the potential of node BS becomes SLO. At this time, the potential of node BG is VSBG-VDATA+SLO due to capacitive coupling of capacitor 113, and the potential of node BG at the beginning of the supply of slope potential SLO can be said to be VSBG-VDATA+SLO_H.

[0112] Subsequently, the potential of node BG decreases according to the slope potential SLO. As shown in Figure 2D, the slope potential SLO is also supplied to the source of transistor 104. Therefore, the Vbgs of transistor 104 becomes VSBG - VDATA + SLO - SLO = VSBG - VDATA, and remains constant regardless of the magnitude of the slope potential SLO, which changes over time.

[0113] This allows the V of transistor 104 to change according to the magnitude of the data potential VDATA. th The V can be shifted by a certain amount. The pulse signal generation unit 11 generates V according to the magnitude of this data potential VDATA. th By using the shift function, the width of the generated pulse signal can be controlled.

[0114] Next, the operation of pixel 10a will be explained for each grayscale level. The data potentials VDATA described below are VDATA1 for low grayscale, VDATA2 for mid-tone, and VDATA3 for high grayscale. Since the drive transistor 103 of the light-emitting device 110 is a p-channel type transistor, the magnitude of the potentials is VDATA1 > VDATA2 > VDATA3.

[0115] For example, VDATA1 is the data potential for illuminating the light-emitting device 110 in an 8-bit grayscale range from grayscale 0 to a grayscale level smaller than the lower end of the intermediate grayscale. VDATA2 is the data potential for illuminating the light-emitting device 110 in a grayscale range from the lower end to the upper end of the intermediate grayscale. VDATA3 is the data potential for illuminating the light-emitting device 110 in a grayscale range from a grayscale level greater than the upper end of the intermediate grayscale to grayscale 255. Here, the range of intermediate grayscale can be set arbitrarily, for example, from grayscale 32 to grayscale 127.

[0116] Figure 4A shows the transistor 104 and its drain current-gate voltage (I) when the light-emitting device 110 is lit in low gradation using VDATA1 as the data potential. d -V g)It is a diagram related to characteristics.

[0117] First, a potential VSBG is supplied to the node BG of the transistor 104. When Vbgs = VSBG - SLO_H, the I of the transistor 104 d -V g curve shifts positively from the initial position (not shown) to the position represented by the dashed line. Then, when Vbgs = VSBG - VDATA1 due to the capacitive coupling of the capacitor 113, the I of the transistor 104 d -V g curve shifts negatively to the position shown by the solid line and is fixed. The change in Vbgs will be described in detail in the explanation of the operation of the pixel 10a described later.

[0118] In FIG. 4A, the data potential VDATA1 applied to the first gate of the transistor 104 and the threshold voltage (V th 1) are shown. When V gs becomes greater than +V gs 1, it indicates that the transistor 104 conducts.

[0119] In the transistor 104, the potential applied to the first gate is fixed at VDATA1, and V gs is changed by supplying a slope potential SLO that sweeps the potential at the source from high to low.

[0120] FIG. 4B is a diagram for explaining the relationship between the slope potential SLO, the data potential VDATA1, and the lighting period of the light-emitting device 110.

[0121] The data potential VDATA1 is a value close to the vicinity of the upper end (SLO_H) of the slope potential SLO. When SLO = VDATA1, V gs = 0. From here, when the slope potential SLO decreases so that V gs increases by only +V gs 1, the V of the transistor 104 g reaches V th 1, and the transistor 104 conducts.

[0122] The light-emitting device 110 starts to light up after the reset operations of nodes N and W, and after the writing of data potential DATA1 to node A. The light-emitting device 110 continues to light up until transistor 104 conducts. When transistor 104 conducts, the potential of node W decreases, causing transistor 107 to conduct, and the potential of node A can be changed from DATA1 to the reset potential VRESA. Therefore, the light-emitting device 110 turns off.

[0123] As shown in Figure 4B, transistor 104 is made to conduct just before the slope potential SLO reaches the lower limit SLO_L. To enable this operation, the slope potential SLO, data potential VDATA1 and V th By adjusting the relationship between the shift amount of 1 and other factors, the light-emitting device 110 can be made to light up for most of the frame duration. In other words, when VDATA1 is used for the data potential, it can be said that PAM control is being performed.

[0124] Figure 5A shows the transistor 104 and its drain current-gate voltage (I) when the light-emitting device 110 is lit in intermediate tone using VDATA2 as the data potential. d -V g This is a diagram illustrating the characteristics.

[0125] First, when the potential VSBG is supplied to node BG of transistor 104, and Vbgs = VSBG - SLO_H, the I of transistor 104 d -V g The curve shifts positively from its initial position (not shown) to the position represented by the dashed line. Subsequently, when Vbgs = VSBG - VDATA2 due to the capacitive coupling of capacitor 113, the I of transistor 104 d -V g The curve is shifted negatively and fixed at the position indicated by the solid line.

[0126] In Figure 5A, the data potential VDATA2 and threshold voltage (V) applied to the first gate of transistor 104 at this time are shown. th 2) shows Vgs And further +V gs A value greater than 2 indicates that transistor 104 conducts.

[0127] In transistor 104, the potential applied to the first gate is fixed at VDATA2, and a slope potential SLO is supplied to the source to sweep the potential from high to low, thereby V gs Change it.

[0128] Figure 5B illustrates the relationship between the slope potential SLO, the data potential VDATA2, and the illumination period of the light-emitting device 110.

[0129] The data potential VDATA2 is smaller than VDATA1, and when SLO = VDATA2, V gs = 0. From here, V gs ga + V gs When the SLO decreases so that it rises for only 2 minutes, the Vg of transistor 104 is V th When it reaches 2, transistor 104 conducts.

[0130] The light-emitting device 110 starts to light up after the reset operations of nodes N and W, and after the writing of the data potential DATA2 to node A. The light-emitting device 110 continues to light up until transistor 104 conducts. When transistor 104 conducts, the potential of node W decreases, causing transistor 107 to conduct, and the potential of node A can be changed from DATA2 to the reset potential VRESA. Therefore, the light-emitting device 110 turns off.

[0131] As shown in Figure 5B, transistor 104 is made to conduct during the decrease of the slope potential SLO. To enable this operation, the slope potential SLO, data potential VDATA2 and V thBy adjusting the relationship between the shift amount of 2 and other parameters, the light-emitting device 110 can be turned off in the middle of the frame period. In other words, since it is lit at the data potential DATA2 and the lighting period is controlled to be short, it can be said that PAM+PWM control is being performed when VDATA2 is used as the data potential.

[0132] Figure 6A shows the transistor 104 and its drain current-gate voltage (I) when the light-emitting device 110 is lit with high gradation using VDATA3 as the data potential. d -V g This is a diagram illustrating the characteristics.

[0133] First, when the potential VSBG is supplied to node BG of transistor 104, and Vbgs = VSBG - SLO_H, the I of transistor 104 d -V g The curve shifts positively from its initial position (not shown) to the position represented by the dashed line. Subsequently, due to the capacitive coupling of capacitor 113, when Vbgs = VSBG - VDATA1, the I of transistor 104 d -V g The curve is shifted negatively and fixed at the position indicated by the solid line.

[0134] In Figure 6A, the data potential VDATA3 and threshold voltage (V) are applied to the first gate of transistor 104 at this time. th 3) indicates V gs And further +V gs A value greater than 3 indicates that transistor 104 conducts.

[0135] In transistor 104, the potential applied to the first gate is fixed at VDATA3, and a slope potential SLO is supplied to the source to sweep the potential from high to low, thereby V gs Change it.

[0136] Figure 6B illustrates the relationship between the slope potential SLO, the data potential VDATA3, and the illumination period of the light-emitting device 110.

[0137] The data potential VDATA3 is close to the upper limit (SLO_H) of the slope potential SLO, and when SLO=VDATA1, V gs = 0. From here, V gs ga + V gs When the SLO decreases so that it rises for only 3 minutes, the Vg of transistor 104 is V th When it reaches 3, transistor 104 conducts.

[0138] The light-emitting device 110 starts to light up after the reset operations of nodes N and W, and after the writing of the data potential DATA3 to node A. The light-emitting device 110 continues to light up until transistor 104 conducts. When transistor 104 conducts, the potential of node W decreases, causing transistor 107 to conduct, and the potential of node A can be changed from DATA3 to the reset potential VRESA. Therefore, the light-emitting device 110 turns off.

[0139] As shown in Figure 6B, transistor 104 is made to conduct just before the slope potential SLO reaches the lower limit SLO_L. To enable this operation, the slope potential SLO, data potential VDATA3 and V th By adjusting the relationship between the shift amount of 3 and other parameters, the light-emitting device 110 can be made to light up for most of the frame duration. In other words, when VDATA3 is used for the data potential, it can be said that PAM control is being performed.

[0140] Next, the operation of pixel 10a when using the intermediate tone data potential VDATA2 will be explained using the timing chart shown in Figure 7 and the circuit operation diagrams shown in Figures 8A to 9B. Note that the dashed arrows in Figures 8A to 9B represent the potential supplied to the circuit, and the dotted arrows represent the current (I) flowing through the light-emitting device 110. LED This indicates that...

[0141] First, at time T1, a low potential (“L”) is supplied to wirings 131, 132, 133, 134, 135, and 136. At this time, transistor 107 conducts, and the reset potential VRESW (low potential) supplied to wiring 123 is supplied to node W (see FIG. 8A). This operation is the reset operation of node W, and at this time, transistor 106 becomes non-conductive.

[0142] At time T2, a high potential (“H”) is supplied to wirings 131, 132, 133, 134, 135, and a low potential (“L”) is supplied to wiring 136. At this time, transistor 107 becomes non-conductive. Also, transistors 101, 102, and 105 conduct, and data potential VDATA2 is supplied to node N, node BS, and node A. Then, transistor 103 conducts, and light-emitting device 110 lights up according to data potential VDATA2 (see FIG. 8B).

[0143] Also, transistor 108 conducts, and potential VSBG (low potential) supplied to wiring 128 is supplied to node BG. At this time, the same potential as the upper end (SLO_H) of slope potential SLO is supplied to wiring 122, and Vbgs of transistor 104 becomes VSBG - SLO_H. Here, since VSBG < SLO_H, the Id-Vg characteristics of transistor 104 shift greatly positively like the Id-Vg curve shown by the broken line in FIG. 5A.

[0144] At time T3, a low potential (“L”) is supplied to wirings 131, 132, 133, 135, and a high potential (“H”) is supplied to wirings 134 and 136. At this time, transistors 101, 102, 105, and 108 become non-conductive, and transistor 109 conducts (see FIG. 9A).

[0145] Also, from time T3 to time T10, slope potential SLO is supplied to wiring 122. Here, since the potential of node BS is rewritten from VDATA2 to SLO, the potential of node BG becomes VSBG - VDATA2 + SLO due to the capacitive coupling of capacitor 113.

[0146] Furthermore, the slope potential SLO is also supplied to the source of transistor 104. Therefore, the Vbgs of transistor 104 becomes VSBG - VDATA2 + SLO - SLO = VSBG - VDATA2, and is a constant value independent of the slope potential SLO. Consequently, the Id-Vg characteristic of transistor 104 is negatively shifted and fixed as shown by the solid line Id-Vg curve in Figure 5A.

[0147] Transistor 104 is affected by the decrease in slope potential SLO. gs The increase is +V gs No conductivity is maintained until it reaches 2 (see Figures 5A and 5B). Figure 9A shows V gs The increase is +V gs The state before reaching 2 (VDATA2-SLO<+V gs 2) is shown, and during this time, the light-emitting device 110 remains lit.

[0148] Figure 9B shows V at time T8. gs The increase is +V gs The state where it is greater than 2 (VDATA2-SLO>+V gs 2) is illustrated as an example, where transistor 104 conducts, the potential of node W drops to SLO, and transistor 106 conducts. Then, the reset potential VRESA (high potential) supplied to wiring 124 is supplied to node A, transistor 103 becomes non-conductive, and the light-emitting device 110 turns off.

[0149] As explained above, by using a data potential DATA2 such that the light-emitting device 110 turns off during the decrease of the slope potential SLO, PAM+PWM control becomes possible.

[0150] Figure 10 is a timing chart illustrating the operation of pixel 10a when using low-gradation data potential VDATA1 or high-gradation data potential VDATA3.

[0151] Figure 10 differs from Figure 7 in that it uses either VDATA1 or VDATA3 for the data potential. Transistor 104 does not conduct until the slope potential SLO reaches or near the lower limit SLO_L, and the light-emitting device 110 remains lit. Therefore, since the light-emitting device 110 remains lit for most of the frame period, it can be said that PAM control is being performed.

[0152] In addition, pixel 10a can perform PAM control or PWM control across the entire grayscale range, unlike the operation described above.

[0153] For example, by supplying a reset potential VRESA to node A and preventing transistor 102 from conducting, the light-emitting device 110 can be lit using only PWM control.

[0154] Furthermore, by supplying a high potential (for example, a potential similar to SLO_H) instead of the slope potential SLO, and preventing transistor 104 from conducting, transistor 106 will remain non-conductive at all times, allowing the light-emitting device 110 to be lit using only PAM control.

[0155] In addition, a pixel in one aspect of the present invention may have the configuration of pixel 10b shown in Figure 11A. The configuration shown in Figure 11A differs from pixel 10a shown in Figure 2A in that the other of the source or drain of transistor 108 is electrically connected to wiring 122.

[0156] In pixel 10a, an example was shown where VSBG was supplied to node BG from wiring 128 as the initial back gate potential, but in pixel 10b, a slope potential SLO is supplied. In this case, it is preferable that the initial slope potential be low enough that transistor 104 does not conduct. By adopting this configuration, wiring 128 can be reduced.

[0157] Furthermore, as shown in Figure 11B, wirings 131, 132, 133, and 135 may be connected to a common gate line GL. As shown in the timing charts in Figures 7 and 10, these wirings can be supplied with the same potential at the same timing, thus allowing them to be shared. Although Figure 11B illustrates the configuration of pixel 10a, the common gate line GL can also be applied to pixels with other configurations shown in this embodiment.

[0158] Alternatively, as shown in Figure 12A, pixel 10c may be electrically connected to the wiring 125 with one electrode (anode) of the light-emitting device and to the other electrode (cathode) of the source or drain of transistor 103. The configurations of pixels 10a and 10c can be used interchangeably depending on the specifications of the terminals of the light-emitting device 110 used.

[0159] Furthermore, in the configuration of pixels 10a, 10b, and 10c, when an OS transistor is used as the n-channel transistor, transistors 101, 102, 105, 108, and 109 may be configured to have back gates, as shown in Figure 12B. By supplying the same potential to the back gate as to the front gate, the on-current can be increased. Alternatively, a configuration that can supply a constant potential to the back gate may be used. By supplying a constant potential to the back gate, the threshold voltage can be controlled.

[0160] Furthermore, in order to improve the display quality of the display device, the V of transistor 103, which is the driving transistor of the light-emitting device 110, th Corrections may be made.

[0161] For example, as shown in Figure 13A, by adding transistors 115, 116 and 114 to the configuration shown in Figure 1, the V of transistor 103 th Internal correction can be performed.

[0162] One source or drain of transistor 115 is electrically connected to the other source or drain of transistor 103 and one electrode of capacitor 114. The other source or drain of transistor 115 is electrically connected to the other electrode of capacitor 114 and wiring 125. The gate of transistor 115 is electrically connected to wiring 137.

[0163] One source or drain of transistor 116 is electrically connected to one source or drain of transistor 103. The other source or drain of transistor 116 is electrically connected to wiring 139. The gate of transistor 116 is electrically connected to wiring 138.

[0164] Wires 137 and 138 function as gate lines to control the conduction of each transistor. Wire 139 is a discharge path and can be a low-potential line. The high power supply potential supplied to wire 125 is LVDD. In addition, data potential VDATA and potential V0 are supplied alternately to wire 121 within a certain period of time. Potential V0 can be any potential at which transistor 103 conducts when its source potential is LVDD and its gate potential is V0, and can be a low potential such as 0V.

[0165] Transistor 115 functions as a switch to temporarily fix the source potential of transistor 103. Transistor 116 is V th It functions as a switch connecting transistor 103 and the wiring 139, which is the discharge path, when acquiring the current. In Figure 13A, an example is shown in which n-channel transistors are used for transistors 115 and 116, but p-channel transistors can also be used. Capacitor 114 is the capacitance that holds the source potential of transistor 103 and has a capacitance that is sufficiently larger than capacitor 111.

[0166] Using the timing chart shown in Figure 13B and the diagrams illustrating the circuit operation in Figures 14A to 15B, the V of transistor 103 thThe correction operation will now be explained. Note that the explanation of the operation related to the illumination of the light-emitting device 110 is the same as described above and will therefore be omitted.

[0167] First, at time T1, a high potential ("H") is supplied to wiring 137, causing transistor 115 to conduct. At this time, the source potential of transistor 103 becomes LVDD (see Figure 14A).

[0168] At the beginning of time T2, potential V0 is supplied to wire 121. At this time, high potential ("H") is supplied to wires 131 and 138. Also, low potential ("L") is supplied to wire 137. At this time, transistors 101 and 102 conduct, and potential V0 is supplied to the gate of transistor 103. Also, while transistor 115 is not conducting, transistor 116 conducts, and transistor 103 conducts, causing the source potential to start to decrease. Then, the source potential changes from LVDD to V0-V th When it is discharged to this point, transistor 103 becomes non-conductive (see Figure 14B).

[0169] Between time T2 and time T3, the potential supplied to wiring 121 switches from V0 to VDATA. At this timing, a high potential ("H") is supplied to wiring 132. Also, a low potential ("L") is supplied to wiring 138, making transistor 116 non-conductive. At this time, the data potential VDATA is supplied to the gate of transistor 103.

[0170] Here, since capacitor 114 has a capacitance significantly larger than capacitor 111, the source potential of transistor 103 is effectively V0-V th It is maintained at this level (see Figure 15A). Therefore, the V of transistor 103 at this time gs VDATA-V0+V th This is the result.

[0171] At time T3, a high potential ("H") is supplied to wiring 137, and a low potential ("L") is supplied to wirings 131 and 132. At this time, transistors 101 and 102 become non-conductive, and the source potential of transistor 103 becomes LVDD. Then, the V maintained by capacitor 111 gs =V Retrieve - V0 + V th Accordingly, transistor 103 conducts, and current I flows to light-emitting device 110. LED It flows (see Figure 15B).

[0172] I LED Equation I is the drain current flowing through transistor 103. d =β / 2(V gs -V th ) 2 It follows this. Here, β is the coefficient. V in the given equation. gs =V Retrieve - V0 + V th Substituting this into V th Since the term containing is canceled out, the drain current is V th It can be said that it will no longer depend on I LED This is the V of transistor 103. th Because it becomes independent of variations, the display quality of the display device can be improved.

[0173] Next, the effects of switching between PAM control and PAM+PWM control, which can be implemented in one embodiment of the present invention, will be explained.

[0174] Figure 16A shows the relationship between gray level (input value 8 bits) and brightness (output value) according to a gamma curve (gamma value = 2). In one embodiment of the present invention, pixels 10a to 10c can perform the input and output shown in Figure 16A, and the operation method can be switched within a desired range of gray level.

[0175] For example, the low brightness range (32 levels, corresponding to brightness levels 0 to 31) and the high brightness range (128 levels, corresponding to brightness levels 128 to 255) can be operated using PAM control, while the intermediate range (96 levels, corresponding to brightness levels 32 to 127) can be operated using PAM + PWM control. This operation allows for the display of images with minimal chromaticity shift. However, the operation method and switching timing can be set arbitrarily. It is also possible to operate using either PAM control or PWM control across the entire range.

[0176] Figure 16B illustrates the above operation using the light intensity and light duration of the light-emitting device. The numbers indicated inside the markers or through the arrows represent the input values ​​for the gray level.

[0177] The low-brightness 32-level and high-brightness 128-level modes utilize PAM control operation with a relatively long illumination time to illuminate the light-emitting device. Because PAM control allows for control of the light-emitting device's intensity by controlling the amplitude, it enables precise control even at low brightness levels, which is difficult with PWM control.

[0178] The 96 intermediate levels utilize PAM+PWM control to illuminate the light-emitting device by varying both the light intensity and the pulse signal width within a moderate range. Since the 96 intermediate levels do not require extremely short illumination periods (extremely short pulse signals), they can be controlled without problems using PWM control. Because the control using the 96 intermediate levels varies both the light intensity and illumination time, it can be described as PAM+PWM control.

[0179] Figure 17A illustrates an example of the change in peak wavelength when the brightness of a light-emitting device is changed in PAM control. In this characteristic, the difference between the minimum and maximum values ​​is the chromaticity shift range (R1). When light emission operation is performed with PAM control from low brightness to high brightness, the chromaticity shift is large, which can degrade the display quality.

[0180] Figure 17B illustrates an example of the change in peak wavelength when the brightness of the light-emitting device is changed while performing the operation described using Figures 16A and 16B. Since PAM+PWM control is performed in the range near the minimum value in Figure 17A, the fluctuation of the peak wavelength in that range can be reduced. Therefore, the range of chromaticity shift (R2) can be made smaller than R1. In other words, by using a display device according to one embodiment of the present invention and performing the operation in the above example, the deterioration of display quality can be mitigated.

[0181] Figure 18 is a block diagram illustrating a display device according to one aspect of the present invention. The display device includes a pixel array 13, a source driver 20, and a gate driver 30. The pixel array 13 has pixels 10 arranged in the column and row directions. Pixels 10a to 10c described in this embodiment can be used for the pixels 10. The wiring is shown in a simplified manner, and wiring is provided to connect to the elements of the pixels 10 according to the aforementioned aspect of the present invention.

[0182] Furthermore, a slope potential supply circuit 40 is provided and electrically connected to the pixel 10. The slope potential supply circuit 40 is electrically connected to the slope potential generation circuit 50.

[0183] Sequential circuits such as shift registers can be used for the source driver 20, gate driver 30, and slope potential supply circuit 40. The source driver 20 can supply data potential VDATA to the pixel 10.

[0184] The source driver 20, gate driver 30, and slope potential supply circuit 40 can be formed on layer 310 as shown in Figures 3A and 3B. Alternatively, they can be provided on the connected IC chip using methods such as COF (chip on film), COG (chip on glass), or TCP (tape carrier package).

[0185] The example shown illustrates the gate driver 30 being positioned on one side of the pixel array 13, but two gate drivers may be positioned opposite each other across the pixel array 13 to divide the drive row.

[0186] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments.

[0187] (Embodiment 2) In this embodiment, the stacked structure of a display device according to one aspect of the present invention, as shown in Figures 3A and 3B, will be described.

[0188] Figure 19A shows a cross-sectional view of a display device 100A, which is one embodiment of the present invention. The display device 100A has a configuration in which a layer 310 on which transistors, such as those in the pixel circuit's driving circuit, are provided, a layer 320 on which transistors and wiring, etc., of the pixel circuit are provided, and a layer 330 on which light-emitting devices, such as LEDs, of the pixel circuit are provided are stacked in order.

[0189] In this embodiment, the display device is described as being divided into multiple layers for convenience, but the boundaries between layers are not strictly defined. For example, even if an element is described as an element of layer 310, if that element is near the boundary between layer 310 and layer 320, that element can also be considered an element of layer 320. Furthermore, if the function of the element is not hindered, that element may be located in a layer other than layer 310. In addition, in one embodiment of the present invention, other insulating layers and conductive layers may be provided as needed, in addition to the insulating layer and conductive layer of each layer. Furthermore, some of the insulating layers and conductive layers of each layer may be omitted as needed.

[0190] Layer 310 has transistors 140, which are components of the pixel circuit, such as the drive circuit (gate driver and source driver, or both), memory circuit, and arithmetic circuit. Since high-speed operation is required for transistor 140, it is preferable to use a transistor (hereinafter referred to as a Si transistor) that has silicon (such as single-crystal silicon, polycrystalline silicon, or amorphous silicon) in the channel formation region. Figure 19A shows an example in which single-crystal silicon is used for the substrate 150, and the transistor 140 has a channel formation region in the substrate 150.

[0191] Furthermore, a portion of the pixel circuit's driving circuit may be provided within an external IC chip connected to the pixel circuit.

[0192] The transistor 140 has a conductive layer 145, an insulating layer 144, an insulating layer 146, and a pair of low-resistance regions 143. The conductive layer 145 functions as the gate. The insulating layer 144 is located between the conductive layer 145 and the substrate 150 and functions as a gate insulating layer. The insulating layer 146 covers the sides of the conductive layer 145 and functions as a sidewall. The pair of low-resistance regions 143 are impurity-doped regions in the substrate 150, one of which functions as the source of the transistor and the other as the drain of the transistor. In addition, an element isolation layer 142 is provided around the transistor.

[0193] An insulating layer 149 is provided covering the transistor 140, and a conductive layer 148 is provided on the insulating layer 149. A conductive layer 147 is embedded in an opening in the insulating layer 149. The conductive layer 148 is electrically connected to one of a pair of low-resistance regions 143 via the conductive layer 147. An insulating layer 151 is provided covering the conductive layer 148. The conductive layer 148 functions as wiring. This wiring can electrically connect other transistors, pixel circuits, or other circuits in a circuit that has transistor 140 as an element.

[0194] Layer 320 includes a transistor 160, insulating layer 152, insulating layer 162, insulating layer 163, insulating layer 181, insulating layer 182, insulating layer 183, conductive layer 184a, conductive layer 184b, insulating layer 185, insulating layer 186, insulating layer 187, conductive layer 192, conductive layer 195, conductive layer 196, and conductive layer 197, which are components of the pixel circuit. Although one or more of these elements may be considered components of a transistor, in this embodiment they will not be included as components of a transistor in the description. Note that each conductive layer and each insulating layer of layer 320 is not limited to a single-layer structure but may also be a multilayer structure.

[0195] The insulating layer 152 is provided on layer 310. The insulating layer 152 functions as a barrier layer that prevents impurities such as water and hydrogen from diffusing from layer 310 to transistor 160, and prevents oxygen from detaching from the metal oxide layer 165 of transistor 160 towards layer 310. As the insulating layer 152, for example, a film that is less permeable to the diffusion of hydrogen and oxygen than a silicon oxide film can be used, such as an aluminum oxide film, a hafnium oxide film, or a silicon nitride film.

[0196] The transistor 160 has a conductive layer 161, an insulating layer 163, an insulating layer 164, a metal oxide layer 165, a pair of conductive layers 166, an insulating layer 167, a conductive layer 168, and the like.

[0197] The transistor 160 is preferably an OS transistor having a metal oxide layer 165 in the channel formation region. The metal oxide layer 165 has a first region overlapping with one of the pair of conductive layers 166, a second region overlapping with the other of the pair of conductive layers 166, and a third region between the first region and the second region.

[0198] OS transistors do not require bonding processes and can be formed in the region overlapping with Si transistors via an insulating layer. Therefore, stacked devices can be manufactured using a simple process, reducing manufacturing costs.

[0199] Furthermore, OS transistors have features such as higher mobility, faster operation, and greater reliability compared to transistors using amorphous silicon. Also, the metal oxides used in OS transistors can be formed in a thin-film deposition process, eliminating the need for laser equipment and other devices required in the crystallization process of polycrystalline silicon. Therefore, using OS transistors makes it possible to manufacture inexpensive and highly reliable display devices.

[0200] A conductive layer 161 and an insulating layer 162 are provided on the insulating layer 152, and an insulating layer 163 is provided covering the conductive layer 161 and the insulating layer 162. An insulating layer 164 is provided on the insulating layer 163, and a metal oxide layer 165 is provided on the insulating layer 164.

[0201] The conductive layer 161 functions as a gate electrode, and the insulating layers 163 and 164 function as gate insulating layers. The conductive layer 161 has a region that overlaps with the metal oxide layer 165 via the insulating layers 163 and 164. The insulating layer 163 is preferably formed of a material that functions as a barrier layer, similar to the insulating layer 152. For the insulating layer 164 in contact with the metal oxide layer 165, it is preferable to use an oxide insulating film such as a silicon oxide film.

[0202] A pair of conductive layers 166 are provided spaced apart on the metal oxide layer 165. One of the pair of conductive layers 166 functions as the source of the transistor, and the other functions as the drain. An insulating layer 181 is provided covering the metal oxide layer 165 and the pair of conductive layers 166, and an insulating layer 182 is provided on the insulating layer 181.

[0203] The insulating layers 181 and 182 are provided with openings that reach the metal oxide layer 165, and the insulating layer 167 and the conductive layer 168 are embedded inside these openings. These openings are located in positions that overlap with a third region of the metal oxide layer 165. The insulating layer 167 has regions that overlap with the sides of the insulating layer 181 and the insulating layer 182. The conductive layer 168 has regions that overlap with the sides of the insulating layer 181 and the insulating layer 182 via the insulating layer 167.

[0204] The conductive layer 168 functions as a gate electrode, and the insulating layer 167 functions as a gate insulating layer. The conductive layer 168 has a region that overlaps with the metal oxide layer 165 via the insulating layer 167.

[0205] Furthermore, insulating layers 183 and 185 are provided, covering the upper surfaces of insulating layer 182, insulating layer 167, and conductive layer 168.

[0206] The insulating layer 181 and insulating layer 183 are preferably formed from a material that functions as a barrier layer, similar to the insulating layer 152. By covering the pair of conductive layers 166 with the insulating layer 181, oxidation of the pair of conductive layers 166 by oxygen contained in the insulating layer 182 can be suppressed.

[0207] A plug electrically connected to one of the pair of conductive layers 166 and conductive layer 195 is embedded in an opening provided in insulating layers 181, 182, 183, and 185. The plug may have a conductive layer 184b in contact with the side surface of the opening and the upper surface of one of the pair of conductive layers 166, and a conductive layer 184a embedded inside the conductive layer 184b. The conductive layer 184b is preferably made of a conductive material that does not easily allow hydrogen and oxygen to diffuse.

[0208] A conductive layer 192, a conductive layer 195, and an insulating layer 186 are provided on the insulating layer 185. A conductive layer 196, a conductive layer 197, and an insulating layer 187 are provided on the insulating layer 186. The conductive layer 195 is electrically connected to the conductive layer 196 via a plug. The conductive layer 192 is electrically connected to the conductive layer 197 via a plug.

[0209] Here, the insulating layer 186 can have a planarization function. The insulating layer 187, the conductive layer 196, and the conductive layer 197 function as a bonding layer. The conductive layer 196 and the conductive layer 197 have regions embedded in the insulating layer 187, and the surfaces of the conductive layer 196, the conductive layer 197, and the insulating layer 187 are planarized so that their heights are the same.

[0210] Layer 330 has a light-emitting device 110 provided on the support layer 118. The sides of the light-emitting device 110 are sealed with an insulating layer 189, and the upper surface of the light-emitting device 110 is provided with an insulating layer 188, a conductive layer 198, and a conductive layer 199. The conductive layer 198 is electrically connected to one electrode of the light-emitting device 110, and the conductive layer 199 is electrically connected to the other electrode of the light-emitting device 110. It is preferable to use an insulating resin layer or the like as the insulating layer 189.

[0211] Here, the insulating layer 188, the conductive layer 198, and the conductive layer 199 function as bonding layers. The conductive layer 198 and the conductive layer 199 have regions embedded in the insulating layer 188, and the surfaces of the conductive layer 198, the conductive layer 199, and the insulating layer 188 are flattened so that their heights are the same.

[0212] The surface of layer 330 (insulating layer 188, conductive layer 198, and conductive layer 199) is bonded to the surface of layer 320 (insulating layer 187, conductive layer 196, and conductive layer 197). Here, insulating layer 188 is bonded to insulating layer 187. Conductive layer 198 is bonded to conductive layer 196, and the two are electrically connected. Conductive layer 199 is bonded to conductive layer 197, and the two are electrically connected.

[0213] It is preferable that insulating layer 188 and insulating layer 187 are composed of the same component. Furthermore, it is preferable that conductive layer 198 and conductive layer 196 are formed of the same metal as their main component. Furthermore, it is preferable that conductive layer 199 and conductive layer 197 are formed of the same metal as their main component.

[0214] For example, the insulating layers 187 and 188 are preferably formed using a single layer or laminate having one or more inorganic insulating materials such as silicon oxide, silicon oxide nitride, silicon oxide nitride, silicon nitride, aluminum oxide, hafnium oxide, and titanium nitride.

[0215] Furthermore, the conductive layers 196 to 199 can be made of copper, aluminum, tin, zinc, tungsten, silver, platinum, or gold. For ease of bonding, copper, aluminum, tungsten, or gold are preferred.

[0216] Transistor 160 can be used as a transistor constituting a pixel circuit. Transistor 140 can be used as a transistor constituting a drive circuit (such as one or both of a gate driver and a source driver) for driving the pixel circuit. Transistor 140 may also be a transistor constituting a pixel circuit. Furthermore, transistors 140 and 160 can also be used as transistors constituting various circuits such as arithmetic circuits and memory circuits.

[0217] This configuration allows for the formation of elements such as transistors in the drive circuit, as well as elements such as transistors in the pixel circuit, directly beneath the light-emitting device. This enables miniaturization of the display device compared to cases where the drive circuit is located outside the display unit. Furthermore, it allows for the realization of a display device with a narrow bezel (a small non-display area).

[0218] The light-emitting device 110 has a semiconductor layer 173, a light-emitting layer 174, and a semiconductor layer 175, which are arranged sequentially on the support layer 118 in that order. A conductive layer 176 is also provided on the semiconductor layer 173. The laminated light-emitting layer 174 and semiconductor layer 175 and the conductive layer 176 are covered with an insulating layer 117. The semiconductor layer 175 is electrically connected to the conductive layer 198 through a first opening provided in the insulating layer 117. The conductive layer 176 is electrically connected to the conductive layer 199 through a second opening provided in the insulating layer 117.

[0219] For example, a support layer 118 is formed on a sapphire substrate by epitaxial growth, and a semiconductor layer 173, an emissive layer 174, another semiconductor layer 175, an insulating layer 117, and a conductive layer 176 formed on the support layer 118 are processed to form multiple light-emitting devices 110. The multiple light-emitting devices formed in this process can be called light-emitting devices formed in a monolithic structure.

[0220] Then, an insulating layer 189 and a bonding layer are formed on the light-emitting device 110, and multiple light-emitting devices 110 are bonded to the layer 320 in the same process. Finally, the sapphire substrate is peeled off to obtain the structure shown in the display device 100A.

[0221] The light-emitting layer 174 is sandwiched between semiconductor layers 173 and 175. In the light-emitting layer 174, electrons and holes combine to emit light. One of the semiconductor layers 173 and 175 can be an n-type semiconductor layer, and the other can be a p-type semiconductor layer. Furthermore, the light-emitting layer 174 can be an n-type, i-type, or p-type semiconductor layer.

[0222] The laminated structure, comprising a semiconductor layer 173, a light-emitting layer 174, and a semiconductor layer 175, is formed to emit light such as red, green, blue, blue-violet, violet, or ultraviolet light. For example, compounds containing group 13 and group 15 elements (also called group 3-5 compounds) can be used in this laminated structure. Examples of group 13 elements include aluminum, gallium, and indium. Examples of group 15 elements include nitrogen, phosphorus, arsenic, and antimony.

[0223] For example, a pn junction or pin junction can be formed using gallium-phosphorus compounds, gallium-arsenide compounds, gallium-aluminum-arsenide compounds, aluminum-gallium-indium-phosphorus compounds, gallium nitride, indium-gallium nitride compounds, selenium-zinc compounds, etc., to fabricate a light-emitting device that emits the desired light. Other compounds may also be used.

[0224] Furthermore, the pn junction or pin junction of the light-emitting device 110 may be a homojunction, a heterojunction, or a double heterojunction. Other light-emitting devices, such as those with quantum well junctions or those using nanocolumns, may also be used.

[0225] For example, materials such as gallium nitride can be used for light-emitting devices that emit light in the ultraviolet to blue wavelength range. Materials such as indium-gallium nitride compounds can be used for light-emitting devices that emit light in the ultraviolet to green wavelength range. Materials such as aluminum-gallium-indium-phosphorus compounds or gallium-arsenide compounds can be used for light-emitting devices that emit light in the infrared wavelength range. Materials such as gallium-arsenide compounds can be used for light-emitting devices that emit light in the infrared wavelength range.

[0226] If multiple light-emitting devices 110 arranged on the same surface have different light-emitting colors, such as R (red), G (green), and B (blue), then a color image can be displayed.

[0227] Furthermore, all light-emitting devices 110 provided on the same surface may be configured to emit light of the same color. In this case, the light emitted from the light-emitting layer 174 is taken out of the display device via one or both of the color conversion layer and the coloring layer. This configuration will be described in detail in Embodiment 3.

[0228] Furthermore, the display device of this embodiment may have a light-emitting device that emits infrared light. The light-emitting device that emits infrared light can be used, for example, as a light source for an infrared light sensor.

[0229] Although Figure 19A shows a configuration in which layer 330 is bonded to layer 320, a configuration in which a single light-emitting device 110 is mounted using a flip-chip bonder or the like, as shown in the display device 100B in Figure 19B, and then sealed with an insulating layer 189, is also possible.

[0230] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments.

[0231] (Embodiment 3) In this embodiment, a configuration in which a color conversion layer is provided on the light emission side of the light emitting device with respect to the display device described in Embodiment 2 will be described. Note that detailed descriptions of the components common to Embodiment 2 are omitted.

[0232] FIG. 20 shows a cross-sectional view of the display device 100E. The display device 100E includes a pixel 20R that emits red light, a pixel 20G that emits green light, and a pixel 20B that emits blue light. Further, a layer 340 is provided on the layer 330 where the light emitting device is provided. The layer 340 is provided with a color conversion layer, a coloring layer, a light shielding layer, and the like.

[0233] The pixel 20R includes a light emitting device 110R. The pixel 20G includes a light emitting device 110G. The pixel 20B includes a light emitting device 110B. Each of the light emitting devices 110R, 110G, and 110B emits light of the same color. That is, each of the light emitting devices 110R, 110G, and 110B can have the same configuration.

[0234] Specifically, each of the light emitting devices 110R, 110G, and 110B preferably emits blue light. To form a color image, pixels that emit the three primary colors of light, red (R), green (G), and blue (B), can be used. In the display device described in this embodiment, a color conversion layer is used in the pixel to convert the light emitted by the light emitting device into light of a required color and emit it to the outside. Here, if a light emitting device that emits blue light is used, a color conversion layer is not required for the pixel that emits blue light, so the manufacturing cost can be reduced.

[0235] The red pixel 20R is provided with a color conversion layer 360R and a coloring layer 361R in the area overlapping with the light-emitting device 110R. The light emitted by the light-emitting device 110R is converted from blue to red in the color conversion layer 360R, and the purity of the red light is increased in the coloring layer 361R before being emitted to the outside of the display device 100E. Note that a configuration without the coloring layer 361R is also possible.

[0236] The green pixels 20G are provided with a color conversion layer 360G and a coloring layer 361G in the area overlapping with the light-emitting device 110G. The light emitted by the light-emitting device 110G is converted from blue to green in the color conversion layer 360G, and the purity of the green light is increased in the coloring layer 361G before being emitted outside the display device 100E. Note that a configuration without the coloring layer 361G is also possible.

[0237] A coloring layer 361B is provided in the blue pixel 20B in the area overlapping with the light-emitting device 110B. The light emitted by the light-emitting device 110B has its blue light purity enhanced by the coloring layer 361B and is emitted to the outside of the display device 100E. Note that a configuration without the coloring layer 361B is also possible. As mentioned above, the color conversion layer can be omitted in the blue pixel 20B.

[0238] In the display device 100E, only one type of light-emitting device needs to be manufactured on the substrate, thus simplifying the manufacturing equipment and process compared to manufacturing multiple types of light-emitting devices.

[0239] A light-shielding layer 350 is provided between each color pixel. The light-shielding layer 350 is positioned to block at least the light emitted laterally by the light-emitting device 110. If necessary, it may also be provided to block the light emitted obliquely by the light-emitting device 110. In addition, a light-shielding layer 351 is provided on the support layer 118, covering the area around the pixels.

[0240] By providing the light-shielding layers 350 and 351, it is possible to suppress the light emitted by the light-emitting device from entering adjacent pixel areas of other colors, thereby preventing color mixing. Therefore, the display quality of the display device can be improved. Alternatively, a configuration in which only one of the light-shielding layers 350 or 351 is provided may also be used.

[0241] The materials constituting the light-shielding layers 350 and 351 are not particularly limited. For example, inorganic materials such as metals, or organic materials such as resins containing pigments (such as carbon black) or dyes can be used. The light-shielding layer 351 may also be formed by laminating colored layers of each color. For example, it can be formed by laminating three colored layers of red, green, and blue.

[0242] Furthermore, each of the light-emitting devices 110R, 110G, and 110B may be configured to emit light with a wavelength that has a higher photon energy than blue light. For example, light-emitting devices that can emit blue-violet, violet, or ultraviolet (UV) light can be used. By using light with high photon energy, color conversion can be performed efficiently in the color conversion layer.

[0243] In this case, as shown in the display device 100F in Figure 21, the blue pixels 20B are provided with a color conversion layer 360B and a coloring layer 361B in the area overlapping with the light-emitting device 110B. The light emitted by the light-emitting device 110B is converted from blue-violet, violet, or ultraviolet to blue in the color conversion layer 360B, and the purity of the blue light is increased in the coloring layer 361B before being emitted to the outside of the display device 100E. Note that a configuration without the coloring layer 361B is also possible.

[0244] It is preferable to use a phosphor or a quantum dot (QD) as the color conversion layer. In particular, quantum dots have a narrow peak width in their emission spectrum, allowing for emission with good color purity. This can improve the display quality of the display device.

[0245] The color conversion layer can be formed using methods such as droplet ejection (e.g., inkjet), coating, imprint, and various printing methods (screen printing, offset printing). Alternatively, a color conversion film such as a quantum dot film may be used.

[0246] When processing the film that will become the color conversion layer, lithography can be used. For example, a resist mask can be formed on the thin film to be processed, the thin film can be processed by etching or the like, and the resist mask can be removed. Alternatively, a method can be used in which a photosensitive thin film is formed, and then exposed and developed to process the thin film into the desired shape. For example, an island-shaped color conversion layer can be formed by forming a thin film using a photosensitive material mixed with quantum dots, and then processing the thin film using lithography.

[0247] There are no particular limitations on the materials that constitute quantum dots. Examples include Group 14 elements, Group 15 elements, Group 16 elements, compounds consisting of multiple Group 14 elements, compounds of elements belonging to Groups 4 through 14 and Group 16 elements, compounds of Group 2 elements and Group 16 elements, compounds of Group 13 elements and Group 15 elements, compounds of Group 13 elements and Group 17 elements, compounds of Group 14 elements and Group 15 elements, compounds of Group 11 elements and Group 17 elements, iron oxides, titanium oxides, chalcogenide spinels, and various semiconductor clusters.

[0248] Specifically, cadmium selenide, cadmium sulfide, cadmium telluride, zinc selenide, zinc oxide, zinc sulfide, zinc telluride, mercury sulfide, mercury selenide, mercury telluride, indium arsenide, indium phosphide, gallium arsenide, gallium phosphide, indium nitride, gallium nitride, indium antimonide, gallium antimonide, aluminum phosphide, aluminum arsenide, aluminum antimonide, lead selenide, lead telluride, lead sulfide, indium selenide, telluride Indium sulfide, indium sulfide, gallium selenide, arsenic sulfide, arsenic selenide, arsenic telluride, antimony sulfide, antimony selenide, antimony telluride, bismuth sulfide, bismuth selenide, bismuth telluride, silicon, silicon carbide, germanium, tin, selenium, tellurium, boron, carbon, phosphorus, boron nitride, boron phosphide, boron arsenide, aluminum nitride, aluminum sulfide, barium sulfide, barium selenide, barium telluride, calcium sulfide, gallium selenide Calcium, calcium telluride, beryllium sulfide, beryllium selenide, beryllium telluride, magnesium sulfide, magnesium selenide, germanium sulfide, germanium selenide, germanium telluride, tin sulfide, tin selenide, tin telluride, lead oxide, copper fluoride, copper chloride, copper bromide, copper iodide, copper oxide, copper selenide, nickel oxide, cobalt oxide, cobalt sulfide, iron oxide, iron sulfide, manganese oxide, molybdenum sulfide, vanadium oxide, tungsten oxide, tantalum oxide Examples include titanium dioxide, zirconium oxide, silicon nitride, germanium nitride, aluminum oxide, barium titanate, compounds of selenium, zinc, and cadmium, compounds of indium, arsenic, and phosphorus, compounds of cadmium, selenium, and sulfur, compounds of cadmium, selenium, and tellurium, compounds of indium, gallium, and arsenic, compounds of indium, gallium, and selenium, compounds of indium, selenium, and sulfur, compounds of copper, indium, and sulfur, and combinations thereof. In addition, so-called alloy-type quantum dots, whose composition is expressed in any ratio, may also be used.

[0249] Examples of the structure of quantum dots include core type, core-shell type, core-multi-shell type, etc. Also, since quantum dots have a high proportion of surface atoms, they are highly reactive and prone to aggregation. Therefore, in order to prevent aggregation of quantum dots and enhance their dispersibility in a dispersion medium, it is preferable that a protective agent is attached to the surface of the quantum dots or a protecting group is provided. This can also reduce the reactivity and improve the electrical stability.

[0250] As the size of quantum dots decreases, the bandgap increases. Therefore, the size of quantum dots is appropriately adjusted so as to obtain light of a desired wavelength. As the size of the crystal decreases, the emission of quantum dots shifts to the blue side, that is, to the high-energy side. Therefore, by changing the size of quantum dots, the emission wavelength can be adjusted over the wavelength regions of the spectra in the ultraviolet region, visible region, and infrared region. The size (diameter) of quantum dots is, for example, 0.5 nm or more and 20 nm or less, preferably 1 nm or more and 10 nm or less. The narrower the size distribution of quantum dots, the narrower the emission spectrum and the better the color purity of the emission can be obtained. Also, the shape of quantum dots is not particularly limited and may be spherical, rod-shaped, disk-shaped, or other shapes. Quantum rods, which are rod-shaped quantum dots, have a function of exhibiting light with directivity.

[0251] The colored layer is a colored layer that transmits light in a specific wavelength range. For example, a color filter that transmits light in the wavelength range of red, green, blue, or yellow can be used. Examples of materials that can be used for the colored layer include metal materials, resin materials, resin materials containing pigments or dyes, etc.

[0252] Note that although the basic configurations of the display device 100E and the display device 100F were exemplified using the configuration of the display device 100A, the display device 100B shown in the second embodiment can also be applied.

[0253] This embodiment can be implemented by appropriately combining with the configurations described in other embodiments.

[0254] (Embodiment 4) In this embodiment, a display device according to one aspect of the present invention will be described with reference to Figures 22A and 22B.

[0255] The display device of this embodiment can be a high-definition display device. Therefore, the display device of this embodiment can be used, for example, as a display unit for information terminals (wearable devices) such as wristwatches and bracelets, as well as as a display unit for wearable devices that can be worn on the head, such as VR (Virtual Reality) devices such as head-mounted displays (HMDs) and AR (Augmented Reality) devices such as glasses.

[0256] Figure 22A shows a perspective view of the display module 280. The display module 280 includes the display device 100A described in the previous embodiment and an FPC 290. Note that the display device included in the display module 280 is not limited to the display device 100A, but may be any of the display devices 100B, 100E, or 100F.

[0257] The display module 280 has substrates 291 and 292. The display module 280 has a display unit 281. The display unit 281 is an area in the display module 280 that displays an image, and is an area in which light from each pixel provided in the pixel unit 284, which will be described later, can be seen.

[0258] Figure 22B shows a schematic perspective view illustrating the configuration of the substrate 291. On the substrate 291, a circuit section 282, a pixel circuit section 283 on the circuit section 282, and a pixel section 284 on the pixel circuit section 283 are stacked. In addition, a terminal section 285 for connecting to the FPC 290 is provided in the portion of the substrate 291 that does not overlap with the pixel section 284. The terminal section 285 and the circuit section 282 are electrically connected by a wiring section 286, which is composed of multiple wires.

[0259] The pixel section 284 has a plurality of pixels 284a arranged periodically. A magnified view of one pixel 284a is shown on the right side of Figure 22B. Each pixel 284a has a plurality of subpixels (subpixels 10R, 10G, 10B) with different emission colors. The pixel configuration described in the previous embodiment can be applied to these subpixels.

[0260] The pixel circuit section 283 has a plurality of pixel circuits 283a arranged periodically.

[0261] A single pixel circuit 283a is a circuit that controls the driving of multiple elements in a single pixel 284a. A single pixel circuit 283a can be configured to have three circuits that control the light emission of a single light-emitting device. For example, a single pixel circuit 283a can be configured to have at least one selection transistor, one current control transistor (driving transistor), and a capacitor for each light-emitting device. In this case, a gate signal is input to the gate of the selection transistor, and a source signal is input to the source. This realizes an active-matrix type display device.

[0262] The circuit section 282 has circuits for driving each pixel circuit 283a of the pixel circuit section 283. For example, it is preferable to have one or both of a gate line drive circuit and a source line drive circuit. In addition, it may have at least one of the following: an arithmetic circuit, a memory circuit, and a power supply circuit.

[0263] The FPC290 functions as wiring for supplying video signals or power potential, etc., to the circuit section 282 from an external source. An IC may also be mounted on the FPC290.

[0264] The display module 280 can be configured such that one or both of the pixel circuit section 283 and the circuit section 282 are superimposed on the lower side of the pixel section 284, thereby enabling an extremely high aperture ratio (effective display area ratio) of the display section 281. For example, the aperture ratio of the display section 281 can be 40% or more and less than 100%, preferably 50% or more and 95%, and more preferably 60% or more and 95%. Furthermore, it is possible to arrange the pixels 284a at an extremely high density, enabling an extremely high resolution of the display section 281. For example, it is preferable that the pixels 284a in the display section 281 are arranged with a resolution of 20000 ppi or more, preferably 3000 ppi or more, more preferably 5000 ppi or more, and even more preferably 6000 ppi or more, and with a resolution of 20000 ppi or less, or 30000 ppi or less.

[0265] Because such a display module 280 is extremely high-resolution, it can be suitably used in VR devices such as HMDs or AR devices such as glasses. For example, even in a configuration where the display part of the display module 280 is viewed through lenses, the display module 280 has an extremely high-resolution display part 281, so even when the display part is magnified with lenses, pixels are not visible, and a highly immersive display can be achieved. Furthermore, the display module 280 is not limited to this and can be suitably used in electronic devices with relatively small display parts. For example, it can be suitably used in the display part of wearable electronic devices such as watches.

[0266] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments.

[0267] (Embodiment 5) In this embodiment, an electronic device according to one aspect of the present invention will be described with reference to Figures 23A to 23D.

[0268] The electronic device of this embodiment has a display device according to one aspect of the present invention in its display unit. The display device according to one aspect of the present invention is easily made high-definition and high-resolution. Therefore, it can be used in the display units of various electronic devices.

[0269] A display device according to one aspect of the present invention can be used in electronic devices having a relatively small display area because it can increase the resolution. Examples of such electronic devices include wristwatch-type and bracelet-type information terminals (wearable devices), as well as wearable devices that can be worn on the head, such as VR devices such as head-mounted displays, AR devices such as glasses, and MR (Mixed Reality) devices.

[0270] A display device according to one aspect of the present invention preferably has an extremely high resolution such as HD (1280 x 720 pixels), FHD (1920 x 1080 pixels), WQHD (2560 x 1440 pixels), WQXGA (2560 x 1600 pixels), 4K (3840 x 2160 pixels), or 8K (7680 x 4320 pixels). In particular, a resolution of 4K, 8K, or higher is preferred. Furthermore, the pixel density (resolution) of the display device according to one aspect of the present invention is preferably 100 ppi or more, preferably 300 ppi or more, more preferably 500 ppi or more, more preferably 1000 ppi or more, more preferably 2000 ppi or more, more preferably 3000 ppi or more, more preferably 5000 ppi or more, and even more preferably 7000 ppi or more. By using a display device that has either high resolution or high detail, or both, it becomes possible to enhance the sense of presence and depth in electronic devices such as portable or home-use devices. Furthermore, there are no particular limitations on the aspect ratio of the display device according to one embodiment of the present invention. For example, the display device can support various aspect ratios such as 1:1 (square), 4:3, 16:9, and 16:10.

[0271] The electronic device of this embodiment may have sensors (including those with functions for detecting, detecting, or measuring force, displacement, position, velocity, acceleration, angular velocity, rotational speed, distance, light, liquid, magnetism, temperature, chemical substances, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor, or infrared radiation).

[0272] The electronic device of this embodiment can have a variety of functions. For example, it can have a function to display various information (still images, videos, text images, etc.) on the display unit, a touch panel function, a function to display a calendar, date or time, a function to execute various software (programs), a wireless communication function, a function to read programs or data recorded on a recording medium, and so on.

[0273] Figures 23A to 23D illustrate an example of a wearable device that can be worn on the head. These wearable devices have at least one of the following functions: a function to display AR content, a function to display VR content, a function to display SR (Substitutional Reality) content, and a function to display MR content. By having an electronic device that has the function to display at least one of the following content types, such as AR, VR, SR, and MR, it is possible to enhance the user's sense of immersion.

[0274] The electronic device 700A shown in Figure 23A and the electronic device 700B shown in Figure 23B each include a pair of display panels 751, a pair of housings 721, a communication unit (not shown), a pair of mounting units 723, a control unit (not shown), an imaging unit (not shown), a pair of optical members 753, a frame 757, and a pair of nose pads 758.

[0275] A display device according to one embodiment of the present invention can be applied to the display panel 751. Therefore, an electronic device capable of displaying extremely high resolution can be created.

[0276] Furthermore, if the display device has a light-receiving device, it can capture an image of the pupil and perform iris authentication. It can also perform eye-tracking using the same light-receiving device. Eye-tracking allows the device to identify what the user is looking at and their location, enabling it to select functions on the electronic device and execute software accordingly.

[0277] Electronic devices 700A and 700B can each project an image displayed on the display panel 751 onto the display area 756 of the optical element 753. Because the optical element 753 is translucent, the user can see the image displayed on the display area superimposed on the transmitted image visible through the optical element 753. Therefore, electronic devices 700A and 700B are electronic devices capable of AR display.

[0278] Electronic devices 700A and 700B may be equipped with cameras capable of capturing images of the area in front of them as imaging units. Furthermore, electronic devices 700A and 700B can each be equipped with acceleration sensors such as gyro sensors to detect the orientation of the user's head and display an image corresponding to that orientation in the display area 756.

[0279] The communications unit has a wireless communication device, which can supply video signals and the like. Alternatively, instead of the wireless communication device, or in addition to the wireless communication device, it may be equipped with a connector to which a cable supplying video signals and power potential can be connected.

[0280] Furthermore, electronic devices 700A and 700B are equipped with batteries that can be charged wirelessly, wired, or both.

[0281] The electronic device 800A shown in Figure 23C and the electronic device 800B shown in Figure 23D each include a pair of display units 820, a housing 821, a communication unit 822, a pair of mounting units 823, a control unit 824, a pair of imaging units 825, and a pair of lenses 832.

[0282] A display device according to one embodiment of the present invention can be applied to the display unit 820. Therefore, an electronic device capable of displaying extremely high resolution can be created. This allows the user to experience a high level of immersion.

[0283] The display unit 820 is located inside the housing 821, in a position where it can be seen through the lens 832. Furthermore, by displaying different images on a pair of display units 820, a three-dimensional display using parallax can also be performed.

[0284] Electronic devices 800A and 800B can be described as electronic devices for VR. A user wearing either electronic device 800A or electronic device 800B can view the image displayed on the display unit 820 through the lens 832.

[0285] It is preferable that electronic devices 800A and 800B each have a mechanism that allows adjustment of the left and right positions of the lens 832 and the display unit 820 so that they are in the optimal position according to the user's eye position. It is also preferable that they have a mechanism that adjusts the focus by changing the distance between the lens 832 and the display unit 820.

[0286] The attachment portion 823 allows the user to attach the electronic device 800A or 800B to their head. While the attachment portion 823 is exemplified in Figure 23C and other figures as resembling the temples (or arms) of eyeglasses, it is not limited to this shape. The attachment portion 823 only needs to be wearable by the user; for example, it may be helmet-shaped or band-shaped.

[0287] The imaging unit 825 has the function of acquiring external information. The data acquired by the imaging unit 825 can be output to the display unit 820. An image sensor can be used in the imaging unit 825. In addition, multiple cameras may be provided to accommodate multiple angles of view, such as telephoto and wide-angle.

[0288] Although an example with an imaging unit 825 is shown here, any distance measuring sensor (hereinafter also referred to as a detection unit) capable of measuring the distance to an object can be provided. In other words, the imaging unit 825 is one form of a detection unit. As the detection unit, for example, an image sensor or a distance image sensor such as LiDAR (Light Detection and Ranging) can be used. By using the image obtained by the camera and the image obtained by the distance image sensor, more information can be acquired, enabling more accurate gesture control.

[0289] The electronic device 800A may have a vibration mechanism that functions as a bone conduction earphone. For example, a configuration having such a vibration mechanism can be applied to one or more of the display unit 820, housing 821, and mounting unit 823. This allows users to enjoy video and audio simply by wearing the electronic device 800A, without needing separate audio equipment such as headphones, earphones, or speakers.

[0290] Electronic devices 800A and 800B may each have input terminals. These input terminals can be connected to cables that supply video signals from video output devices, etc., and power for charging batteries located within the electronic devices.

[0291] An electronic device according to one aspect of the present invention may have a function for wireless communication with an earphone 750. The earphone 750 has a communication unit (not shown) and has a wireless communication function. The earphone 750 can receive information (e.g., voice data) from the electronic device through its wireless communication function. For example, the electronic device 700A shown in Figure 23A has a function for transmitting information to the earphone 750 through its wireless communication function. Also, for example, the electronic device 800A shown in Figure 23C has a function for transmitting information to the earphone 750 through its wireless communication function.

[0292] Furthermore, the electronic device may have an earphone section. The electronic device 700B shown in Figure 23B has an earphone section 727. For example, the earphone section 727 and the control section can be connected to each other by a wire. Part of the wiring connecting the earphone section 727 and the control section may be located inside the housing 721 or the mounting section 723.

[0293] Similarly, the electronic device 800B shown in Figure 23D has an earphone unit 827. For example, the earphone unit 827 and the control unit 824 can be connected to each other by a wire. Part of the wiring connecting the earphone unit 827 and the control unit 824 may be located inside the housing 821 or the mounting unit 823. Also, the earphone unit 827 and the mounting unit 823 may have magnets. This allows the earphone unit 827 to be fixed to the mounting unit 823 by magnetic force, which is preferable as it facilitates storage.

[0294] Furthermore, the electronic device may have an audio output terminal to which earphones or headphones can be connected. The electronic device may also have an audio input terminal and / or an audio input mechanism. For example, a sound-collecting device such as a microphone can be used as the audio input mechanism. By having an audio input mechanism, the electronic device may be given the function of a so-called headset.

[0295] Thus, as one embodiment of the present invention, both eyeglass-type (electronic devices 700A and 700B, etc.) and goggle-type (electronic devices 800A and 800B, etc.) are preferred as electronic devices.

[0296] Furthermore, an electronic device according to one aspect of the present invention can transmit information to earphones via wired or wireless means.

[0297] Furthermore, an electronic device to which a display device according to one aspect of the present invention can be applied may be connected to an external server via a network. Alternatively, processing requiring high computing power may be performed on a server connected via the network, rather than on the electronic device itself. Such processing is also known as thin client processing, where the user-side (client-side) terminal (in this case, the electronic device) executes only limited processing, and advanced processing such as application execution and management is performed on the server side, thereby reducing the scale of processing on the client-side terminal. As a result, there is no need to use a computing device with high computing power in the electronic device, making it easier to reduce costs, weight, and size. Furthermore, in an electronic device according to one aspect of the present invention, processing may be performed in combination with the above-mentioned thin client processing and processing requiring high computing power on the electronic device side.

[0298] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments. [Explanation of Symbols]

[0299] BG: Node, BS: Node, GL: Gate line, SLO: Slope potential, VDATA: Data potential, VRESA: Reset potential, VRESW: Reset potential, VSBG: Potential, 10a: Pixel, 10B: Sub-pixel, 10b: Pixel, 10c: Pixel, 10G: Sub-pixel, 10R: Sub-pixel, 10: Pixel, 11: Pulse signal generation unit, 13: Pixel array, 20B: Pixel, 20G: Pixel, 20R: Pixel, 20: Source driver, 30: Gate driver, 32: Grayscale, 40: Slope potential supply circuit, 50: Slope potential generation circuit, 100A: Display device, 100B: Display device, 10 0E: Display device, 100F: Display device, 101: Transistor, 102: Transistor, 103: Transistor, 104: Transistor, 105: Transistor, 106: Transistor, 107: Transistor, 108: Transistor, 109: Transistor, 110B: Light-emitting device, 110G: Light-emitting device, 110R: Light-emitting device, 110: Light-emitting device, 111: Capacitor, 112: Capacitor, 113: Capacitor, 114: Capacitor, 115: Transistor, 116: Transistor, 117: Insulating layer, 118: Support layer, 121: Wiring, 1 22: Wiring, 123: Wiring, 124: Wiring, 125: Wiring, 127: Wiring, 128: Wiring, 129: Wiring, 131: Wiring, 132: Wiring, 133: Wiring, 134: Wiring, 135: Wiring, 136: Wiring, 137: Wiring, 138: Wiring, 139: Wiring, 140: Transistor, 142: Element isolation layer, 143: Low resistance region, 144: Insulating layer, 145: Conductive layer, 146: Insulating layer, 147: Conductive layer, 148: Conductive layer, 149: Insulating layer, 150: Substrate, 151: Insulating layer, 152: Insulating layer, 160: Transistor, 161: Conductive layer, 162: Insulating layer, 163: Insulating layer, 16 4: Insulating layer, 165: Metal oxide layer, 166: Conductive layer, 167: Insulating layer, 168: Conductive layer, 173: Semiconductor layer, 174: Light-emitting layer, 175: Semiconductor layer, 176: Conductive layer, 181: Insulating layer, 182: Insulating layer, 183: Insulating layer, 184a: Conductive layer, 184b: Conductive layer, 185: Insulating layer, 186: Insulating layer, 187: Insulating layer, 188: Insulating layer, 189: Insulating layer, 192: Conductive layer, 195: Conductive layer, 196: Conductive layer, 197: Conductive layer, 198: Conductive layer, 199: Conductive layer, 255: Grayscale, 280: Display module, 281: Display unit, 282: Circuit unit, 283a: Pixel circuit,283: Pixel circuit section, 284a: Pixel, 284: Pixel section, 285: Terminal section, 286: Wiring section, 290: FPC, 291: Substrate, 292: Substrate, 310: Layer, 311: Si transistor, 312: Functional circuit, 320: Layer, 321: OS transistor, 330: Layer, 331: LED array, 340: Layer, 350: Light-shielding layer, 351: Light-shielding layer, 360B: Color conversion layer, 360G: Color conversion layer, 360R: Color conversion layer, 361B: Coloring layer, 361G: Coloring layer ,361R:Coloring layer, 700A:Electronic equipment, 700B:Electronic equipment, 721:Housing, 723:Mounting part, 727:Earphone part, 750:Earphone, 751:Display panel, 753:Optical component, 756:Display area, 757:Frame, 758:Nose pad, 800A:Electronic equipment, 800B:Electronic equipment, 820:Display part, 821:Housing, 822:Communication part, 823:Mounting part, 824:Control unit, 825:Imaging unit, 827:Earphone part, 832:Lens,

Claims

1. The pixel comprises a pulse signal generation unit, a first node, a second node, a first transistor, a second transistor, a third transistor, a first capacitor, and a light-emitting device. The first node is electrically connected to either the source or drain of the first transistor, either the source or drain of the second transistor, and the input of the pulse signal generation unit. The second node is electrically connected to the other side of the source or drain of the second transistor, the gate of the third transistor, one electrode of the first capacitor, and the output of the pulse signal generation unit. The source or drain of the third transistor is electrically connected to one electrode of the light-emitting device. The source or drain of the third transistor is electrically connected to the other electrode of the first capacitor. The pulse signal generation unit comprises a fourth to ninth transistor and a second capacitor. The fourth transistor has a first gate and a second gate, The first gate of the fourth transistor and either the source or drain of the fifth transistor are electrically connected to the first node. Either the source or drain of the fourth transistor is electrically connected to the gate of the sixth transistor and either the source or drain of the seventh transistor. The second gate of the fourth transistor is electrically connected to either the source or drain of the eighth transistor and to one electrode of the second capacitor. The other electrode of the second capacitor is electrically connected to either the source or the drain of the ninth transistor. The source or drain of the ninth transistor is electrically connected to the source or drain of the fourth transistor. The source or drain of the sixth transistor is electrically connected to the second node as a display device.

2. The pixel comprises a pulse signal generation unit, a first node, a second node, a first transistor, a second transistor, a third transistor, a first capacitor, and a light-emitting device. The first node is electrically connected to either the source or drain of the first transistor, either the source or drain of the second transistor, and the input of the pulse signal generation unit. The second node is electrically connected to the other side of the source or drain of the second transistor, the gate of the third transistor, one electrode of the first capacitor, and the output of the pulse signal generation unit. The source or drain of the third transistor is electrically connected to one electrode of the light-emitting device. The source or drain of the third transistor is electrically connected to the other electrode of the first capacitor. The pulse signal generation unit comprises a fourth to ninth transistor and a second capacitor. The fourth transistor has a first gate and a second gate, The first gate of the fourth transistor and either the source or drain of the fifth transistor are electrically connected to the first node. Either the source or drain of the fourth transistor is electrically connected to the gate of the sixth transistor and either the source or drain of the seventh transistor. The second gate of the fourth transistor is electrically connected to either the source or drain of the eighth transistor and to one electrode of the second capacitor. The other electrode of the second capacitor is electrically connected to either the source or the drain of the ninth transistor. The source or drain of the ninth transistor is electrically connected to the source or drain of the fourth transistor. Either the source or the drain of the sixth transistor is electrically connected to the second node. A display device is provided, to which the signal potential of a ramp waveform is input to the source or drain of the fourth transistor.

3. The pixel comprises a pulse signal generation unit, a first node, a second node, a first transistor, a second transistor, a third transistor, a first capacitor, and a light-emitting device. The first node is electrically connected to either the source or drain of the first transistor, either the source or drain of the second transistor, and the input of the pulse signal generation unit. The second node is electrically connected to the other side of the source or drain of the second transistor, the gate of the third transistor, one electrode of the first capacitor, and the output of the pulse signal generation unit. The source or drain of the third transistor is electrically connected to one electrode of the light-emitting device. The source or drain of the third transistor is electrically connected to the other electrode of the first capacitor. The pulse signal generation unit comprises a fourth to ninth transistor and a second capacitor. The fourth transistor has a first gate and a second gate, The first gate of the fourth transistor and either the source or drain of the fifth transistor are electrically connected to the first node. Either the source or drain of the fourth transistor is electrically connected to the gate of the sixth transistor and either the source or drain of the seventh transistor. The second gate of the fourth transistor is electrically connected to either the source or drain of the eighth transistor and to one electrode of the second capacitor. The other electrode of the second capacitor is electrically connected to either the source or the drain of the ninth transistor. The source or drain of the ninth transistor is electrically connected to the source or drain of the fourth transistor. Either the source or the drain of the sixth transistor is electrically connected to the second node. The pixel causes the light-emitting device to emit light in response to the data potential input to the second node. The pulse signal generation unit generates a pulse signal in accordance with the data potential input to the first node. The pixel is a display device that resets the potential of the first node in response to the pulse signal and turns off the light-emitting device.

4. The pixel comprises a pulse signal generation unit, a first node, a second node, a first transistor, a second transistor, a third transistor, a first capacitor, and a light-emitting device. The first node is electrically connected to either the source or drain of the first transistor, either the source or drain of the second transistor, and the input of the pulse signal generation unit. The second node is electrically connected to the other side of the source or drain of the second transistor, the gate of the third transistor, one electrode of the first capacitor, and the output of the pulse signal generation unit. The source or drain of the third transistor is electrically connected to one electrode of the light-emitting device. The source or drain of the third transistor is electrically connected to the other electrode of the first capacitor. The pulse signal generation unit comprises a fourth to ninth transistor and a second capacitor. The fourth transistor has a first gate and a second gate, The first gate of the fourth transistor and either the source or drain of the fifth transistor are electrically connected to the first node. Either the source or drain of the fourth transistor is electrically connected to the gate of the sixth transistor and either the source or drain of the seventh transistor. The second gate of the fourth transistor is electrically connected to either the source or drain of the eighth transistor and to one electrode of the second capacitor. The other electrode of the second capacitor is electrically connected to either the source or the drain of the ninth transistor. The source or drain of the ninth transistor is electrically connected to the source or drain of the fourth transistor. Either the source or the drain of the sixth transistor is electrically connected to the second node. A signal potential of a ramp waveform is input to the other of the source or drain of the fourth transistor. The pixel causes the light-emitting device to emit light in response to the data potential input to the second node. The pulse signal generation unit generates a pulse signal in accordance with the data potential input to the first node. The pixel is a display device that resets the potential of the first node in response to the pulse signal and turns off the light-emitting device.

5. In any one of claims 1 to 4, The first transistor, the second transistor, the fourth transistor, the fifth transistor, the eighth transistor, and the ninth transistor are each n-channel transistors. The third transistor, the sixth transistor, and the seventh transistor are each p-channel type transistors in this display device.

6. In claim 5, The aforementioned n-channel transistor has a metal oxide in the channel formation region. The p-channel transistor is a display device having silicon in the channel formation region.

7. In any one of claims 1 to 4, The light-emitting device is a display device that is a microLED.

8. An electronic device having a display device according to any one of claims 1 to 4 and a camera.

Images