Semiconductor equipment

Abstract

To provide a semiconductor device with which product-sum computation can be performed with little power consumption.SOLUTION: An arithmetic circuit 110 is a semiconductor device for processing a plurality of signals zm(k-1) inputted to a plurality of k-th layer neurons Nn(k) and generating a plurality of zn(k) outputted from each of the plurality of neurons Nn(k). A circuit ILD is electrically connected to a plurality of wirings IL[n] and a plurality of wirings ILB[n], a circuit WLD is electrically connected to a plurality of wirings WLS[m], a circuit XLD is electrically connected to a plurality of wirings XLS[m], and a circuit AFP is electrically connected to a plurality of wirings OL[n] and a plurality of wirings OLB[n]. An array unit ALP has m×n circuits MP, and is arranged in a m row by n column matrix and electrically connected to, for example, a wiring IL[j], a wiring ILB[j], a wiring WLS[i], a wiring XLS[i], a wiring OL[j], and a wiring OLB[j].SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] One aspect of the present invention relates to semiconductor devices and electronic devices.

[0002] One aspect of the present invention is not limited to the above-mentioned technical field. The technical field relates to a product, a method, or a method of manufacture. Alternatively, one aspect of the present invention is: Process, machine, manufacture, or composition of matter This relates to the technology of one aspect of the present invention disclosed more specifically herein. The fields include semiconductor devices, display devices, liquid crystal display devices, light-emitting devices, energy storage devices, imaging devices, Memory devices, signal processing devices, processors, electronic devices, systems, methods for driving them, and A manufacturing method or inspection method thereof can be given as an example. [Background technology]

[0003] Currently, there is a lot of activity in developing integrated circuits that mimic the structure of the human brain. The pathway is an electronic circuit that incorporates the brain's structure, and the "neurons" and "s It has a circuit equivalent to a "naps." Therefore, such an integrated circuit is called a "neuromorph." It is sometimes called "Brainmorphic," "Brain-Inspired," or "Brain-Inspired." The integrated circuit has a non-von Neumann architecture, and its power consumption increases with increasing processing speed. Compared to the larger von Neumann architecture, it performs parallel processing with extremely low power consumption. It is expected to happen.

[0004] Information processing models that mimic neural networks with "neurons" and "synapses" are artificial It is called an artificial neural network (ANN). For example, Non-Patent Document 1 and Non-Patent Document 2 disclose an arithmetic unit that uses SRAM (Static Random Access Memory) to construct an artificial neural network.

Prior Art Documents

Non-Patent Documents

[0005]

Non-Patent Document 1

Non-Patent Document 2

Summary of the Invention

Problems to be Solved by the Invention

[0006] In an artificial neural network, a calculation is performed by multiplying the connection strength (which may be referred to as a weight coefficient) of a synapse that connects two neurons and the signal transmitted between the two neurons. In particular, in a hierarchical artificial neural network, it is necessary to multiply and sum the connection strength of each synapse between a plurality of first neurons in the first layer and a first neuron in the second layer, and each signal input from the plurality of first neurons in the first layer to the first neuron in the second layer. Depending on the scale of the artificial neural network, for example, the number of the connection strengths and the number of parameters indicating the signals are determined. That is, in the artificial neural network (the connection strength may be called a weight coefficient in some cases) and the signal transmitted between the two neurons are multiplied to perform a calculation. In particular, in a hierarchical artificial neural network, it is necessary to multiply and sum the connection strength of each synapse between a plurality of first neurons in the first layer and a first neuron in the second layer, and each signal input from the plurality of first neurons in the first layer to the first neuron in the second layer. Depending on the scale of the artificial neural network, for example, the number of the connection strengths and the number of parameters indicating the signals are determined. That is, in the artificial neural network between a plurality of first neurons in the first layer and a first neuron in the second layer, and add them together after multiplying each connection strength of the synapses and each signal input from the plurality of first neurons in the first layer to the first neuron in the second layer. Depending on the scale of the artificial neural network, for example, the number of the connection strengths and the number of parameters indicating the signals are determined. That is, in the artificial neural network from a plurality of first neurons in the first layer to a first neuron in the second layer, and add them together after multiplying each connection strength of the synapses and each signal input from the plurality of first neurons in the first layer to the first neuron in the second layer. Depending on the scale of the artificial neural network, for example, the number of the connection strengths and the number of parameters indicating the signals are determined. That is, in the artificial neural network depending on the scale of the artificial neural network, for example, the number of the connection strengths and the number of parameters indicating the signals are determined. That is, in the artificial neural network for example, the number of the connection strengths and the number of parameters indicating the signals are determined according to the scale of the artificial neural network. That is, in the artificial neural network In a neural network, as the number of layers, the number of neurons, etc. increase, the number of circuits corresponding to each of the "neurons" and "synapses" increases, and the amount of computation may become extremely large. .

[0007] As the number of circuits constituting the chip increases, the power consumption increases, and the amount of heat generated during the operation of the device also increases. In particular, the higher the amount of heat generated, the more the characteristics of the circuit elements included in the chip are affected. Therefore, it is preferable that the circuits constituting the chip have circuit elements that are less affected by temperature.

[0008] One aspect of the present invention is to provide a semiconductor device in which a hierarchical artificial neural network is constructed, etc. Or, one aspect of the present invention is to provide a semiconductor device with low power consumption, etc. Or, one aspect of the present invention is to provide a semiconductor device that is less affected by the temperature of the environment, etc. Or, one aspect of the present invention is to provide a new type of semiconductor device, etc.

[0009] Note that the problems of one aspect of the present invention are not limited to the problems listed above. The problems listed above do not prevent the existence of other problems. Other problems are those not mentioned in this section described below. Problems not mentioned in this section can be derived by those skilled in the art from the descriptions in the specification or drawings, etc., and can be appropriately extracted from these descriptions. Note that one aspect of the present invention solves at least one of the problems listed above and other problems. Note that one aspect of the present invention does not necessarily solve all of the problems listed above and other problems.

Means for Solving the Problems

[0010] (1) One aspect of the present invention has a first circuit, the first circuit comprising a first transistor and a second transistor The first transistor has a first gate and a second gate, The first transistor has a first gate which is electrically connected to the first input wiring, and the first transistor The second gate of the transistor is connected to the first terminal of the second transistor and the first terminal of the first capacitor element. Electrically connected, the first circuit turns off the second transistor, Function to maintain the first potential between the first terminal of a capacitance element and the second gate of a first transistor. Then, depending on the first potential and the second potential input to the first input wiring, the first transistor is... This is a semiconductor device having a function to either be in an ON state or an OFF state.

[0011] (2) Alternatively, in one aspect of the present invention, in the configuration of (1) above, the first potential is an analog value. When the first transistor is ON, an analog current flows through the first transistor. It is a body device.

[0012] (3) Alternatively, in one aspect of the present invention, in the configuration of (1) or (2) above, the third transistor is The third transistor has a first gate and a second gate, and the third transistor The first gate is electrically connected to the second input wiring, and the second gate of the third transistor is The first terminal of the 2 transistors, the first terminal of the first capacitance element, and the second gate of the first transistor. It is electrically connected to the first potential and the third potential input to the second input wiring. A semiconductor device having the function of either turning the third transistor on or off. be.

[0013] (4) Alternatively, one aspect of the present invention is that in the configuration of (3) above, it has a second circuit, and the second circuit has a fourth to sixth transistors and a second capacitive element. Each of the fourth transistor and the sixth transistor has a first gate and a second gate. The first gate of the fourth transistor is electrically connected to the first input wiring, and the first gate of the sixth transistor is electrically connected to the second input power wiring. The second gate of the fourth transistor is electrically connected to the first terminal of the fifth transistor, the first terminal of the second capacitive element, and the second gate of the sixth transistor. The first terminal of the first transistor is electrically connected to the first wiring, the first terminal of the third transistor is electrically connected to the second wiring, the first terminal of the fourth transistor is electrically connected to the second wiring The first terminal of the sixth transistor is electrically connected to the first wiring. The second circuit has a function of maintaining the fourth potential of the first terminal of the second capacitive element, the second gate of the fourth transistor, and the second gate of the sixth transistor by turning off the fifth transistor, and a function of turning on or off the fourth transistor according to the fourth potential and the second potential input to the first input wiring, and a function of turning on or off the sixth transistor according to the fourth potential and the third potential input to the second input wiring. It is a semiconductor device having By turning off the fifth transistor, the second circuit maintains the fourth potential of the first terminal of the second capacitive element, the second gate of the fourth transistor, and the second gate of the sixth transistor, and turns on or off the fourth transistor according to the fourth potential and the second potential input to the first input wiring, and turns on or off the sixth transistor according to the fourth potential and the third potential input to the second input wiring. It is a semiconductor device having

[0014] (5) Alternatively, one aspect of the present invention is that in the configuration of (4) above, the fourth potential is an analog value, and when the fourth transistor is in the on state, an analog current flows through the fourth transistor, and the sixth ​​​​​​​​​​When the transistor is ON, an analog current flows through the sixth transistor in the semiconductor device. That is the case.

[0015] (6) Alternatively, in one aspect of the present invention, the third circuit and the fourth circuit are provided in (5) above, Potential 1 and Potential 4 are potentials corresponding to the first data, and the third circuit is the first input distribution The function to input the first and third potentials corresponding to the second data to each of the wires and the second input wiring. The fourth circuit compares the currents flowing from the first and second wirings, and then the fourth circuit A semiconductor has the function of outputting a potential corresponding to the product of the first data and the second data from its output terminal. It is a body device.

[0016] (7) Alternatively, one aspect of the present invention comprises any one of the semiconductor devices described in (1) to (6) above, and semi This is an electronic device that performs neural network calculations using conductive devices.

[0017] In this specification, a semiconductor device is a device that utilizes semiconductor properties. Circuits containing structural elements (transistors, diodes, photodiodes, etc.), and circuits having the same This refers to devices, etc. It also refers to all devices that can function by utilizing semiconductor properties. For example, Integrated circuits, chips containing integrated circuits, and electronic components that house chips in a package are called semiconductors. This is an example of a device. Furthermore, storage devices, display devices, light-emitting devices, lighting devices, and electronic equipment are also examples. It is a semiconductor device in itself, and may have a semiconductor device.

[0018] Furthermore, if it is stated in this specification, etc., that X and Y are connected, then X and When Y is electrically connected, when X and Y are functionally connected, and when X and The case in which Y and are directly connected is disclosed in this specification, etc. Furthermore, the predetermined connection relationships, for example, the connection relationships shown in the diagram or text, are not limited to those shown in the diagram or text. Other connection relationships besides those shown are also disclosed in the diagram or text. X and Y are, Let's assume the object is (for example, a device, element, circuit, wiring, electrode, terminal, conductive film, layer, etc.). .

[0019] One example of a case where X and Y are electrically connected is when the electrical connection between X and Y is possible. Elements that perform this function (for example, switches, transistors, capacitive elements, inductors, resistive elements, etc.) One or more elements (such as ions, display elements, light-emitting elements, and loads) are connected between X and Y. This is possible. Furthermore, the switch has a function that allows it to be controlled to be on or off. In other words, A switch can be either conductive (on) or non-conductive (off), allowing current to flow. It has a function to control whether or not it is released.

[0020] One example of a functional connection between X and Y is a functional connection between X and Y. Circuits that can perform this function (for example, logic circuits (inverters, NAND gates, NOR gates, etc.), signals) Conversion circuits (digital-to-analog conversion circuits, analog-to-digital conversion circuits, gamma correction circuits, etc.) ), potential level conversion circuit (power supply circuit (boost circuit, buck circuit, etc.), changes the potential level of the signal Level shifter circuits, etc.), voltage sources, current sources, switching circuits, amplification circuits (signal amplitude or Circuits that can increase the amount of current, etc., operational amplifiers, differential amplifiers, source follower circuits, batteries One or more circuits (such as FA circuits, signal generation circuits, memory circuits, control circuits, etc.) are located between X and Y. It is possible to connect them. For example, if another circuit is placed between X and Y... However, if a signal output from X is transmitted to Y, then X and Y are functionally connected. It shall be considered as such.

[0021] Furthermore, if it is explicitly stated that X and Y are electrically connected, then X and Y are electrically connected. When connected electrically (i.e., connected with another element or circuit in between X and Y) (if such a connection exists) and (if X and Y are functionally connected) (When connected with another circuit in between) and when X and Y are directly connected (that is (including cases where X and Y are connected without another element or circuit in between) In other words, if you explicitly state that they are electrically connected, then simply say they are connected. This is equivalent to the case where it is explicitly stated that it is present.

[0022] Also, for example, "X and Y and the source (or first terminal, etc.) and drain of the transistor ( (or the second terminal, etc.) are electrically connected to each other, and X is the source of the transistor. (or the first terminal, etc.), the transistor drain (or the second terminal, etc.), and Y in that order. It can be expressed as, "It is electrically connected." Or, "The source of the transistor ( The first terminal (or the first terminal, etc.) is electrically connected to X, and the drain (or second terminal) of the transistor is connected to X. The terminals (or other terminals) are electrically connected to Y, and X is the source of the transistor (or the first terminal, etc.). The transistor's drain (or second terminal, etc.), Y, are electrically connected in this order. It can be expressed as "X is the source (or first terminal) of the transistor." Alternatively, "X is the source (or first terminal) of the transistor." Y is electrically connected to X, via the drain (or second terminal, etc.) and X, The source of the transistor (or the first terminal, etc.), the drain of the transistor (or the second terminal) (etc.), Y is provided in this connection order. By using a similar method of expression to specify the order of connections in the circuit configuration, Connect the source (or first terminal, etc.) and the drain (or second terminal, etc.) of the transistor. By distinguishing between them, the technical scope can be determined. Note that these expressions are just examples. However, it is not limited to these methods of expression. Here, X and Y are objects (e.g., devices, elements, (This refers to circuits, wiring, electrodes, terminals, conductive films, layers, etc.)

[0023] Note that, in circuit diagrams, independent components are shown as being electrically connected to each other. Even if such a combination exists, one component may possess the functions of multiple components. Yes. For example, if part of the wiring also functions as an electrode, one conductive film will function as the wiring, and It possesses the functions of both components of the electrode. Therefore, in this specification Electrically connected means that a single conductive film combines the functions of multiple components. This also falls under that category.

[0024] Furthermore, in this specification, a transistor is referred to as gate, source, and drain. It has three terminals. The gate is a control terminal that controls the conduction state of the transistor. The two terminals that function as source or drain are the input and output terminals of the transistor. The input / output terminals specify the transistor's conductivity type (n-channel type, p-channel type) and the transistor's... Depending on the potential applied to the three terminals of the sta, one becomes the source and the other the drain. Therefore, in this specification, the terms source and drain may be rephrased. It shall be possible to do so. Furthermore, in this specification, when describing the connection relationships of transistors, "either the source or the drain" (or the first electrode or the first terminal), "either the source or the drain The notation "the other side" (or second electrode, or second terminal) is used. Note that the structure of a transistor Depending on the model, in addition to the three terminals mentioned above, there may be a back gate. In this specification, either the gate or the back gate of a transistor is referred to as the first gate. The other side of the transistor's gate or back gate is sometimes referred to as the second gate. Furthermore, within the same transistor, the terms "gate" and "back gate" are interchangeable. It may be possible to replace it. Also, if the transistor has 3 or more gates In this specification, etc., each gate is referred to as the first gate, the second gate, the third gate, etc. It is sometimes referred to as such.

[0025] Furthermore, in this specification, etc., a node has terminals, distributions, etc., depending on the circuit configuration and device structure. These can be rephrased as wire, electrode, conductive layer, conductor, impurity region, etc. Also, terminal, Wiring and other components can be referred to as nodes.

[0026] Furthermore, in this specification and other documents, "voltage" and "potential" may be used interchangeably as appropriate. Voltage is the potential difference from a reference potential. For example, if the reference potential is ground... If we consider it as ground potential, then "voltage" can be replaced with "potential". The potential does not necessarily mean 0V. Furthermore, potential is relative, and it is based on a reference point. Depending on the potential, it may change the potential supplied to wiring, etc.

[0027] "Electric current" refers to the phenomenon of electric charge movement (electrical conduction), for example, "electricity of a positively charged body." The statement "conduction is occurring" means "electrical conduction of a negatively charged body is occurring in the opposite direction." This can be rephrased as follows. Therefore, in this specification, the term "electric current" is not used unless otherwise specified. In this context, it refers to the phenomenon of charge transfer associated with carrier movement (electrical conduction). Carriers include electrons, holes, anions, cations, complex ions, etc., which are involved in the flow of electric current. The carriers differ depending on the system (e.g., semiconductor, metal, electrolyte, vacuum, etc.). In lines and other structures, the "direction of current" is defined as the direction in which positive carriers move, and is expressed as a positive current quantity. In other words, the direction in which negative carriers move is opposite to the direction of the current, and the negative current It is expressed in terms of flow rate. Therefore, in this specification, etc., the positive and negative (or direction of the current) of the current is not specified. Unless otherwise stated, descriptions such as "current flows from element A to element B" should be interpreted as "current flows from element B to element B." This can be rephrased as "current flows through A," etc. Also, "current enters element A." Descriptions such as "forced" can be rephrased as "current is output from element A," etc. Let's assume that.

[0028] Furthermore, in this specification, the ordinal numbers "1st," "2nd," and "3rd" refer to constituent elements. This was added to avoid confusion. Therefore, it does not limit the number of constituent elements. Furthermore, this does not limit the order of the components. For example, one of the embodiments described herein The components referred to as "first" in this invention may be used in other embodiments or claims. It may also be the component referred to in "Section 2". For example, in this specification, etc. In one embodiment, the component referred to as "first" may be used in other embodiments, or in other embodiments. It may be possible to omit certain details within the scope of the permitted claim.

[0029] Furthermore, in this specification, phrases indicating placement such as "above" and "below" refer to the relative positions of the components. In some cases, positional relationships are used for convenience in explaining them by referring to diagrams. The relative positions of the elements change appropriately depending on the direction in which each element is depicted. Therefore, The terminology is not limited to what is explained in the detailed document, etc., and can be appropriately rephrased depending on the situation. For example, However, in the expression "insulator located on the upper surface of the conductor," the orientation of the diagram shown should be rotated 180 degrees. By rephrasing it, it can be described as "an insulator located on the underside of a conductor."

[0030] Furthermore, the terms "up" and "down" refer to situations where the relative positions of the constituent elements are directly above or directly below, and directly connected. It does not limit what is being done. For example, if the expression is "electrode B on insulating layer A", It is not necessary for electrode B to be directly in contact with insulating layer A, and the insulating layer A and electrode B are not in direct contact. This does not exclude those that include other components in between.

[0031] Furthermore, in this specification, terms such as "membrane" and "layer" may be interchanged depending on the context. It is possible to change the term. For example, the term "conductive layer" can be changed to the term "conductive film." It may be possible to change it. Or, for example, change the term "insulating film" to "insulating layer". It may be possible to change the terminology to this. Or, depending on the circumstances, or depending on the situation. Therefore, it is possible to replace terms such as "membrane" and "layer" with other terms without using them. For example, changing the term "conductive layer" or "conductive film" to the term "conductor" It may be possible. Or, for example, the terms "insulating layer" and "insulating film" could be changed to "insulator". It may be possible to change the terminology.

[0032] Furthermore, in this specification, the terms "electrode" and "wiring" refer to these components functionally. It is not limited to this. For example, "electrode" can be used as part of "wiring". And the reverse is also true. Furthermore, the terms "electrode" and "wiring" can refer to multiple "electrodes" or " This includes cases where the wiring is formed as a single integrated unit.

[0033] Furthermore, in this specification, terms such as "wiring," "signal line," and "power line" may be used in some cases. Therefore, or depending on the situation, they can be interchanged. For example, "wiring" In some cases, it is possible to change the term "signal line" to "signal line". Also, for example In some cases, the term "wiring" can be changed to terms such as "power lines." Conversely, terms such as "signal line" and "power line" should be changed to the term "wiring." In some cases, this may be possible. Terms such as "power lines" should be changed to terms such as "signal lines." In some cases, this is possible. Conversely, terms like "signal line" can also be used for "power line." It may be possible to change the terminology. Also, the "potential" applied to the wiring Depending on the circumstances, or in some cases, the term may be changed to a term such as "signal". This is sometimes possible. Conversely, terms like "signal" can also be expressed as "electric potential." It may be possible to change the terminology.

[0034] In this specification, semiconductor impurities refer to, for example, components other than the main components that constitute the semiconductor layer. For example, elements with a concentration of less than 0.1 atomic percent are considered impurities. For example, when DOS (Density of States) is formed in a semiconductor... In some cases, this can lead to a decrease in carrier mobility or a decrease in crystallinity. If the semiconductor is an oxide semiconductor, impurities that change the properties of the semiconductor include, for example, Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, and elements other than the main component. These include transition metals, and in particular, for example, hydrogen (also found in water), lithium, sodium, These include silicon, boron, phosphorus, carbon, and nitrogen. Specifically, semiconductors are made up of silicon layers. In this case, impurities that alter the properties of semiconductors include, for example, Group 1 elements other than oxygen and hydrogen. These include elements from Group 2, Group 13, Group 15, and so on.

[0035] In this specification, a switch refers to a conductive state (on state) or a non-conductive state (off state). This refers to a device that has the function of controlling whether or not to allow current to flow when it enters a certain state. Alternatively, it can refer to a switch. A switch is a device that has the function of selecting and switching the path through which electric current flows. One example is... Electrical switches, mechanical switches, etc. can be used. In other words, switches are Any device capable of controlling the current will suffice; it is not limited to any specific device.

[0036] An example of an electrical switch is a transistor (for example, a bipolar transistor). MOS transistors, diodes (for example, PN diodes, PIN diodes, Schottky diode, MIM (Metal Insulator Metal) die Od, MIS (Metal Insulator Semiconductor) die Odes, diode-connected transistors, etc., or logic circuits combining these. There is. Furthermore, when using a transistor as a switch, the "conductivity state" of the transistor... This refers to a state where the source and drain electrodes of a transistor can be considered to be electrically short-circuited. It refers to a state. Also, the "non-conductive state" of a transistor is when the source electrode and the drive of the transistor are not connected. This refers to a state in which the input electrode can be considered electrically isolated. Note that a transistor is not simply a transistor. When operating as a switch, the polarity (conductivity type) of the transistor is not particularly limited.

[0037] One example of a mechanical switch is MEMS (Micro-Electro-Mechanical Systems). There are switches that use (STEM) technology. These switches are capable of being moved mechanically. It has electrodes, and operates by controlling the transition between conductivity and non-conductivity through the movement of these electrodes. [Effects of the Invention]

[0038] According to one aspect of the present invention, a semiconductor device in which a hierarchical artificial neural network is constructed It can provide a place for, etc. Alternatively, according to one aspect of the present invention, a semiconductor with low power consumption. The present invention can provide devices, etc. Alternatively, according to one aspect of the present invention, the influence of ambient temperature can be reduced. It is possible to provide semiconductor devices that are less susceptible to damage. Or, according to one aspect of the present invention, We can provide standard semiconductor devices and the like.

[0039] The effects of one embodiment of the present invention are not limited to those listed above. This does not preclude the existence of other effects. These other effects are described in the following section. This is an effect not mentioned in the specification. Effects not mentioned in this section can be described in the specification or by those skilled in the art. This can be derived from drawings and other descriptions, and can be extracted as appropriate from these descriptions. Furthermore, one aspect of the present invention provides at least one of the effects listed above and other effects. It has the effect of, in some cases, the effects listed above. They may not always be present. [Brief explanation of the drawing]

[0040] [Figure 1] Figures 1A and 1B illustrate a hierarchical neural network. [Figure 2] Figure 2 is a circuit diagram showing an example of a semiconductor device configuration. [Figure 3] Figures 3A, 3B, 3C, 3D, 3E, and 3F are circuit diagrams showing example circuit configurations of semiconductor devices. [Figure 4] Figures 4A, 4B, 4C, 4D, 4E, and 4F are circuit diagrams showing example circuit configurations of semiconductor devices. [Figure 5] Figures 5A, 5B, 5C, 5D, and 5E are circuit diagrams showing examples of circuit configurations of semiconductor devices. [Figure 6] Figure 6 is a circuit diagram showing an example of a semiconductor device configuration. [Figure 7] Figure 7 is a circuit diagram showing an example of the configuration of a semiconductor device. [Figure 8] Figure 8 is a circuit diagram showing an example of a semiconductor device configuration. [Figure 9] Figures 9A and 9B are circuit diagrams showing examples of the circuit configuration of a semiconductor device. [Figure 10] Figure 10 is a circuit diagram showing an example of the circuit configuration of a semiconductor device. [Figure 11] Figures 11A and 11B are circuit diagrams showing examples of the circuit configuration of a semiconductor device. [Figure 12] Figures 12A and 12B show the voltage-current characteristics of transistors in a semiconductor device. [Figure 13] Figures 13A, 13B, and 13C are timing charts showing examples of circuit operation in a semiconductor device. [Figure 14]Figures 14A, 14B, and 14C are timing charts showing examples of circuit operation in a semiconductor device. [Figure 15] Figures 15A, 15B, and 15C are timing charts showing examples of the operation of circuits in semiconductor devices. [Figure 16] Figures 16A and 16B are circuit diagrams showing examples of the circuit configuration of a semiconductor device. [Figure 17] Figure 17 is a circuit diagram showing an example of the circuit configuration of a semiconductor device. [Figure 18] Figure 18 is a circuit diagram showing an example of the circuit configuration of a semiconductor device. [Figure 19] Figure 19 is a circuit diagram showing an example of the circuit configuration of a semiconductor device. [Figure 20] Figures 20A and 20B are circuit diagrams showing examples of the circuit configuration of a semiconductor device. [Figure 21] Figures 21A and 21B are circuit diagrams showing examples of the circuit configuration of a semiconductor device. [Figure 22] Figures 22A and 22B are circuit diagrams showing examples of the circuit configuration of a semiconductor device. [Figure 23] Figure 23 is a cross-sectional view showing an example of the configuration of a semiconductor device. [Figure 24] Figure 24 is a cross-sectional view showing an example of the configuration of a semiconductor device. [Figure 25] Figures 25A, 25B, and 25C are cross-sectional views showing examples of transistor structures. [Figure 26] Figures 26A, 26B, and 26C are top views and cross-sectional views showing examples of transistor structures. [Figure 27] Figures 27A, 27B, and 27C are top views and cross-sectional views showing examples of transistor structures. [Figure 28] Figures 28A, 28B, and 28C are top views and cross-sectional views showing examples of transistor structures. [Figure 29] Figures 29A, 29B, and 29C are top views and cross-sectional views showing examples of transistor structures. [Figure 30]Figures 30A, 30B, and 30C are top views and cross-sectional views showing examples of transistor structures. [Figure 31] Figures 31A and 31B are top and perspective views, respectively, illustrating examples of transistor structures. [Figure 32] Figures 32A and 32B are cross-sectional views showing examples of transistor structures. [Figure 33] Figures 33A, 33B, and 33C are top views and perspective views showing examples of the structure of a capacitive element. [Figure 34] Figures 34A, 34B, and 34C are top views and perspective views showing examples of the structure of a capacitive element. [Figure 35] Figures 35A, 35B, 35C, and 35D are perspective views showing examples of semiconductor wafers and electronic components. [Figure 36] Figure 36 is a perspective view showing an example of an electronic device. [Figure 37] Figure 37A is a front view showing an example of an electronic device, while Figures 37B and 37C are perspective views showing an example of an electronic device. [Modes for carrying out the invention]

[0041] In artificial neural networks (hereinafter referred to as neural networks): The synaptic connection strength is determined by providing existing information to the neural network. It can be changed. In this way, by providing existing information to a neural network, The process of determining bond strength is sometimes called "learning."

[0042] Furthermore, for a neural network that has undergone "learning" (where connection strengths have been defined), By providing that information, new information can be output based on the bond strength. Thus, in a neural network, based on the given information and connection strength... The process of outputting new information is sometimes called "inference" or "cognition."

[0043] Examples of neural network models include the Hopfield type and the hierarchical type. One example is a multi-layered neural network called a "deep neural network." It is called a "deep neural network" (DNN), and machine learning using deep neural networks is called It is sometimes referred to as "deep learning."

[0044] In this specification, metal oxide refers to metal in a broad sense. It is an oxide. Metal oxides are oxide insulators and oxide conductors (including transparent oxide conductors). ), oxide semiconductor (also called OS) They are classified into the following categories. For example, when a metal oxide is used in the active layer of a transistor, the metal acid These oxides are sometimes called oxide semiconductors. In other words, metal oxides have amplification and rectification effects. and constitute a channel formation region of a transistor having at least one switching action. If possible, the metal oxide is used as a metal oxide semiconductor. It can also be called an OS FET or OS transistor. When this is stated, it is equivalent to a transistor having a metal oxide or oxide semiconductor. It is possible.

[0045] Furthermore, in this specification, metal oxides containing nitrogen are also referred to as metal oxides (metal oxides). They are sometimes collectively referred to as metal oxynitrides (metal oxides). Also, metal oxides containing nitrogen are sometimes called metal oxynitrides (metal oxides). It may also be called tal oxynitride.

[0046] Furthermore, in this specification, the configurations shown in each embodiment are different from the configurations shown in other embodiments. By combining them as appropriate, one embodiment of the present invention can be formed. If multiple configuration examples are provided, it is possible to combine them as appropriate.

[0047] Furthermore, the content described in one embodiment (even a part of it) may be subject to change in implementation. Other details (even partial details) described in the form, and one or more other embodiments The content to be stated (even if only a part of it) should be applied to or combined with at least one other content. It is possible to replace or otherwise perform actions such as [doing something else].

[0048] Furthermore, the content described in each embodiment refers to the use of various figures in each embodiment. This refers to the content described or the content described using the text included in the specification.

[0049] Note that a diagram (even a part of it) described in one embodiment may be a part of that diagram. In that embodiment, another figure (even if only a part of it) and one or more other figures For at least one of the diagrams (even if only a part of it) described in the form of the installation, the combination By doing so, even more diagrams can be constructed.

[0050] Embodiments described herein are explained with reference to the drawings. However, implementation may differ. The form can be implemented in many different ways, and it does not deviate from the purpose and scope. It will be easily understood by those skilled in the art that its form and details can be changed in various ways. Therefore, the present invention is not to be interpreted as being limited to the contents described in the embodiments. In the configuration of the invention in the form of application, the same reference numeral is used for identical parts or parts having similar functions. In some cases, explanations of repetitions used across different drawings may be omitted. Also, perspective drawings. In some cases, the description of certain components may be omitted in order to ensure clarity in the drawings. be.

[0051] In this specification, when the same reference numeral is used for multiple elements, it is particularly important to distinguish between them. When necessary, add identifying codes such as "_1", "[n]", or "[m,n]" to the code. It may be noted or written down.

[0052] Furthermore, in the drawings of this specification, the size, thickness of the layers, or the area may be exaggerated for clarity. In some cases, this may be the case. Therefore, it is not necessarily limited to that scale. Note that the drawings are for reference only. This is a schematic representation of a hypothetical example and is not limited to the shapes or values ​​shown in the drawing. This can be due to variations in signals, voltages, or currents caused by noise, or to timing discrepancies. This can include variations in signals, voltages, or currents.

[0053] (Embodiment 1) In this embodiment, a semiconductor device according to one aspect of the present invention is used to perform a neural network This section explains the arithmetic circuits that perform calculations.

[0054] <Hierarchical Neural Network> First, let's explain hierarchical neural networks. A network, for example, consists of one input layer, one or more intermediate layers (hidden layers), and one output layer. It has layers and is composed of a total of 3 or more layers. Figure 1A shows a hierarchical neural network. The neural network 100 is an example of this, and the neural network 100 is the first It has layers up to the Rth layer (where R can be an integer greater than or equal to 4). In particular, The first layer corresponds to the input layer, the R-th layer corresponds to the output layer, and the other layers correspond to the intermediate layers. . In FIG. 1A, the (k - 1)-th layer and the k-th layer (where k is an integer of 3 or more and R - 1 or less) are illustrated as intermediate layers, and the illustration of the other intermediate layers is omitted. .

[0055] Each layer of the neural network 100 has one or more neurons. In FIG. 1A , the first layer has neurons N1 (1) to neuron N p (1) (where p is an integer of 1 or more ). The (k - 1)-th layer has neurons N1 (k-1) to neuron N m (k-1) (where m is an integer of 1 or more). The k-th layer has neurons N1 ( k) to neuron N n (k) (where n is an integer of 1 or more). The R-th layer has neurons N1 (R) to neuron N q (R) (where q is an integer of 1 or more). has.

[0056] . In addition to neurons N1 (1) , neuron N p (1) , neurons N1 ( k-1) , neuron N m (k-1) , neurons N1 (k) , neuron N n (k) , neurons N1 (R) , neuron N q (R) , in FIG. 1A, in addition to the neurons N i (k-1) (Here, i is an integer between 1 and m, inclusive.) Neuron N of layer k j ( k) (Here, j is an integer between 1 and n, inclusive.) is also illustrated, as are other neurons The diagram for "n" has been omitted.

[0057] Next, the transmission of signals from neurons in the previous layer to neurons in the next layer, and each of the neurons This section describes the signals that are input and output in the ron. Note that in this explanation, the k-th layer of the neurons... N j (k) We are focusing on that.

[0058] Figure 1B shows neurons N in layer k. j (k) And, neuron N j (k) The signal input to And, neuron N j (k) This shows the signal output from and .

[0059] Specifically, the (k-1) neuron N1 (k-1) Neuron N m (k-1 ) z1 is the output signal of each of the following: (k-1) ~z m (k-1) However, neuron N j ( k) It is outputting towards neuron N. j (k) is z1 (k-1) ~z m (k-1) z j (k) Generate z j (k) The (k+1)th is used as the output signal. Output is sent to each neuron in the layer (not shown in the diagram).

[0060] The signals that are input from neurons in the previous layer to neurons in the next layer are transmitted between those neurons. The strength of the synaptic connections (hereinafter referred to as the weighting coefficient) determines the transmission of signals. The degree is determined. In neural network 100, the output from the neurons of the previous layer The signal is multiplied by the corresponding weight coefficient and input to the neuron in the next layer. i is greater than or equal to m Let the following integers represent the (k-1)th neuron N i (k-1) and the k-th layer of neurons N j (k) The weight coefficient of the synapse between w i (k-1) j (k) When this is the case, the kth layer URON N j (k) The signal input to the device can be expressed by equation (1.1).

[0061]

number

[0062] In other words, the (k-1)th layer neuron N1 (k-1) Neuron N m (k-1) of From each, the k-th layer neurons N j (k) When a signal is transmitted to z1, the signal in question is z1 (k-1) ~z m (k-1) Each of these has a weighting coefficient w1 corresponding to the respective signal. (k-1) j (k) Or maybe lol m (k-1) j (k) This is multiplied. Then, the neuron N in layer k...j ( k) includes w1 (k-1) j (k) ·z1 (k-1) to w m (k-1) j (k) ·z m (k-1) is input. At this time, the neuron N in the k-th layer j (k) The sum u of the signals input to is given by Equation (1.2). j (k) <000**********

[0063]

Equation

[0064] Neuron N j (k) generates an output signal z according to u j (k) Here j The output signal z from neuron N (k) is defined by the following equation. j (k) j (k) <000**********

[0065] <000**********

Equation

[0066] The function f(u j (k) ) is an activation function in a hierarchical neural network and functions such as the step function, linear ramp function, sigmoid function, etc. can be used. Note that the activation function may be the same for all neurons, or may be different. In addition the activation function of neurons may be the same or different for each layer.

[0067] By the way, the signals output by neurons in each layer may be analog values ​​or digital values. It can be treated as a value. As a digital value, for example, it can be a binary value or a ternary value. For analog values, activation functions include, for example, the linear ramp function and the sigmoid function. You can use this. In the case of a binary digital value, for example, the output can be -1 or 1, or 0. Alternatively, a step function set to 1 can be used. Also, the signals output by neurons in each layer It may have three or more values, in which case the activation function has three values, for example the outputs are -1, 0, or If you use a step function where is 1, or a step function where is 0, 1, or 2, good.

[0068] The neural network 100 is formed when an input signal is input to the first layer (input layer) So, in each layer from the first layer (input layer) to the last layer (output layer), the input is processed sequentially from the previous layer. Based on the transmitted signal, an output signal is generated using equations (1.1) to (1.3), and the output The operation involves outputting a force signal to the next layer. The signal output from the last layer (output layer) is then used to generate a new signal. This corresponds to the result calculated by RAL network 100.

[0069] <Example of arithmetic circuit configuration> Here, in the neural network 100 described above, equation (1.2) and equation (1 An example of an arithmetic circuit that can perform the calculation in 3) will be described. For example, the weight coefficients of the synaptic circuits in neural network 100 are binary. (A combination of "-1" and "+1", or a combination of "0" and "+1", etc.), or 3 The value is a combination of "-1", "0", and "1", and the neuron's activation function is binary. (A combination of "-1" and "+1", or a combination of "0" and "+1", etc.), or 3 This function will output a value (such as a combination of "-1", "0", and "1"). In books and other texts, the weight coefficient and the signal input from the previous layer neuron to the next layer neuron are used. Regarding the value (sometimes called the calculated value), one of them shall be called the first data. The other is sometimes referred to as the second data.

[0070] The calculation circuit 110 shown in Figure 2 includes, as an example, an array unit ALP, a circuit ILD, and a circuit W This is a semiconductor device having an LD, an XLD circuit, and an AFP circuit. The arithmetic circuit 110 is Neurons N1 in layer k in Figures 1A and 1B (k) Neuron N n (k) to Input signal z1 (k-1) ~z m (k-1) Process, neuron N1 (k) No Destination neuron N n (k) The signal z1 is output from each of them. (k) ~z n (k) generate This is a circuit that does that.

[0071] Furthermore, the entirety or a part thereof of the arithmetic circuit 110 may be subjected to a neural network or It can be used for purposes other than AI. For example, for calculations related to graphics or scientific calculations. And when performing multiply-accumulate operations or matrix operations, the entire arithmetic circuit 110, or its You may use a portion of it to perform processing. In other words, not only calculations for AI, but also general calculations. For this purpose, the entirety or a part thereof of the arithmetic circuit 110 may be used.

[0072] Circuit ILD is, for example, a wiring IL[1] through wiring IL[n] and wiring ILB[1] The circuit WLD is electrically connected to the wiring ILB[n]. For example, the wiring WL It is electrically connected to S[1] or wiring WLS[m]. Circuit XLD is, for example, wiring It is electrically connected to XLS[1] or wiring XLS[m]. Circuit AFP is an example. And, wiring OL[1] to wiring OL[n] and wiring OLB[1] to wiring OLB[n], It is electrically connected to it.

[0073] <<Array Unit ALP>> The array unit ALP has, for example, m × n circuits MP. Within the ALP array section, they are arranged in an m x n matrix. In Figure 2, row i, column j (where i is an integer between 1 and m, and j is an integer between 1 and n). It is a number. The circuit MP located at ( ) is denoted as circuit MP[i,j]. However, in Figure 2 These are circuit MP[1,1], circuit MP[m,1], circuit MP[i,j], and circuit MP[1,n Only circuit MP[m,n] is shown in the diagram; other circuit MPs are omitted from the diagram. It is.

[0074] Circuit MP[i,j] is, for example, a combination of wiring IL[j], wiring ILB[j], and wiring W LS[i], wiring XLS[i], wiring OL[j], wiring OLB[j], and electrical Connected.

[0075] Circuit MP[i,j] is, for example, a neuron N i (k-1) and neuron N j (k ) The weight coefficient between (sometimes referred to as either the first data or the second data. Here) It has the function of holding (referred to as the first data). Specifically, the circuit MP[i,j] is Based on the first data (weighting coefficient) input from wiring IL[j] and wiring ILB[j] It stores information (e.g., potential, resistance, current, etc.). Also, the circuit MP[i,j] , Neuron N i (k-1) The signal z output from i (k-1) (First data or second data) The product of the other data (sometimes referred to as the second data, which we will call the second data here) and the first data. It has the function of outputting. For example, circuit MP[i,j] is wired XLS[i ] from the second data z i (k-1) When this is input, the product of the first data and the second data is The corresponding current (e.g., current, voltage, etc.) is output to wiring OL[j] and wiring OLB[j]. This relates to information (e.g., current, voltage, etc.) or the product of the first data and the second data. Information (e.g., current, voltage, etc.) is output to wiring OL[j] and wiring OLB[j]. Oh, an example has been shown where wiring IL[j] and wiring ILB[j] are arranged, but the present invention One embodiment is not limited to this. Either one of wiring IL[j] and wiring ILB[j] Only may be placed. Note that wiring OL[j] and wiring OLB[j] are placed. Although an example of the case has been shown, one aspect of the present invention is not limited thereto. Wiring OL[j] and Only one of the wiring OLB[j] may be present.

[0076] <<Circuit ILD>> Circuit ILD is, for example, a wiring IL[1] through wiring IL[n] and wiring ILB[1] Through the wiring ILB[n], the same of circuit MP[1,1] to circuit MP[m,n] For each of these, the weight coefficient is the first data w1 (k-1) 1 (k) Or maybe lol m (k-1) n (k) It has a function to input corresponding information (e.g., electric potential, resistance value, current value, etc.). As a specific example, circuit ILD has a first weighting coefficient for circuit MP[i,j] Data w i (k-1) j (k) Corresponding information (e.g., electric potential, resistance, or current value) These are supplied by wiring IL[j] and wiring ILB[j].

[0077] <<Circuit WLD>> Circuit WLD is, for example, a source of information corresponding to the first data input from circuit ILD (for example) It also has a function to select the circuit MP to which values ​​(such as potential, resistance, and current) will be written. For example, circuits MP[i,1] to MP[i,n] located in row i of the array ALP When writing information (e.g., potential, resistance, current, etc.) to the WLD circuit, for example, For example, the writing switching element included in circuit MP[i,1] to circuit MP[i,n] A signal is supplied to the wiring WLS[i] to turn the child on or off, except for row i. A potential that turns off the writing switching element included in the circuit MP is supplied to the wiring WLS. It is sufficient to supply it. Note that the example shown is for the case where wiring WLS[i] is installed, but this invention The embodiment is not limited thereto. For example, the wiring WLS[i] is arranged as multiple wirings. That's fine.

[0078] <<Circuit XLD>> Circuit XLD, for example, connects to circuit M via wiring XLS[1] to wiring XLS[n]. For each of P[1,1] or the circuit MP[m,n], neuron N1 (k-1) No Destination neuron N m (k-1) The second data z1 corresponds to the calculated value output from (k-1) ~z m (k-1) It has the function of supplying. Specifically, circuit XLD has the function of supplying circuit MP[i For a circuit MP[i,n], neuron N i (k-1) The second output from Data Z i (k-1) The corresponding information (e.g., potential, current value, etc.) is stored in the wiring XLS[i It is supplied by ]. Note that the example shown is for when wiring XLS[i] is present, but this One aspect of the invention is not limited thereto. For example, the wiring XLS[i] may be a plurality of wirings. You may place it there.

[0079] <<Circuit AFP>> Circuit AFP may include, for example, circuits ACTF[1] to ACTF[n]. Circuit ACTF[j] is, for example, a combination of wiring OL[j] and wiring OLB[j]. They are electrically connected. Circuit ACTF[j] is, for example, wiring OL[j] And according to the information input from the wiring OLB[j] (e.g., potential, current value, etc.) It generates a signal. For example, it takes input from wiring OL[j] and wiring OLB[j]. The information (for example, electric potential or current value) is compared, and the reliability is determined based on the comparison result. It generates a signal. This signal is sent to neuron N. j (k) The signal z output from j (k) Equivalent to In other words, circuits ACTF[1] through ACTF[n] are, for example, as described above. It functions as a circuit that performs calculations on the activation function of a neural network. However, this invention This is not limited to the above. For example, circuits ACTF[1] to ACTF[n] It may have the function of converting analog signals to digital signals. Or, for example, Circuit ACTF[1] or ACTF[n] has the function of amplifying and outputting analog signals. Furthermore, it may also have a function to convert the output impedance. Note that the ACTF circuit is While examples of placement have been shown, the present invention is not limited thereto. It is not necessary for F to be placed.

[0080] Circuits ACTF[1] to ACTF[n] have, as an example, the circuit configuration shown in Figure 3A. This is possible. Figure 3A shows an example of input from wiring OL[j] and wiring OLB[j]. Depending on the current applied, the signal z j (k) This is a circuit that generates [something]. Specifically, Figure 3A shows: The output signal z is represented by two values. j (k) This shows an example of an activation function arithmetic circuit that outputs [the specified value]. It is.

[0081] In Figure 3A, the circuit ACTF[j] consists of resistor RE, resistor REB, and comparator CM. It has P. Resistor elements RE and REB have the function of converting current to voltage. Therefore, any element or circuit that has the function of converting electric current into voltage is not limited to resistive elements. It is not done. Wiring OL[j] is the first terminal of the resistor RE and the first input terminal of the comparator CMP. Electrically connected, the wiring OLB[j] is connected to the first terminal of the resistive element REB and the comparator CM. It is electrically connected to the second input terminal of P. Also, the second terminal of the resistor RE is wired The second terminal of the resistor REB is electrically connected to VAL, and the wiring VAL is electrically connected to VAL. It is connected to the same wiring. It may be connected to the same wire. Alternatively, it may be connected to another wire with the same potential.

[0082] It is preferable that the resistance values ​​of resistor element RE and resistor element REB are equal to each other. For example, the difference in resistance values ​​between resistor RE and resistor REB should be within 10%, which is preferable. Ideally, it should be within 5%. However, in one aspect of the present invention, this is not the case. Not limited to. Depending on the circumstances, or depending on the situation, resistor element RE, resistor element REB Each resistance value may be different from the others.

[0083] Wiring VAL functions, for example, as wiring that provides a constant voltage. For example, VDD is a high-level potential, VSS is a low-level potential, and GND is the ground potential. ) and so on. Furthermore, the constant voltage can be set appropriately according to the configuration of the circuit MP. It is preferable to do so. Furthermore, for example, a pulse signal, rather than a constant voltage, is supplied to the wiring VAL. It's okay if it's not allowed.

[0084] The voltage between the first and second terminals of the resistor RE is the voltage from the wire OL[j]. It is determined according to the current. For this reason, the resistance value of the resistive element RE is set at the first input terminal of the comparator CMP. A voltage corresponding to the current is input. Similarly, the first and second terminals of the resistor REB and The voltage between them is determined by the current flowing from the wiring OLB[j]. Therefore, comparator CM The second input terminal of P receives the resistance value of the resistor REB and a voltage corresponding to the current.

[0085] The comparator CMP, for example, is input to the first input terminal and the second input terminal respectively. A device that compares voltages and outputs a signal from the output terminal of a comparator CMP according to the comparison result. It has the ability to... For example, the comparator CMP... When the voltage input to the child is high, a high-level potential is output from the output terminal of the comparator CMP. If the voltage input to the first input terminal is higher than the voltage input to the second input terminal, low-level The bell potential can be output from the output terminal of the comparator CMP. In other words, the comparator CMP The potential output from the output terminal can be either a high-level potential or a low-level potential, therefore the circuit The output signal z of ACTF[j] j (k) It can be represented as a binary value. For example, comparison The high-level potential and low-level potential output from the output terminal of the CMP unit are, respectively, the output signals. z j (k) It can be used to correspond to "+1" and "-1". Also, in some cases, The high-level potential and low-level potential output from the output terminal of the comparator CMP are, respectively, the output signal z j (k) It can also be represented as "+1" and "0".

[0086] Furthermore, in the circuit ACTF[j] in Figure 3A, resistors RE and REB were used, Any element or circuit that has the function of converting electric current into voltage is not limited to a resistive element. Therefore, the resistors RE and REB in the circuit ACTF[j] in Figure 3A are separate circuit elements. It can be replaced with a child. For example, the circuit ACTF[j] shown in Figure 3B is the same as the circuit in Figure 3A. Resistors RE and REB included in path ACTF[j] are capacitive elements CE and capacitive elements This circuit replaces CEB and performs almost the same operation as the ACTF[j] circuit in Figure 3A. This is possible. Note that the capacitance values ​​of the capacitive elements CE and CEB are relative to each other. It is preferable that they be equal. For example, the respective capacitance values ​​of capacitive element CE and capacitive element CEB. The difference should preferably be within 10%, and more preferably within 5%. However, the present invention is not limited to this aspect. A circuit for initializing the charged charge may be provided. For example, in parallel with the capacitive element CE, A switch may be provided. That is, the second terminal of the switch is connected to the wiring VAL. The first terminal of the switch is connected to the first terminal of the capacitive element CE, the wiring OL[j], and the comparator. It may be connected to the first input terminal of the CMP. Alternatively, the second terminal of the switch may be connected to wiring V AL is connected to a different wiring, and the first terminal of the switch is connected to the first terminal of the capacitive element CE, and the wiring OL[j] and the first input terminal of the comparator CMP may also be connected. Also, see Figure 3 The circuit ACTF[j] shown in C includes the resistor RE, which is included in the circuit ACTF[j] in Figure 3A. This circuit replaces the resistor REB with diodes DE and DEB. The circuit ACTF[j] in Figure 3A can perform almost the same operation. Diode element D E. The orientation of diode element DEB (the connection point between the anode and cathode) is determined by the power of the wiring VAL. It is desirable to adjust the size as appropriate depending on the magnitude of the position.

[0087] Furthermore, the comparator CMP included in the ACTF[j] circuit in Figures 3A to 3C is, as an example, It can be replaced with an operational amplifier OP. The circuit ACTF[j] shown in Figure 3D is shown in Figure 3 The circuit diagram shows the ACTF[j] circuit A with the comparator CMP replaced by an operational amplifier OP. ru.

[0088] Also, even if switches S01a and S01b are added to the ACTF[j] circuit in Figure 3B Good. As a result, the circuit ACTF[j] is determined by the capacitance elements CE and CEB respectively. It is possible to maintain a potential corresponding to the current input from wiring OL[j] and wiring OLB[j]. Yes. As an example of a specific circuit, as shown in Figure 3E, the first of switch S01a A wire OL[j] is electrically connected to the terminal, and a capacitive element CE is connected to the second terminal of switch S01a. The first terminal of the switch S01b is electrically connected to the first input terminal of the comparator CMP, and the first terminal of the switch S01b is electrically connected to the first input terminal of the comparator CMP. A wiring OLB[j] is electrically connected to terminal 1, and a capacitive element is connected to terminal 2 of switch S01b. The configuration should be such that the first terminal of the CEB is electrically connected to the second input terminal of the comparator CMP. i. In the ACTF[j] circuit of Figure 3E, the first and second input terminals of the comparator CMP are respectively When the potentials of wiring OL[j] and wiring OLB[j] are input, switch S01a, switch This can be done by turning on each of the S01b switches. By turning off switches S01a and S01b respectively, a comparison can be made. The potentials input to the first and second input terminals of the CMP are measured by the capacitive element CE. It can be held in the quantitative element CEB. Note that switches S01a and S01b are used. For example, applying an electrical switch such as an analog switch or a transistor. This is possible. Also, as switches S01a and S01b, for example, mechanical switches A switch may be applied. Furthermore, transistors may be applied to switches S01a and S01b. When used, the transistor is an OS transistor, or a silicon transistor in the channel formation region. It can be a transistor having a silicon (hereinafter referred to as a Si transistor). Alternatively, control the duration for which each of switches S01a and S01b remains in the ON state. By doing so, the voltage values ​​of capacitive elements CE and CEB can be controlled. For example, if the current flowing through capacitive elements CE and CEB is large, switch S01 a. By shortening the period during which each of switches S01b is kept in the ON state, This prevents the voltage values ​​of capacitive elements CE and CEB from becoming too high.

[0089] Furthermore, the comparator CMP included in the circuit ACTF[j] in Figures 3A to 3C and 3E is, for example, For example, it can be a chopper-type comparator. The comparator CMP shown in Figure 3F is a chopper This shows the type of comparator, and the comparator CMP is for switch S02a, switch S02b, switch It has a switch S03, a capacitive element CC, and an inverter circuit INV3. Switch S02b and Switch S03 are the same as the aforementioned Switch S01a and Switch S Similar to 01b, transistors such as mechanical switches, OS transistors, and Si transistors. It can be made into a zista.

[0090] The first terminal of switch S02a is electrically connected to terminal VinT, and switch S02b The first terminal of the switch S02a is electrically connected to terminal VrefT, and the second terminal of the switch S02a is The second terminal of switch S02b is electrically connected to the first terminal of capacitive element CC. The second terminal of the capacitive element CC is connected to the input terminal of the inverter circuit INV3 and the terminal of the switch S03. Terminal 1 is electrically connected to the output of the inverter circuit INV3. Terminal VoutT is the output of the inverter circuit INV3. The power terminal is electrically connected to the second terminal of switch S03.

[0091] Terminal VinT functions as a terminal for inputting the input potential to comparator CMP, and terminal V refT functions as a terminal for inputting a reference potential to the comparator CMP, and terminal Vout T functions as a terminal for outputting the output potential from the comparator CMP. Note that terminal Vi nT corresponds to either the first or second terminal of the comparator CMP in Figures 3A to 3C and 3E. The terminal VrefT is the first or second terminal of the comparator CMP in Figures 3A to 3C and 3E. It can respond to the other side of the child.

[0092] The circuit ACTF[j] in Figures 3A to 3E is an output signal z represented by a binary value. j (k) This is an activation function arithmetic circuit that outputs z, but the circuit ACTF[j] is the output signal z j (k) of The configuration may also output three or more values, or as analog values.

[0093] Figures 4A to 4F show the current input from wiring OL[j] and wiring OLB[j]. , signal z j (k) This is a circuit that generates an output signal z, which is represented by three values. j (k) Leave An example of an operational circuit for the activation function is shown.

[0094] The circuit ACTF[j] shown in Figure 4A consists of resistor RE, resistor REB, and comparator CMPa , and has a comparator CMPb. Wiring OL[j] is connected to the first terminal of the resistor RE and comparator CM The first input terminal of Pa is electrically connected to the wiring OLB[j], and the first resistor of REB The terminal is electrically connected to the first input terminal of comparator CMPb. The second input terminal of Pa and the second input terminal of comparator CMPb are electrically connected to the wiring VrefL. It is connected to the following. Furthermore, the second terminal of the resistor RE is electrically connected to the wiring VAL. The second terminal of resistor REB is electrically connected to wiring VAL.

[0095] Wiring VrefL is constant voltage V ref It functions as a voltage line that provides V ref For example, It is preferable that it be above GND and below VDD. Also, depending on the situation, V ref G The potential may be less than ND, or higher than VDD. ref The comparator is CMPa. This is treated as the reference potential (comparison potential) in the comparator CMPb.

[0096] The voltage between the first and second terminals of the resistor RE is the voltage from the wire OL[j]. It is determined according to the current. For this reason, the resistance of the resistive element RE is connected to the first input terminal of the comparator CMPa. A voltage corresponding to the value and current is input. Similarly, the first and second terminals of the resistor REB The voltage between them is determined by the current flowing from the wiring OLB[j]. Therefore, comparison The first input terminal of the CMPb device receives the resistance value of the REB resistor and a voltage corresponding to the current. It will be done.

[0097] The comparator CMPa compares the voltages input to the first input terminal and the second input terminal, respectively. Then, depending on the comparison result, a signal is output from the output terminal of the comparator CMPa. For example, The comparator CMPa is determined by the voltage input to the second input terminal being greater than the voltage input to the first input terminal. V ref When the ) is high, the high-level potential is output from the output terminal of comparator CMPa, and the second input Voltage (V) input to the power terminal ref When the voltage input to the first input terminal is higher than ) The low-level potential can be output from the output terminal of the comparator CMPa.

[0098] Comparator CMPb, like comparator CMPa, uses the first input terminal and the second input terminal respectively. The input voltage is compared, and according to the comparison result, a signal is sent from the output terminal of the comparator CMPb. It outputs a number. For example, comparator CMPb outputs a number that is higher than the voltage input to the first input terminal. Voltage (V) input to the power terminal ref When the high level potential is high, the output of comparator CMPb The voltage (V) output from the power terminal and input to the second input terminal is measured. ref ) is entered into the first input terminal When the applied voltage is high, a low-level potential is output from the output terminal of the comparator CMPb. It is possible.

[0099] At this time, the potentials output from the respective output terminals of comparator CMPa and comparator CMPb Accordingly, the three-value output signal z j (k) It can represent the output of comparator CMPa. For example, the output of comparator CMPa A high-level potential is output from the power terminal, and a low-level potential is output from the output terminal of comparator CMPb. If this occurs, the output signal z j (k) Set to "+1", and the low level is output from the output terminal of the comparator CMPa. If a low potential is output and a high-level potential is output from the output terminal of comparator CMPb, the output signal z j (k)Set to "-1", and a low-level potential is output from the output terminal of the comparator CMPa. If a low-level potential is output from the output terminal of comparator CMPb, the output signal z j (k) teeth It can be set to "+0".

[0100] Furthermore, the ACTF[j] circuit is not limited to the circuit configuration shown in Figure 4A, but can be adapted depending on the situation. It can be changed. For example, in the circuit ACTF[j] in Figure 4A, the comparator CMPa If you want to combine the two output results of the comparator CMPb into a single signal, use the ACTF circuit. A conversion circuit TRF can be provided at [j]. The circuit ACTF[j] in Figure 4B is the same as the circuit in Figure 4A. This is an example configuration in which a conversion circuit TRF is provided to ACTF[j], and the comparators CMPa and CMPb Each output terminal is electrically connected to the input terminal of the conversion circuit TRF. A concrete example of RF is a digital-to-analog conversion circuit (in this case, the signal z j (k) is A This will be an analog value. ) (This can be expressed as follows.)

[0101] Furthermore, for example, in Figure 4A, the second inputs of comparators CMPa and CMPb The wiring VrefL that is electrically connected to the power terminal is connected to the wiring Vref1L and Vref2L. They can be replaced with separate wires. Circuit ACTF[j] in Figure 4C is the same as circuit ACTF in Figure 4A. The second terminal of comparator CMPa included in [j] is wired Vref1, not wired VrefL. Electrically connected to L, the second terminal of comparator CMPb is wired Vref, not wired VrefL. It is configured to be electrically connected to 2L. Wiring Vref1L and Vref2L are input. By setting the potentials to be applied to each other to different values, the comparators CMPa and CMPb The reference potentials can be set separately.

[0102] Furthermore, for example, an amplifier circuit is a configuration different from the ACTF[j] circuit shown in Figures 4A to 4C. Alternatively, an impedance conversion circuit may be used. For example, the circuit AC shown in Figure 4D. TF[j] can be applied to the circuit AFP of the calculation circuit 110 in Figure 2. Circuit in Figure 4D ACTF[j] refers to the resistor RE, the resistor REB, the operational amplifier OPa, and the operational amplifier OP. It has b and functions as an amplification circuit.

[0103] Wiring OL[j] connects the first terminal of the resistor RE and the non-inverting input terminal of the operational amplifier OPa. Electrically connected, the wiring OLB[j] is connected to the first terminal of the resistive element REB and the op-amp O It is electrically connected to the non-inverting input terminal of Pb. Also, it is connected to the inverting input of the operational amplifier OPa. The terminal is electrically connected to the output terminal of op-amp OPa and to the inverting input of op-amp OPb. The terminal is electrically connected to the output terminal of the operational amplifier OPb. Furthermore, the resistor RE The second terminal is electrically connected to the wiring VAL, and the second terminal of the resistor REB is connected to the wiring VAL. It is electrically connected to it.

[0104] In other words, the operational amplifiers OPa and O are included in the ACTF[j] circuit in Figure 4D. Pb is configured as a voltage follower. This allows the op-amp OPa to The potential output from the output terminal is the same as the potential input to the non-inverting input terminal of the operational amplifier OPa. They become almost equal, and the potential output from the output terminal of the op-amp OPb is, This becomes approximately equal to the potential input to the non-inverting input terminal. In this case, the output signal z j (k) teeth The two analog values ​​are output from the ACTF[j] circuit. Note that the operational amplifier OPa Connect the output terminal of the op-amp OPb to the input terminal of the comparator CMP, respectively. You may continue. Then, take the output from comparator CMP as the output signal z j (k) That is also acceptable.

[0105] Furthermore, for example, as a configuration different from the ACTF[j] circuit in Figures 4A to 4D, an integrating circuit Alternatively, a current-voltage conversion circuit may be used. Furthermore, an operational amplifier can be used to perform integration. A circuit or current-voltage conversion circuit may be constructed. As an example, the circuit ACT shown in Figure 4E. F[j] can be applied to circuit AFP of the calculation circuit 110 in Figure 2. CTF[j] refers to the operational amplifiers OPa, OPb, load element LEa, and load element LE. It has b.

[0106] Wiring OL[j] connects to the first input terminal of the operational amplifier OPa (e.g., the inverting input terminal) and the negative The first terminal of the charge element LEa is electrically connected to the OLB[j] wiring, and the op-amp OP The first input terminal of b (for example, the inverting input terminal) and the first terminal of the load element LEb are electrically connected. They are connected. Also, the second input terminal of the op-amp OPa (for example, the non-inverting input terminal) is , electrically connected to the wiring Vref1L, and the second input terminal of the op-amp OPb (for example, non The inverting input terminal is electrically connected to wiring Vref2L. The second of the load element LEa The terminal is electrically connected to the output terminal of the operational amplifier OPa, and the second terminal of the load element LEa is It is electrically connected to the output terminal of the operational amplifier OPb.

[0107] Note that the wiring Vref1L and Vref2L here have the same voltage, or different voltages. It functions as wiring that supplies voltage. Therefore, wiring Vref1L, wiring Vref2 L can sometimes be combined into a single wire.

[0108] In the circuit ACTF[j] in Figure 4E, the load elements LEa and LEb are, for example, For example, they can be resistive elements or capacitive elements. In particular, load elements LEa and load elements LEb By using a capacitive element, the operational amplifier OPa and load element LEa, the operational amplifier OPb and the load element LEb each function as an integrating circuit. In other words, the wiring OL[j] Alternatively, depending on the amount of current flowing through the wiring OLB[j], each capacitive element (load element LEa Charge is stored in (LEb). In other words, it flows from wiring OL[j] and wiring OLB[j]. The current is converted into a voltage by an integrating circuit, and the integrated current is then converted into a signal z j (k) year The output is then connected to the output terminals of the operational amplifier OPa and the output terminals of the operational amplifier OPB. They may be connected to the input terminals of the comparator CMP. And the output from the comparator CMP output signal z j (k) This is also acceptable. Note that the capacitive elements of load element LEa and load element LEb A circuit may be provided to initialize the charge accumulated in the load element LEa( A switch may be provided in parallel with the capacitive element. That is, the second terminal of the switch is The output terminal of the op-amp OPa is connected, and the first terminal of the switch is wired OL[j], Furthermore, it may be connected to the first input terminal of the operational amplifier OPa (for example, the inverting input terminal). stomach.

[0109] Furthermore, in the circuit ACTF[j] in Figure 4E, from wiring OL[j] and wiring OLB[j] If you want to convert the flowing current into a voltage and output it, the load elements LEa and LEb are as follows: Besides capacitive elements, resistive elements can also be used.

[0110] Furthermore, for example, as a configuration different from the circuit ACTF[j] in Figures 4A to 4E, Figure 4F shows The circuit ACTF[j] shown can be applied to the circuit AFP of the calculation circuit 110 in Figure 2. The circuit ACTF[j] in Figure 4F consists of resistor RE, resistor REB, and analog-to-digital converter. It has an ADCa circuit and an ADCb analog-to-digital conversion circuit.

[0111] Wiring OL[j] connects the input terminal of the analog-to-digital conversion circuit ADCa to the resistor RE. The first terminal is electrically connected to the wiring OLB[j], and the analog-to-digital conversion circuit AD The input terminal of Cb is electrically connected to the first terminal of the resistive element REB. The second terminal of RE is electrically connected to the wiring VAL, and the second terminal of the resistor REB is connected to the wiring It is electrically connected to VAL.

[0112] In the circuit ACTF[j] in Figure 4F, the current flows from wiring OL[j] and wiring OLB[j]. The potential of the first terminals of resistor RE and resistor REB is determined according to the current. The ACTF[j] circuit converts the analog potential to an analog-to-digital value. The ADCa and ADCb lines produce binary or triple or more (e.g., 256 values) digital signals. Convert to z value and the signal z j (k) It has the function to output as such.

[0113] Note that the resistors RE and REB shown in Figures 4A to 4F are the same as those in Figures 3B and 3C. Similarly, capacitive element CE, capacitive element CEB, or diode element DE, diode element DE It can be replaced with B. In particular, the resistive element RE shown in Figures 4A to 4F, resistive element If REB is replaced with capacitive elements CE and CEB, the switch will be similar to that shown in Figure 3E. By providing switch S01a and switch S01b, wiring OL[j] and wiring OLB[j] It can retain the input potential.

[0114] Note that the calculation circuit 110 in Figure 2 is configured according to the circuit configuration of circuit MP[i,j] The number of wires electrically connected to i,j can be changed. For example, in Figure 2 In the arithmetic circuit 110, the wiring WLS[i ] can be one or more wires. Also, for example, in circuit MP[i,j] The electrically connected wiring XLS[i] can consist of one or more wires. .

[0115] <<Circuit MP>> Next, we will describe an example of the configuration of the circuit MP[i,j] included in the arithmetic circuit 110.

[0116] Figure 5A shows an example configuration of the circuit MP[i,j] that can be applied to the arithmetic circuit 110. A path MP[i,j] includes, for example, circuit MC and circuit MCr. In circuit MCr, the weight coefficient and the input signal (calculated value) of the neuron are used in circuit MP. This is a circuit that calculates the product of [the two numbers]. Circuit MC has the same configuration as circuit MCr, or a different configuration from circuit MCr. This configuration is possible. Therefore, to distinguish the circuit MCr from the circuit MC, The letter "r" is added to the number. Also, the symbols of the circuit elements described later, which are included in circuit MCr, It also has "r" added to it.

[0117] For example, a circuit MC has a retaining part HC, and a circuit MCr has a retaining part HCr. The retaining part HC and the retaining part HCr each contain information (e.g., potential, resistance, or electric current). It has a function to hold (such as current values). Note that the first data set in circuit MP[i,j] w i (k-1) j (k) This refers to the information held in the retaining part HC and the retaining part HCr, respectively (example) For example, it is determined according to the potential, resistance, or current value. Therefore, the holding part HC And each of the holding part HCr is the first data w i (k-1) j (k) Each piece of information corresponding to (example) For example, wiring IL[j] and wiring ILB[ that supply potential, resistance, or current values, etc. It is electrically connected to [j].

[0118] Wiring WL[i] shown in Figure 5A corresponds to wiring WLS[i] in Figure 2. Wiring W L[i] is electrically connected to the holding part HC and the holding part HCr, respectively. Circuit M The first data w is assigned to each of the retaining part HC and retaining part HCr contained in P[i,j]. i (k -1) j (k) Write down the corresponding information (e.g., electric potential, resistance, or current). At that time, by supplying a predetermined potential to the wiring WL[i], the wiring IL[j] and the holding part H Connect C to a conductive state, and connect the wiring ILB[j] to the retaining part HCr to a conductive state. The first data w is set for each of the wirings IL[j] and ILB[j]. i (k-1) j (k) to By supplying the appropriate potential, the holding part HC and the holding part HCr are respectively affected. The potential and other parameters can be input. Then, a predetermined potential is supplied to the wiring WL[i], The wiring IL[j] and the retaining part HC are made non-conductive, and the wiring ILB[j] and the retaining part HCr The two are made non-conductive. Then, the first data is applied to the holding part HC and the holding part HCr respectively. w i (k-1) j (k) Each potential and other parameters corresponding to the current are maintained.

[0119] For example, the first data w i (k-1) j (k) The three values ​​are "-1", "0", and "1". Let's consider the case where we choose either one. First data w i (k-1) j (k) If it is "1", here is an example Therefore, a high-level potential is maintained in the holding part HC, and a low-level potential is maintained in the holding part HCr. Also, the first data w i (k-1) j (k) If it is "-1", as an example, the holding part H A low-level potential is maintained in C, and a high-level potential is maintained in the holding part HCr. And, Day 1 Ta lol i (k-1) j (k) If it is "0", for example, a low-level potential is present in the holding part HC. It maintains a low potential in the holding part HCr. As another example, the first data w i (k-1) j (k) This is an analog value, specifically a "negative analog value", "0", or Let's consider the case where it takes a "positive analog value". First data w i(k-1) j (k) is “positive In the case of an "analog value," for example, a high level of analog potential is held in the holding part HC. The holding part HCr maintains a low level potential. Also, the first data w i (k-1) j (k) but" In the case of a "negative analog value," for example, a low-level potential is held in the holding part HC, and the holding part A high level of analog potential is maintained in HCr. And the first data w i (k-1) j (k ) If it is "0", as an example, a low-level potential is maintained in the holding part HC, and the holding part HCr It maintains a low level potential. Note that the analog value is a multi-bit (multi-level) digital value. This is also acceptable. For example, the first data w i (k-1) j (k) However, “1”, If the values ​​are "2" and "3", for example, the retaining part HC will correspond to "1", "2", and "3". It maintains a high potential with a variable potential, and maintains a low potential in the holding part HCr. , 1st data w i (k-1) j (k) For example, if the values ​​are "-1", "-2", and "-3", The holding part HC maintains a low level potential, and the holding part HCr has "-1" and "-2" It maintains a high level of potential corresponding to the absolute values ​​of "-3," which are "1," "2," and "3." And then, the first data w i (k-1) j (k) If it is "0", as an example, the holding part A low potential is maintained in the HC, and a low potential is maintained in the holding part HCr.

[0120] As another example, the circuit MC stores information (for example, potential, resistance value) in the holding part HC. Current or voltage, etc., according to the current value, etc., of the wiring OL[j] or wiring OLB[j] It has the function of outputting to one side, and the circuit MCr has the information (for example, electricity) held in the holding part HCr. Current or voltage, etc., according to position, resistance value, current value, etc., wiring OL[j] or wiring OL It has the function of outputting to the other side of B[j]. For example, a high level potential is held in the holding part HC. If this is the case, the circuit MC outputs a current with a first current value, and a low-level potential is maintained in the holding part HC. If held, the circuit MC shall output a current with a second current value. Similarly, When a high-level potential is maintained in the HCr component, the circuit MCr generates a current with a first current value. When outputting and a low-level potential is maintained in the holding section HCr, the circuit MCr will set the second current value It shall output the current it possesses. The magnitudes of the first current value and the second current value are as follows: The configuration of the circuit MC, circuit MCr, retaining part HC, retaining part HCr, etc., and the first data w i (k- 1) j (k) It is determined by the value of . For example, the first current value is greater than the second current value. It may be large, or it may be small. Furthermore, either the first current value or the second current value may be zero. The current, or current value, may be 0. Alternatively, there may be a current with a first current value and a current with a second current value. In some cases, the direction of current flow may differ between two currents. In particular, for example, the first data w i (k -1) j (k) If it takes one of the three values ​​"-1", "0", or "1", the first current value or It is preferable to configure circuits MC and MCr such that one of the second current values ​​becomes zero. It's fine. Also, the first data w i (k-1) j (k) This is an analog value, for example, "negative analog". If the value is "", "0", or "a positive analog value", then the first current value or the second current value In this regard, one example is that it can take an analog value.

[0121] Furthermore, in this specification, etc., the retaining part HC and the information held in the retaining part HCr (for example) For example, current or voltage corresponding to potential, resistance, current value, etc., is a positive current, voltage, etc. It may be a positive or negative current, a negative voltage, or a mixture of both. In other words, for example, the information held in the aforementioned "holding part HC" (e.g., potential, resistance, current) A current or voltage corresponding to the value (such as) is applied to either wiring OL[j] or wiring OLB[j]. The circuit MCr has an output function, and the information held in the holding part HCr (e.g., potential, resistance) is output. Current, voltage, etc., according to resistance value, current value, etc., of wiring OL[j] or wiring OLB[j] The description "has the function of outputting to the other side" means "information held in the holding unit HC (for example, Current or voltage, etc., according to potential, resistance, current value, etc., is transmitted to wiring OL[j] or wiring O It has the function of discharging from one side of LB[j], and the circuit MCr holds the electricity held in the holding part HCr. It has the function of discharging current corresponding to the position from the other of wiring OL[j] or wiring OLB[j]. This can be rephrased as "ru".

[0122] The wiring X1L[i] and wiring X2L[i] shown in Figure 5A correspond to the wiring XLS in Figure 2. This corresponds to [i]. Note that the second data z is input to circuit MP[i,j].i (k-1) teeth For example, the potential and current of wiring X1L[i] and wiring X2L[i], etc. It is determined by the following. Therefore, for example, the circuit MC and circuit MCr have wiring X1L[ i] and wiring X2L[i], the second data z i (k-1) Each potential corresponding to the input is input. It can be done.

[0123] Circuit MC is electrically connected to wiring OL[j] and wiring OLB[j], and circuit MC r is electrically connected to wiring OL[j] and wiring OLB[j]. Circuit MC and Circuit MCr is, for example, a circuit that receives power input to wiring X1L[i] and wiring X2L[i]. Depending on the position, current, etc., the first data w is sent to wiring OL[j] and wiring OLB[j]. i (k- 1) j (k) and the second data z i (k-1) It outputs current, potential, etc., corresponding to the product of the two. As a concrete example, the output destination of the current from circuit MC and circuit MCr is wiring X1L[i] And determined by the potential of wiring X2L[i]. For example, circuit MC and circuit MCr Each of these is where the current output from the circuit MC is either wiring OL[j] or wiring OLB[j]. The current flows through, and the current output from circuit MCr is sent to the other side of wiring OL[j] or wiring OLB[j]. It has a flowing circuit configuration. In other words, the output from circuit MC and circuit MCr Each current flows through different wiring, not the same wiring. For example, From circuit MC and circuit MCr, electricity is supplied to either wiring OL[j] or wiring OLB[j]. Sometimes the water doesn't flow.

[0124] For example, the second data z i (k-1) The value is one of the three values: "-1", "0", or "1". Let's consider the case where, for example, the second data z i (k-1) If it is "1", then circuit MP is The circuit MC and wiring OL[j] are in a conductive state, and the circuit MCr and wiring OLB[j] This is considered a conductive state. For example, the second data z i (k-1) If it is "-1", then the circuit MP This creates a conductive state between circuit MC and wiring OLB[j], and the circuit MCr and wiring OL[j] The connection between them is made conductive. For example, the second data z i (k-1) If it is "0", then circuit M The currents output by C and circuit MCr are measured by wiring OL[j] and wiring OLB[j]. To prevent flow to either of the ], circuit MP is positioned between circuit MC and wiring OL[j]. , and the circuit MC and the wiring OLB[j] are made non-conductive, and the circuit MCr and the wiring OL[ The connection between [j] and the circuit MCr and the wiring OLB[j] is made non-conductive.

[0125] An example of combining the above actions is shown below. Data 1 w i (k-1) j (k) is "1" In this case, the circuit MC outputs current, and the first data w i (k-1) j (k) is "-1" In this case, the circuit MCr outputs current. Then, the second data z i (k-1) is “1” In this case, the connection between circuit MC and wiring OL[j], and between circuit MCr and wiring OLB[j] A conductive state is established between them. Second data z i(k-1) If it is "-1", then the circuit MC and Conduction occurs between the wiring OLB[j] and the circuit MCr and the wiring OL[j]. Based on the above, the first data w i (k-1) j (k) and the second data z i (k-1) product If the value is positive, current is output to the wiring OL[j]. First data w i (k-1) j (k) and the second data z i (k-1) If the product of the two values ​​is negative, then current flows through the wiring OLB[j]. Output. First data w i (k-1) j (k) and the second data z i (k-1) The product is zero In the case of this value, no current is output to either wire.

[0126] To illustrate the above example with a concrete example, the first data w i (k-1) j (k) is “1” There is, the second data z i (k-1) If it is "1", for example, from circuit MC to wiring OL A current I1[i, j] with a first current value flows through [j], and the circuit MCr is connected to the OLB[j]. A current I2[i,j] with a second current value flows through it. At this time, the magnitude of the second current value is one For example, it is zero. In other words, strictly speaking, the current from circuit MCr to wiring OLB[j] It won't flow. First data lol i (k-1) j (k) The second data z is "-1", and i (k -1) If it is "1", for example, a second current value is transmitted from circuit MC to wiring OL[j]. A current I1[i,j] flows, and a current I2 with a first current value flows from the circuit MCr to the wiring OLB[j]. Currents [i, j] flow. In this case, the magnitude of the second current is, for example, zero. More precisely, no current flows from the circuit MC to the wiring OL[j]. (First data w) i (k- 1) j (k) The second data z is "0". i (k-1) If it is "1", then circuit M A current I1[i,j] with a second current value flows from C to wiring OL[j], and from circuit MCr A current I2[i,j] with a second current value flows through line OLB[j]. At this time, the second current value The magnitude of is, for example, zero. In other words, strictly speaking, the wiring OL[j No current flows through ], and no current flows from circuit MCr to wiring OLB[j].

[0127] Also, the first data w i (k-1) j (k) The second data z is "1", i (k-1 ) If it is "-1", then a current I1[ with the first current value is sent from the circuit MC to the wiring OLB[j] Currents i and j flow, and a second current I2[i, j] with a second current value is drawn from circuit MCr to wiring OL[j]. A current flows. At this time, the magnitude of the second current value is, for example, zero. In other words, strictly speaking In this case, no current flows from circuit MCr to wiring OL[j]. First data w i (k-1) j ( k) The second data z is "-1", andi (k-1) If it is "-1", then the circuit MC or A current I1[i,j] with a second current value flows through the wiring OLB[j], and the wiring from the circuit MCr A current I2[i,j] with a first current value flows through OL[j]. At this time, the second current value For example, the size is zero. In other words, strictly speaking, the wiring from the circuit MC to the OLB[j] No current flows through it. First data w i (k-1) j (k) The second data z is "0". i (k-1) If it is "-1", then the circuit MC has a second current value in the wiring OLB[j]. A current I1[i,j] flows, and a second current I2 with a specific value flows from the circuit MCr to the wiring OL[j]. Currents [i, j] flow. In this case, the magnitude of the second current is, for example, zero. More precisely, no current flows from circuit MC to wiring OLB[j], and no current flows from circuit MCr to wiring O No current flows through L[j].

[0128] Also, the second data z i (k-1) If it is "0", one example is the circuit MC and wiring. The connection between OL[j] and the circuit MC and the wiring OLB[j] becomes non-conductive. Furthermore, between circuit MCr and wiring OL[j], and between circuit MCr and wiring OLB[j] It becomes non-conductive. Therefore, the first data w i (k-1) j (k) Whatever the value No current is output from circuits MC and MCr to wiring OL[j] and wiring OLB[j]. stomach.

[0129] Thus, as an example, the first data w i (k-1)j (k) and the second data z i (k -1) If the product of the two takes a positive value, then either circuit MC or circuit MCr is used for wiring. Current flows through OL[j]. At this time, the first data w i (k-1) j (k) In the case where the value is positive In this case, current flows from the circuit MC to the wiring OL[j], and the first data w i (k-1) j (k) If the value is negative, current flows from circuit MCr to wiring OL[j]. On the other hand, the first data w i (k-1) j (k) and the second data z i (k-1) If the product of these two values ​​is negative, then Current flows through the wiring OLB[j] from either the path MC or the circuit MCr. At this time, First data w i (k-1) j (k) If the value is positive, the wiring OLB[j] from the circuit MC Current flows through it, and the first data w i (k-1) j (k) If the value is negative, then from the circuit MCr Current flows through wiring OLB[j]. Therefore, multiple circuits M connected to wiring OL[j] are affected. The sum of the currents output from C or circuit MCr will flow through wiring OL[j]. In other words, the current flowing through wiring OL[j] will be the sum of positive values. On the other hand, current output from multiple circuit MCs or circuit MCrs connected to the wiring OLB[j] The sum of these will flow into wiring OLB[j]. In other words, in wiring OLB[j], negative A current equal to the sum of the values ​​will flow. As a result of the above operation, the wiring OL[ The total current value flowing through [j], that is, the sum of positive values, and the total current value flowing through the wiring OLB[j], In other words, by using the sum of negative values, it is possible to perform sum-of-products operations. If the total current flowing through wiring OL[j] is greater than the total current flowing through wiring OLB[j] If the value is large, it can be determined that the result of the sum-of-products operation will be a positive value. If the total current flowing through OL[j] is less than the total current flowing through wiring OLB[j] In this case, it can be determined that the result of the sum-of-products operation will be a negative value. Wiring OL[j When the total current flowing through ] and the total current flowing through wiring OLB[j] are approximately the same value. It can be concluded that the result of the sum-of-products operation will be zero.

[0130] Note that the second data z i (k-1) is one of the binary values ​​"-1", "0", or "1". For example, in the case of binary values ​​"-1" and "1", or in the case of binary values ​​"0" and "1", the same applies. It can be made to work in this way. Similarly, the first data w i (k-1) j (k) is "-1", If the binary values ​​are either "0" or "1", for example, "-1" and "1", Alternatively, the same operation can be performed for the binary values ​​"0" and "1".

[0131] Note that the first data w i (k-1) j (k) This refers to analog values, or multi-bit (multi-level) values. It may also take a digital value. For example, instead of "-1", you can use "negative analog". The value can be ", and a "positive analog value" can be taken instead of "1". In this case, circuit M The magnitude of the current flowing from C or circuit MCr is also, as an example, the first data w i (k-1 ) j (k) The value will be an analog value corresponding to the absolute value of the value.

[0132] Next, we will explain an example of a modified circuit MP[i,j] in Figure 5A. Regarding the modified version of [i,j], we will mainly explain the differences from the circuit MP[i,j] in Figure 5A. In some cases, the explanation of the parts common to the circuit MP[i,j] in Figure 5A may be omitted.

[0133] The circuit MP[i,j] shown in Figure 5B is a modified version of the circuit MP[i,j] in Figure 5A. Circuit MP[i,j] in 5B is similar to circuit MP[i,j] in Figure 5A, consisting of circuit MC and circuit It has MCr and, however, circuit MP[i,j] in Figure 5B has a holding part HCr in circuit MCr. It differs from the circuit MP[i,j] in Figure 5A in that it does not include [a specific element].

[0134] Furthermore, since the circuit MCr does not have a holding part HCr, the circuit MP[i,j] in Figure 5B The applied calculation circuit uses wiring ILB[j] to supply the potential to be held in the holding part HCr. It is not necessary to have it. In addition, circuit MCr is not electrically connected to wiring WL[i]. That's good too.

[0135] In circuit MP[i,j] in Figure 5B, the retaining part HC included in circuit MC is located in circuit MCr. It is electrically connected to circuit MCr. In other words, circuit MP[i,j] in Figure 5B is electrically connected to circuit MCr. The configuration is such that MC and share a holding part HC with each other. One example is the holding part H The inverted signal of the signal held by C is supplied from the holding unit HC to the circuit MCr. This makes it possible for circuit MC and circuit MCr to operate differently. Alternatively, the internal circuit configurations of circuit MC and circuit MCr may be different, and as a result For the same signal held in the holding section HC, the output voltage is determined by the circuit MC and the circuit MCr. It is also possible to make the flow magnitudes different. Here, the first data w is entered into the holding part HC. i (k-1) j (k) Maintain the potential corresponding to the second data z i (k-1) The potential is distributed according to the By supplying power to line X1L[i] and wiring X2L[i], circuit MP[i,j] is supplied. The first data w is entered into the wiring OL[j] and wiring OLB[j]. i (k-1) j (k) and Day 2 Ta z i (k-1) It can output a current corresponding to the product of the two factors.

[0136] Furthermore, the arithmetic circuit 110 to which the circuit MP shown in Figure 5B is applied is the same as the arithmetic circuit 120 shown in Figure 6. The circuit configuration can be changed. The calculation circuit 120 is wired from the calculation circuit 110 in Figure 2 to IL. The configuration excludes B[1] or wiring ILB[m].

[0137] The circuit MP[i,j] shown in Figure 5C is a modified version of the circuit MP[i,j] in Figure 5A. In essence, this is an example of the configuration of circuit MP[i,j] that can be applied to the arithmetic circuit 120 in Figure 6. Figure 5 Circuit MP[i,j] of C is similar to circuit MP[i,j] in Figure 5A, consisting of circuit MC and circuit M It has Cr and, however, the circuit MP[i,j] in Figure 5C and the circuit MP[i,j] in Figure 5A are The configuration of the electrically connected wiring is different.

[0138] Wiring W1L[i] and W2L[i] shown in Figure 5C correspond to wiring WLS in Figure 6. This corresponds to [i]. Wiring W1L[i] is electrically connected to the retaining part HC, and wiring W2L[i ] is electrically connected to the holding part HCr.

[0139] Furthermore, the wiring IL[j] is electrically connected to the retaining part HC and the retaining part HCr. .

[0140] In the circuit MP[i,j] in Figure 5C, the holding part HC and the holding part HCr are different When maintaining potential, the potential-maintaining operations to the holding part HC and the holding part HCr are not simultaneous. It is preferable to perform the operations sequentially. For example, the first data w of circuit MP[i,j] i (k-1) j (k ) This can be expressed by maintaining a first potential in the holding part HC and a second potential in the holding part HCr. Let's consider the case where a predetermined electrical current is applied to each of the wires W1L[i] and W2L[i]. By assigning a position, electrical contact is established between the retaining part HC and the wiring IL[j], and the retaining part HCr and the wiring The connection between the wire IL[j] and the circuit is made non-conductive. Next, the first potential is supplied to the wiring IL[j]. This allows the first potential to be applied to the holding part HC. After that, the wiring W1L[i] and the wiring A predetermined potential is applied to each of the lines W2L[i], and the distance between the holding part HC and the wiring IL[j] is The connection is made non-conductive, and the connection between the retaining part HCr and the wiring IL[j] is made conductive. Then, By supplying a second potential to the wiring IL[j], a second potential can be applied to the holding part HCr. This allows the circuit MP[i,j] to use w as the first data. i(k-1) j (k) of It can be configured.

[0141] Furthermore, when approximately equal potentials are maintained in both the holding part HC and the holding part HCr (circuit M The first data point w of P[i,j] i (k-1) j (k) However, the same applies to the retaining part HC and the retaining part HCr. (When set by maintaining approximately equal potentials to each other), the holding part HC and the wiring IL The connection between [j] and the holding part HCr and the wiring IL[j] are made conductive. To that end, a predetermined potential is applied to each of the wires W1L[i] and W2L[i], After that, the relevant potential should be supplied to the wiring IL[j].

[0142] The circuit MP[i,j] in Figure 5C has a holding part HC and a holding part HCr with the first data w i (k -1) j (k) Maintain the potential corresponding to the second data z i (k-1) Wiring X to determine the appropriate potential By supplying 1L[i] and wiring X2L[i], the circuit MP[i,j] in Figure 5A Similarly, the first data w is set for wiring OL[j] and wiring OLB[j]. i (k-1) j (k) and the second data z i (k-1) It can output a current corresponding to the product of the two factors.

[0143] The circuit MP[i,j] shown in Figure 5D is a modified version of the circuit MP[i,j] in Figure 5A. Circuit MP[i,j] in 5D is similar to circuit MP[i,j] in Figure 5A, consisting of circuit MC and circuit It has MCr and, however, circuit MP[i,j] in Figure 5D and circuit MP[i,j] in Figure 5A The configuration of the electrically connected wiring is different.

[0144] The wiring IOL[j] in Figure 5D is the same as the wiring IL[j] and wiring OL[j] in Figure 5A. It functions as a wiring diagram compiled in a book, and wiring IOLB[j] in Figure 5D corresponds to wiring I in Figure 5A. It functions as a single wire combining LB[j] and wiring OLB[j]. Therefore, wiring IOL[j] is electrically connected to the retaining part HC, the circuit MC, and the circuit MCr, and wiring IOLB[j] is electrically connected to the holding part HCr, the circuit MC, and the circuit MCr. Yes, they are.

[0145] The first data point w is in the circuit MP[i,j] in Figure 5D. i (k-1) j (k) When holding, Therefore, between circuit MC and wiring IOL[j], and between circuit MC and wiring IOLB[j] The circuit becomes non-conductive, and the circuit MCr and the wiring IOL[j], and the circuit MCr and the wiring Wiring X1L[i] and wiring X2L[ A predetermined potential is input to [i]. Then, a predetermined potential is input to the wiring WL[i] and held. The connection between part HC and wiring IOL[j] is made conductive, and the connection between the holding part HCr and wiring IOL[j] By creating a conductive state between ] and each of the wiring IOL[j] and wiring IOLB[j], 1 data w i (k-1) j (k) By supplying various potentials according to the requirements, the holding part HC, Each of the holding part HCr can be input to a different potential. The connection between the wire IOL[j] and the holding part HCr and the wiring IOLB[j] is non-conductive, and the connection between the holding part HCr and the wiring IOLB[j] By inputting a predetermined potential to the wiring WL[i] so that the space between them becomes non-conductive, For each of the holding part HC and the retaining part HCr, the first data w i (k-1) j (k) Each It can maintain electrical potential.

[0146] First data w for each of the retaining part HC and retaining part HCr i (k-1) j (k) in response After maintaining the potential, the second data z i (k-1) The potential corresponding to the wiring X1L[i] and By supplying power to wiring X2L[i], the wiring is configured similarly to circuit MP[i,j] in Figure 5A. OL[j] and wiring OLB[j], first data w i (k-1) j (k) and the second data z i (k-1) It can output a current corresponding to the product of the two factors.

[0147] Furthermore, the calculation circuit 110 to which the circuit MP shown in Figure 5D is applied is the same as the calculation circuit 130 shown in Figure 7. The circuit configuration can be changed. The arithmetic circuit 130 is arranged in the arithmetic circuit 110 of Figure 2. Lines IL[1] through wiring IL[n] and wiring OL[1] through wiring OL[n] are connected to wiring IO. Group them together as L[1] or wiring IOL[n], and wiring ILB[1] or wiring ILB[n] , wiring OLB[1] to wiring OLB[n] and, wiring IOLB[1] to wiring IOLB[ The configuration is grouped as n]. Also, in the arithmetic circuit 130, the wiring IOL[1 ] or wiring IOL[n], wiring IOLB[1] or wiring IOLB[n] are connected to circuit ILD and It is electrically connected to circuits ACTF[1] through ACTF[n]. That is, wiring I OL[1] to wiring IOL[n], wiring IOLB[1] to wiring IOLB[n] are circuits For MP[1,j] to MP[m,j], the first data w i (k-1) j (k) Send It has the functions of a signal line for doing so and a current line for supplying current to the ACTF[j] circuit. In this case, when transmitting the first data wi(k-1)j(k) to circuit MP[i,j] Circuit ILD is connected to the wiring IOL[j] and to the circuit ILD and IOLB[j]. By creating a conductive state between the two, circuit ACTF[j] and wiring IOL[j] It is preferable to make the connection between and and the connection between circuits ACTF[j] and IOLB[j] non-conductive. And when supplying current to circuit ACTF[j], circuit ILD and The connection between wiring IOL[j] and circuit ILD and IOLB[j] is made non-conductive, and the circuit ACTF[j] is between circuit ACTF[j] and wiring IOL[j], and circuit ACTF[j It is preferable to have a conductive state between ] and IOLB[j].

[0148] The circuit MP[i,j] shown in Figure 5E is a modified example of the circuit MP[i,j] in Figure 5A. In essence, this is an example of the configuration of circuit MP[i,j] that can be applied to the arithmetic circuit 110 in Figure 2. Figure 5 Circuit MP[i,j] of E is similar to circuit MP[i,j] in Figure 5A, consisting of circuit MC and circuit M It has Cr and, however, in the circuit MP[i,j] of Figure 5E, the circuit MC is wired OLB[j] The fact that it is not electrically connected, and that circuit MCr is electrically connected to wiring OL[j] It differs from the circuit MP[i,j] in Figure 5A in that it does not have [a certain feature].

[0149] Wiring WL[i] shown in Figure 5E corresponds to wiring WLS[i] in Figure 2. Wiring W L[i] is electrically connected to the retaining part HC and the retaining part HCr.

[0150] Furthermore, the wiring XL[i] shown in Figure 5E corresponds to the wiring XLS[i] in Figure 2. Wiring XL[i] is electrically connected to circuit MC and circuit MCr.

[0151] As described later, circuit MP[i,j] in Figure 5E has circuit MC electrically connected to wiring OLB[j]. It is not connected, and circuit MCr is not electrically connected to wiring OL[j]. Unlike the circuits MP[i,j] in Figures 5A to 5E, the circuit MP[i,j] in Figure 5E is different in that it is The current output from the circuit MC does not flow into the wiring OLB[j], but the current output from the circuit MCr The configuration is such that the current does not flow into wiring OL[j].

[0152] Therefore, the circuit MP[i,j] in Figure 5E is the second data z i (k-1) is "0", or It is preferable to apply this to the arithmetic circuit when the value is a binary "1". For example, the second data z i (k-1) If it is "1", then circuit MP is conductive between circuit MC and wiring OL[j]. Set the circuit MCr and the wiring OLB[j] to a conductive state. Also, for example, the second taz i (k-1) If it is "0", the power output from circuit MC and circuit MCr respectively In order to prevent current from flowing through either wiring OL[j] or OLB[j], circuit MP is configured to avoid the current flowing through either wiring OL[j] or OLB[j]. The circuit MC and wiring OL[j], and the circuit MC and wiring OLB[j] are made non-conductive. And between circuit MCr and wiring OL[j], and between circuit MCr and wiring OLB[j] To deconduct.

[0153] The circuit MP[i,j] in Figure 5E, when applied to the arithmetic circuit 110, is shown as an example. This is the first data w i (k-1) j (k) The value is one of the three values: "-1", "0", or "1". For the second data z i (k-1) When the value can take two values, "0" or "1", the operation is performed. This can be done. Note that the circuit MP[i,j] in Figure 5E is the first data w i (k-1) j ( k) The value is one of the following two values: "-1", "0", or "1", for example, "-1", "1 It can also be operated in the case of two values, such as "" or "0" and "1". Oh, first data lol i (k-1) j (k) This refers to analog values, or multi-bit (multi-level) data. Digital values ​​can also be used. A concrete example would be using a "negative analog value" instead of "-1". And, instead of "1", you may take a "positive analog value". In this case, the circuit MC Alternatively, the magnitude of the current flowing from the circuit MCr is, for example, the first data w i (k-1) j (k) The value will be an analog value corresponding to the absolute value of the value.

[0154] <Example of operation of the arithmetic circuit> Next, an example of the operation of the arithmetic circuit 110 in Figure 2 will be described. Note that in this explanation of the operation example, As an example, we use the arithmetic circuit 110 shown in Figure 8.

[0155] The arithmetic circuit 110 in Figure 8 focuses on the circuit located in the j-th column of the arithmetic circuit 110 in Figure 2. This is what has been shown. In other words, the arithmetic circuit 110 in Figure 8 is the neural network shown in Figure 1A. Neuron N in twerk 100 j (k) The input is sent to neuron N1 (k-1 ) Neuron N m (k-1) Signal z1 from (k-1) ~z m (k-1) And weight coefficient w1 (k-1) j (k) Or maybe lol m (k-1) j (k) The sum-of-products operation and the said sum-of-products operation This corresponds to a circuit that performs calculations on the activation function using the result of the calculation. Furthermore, Figure 8 shows calculation circuit 1. The circuit MP included in the 10 array section ALP is the one that applies the circuit MP shown in Figure 5A. Let's assume that.

[0156] First, in the arithmetic circuit 110, the first circuit MP[1,j] to the circuit MP[m,j] Data w1 (k-1) j (k) Or maybe lol m (k-1) j (k) This is set. First data w i (k-1) j (k) The method of setting this up is by using the circuit WLD, and wiring WLS[1] A predetermined potential is applied sequentially to the wiring WLS[m], and then to circuit MP[1,j] to circuit MP[m] Select ,j] in order, and the holding part HC of the circuit MC included in the selected circuit MP, And to the holding part HCr of the circuit MCr, from the circuit ILD, wiring IL[j], wiring ILB A potential corresponding to the first data is supplied via [j]. Then, after the potential is supplied, circuit W The LD is used to deselect each of the circuits MP[1,j] through MP[m,j]. This allows each of circuits MP[1,j] through MP[m,j] to maintain the circuit MC. The first data w1 is entered in the holding part HC and the circuit MCr of the holding part HCr. (k-1) j (k) Or maybe lol m ( k-1) j (k) It can maintain a potential corresponding to the first data w1 (k-1) j (k) Or maybe lol m (k-1) j (k) If each of them takes a positive value For the holding part HC, input a value corresponding to its positive value, and for the holding part HCr, input a value equivalent to zero. Enter the value to be used. Meanwhile, the first data w1 (k-1) j (k) Or maybe lol m (k-1) j (k ) If each of these values ​​is negative, the holding part HC will be assigned a value equivalent to zero. Then, input a value corresponding to the absolute value of a negative value into the holding part HCr.

[0157] Next, the circuit XLD will route the wiring X1L[1] to wiring X1L[m], wiring X2L[1 ] or each of the wiring X2L[m], second data z1 (k-1) ~z m (k-1) of To supply. As a specific example, the second data to wiring X1L[i] and wiring X2L[i] z i (k-1) The following will be supplied. Note that wiring X1L[i] and wiring X2L[i] are shown in Figure 2. This corresponds to the wiring XLS[i] of the arithmetic circuit 110.

[0158] The second data z1 is input to each of the circuits MP[1,j] through MP[m,j]. ( k-1) ~z m (k-1) Depending on the circuit, the contents of circuit MP[1,j] to circuit MP[m,j] are included. The continuity state between the circuit MC and circuit MCr, and the wiring OL[j] and circuit OLB[j]. This is determined. As a specific example, the circuit MP[i,j] is determined by the second data z i (k-1) in response Then, "conductivity occurs between circuit MC and wiring OL[j], and circuit MCr and wiring OLB[j] The state in which there is conductivity between the circuit MC and the wiring OLB[j], and the state in which there is conductivity between the circuit MC and the wiring OLB[j], and the circuit The state in which there is conductivity between MCr and wiring OL[j], and the state in which circuit MC and circuit MCr are The state in which the wiring OL[j] and wiring OLB[j] are non-conductive is one of the following: For example, the second data z1 (k-1) Regarding this, if it takes a positive value, then wiring X1 In L[1], there is conduction between circuit MC and wiring OL[j], and circuit MCr and Enter a value that creates a conductive state between the wiring OLB[j] and the wire X2L[1]. , the circuit MC and the wiring OLB[j] become non-conductive, and the circuit MCr and wiring OL Enter a value that results in a non-conductive state between [j] and the second data z1. (k-1) nitsu And if it takes a negative value, then the wiring X2L[1] is between circuit MC and wiring OLB[j] Enter a value that results in a conductive state between the two points, and also in a conductive state between circuit MCr and wiring OL[j]. And, the circuit MC and the wiring OL[j] are in a non-conductive state in wiring X1L[1]. The input value is such that the circuit MCr and the wiring OLB[j] are in a non-conductive state. And then, the second data z1 (k-1) Regarding this, if it takes a value of zero, then wiring X2L[1 In this case, the circuit MC and the wiring OLB[j] are in a non-conductive state, and the circuit MCr and the wiring Input a value that results in a non-conductive state between the line OL[j] and the wire X1L[1]. The circuit MC and wiring OL[j] become non-conductive, and the circuit MCr and wiring OLB[ Enter a value that results in a non-conductive state between [j] and [j].

[0159] The second data z is input to circuit MP[i,j] i (k-1) Depending on the circuit MP[i, The circuit MC included in [j], and the relationship between circuit MCr and wiring OL[j] and circuit OLB[j] The conduction or non-conduction state between them determines the connection between circuit MC and circuit MCr and the wiring. Current input and output occurs between OL[j] and the wiring OLB[j]. Furthermore, the current The quantity is the first data w set in circuit MP[i,j] i (k-1) j (k) and / or the 2 data z i (k-1) It depends on the circumstances.

[0160] For example, in circuit MP[i,j], from wiring OL[j], circuit MC or circuit MCr Let I[i,j] be the current flowing through it, and let the current flow from wiring OLB[j] to circuit MC or circuit MCr. The current is I B Let [i,j] be the points. Then, flow from circuit ACTF[j] to wiring OL[j]. The current is I out Let [j] be the current flowing from the wiring OLB[j] to the circuit ACTF[j]. to I Bout If we set it to [j], then I out [j] and I Bout [j] can be expressed by the following formula: It is possible.

[0161]

number

[0162] In circuit MP[i,j], as an example, the first data w i (k-1) j (k) ga “+ When it is 1”, circuit MC emits I(+1) and circuit MCr emits I(-1). That year, the first data w i (k-1) j (k) When is "-1", the circuit MC is I(-1 ) is discharged, and the circuit MCr discharges I(+1), and the first data w i (k-1) j (k) When is "0", circuit MC discharges I(-1) and circuit MCr discharges I(-1) It shall be discharged.

[0163] Furthermore, the circuit MP[i,j] is given by the second data z i (k-1) When is "+1", The circuit MC and wiring OL[j] become conductive, and the circuit MCr and wiring OLB[j] Continuity is established, and the connection between circuit MC and wiring OLB[j] becomes non-conductive, and the connection between circuit MCr and wiring OL The state in which there is no conduction between [j] and the second data z i (k-1) is "-1" Sometimes, there is conduction between circuit MC and wiring OLB[j], and circuit MCr and wiring OL[j The connection between ] becomes conductive, the connection between circuit MC and wiring OL[j] becomes non-conductive, and circuit MCr and The state in which there is no conductivity between the wiring OLB[j] and the second data z i (k-1) is “0 "When this is the case, the relationship between circuit MC and wiring OL[j], and between circuit MC and OLB[j] The connection between the circuit MCr and the wiring OL[j] is non-conductive, and the connection between the circuit MCr and the wiring The connection between the line OLB[j] is non-conductive, and the connection between the circuit MCr and the wiring OL[j], The circuit MCr and OLB[j] are assumed to be in a non-conductive state.

[0164] At this time, in circuit MP[i,j], from wiring OL[j], circuit MC or circuit MC The current I[i,j] flowing through r and the current flowing from the wiring OLB[j] to circuit MC or circuit MCr Current I B [i,j] are as shown in the table below. Note that in some cases, I(- The circuit MP[i,j] may be configured such that the current in 1) becomes 0. Note that the current I[ i,j] may be the current flowing from circuit MC or circuit MCr to wiring OL[j]. Similarly, current I B [i,j] represents the flow from circuit MC or circuit MCr to wiring OLB[j]. Electric current is also acceptable.

[0165] [Table 1]

[0166] Then, I flow from wiring OL[j] and wiring OLB[j] out [ j] and I Bout Each of [j] is input to the circuit ACTF[j] For example, the circuit ACTF[j] is I out [j] and I Bout [j] comparison The circuit ACTF[j] is, for example, determined by the result of the comparison, by the neuron. N j (k) The signal z that is sent to the (k+1)th layer neuron j (k) Outputs.

[0167] As an example, the arithmetic circuit 110 in Figure 8 can be used to process neuron N j (k) The input is, Neuron N1 (k-1) Neuron N m (k-1) Signal z1 from (k-1) ~ z m (k-1) And the weight coefficient w1 (k-1) j (k) Or maybe lol m (k-1) j (k) And, It can perform sum-of-products operations and the calculation of activation functions using the results of those sum-of-products operations. In the array section ALP of the arithmetic circuit in Figure 8, by providing n rows of circuit MP, the calculation in Figure 2 is achieved. A circuit equivalent to the arithmetic circuit 110 can be constructed. In other words, the arithmetic circuit 110 in Figure 2 can be used to generate a new - Ron N1 (k) Neuron N n (k) In each of these, the sum-of-products operation and the sum-of-products operation The calculation of the activation function using the result of the operation can be performed simultaneously.

[0168] <<Examples of changes to circuits included in the arithmetic circuitry>> The above-mentioned array section ALP, circuit ILD, circuit WLD, circuit XLD, circuit AFP, circuit Some or all of the transistors contained in each of the MPs, for example, It is preferable that the transistor be an OS transistor. For example, it is desirable to have a low off-current. Such transistors, specifically those that have the function of retaining the charge stored in a capacitive element, The transistor is preferably an OS transistor. In particular, the transistor and When an OS transistor is applied, the OS transistor is as described in particular in Embodiment 3. A transistor structure is more preferable. However, one aspect of the present invention is not limited thereto. It is not determined.

[0169] Additionally, there are the array section ALP, circuits ILD, WLD, XLD, AFP, and MP. Transistors included in these include, besides OS transistors, channel type transistors, for example. Even as a transistor containing silicon in its region (hereinafter referred to as a Si transistor) Good. Also, as for silicon, for example, single-crystal silicon, hydrogenated amorphous silicon. Microcrystalline silicon or polycrystalline silicon can be used. Also, OS Transition Besides Si transistors, other transistors include, for example, activated semiconductors such as Ge. Layered transistors, ZnSe, CdS, GaAs, InP, GaN, SiGe, etc. Transistors with compound semiconductors as the active layer, transistors with carbon nanotubes as the active layer A transistor with an organic semiconductor as the active layer can be used.

[0170] Furthermore, in the metal oxide of the semiconductor layer of the OS transistor, metal oxide containing indium In materials (e.g., In oxide), or metal oxides containing zinc (e.g., Zn oxide), While n-type semiconductors can be fabricated, p-type semiconductors are difficult to fabricate due to their mobility and reliability. There are also cases where this is the case. Therefore, the calculation circuit 110, calculation circuit 120, and calculation circuit 130 are located in the array section A LP, circuit ILD, circuit WLD, circuit XLD, circuit AFP, circuit MP etc. include n An OS transistor is applied as a channel-type transistor, and it is a p-channel type transistor. A configuration using Si transistors may also be used.

[0171] This embodiment can be appropriately combined with other embodiments shown herein. ru.

[0172] (Embodiment 2) This embodiment describes a specific configuration example of the circuit MP described in Embodiment 1. ru.

[0173] In Embodiment 1, the code for circuit MP indicates its position within the array section ALP [1,1 Although ], [i,j], [m,n], etc. are noted, in this embodiment, unless otherwise specified, the number of times The notation [1,1], [i,j], [m,n], etc. is omitted for the route MP symbols.

[0174] <Configuration Example 1> First, we will describe an example of a circuit configuration that can be applied to circuit MP in Figure 5A. (See Figure 9A) Circuit MP is an example of the configuration of circuit MP in Figure 5A, and the circuits included in circuit MP in Figure 9A For example, the circuit MC consists of transistors M3, M4, and M8. It has a capacitive element C3. For example, by the transistor M8 and the capacitive element C3 The holding portion HC is then formed.

[0175] Transistors M3, M4, and M8 shown in Figure 9A are An example is an n-channel transient with a multi-gate structure that has gates above and below the channel. As a starting point, transistors M3, M4, and M8 are each It has a first gate and a second gate. In particular, as an example, transistors M3 and M4 It is preferable that the sizes of each component be equal. However, for convenience, in this specification, etc., as an example... Then, the first gate is called the gate (sometimes referred to as the front gate), and the second gate is called the back gate. Although they are described as separate gates, the first and second gates are interchangeable. It is possible to obtain. Therefore, in this specification, the term "gate" is used for "backgate". It can be written by replacing the word "gate" with the same word. Similarly, "backgate" The word can be replaced with the word "gate". For example, "Gate The back gate is electrically connected to the first wiring harness, and the back gate is electrically connected to the second wiring harness. The connection configuration is such that "the back gate is electrically connected to the first wiring, and the gate is connected to the second wiring." This can be replaced with a connection configuration that states, "It is electrically connected to..."

[0176] Furthermore, the connection configuration of the back gate of a transistor included in a semiconductor device according to one aspect of the present invention. This is not particularly limited. Transistor M8 shown in Figure 9A has a back gate. Although it is shown in the diagram, the connection configuration of the back gate is not shown in the diagram, The electrical connection destinations can be determined at the design stage. For example, if a back gate is present... In a transistor, in order to increase the on-current of that transistor, the gate and buck The gate may be electrically connected. That is, for example, the gate of transistor M8 and the battery The back gate may be electrically connected. Also, for example, a transistor with a back gate In a transistor, in order to vary the threshold voltage of that transistor, or the transistor To reduce the off-current of the sta, wiring is provided that is electrically connected to external circuits, etc. The external circuit may then apply a potential to the back gate of the transistor. Regarding this, the transistors described not only in Figure 9A but also in other parts of the specification are shown. The same applies to transistors shown in other drawings.

[0177] Furthermore, the structure of the transistor included in the semiconductor device according to one aspect of the present invention is not particularly limited. It cannot be. For example, the transistor M8 shown in Figure 9A is, as shown in Figure 9B, It can also be configured without a gate, that is, as a single-gate transistor. Also, some transistors have a back gate configuration, and some other transistors The inverter may also have a configuration without a back gate. See Figure 9 for details. Not only the circuit diagram shown in A, but also transistors, or other transistors, as described elsewhere in the specification. The same applies to the transistors shown in the diagram.

[0178] Furthermore, in this specification, transistors of various structures are used as transistors. This is possible. Therefore, there are no restrictions on the type of transistor used. An example of a transistor is... For example, transistors made of single-crystal silicon, or amorphous silicon, polycrystalline silicon N, microcrystals (also called nanocrystals or semi-amorphous silicon) Transistors having non-single-crystal semiconductor films, such as those represented by , can be used. Alternatively, thin-film transistors (TFTs) made by thinning these semiconductors can be used. Yes, it is possible. When using TFTs, there are various advantages. For example, compared to single-crystal silicon... Because it can be manufactured at a low temperature, it is possible to reduce manufacturing costs or to increase the size of the manufacturing equipment. It is possible. Because the manufacturing equipment can be made larger, it is possible to manufacture on large substrates. Therefore, many can be manufactured simultaneously. Because individual display devices can be manufactured, they can be produced at a low cost. Alternatively, because the manufacturing temperature is low. Therefore, substrates with poor heat resistance can be used. It is possible to manufacture transistors. Alternatively, transistors on a light-transmitting substrate can be used in display elements. Light transmission can be controlled. Or, because the transistor film thickness is thin, the transistor A portion of the film that forms the aperture can transmit light. Therefore, the aperture ratio can be improved. It is possible.

[0179] For example, a transistor is a compound semiconductor (e.g., SiGe, GaAs, etc.). ), or oxide semiconductors (e.g., Zn-O, In-Ga-Zn-O, In-Zn-O, I n-Sn-O(ITO), Sn-O, Ti-O, Al-Zn-Sn-O(AZTO), I A transistor having n-Sn-Zn-O, etc., can be used. These compound semiconductors, or thin-film transistors made by thinning these oxide semiconductors, etc. These can be used. This allows for lower manufacturing temperatures, so for example, at room temperature... This makes it possible to manufacture ZISTAS. As a result, substrates with low heat resistance, such as plastics, can be used. Transistors can be formed directly on a substrate or film substrate. Compound semiconductors or oxide semiconductors are used not only in the channel portion of transistors, but also They can also be used for other purposes. For example, these compound semiconductors or oxide semiconductors It can be used as wiring, resistive elements, pixel electrodes, or light-transmitting electrodes, etc. Since these can be deposited or formed simultaneously with the transistor, costs can be reduced.

[0180] As an example of a transistor, a transistor formed using an inkjet method or printing method is... Rangistas and the like can be used. These allow for manufacturing at room temperature, manufacturing at low vacuum levels, and It can be manufactured on a large substrate. Therefore, it can be manufactured without using a mask (reticle). This makes it possible to easily change the layout of the transistors. Alternatively, since it is possible to manufacture without using resist, material costs are reduced and the number of processes is eliminated. It can be reduced. Or, it is possible to apply the film only to the necessary parts, so after forming a film over the entire surface... This method is less wasteful and lower-cost than etching.

[0181] As an example of a transistor, there is a transistor that has organic semiconductors or carbon nanotubes. Transistors and the like can be used. With these, transients can be applied to a bendable substrate. It is possible to form transistors using organic semiconductors or carbon nanotubes. Devices using this technology can be made more resistant to impact.

[0182] Furthermore, transistors with various other structures can also be used. For example, transistors include MOS type transistors, junction type transistors, and bipod type transistors. A transistor such as a MOS-type transistor can be used. By using this, the size of the transistor can be reduced. Therefore, a large number of transistors It can be equipped with a transistor. Bipolar transistors are used as transistors. This allows for the flow of a large current. Therefore, it is possible to operate the circuit at high speed. Yes, it is possible. Furthermore, MOS transistors and bipolar transistors can be mixed on a single substrate. It may be formed in this way. This will enable low power consumption, miniaturization, and high-speed operation. can.

[0183] One example of a transistor is a structure in which gate electrodes are arranged above and below the active layer. This transistor can be applied. The structure has gate electrodes positioned above and below the active layer. This results in a circuit configuration where multiple transistors are connected in parallel. Therefore, the channel formation region increases, making it possible to increase the current value. Alternatively, the active layer By arranging the gate electrodes at the top and bottom, a depletion layer is more likely to form. This allows for improvement of the S value.

[0184] For example, one transistor has a structure in which the gate electrode is placed on top of the active layer. Structures in which the gate electrode is positioned below the active layer, positive staggered structure, inverse staggered structure, channel Structures in which the region is divided into multiple regions, structures in which the active layers are connected in parallel, or structures in which the active layers are connected in series. A transistor with a structure such as the following can be used. Alternatively, as a transistor, Fin type, FIN type, TRI-GATE type, Top Gate Type, bottom gate type, double gate type (gates are located above and below the channel), It can take on a variety of configurations.

[0185] As an example of a transistor, the active layer (or part thereof) has source electrodes and drains. A transistor with an overlapping in electrode structure can be used. By creating a structure in which the source electrode and drain electrode overlap a part of the active layer, This prevents the device from becoming unstable due to the accumulation of electric charge.

[0186] As an example of a transistor, a structure with an LDD region can be applied. By creating a range, the off-current can be reduced, or the transistor's breakdown voltage can be improved (reliability can be improved). This can be achieved. Alternatively, by providing an LDD region, when operating in the saturation region... Even if the voltage between the drain and source changes, the drain current does not change much, and the slope is A flat voltage-current characteristic can be obtained.

[0187] For example, in this specification, it is possible to form transistors using various substrates. It will come. The type of circuit board is not limited to a specific one. One example of such a circuit board is a semi-circular one. Conductive substrates (e.g., single crystal substrates or silicon substrates), SOI substrates, glass substrates, quartz substrates, Plastic substrates, sapphire glass substrates, metal substrates, stainless steel substrates, stainless steel Substrate having a resin-steel foil, tungsten substrate, having a tungsten foil Substrates, flexible substrates, laminated films, paper containing fibrous materials, or base film, etc. Examples of glass substrates include barium borosilicate glass and aluminoborosilicate glass. Examples include glass or soda-lime glass. Flexible substrates, laminated films, and base material films. Examples of materials include the following: For example, polyethylene terephthalate. PET, polyethylene naphthalate (PEN), polyethersulfone (PES) ), there are plastics such as polytetrafluoroethylene (PTFE). One example is synthetic resins such as acrylic. Alternatively, another example is polypropylene. Examples include polyester, polyvinyl fluoride, or polyvinyl chloride. Examples include polyamide, polyimide, aramid, epoxy resin, inorganic vapor-deposited film, or Paper products are among them. In particular, semiconductor substrates, single crystal substrates, or SOI substrates are used for transients. By manufacturing the staves, variations in characteristics, size, and shape are minimized, and current capacity is reduced. It is possible to manufacture transistors that are powerful and small in size. By configuring the circuit using this method, it is possible to reduce the power consumption of the circuit or increase its integration. Cut.

[0188] Furthermore, a flexible substrate is used as the substrate, and transistors are formed directly on the flexible substrate. Alternatively, a release layer may be provided between the substrate and the transistor. After partially or completely completing a semiconductor device, it is separated from the circuit board and transferred to another circuit board. It can be used in this way. In this case, the transistor can be used on substrates with poor heat resistance or flexible substrates. It can be mounted. Furthermore, the aforementioned release layer may include, for example, an inorganic tungsten film and a silicon oxide film. This method utilizes a layered film structure or a configuration in which an organic resin film such as polyimide is formed on a substrate. It is possible.

[0189] In other words, a transistor is formed using one substrate, and then the transistor is placed on another substrate. The transistor may be transposed and placed on a different substrate. As an example, in addition to the substrates on which the transistors described above can be formed, paper substrates, cellophane Fan boards, aramid film boards, polyimide film boards, stone boards, wood boards, cloth Substrate (natural fibers (silk, cotton, linen), synthetic fibers (nylon, polyurethane, polyester) (or recycled fibers (acetate, cupro, rayon, recycled polyester, etc.)) These include leather substrates and rubber substrates. By using these substrates, a tiger with good characteristics can be produced. Formation of transistors, formation of low-power transistors, manufacturing of durable devices, heat resistance This allows for the addition of features, weight reduction, or thinning of the material.

[0190] Furthermore, all the circuits necessary to realize the specified function are placed on the same circuit board (for example, glass It can be formed on substrates such as stainless steel substrates, plastic substrates, single crystal substrates, or SOI substrates. Yes. In this way, costs are reduced by reducing the number of parts, or the number of connection points with circuit components is reduced. This can improve reliability.

[0191] Furthermore, it is not necessary to form all the circuits required to achieve a specific function on the same circuit board. It is possible. In other words, some of the circuits necessary to achieve a certain function can be formed on a certain circuit board. Another part of the circuitry necessary to achieve the predetermined function is formed on a separate substrate. It is possible that some of the circuits necessary to achieve a certain function are gas Another part of the circuitry, which is formed on the lath substrate and necessary to realize a predetermined function, is a single crystal base. It can be formed on a plate (or SOI substrate). And it can realize a predetermined function. A single-crystal substrate (also called an IC chip) on which another part of the necessary circuitry is formed is called COG (Chip On Glass) connects to a glass substrate, and its I It is possible to place a C chip. Alternatively, the IC chip can be placed in a TAB (Tape Au tomated Bonding), COF(Chip On Film), SMT(S Surface Mount Technology, or using printed circuit boards, etc. It is possible to connect to a lath substrate. In this way, a part of the circuit is formed on the same substrate as the pixel section. This reduces costs by decreasing the number of components, or by reducing the connection points with circuit components. Reliability can be improved by reducing the number of components. In particular, in circuits where the drive voltage is high, Alternatively, circuits with high drive frequencies often consume a lot of power. Therefore, by forming such a circuit on a substrate separate from the pixel section (for example, a single-crystal substrate), the IC chip is formed. This constitutes the chip. By using this IC chip, it is possible to prevent an increase in power consumption. Cut.

[0192] In circuit MP of Figure 9A, the first terminal of transistor M8 is electrically connected to wiring IL. The second terminal of transistor M8 is connected to the first terminal of the capacitive element C3, and transistor M3 The back gate of the transistor is electrically connected to the back gate of transistor M4. The gate of the Zistor M8 is electrically connected to the wiring WL. The second terminal of the capacitive element C3 is , electrically connected to the wiring VLs. The first terminal of transistor M3 and transistor The first terminal of M4 is electrically connected to the wiring VL. The second terminal of transistor M3 It is electrically connected to wiring OL. The gate of transistor M3 is electrically connected to wiring X1L. It is connected to the OLB. The second terminal of transistor M4 is electrically connected to the OLB wiring. The gate of transistor M4 is electrically connected to wiring X2L. (See Figure 10) Therefore, the first terminal of transistor M4 is electrically connected to another wire VLm, not to the wire VL. It may also be connected to the wiring VLr. Similarly, the first terminal of transistor M4r is connected to the wiring VLr. Alternatively, it may be electrically connected to another wiring VLmr. Note that this applies not only to Figure 9A. In the circuit diagrams of other drawings, the first terminal of transistor M4 is connected to a different wire, VL. A configuration in which the wiring VLm is electrically connected, and / or the first of transistor M4r The terminal is configured to be electrically connected to a different wire, VLmr, rather than to the VLr wire. This is also acceptable. Furthermore, in Figure 10, for example, wiring VL and wiring VLr are treated as a single identical wiring. Alternatively, wiring VLm and wiring VLmr may be treated as a single, identical wire (not shown in the diagram).

[0193] In the holding portion HC shown in Figure 9A, the second terminal of transistor M8 and the capacitive element C The first terminal of 3, the back gate of transistor M3, and the back gate of transistor M4 The electrical connection point between these is designated as node nd3.

[0194] The holding part HC, as described in Embodiment 1, for example, corresponds to the first data w It has the function of maintaining the potential. The potential is maintained at the holding part HC included in the circuit MC in Figure 9A. The holding state is maintained when transistor M8 is turned ON, and the corresponding potential is input from wiring IL. This is done by writing to the capacitive element C3 and then turning off the transistor M8. This allows the potential of node nd3 to be maintained as the potential corresponding to the first data. can.

[0195] Furthermore, transistor M8 maintains the potential of node nd3 for a long time, resulting in low off-current. It is preferable to use transistors that do not have an off-current. Examples of transistors with low off-current include For example, an OS transistor can be used. Also, as transistor M8, A transistor with a gate is applied, and a low-level potential is applied to the back gate, thereby reducing the threshold voltage. Alternatively, the voltage may be shifted to the positive side to reduce the off-current.

[0196] Circuit MCr has almost the same circuit configuration as Circuit MC. Therefore, Circuit MCr The circuit elements possessed are designated with the letter "r" to distinguish them from the circuit elements possessed by the circuit MC. It is.

[0197] In circuit MCr, a different connection configuration from circuit MC will be explained. Transistor M3 The second terminal of r is electrically connected to wiring OLB, not wiring OL, and transistor M4r The second terminal is electrically connected to wiring OL, not wiring OLB. Transistor M The first terminal of 3r and the first terminal of transistor M4r are electrically connected to the wiring VLr. It is being done.

[0198] In the operation example described later, to briefly explain the current entering and leaving circuit MP, Figure The ends of wiring OL shown in 9A are designated as node ina and node outa, and the ends of wiring OLB are designated as node Let node inb and node outb.

[0199] Wiring VL functions, for example, as wiring that supplies a constant voltage. This refers to transistor M3, transistor M3r, transistor M4, or transistor If M4r is an n-channel transistor, for example, the VSS is a low-level potential. This can be the ground potential, or any other low-level potential. Also, the wiring V Ls, wiring VLr, and wiring VLsr each supply a constant voltage, similar to wiring VL. It functions as a voltage line, and as a constant voltage, it is a low-level potential VSS, and other low-level potentials besides VSS. This can be the Bell potential, ground potential, etc. Furthermore, the constant voltage can be the high-level potential. VDD may also be set to VDD. In this case, arithmetic circuit 110, arithmetic circuit 120, arithmetic circuit 13 Circuit ACTF[1] to ACTF[n] of 0 are shown in Figures 3A to 3E and Figures 4A to 4A. When 4D and Figure 4F are applied, electrical currents are supplied to circuits ACTF[1] through ACTF[n]. The constant voltage supplied by the connected VAL is greater than the potential supplied by the wiring VL and wiring VLr. It is preferable to use a high potential, such as VDD.

[0200] Furthermore, the fixed values ​​supplied by each of the wiring VL, wiring VLs, wiring VLr, and wiring VLsr The voltages may be different from each other, or some or all of them may be the same. If the voltage supplied by the wiring is the same, select those wirings and use them as the same wiring. This is also acceptable. For example, each of the following: wiring VL, wiring VLs, wiring VLr, and wiring VLsr When the applied constant voltage is approximately equal, the wiring VLs and wiring VLr are as shown in circuit MP in Figure 11A. Wiring VLsr can be the same wiring as wiring VL. Or, for example, wiring VL When the constant voltage supplied by each of the wires VLr is approximately equal, the wires VL and VLr are one The wiring can be the same for all of them. Or, for example, wiring VLs and wiring VLsr If the constant voltages supplied are approximately equal, then wiring VLs and wiring VLsr are treated as a single identical wiring. It is possible. Similarly, in Figure 10, for example, wiring VL and wiring VLr can be connected as a single wire. As identical wiring, wiring VLm and wiring VLmr may be treated as a single, identical wiring. For example, if wiring VL and wiring VLmr are treated as a single identical wiring, then wiring VLm and wiring V Lr and the other wire may be connected using a single, identical wire.

[0201] Furthermore, the configuration of circuit MP in Figure 9A can be changed depending on the situation. For example, Figure As shown in 11B, transistors M3, M3r, and tra Transistor M4 and transistor M4r are both p-channel type transistors. Place the transistors M3p, M3pr, M4p, and M4pr in the following locations: You can swap them. Transistor M3p, transistor M3pr, transistor M4p, As for the Rangista M4pr, one example is SOI (Silicon On Insulation). A p-channel transistor with a (lator) structure can be applied. In this case, The constant voltage supplied by the wiring VL and VLr should preferably be VDD, which is a high-level potential. In addition to this case, the calculation circuit 110, calculation circuit 120, or calculation circuit 130 As paths ACTF[1] or circuits ACTF[n], see Figures 3A to 3E, 4A to 4D. When Figure 4F is applied, it is electrically connected to circuits ACTF[1] through ACTF[n]. The constant voltage supplied by the VAL is preferably the ground potential or VSS. Therefore, if the potential of the wiring is changed, the direction in which the current flows will also change.

[0202] Similarly, transistor M8 can also be replaced with a p-channel type transistor. That's good too.

[0203] Also, transistor M3, shown in Figures 9A, 9B, 10, 11A, and 11B, The sizes of transistors M3r, M4, and M4r, for example, It is preferable that the channel length L or channel width is equal. This may allow for more efficient layout. Also, transistor M3, The current flowing through transistors M3r, M4, and M4r is equalized. There is a possibility that it will be possible.

[0204] <<Example of operation>> First, regarding the operating characteristics of transistor M3 or transistor M4 included in circuit MP... Let me explain. Figure 12A shows transistor M3, which is included in circuit MP of Figure 9A. The gate of one of the transistors M3r, M4, or M4r -This is a simplified graph showing the characteristics of source voltage and drain current. The horizontal axis is the current. This chart shows the gate-source voltage Vgs of a transistor, with the vertical axis representing the drain of the transistor. This shows the current Id. Note that the vertical axis in Figure 12A is on a linear scale.

[0205] Furthermore, in Figure 12A, the potential applied to the gate of the transistor is denoted as Vg, Let Vbg be the potential applied to the back gate of the transistor. Let's assume, for example, that the constant potential applied to the source of the device is 0V.

[0206] Figure 12A shows two curves, one of which represents a high Vbg of the transistor. Gate-source current when the level potential (shown as High in Figure 12A) This shows the characteristics of voltage Vgs and drain current Id, and the other curve represents the V of the transistor. Gate-saw when bg is at a low potential (shown as Low in Figure 12A) This shows the characteristics of the voltage between the tubes Vgs and the drain current Id. From Figure 12A, Vbg is high When the potential is Bell, the threshold voltage Vth2 of the transistor is when Vbg is at a low level. It can be seen that this value is lower than the threshold voltage Vth1 of the transistor when it is in that position. In other words, by changing the Vbg of the transistor, the transistor can be turned on. To achieve this state, Vgs (since the source potential is set to 0V, this can be rephrased as Vg) is needed. It is possible to change ( ).

[0207] Here, when the Vbg of the transistor is at a high potential, the transistor is When the transistor enters a state where the Vbg of the transistor is at a low level potential, the transistor The Vg of the transistor is set so that the transistor is in the OFF state. In Figure 12A, that transistor The voltage Vg of the transistor is shown as Vg1. In other words, Vg1 is the voltage at which Vbg is at a high level. When Vbg is at a low level potential and is higher than the threshold voltage Vth2 of a certain transistor, The potential should be lower than the threshold voltage Vth1 of the transistor.

[0208] Furthermore, when the Vbg of the transistor is at a high potential, the transistor turns off. When the state is reached and the Vbg of the transistor is at a low level potential, the transistor The Vg of the transistor is set so that the transistor is in the OFF state. In Figure 12A, that transistor... The Vg of the inverter is shown as Vg2. In other words, Vg2 is when Vbg is at a high potential. If the potential is lower than the threshold voltage Vth2 of transistor M3 (transistor M4), good.

[0209] Also, for example, from Figure 9A, the gate potential V of transistors M3 and M3r g is given from wiring X1L. Therefore, Vg1 and Vg2 are given from wiring X1L. The potential can be set to such a potential. Similarly, transistors M4 and M4r The gate potential Vg is supplied from wiring X2L. Therefore, Vg1 and Vg2 are supplied from wiring X The potential can be supplied from 2L. In this specification, Vg1 and Vg2 are... These can be rephrased as high-level potential and low-level potential, respectively.

[0210] In this specification and elsewhere, the terms "low-level potential" and "high-level potential" refer to a specific electric field. This does not mean a specific position; if the wiring is different, the specific potential may also differ. Therefore, transistor M3, transistor M3r, transistor M4, transistor M4r The high-level potential applied to the back gate is the same as the high-level potential applied to wiring X1L and wiring X2L. The potential may be different from the potential (Vg1). Similarly, transistor M3, transistor Low level applied to the back gates of transistors M3r, M4, and M4r The potential is different from the low-level potential (Vg2) applied to wiring X1L and wiring X2L. This is also acceptable. For example, transistor M3, transistor M3r, transistor M4, and The high-level potential applied to the back gate of transistor M4r is transmitted to transistor M3, The source potentials of transistors M3r, M4, and M4r are set to be the same. It may also be the case that transistor M3, transistor M3r, transistor M4, and The low-level potential applied to the back gate of transistor M4r is, transistor M3, Lower than the source potential of transistors M3r, M4, and M4r. The potential may be set to a certain value. For example, transistor M3, transistor M3r, transistor When the source potential of transistor M4 and transistor M4r is 0V, transistor M3 Marks on the back gates of transistors M3r, M4, and M4r. The low-level potential that is applied will be a negative potential, for example, between -11V and -2V. Preferably, the voltage may be around -3V.

[0211] In the operation example described below, the potential (Vg1) applied to wiring X1L and wiring X2L is as follows: Alternatively, Vg2) and transistor M3, transistor M3r, transistor M4, and transistor The potential of the back gate of the converter M4r is described as a binary (digital) value, but The invention is not limited to this embodiment. For example, as shown in Figure 12B, the transistor When the gate is Vga1, the potential of the back gate of the transistor is Vbg1, Vbg 2. By varying Vbg3 to one of the two values, the drain current Id of the transistor can be controlled. It can be increased or decreased. Now, let's consider the case of circuit MP in Figures 9A and 11. Transition The gates of transistors M3, M3r, M4, and M4r With the potential constant, transistors M3, M3r, M4, and By varying the back gate potential of transistor M4r, transistor M3 and transistor M Vary the drain current Id of transistors 3r, M4, and M4r. This allows you to increase or decrease the amount of current flowing through wiring OL and wiring OLB. In other words, the transistor Backgear for transistors M3, M3r, M4, and M4r By varying the potential of the terminal as an analog value, the circuit MP utilizes the analog value. It can perform calculations.

[0212] Also, for example, as shown in Figure 12B, the potential of the back gate of the transistor is Vbg1 When Vbg2 or Vbg3 is set to one of the above, the gate potential of the transistor is By changing it to one of Vga1, Vga2, or Vga3, the transistor The drain current Id of the terminal can be increased or decreased. Consider the case of circuit MP in Figures 9A and 11. When this happens, transistor M3, transistor M3r, transistor M4, and transistor The back gate potential of M4r is kept constant, and transistors M3, M3r, and By varying the gate potential of transistor M4 and transistor M4r, transistor M3 The drain current Id of transistors M3r, M4, and M4r. By changing this, the amount of current flowing through wiring OL and wiring OLB can be increased or decreased. Also, transistor M3, transistor M3r, transistor M4, and transistor M By varying the gate potential of 4r as an analog value, the circuit MP becomes an analog value It is possible to perform calculations using transistor M3, transistor M3r, and The gate and back gate potentials of transistor M4 and transistor M4r are kept constant. The potential of the source electrode is varied as an analog value, and transistors M3 and M3r The configuration changes the drain current Id of transistors M4 and M4r. This is also acceptable (not shown in the diagram).

[0213] Next, an example of the operation of circuit MP shown in Figure 9A will be described. Figures 13A to 13C, Figures 14A to 14C and 15A to 15C show an example of the operation of the timing control of circuit MP. These are charts, and each is a wiring IL, wiring ILB, wiring WL, wiring X1L, wiring X2L, The potential fluctuations at nodes nd3 and nd3r are shown. See Figures 13A to 13C. In Figures 14A to 14C and 15A to 15C, "high" refers to the high-level potential. This indicates that low indicates a low level potential. Also, in this example of operation, the wiring from OL to NO I is the amount of current output to node outa (or from node outa to wiring OL). OL and It is done. Also, wiring from OLB to node outb (or from node outb to wiring O The amount of current output to LB is I OLB This is as follows: Figures 13A to 13C, Figures 14A to In the timing charts shown in Figures 14C, 15A, and 15C, the current quantity I OL , I OL B The change in [the variable] is also illustrated.

[0214] In this example, the constant power supplied by wiring VL, wiring VLs, wiring VLr, and wiring VLsr is The voltage is VSS (low level potential). In this case, from wiring VAL through wiring OL, Current will flow through wiring VL. Similarly, from wiring VAL through wiring OLB, Current will flow through VLr.

[0215] Before explaining the operation example, the weight coefficient held by circuit MP is defined as follows: Holding part H A high-level potential is maintained at node nd3 of C, and a low-level potential is maintained at node nd3r of the holding part HCr. When this is done, the circuit MP is assumed to hold a weight coefficient of "+1". A low-level potential is maintained at node nd3 of the HC, and a high-level potential is maintained at node nd3r of the holding part HCr. When held, circuit MP is assumed to hold "-1" as a weighting coefficient. A low-level potential is present at node nd3 of part HC, and a low-level potential is present at node nd3r of holding part HCr. When held, circuit MP is assumed to hold "0" as its weight coefficient. The high-level potentials held at node nd3 and node nd3r are, for example, VD D can be a potential slightly lower than VDD, and node nd3, and node ND3, and The low-level potential held in nd3r can be, for example, VSS. For example, the high-level potentials held at node nd3 and node nd3r are V It can be made into SS, and the low-level potential held at node nd3 and node nd3r Therefore, the potential can be lower than VSS, for example, a negative potential. It is also possible to use analog values ​​for the weight coefficients. In that case, for example, a positive weight coefficient can be used. In the case of "analog value", a high level analog potential is applied to node nd3 of the holding unit HC, holding unit A low-level potential is maintained at node nd3r of HCr. A negative analog is used as the weighting coefficient. In the case of a "value", for example, a low-level potential at node nd3 of the holding part HC, and the holding part HCr A high level of analog potential is maintained at node nd3r. The weight coefficient is set to "0". For example, a low-level potential is set at node nd3 of the holding part HC, and node nd of the holding part HCr. A low-level potential is maintained at 3r.

[0216] Furthermore, the neuron signal (calculated value) input to circuit MP is defined as follows, as an example. A high-level potential (Vg1) is marked on wiring X1L, and a low-level potential (Vg2) is marked on wiring X2L. When input is applied, circuit MP receives a "+1" signal as the neuron's signal. A low-level potential (Vg2) is applied to wiring X1L, and a high-level potential (Vg1) is applied to wiring X2L. When this is happening, circuit MP receives "-1" as the neuron's signal. Wiring X A low-level potential (Vg2) is applied to 1L, and a low-level potential (Vg2) is applied to wiring X2L. In this case, the circuit MP is assumed to receive "0" as the neuron's signal. For example, the high-level potential (Vg1) is VDD, or less than 10% above VDD. Take a higher potential, or one that is 20% or more higher.

[0217] Furthermore, in this example, one example is the transistor M3 included in the circuit MP, Transistors M3r, M4, and M4r are described in Figure 12A. As shown, a high potential is applied to the back gate, shifting the threshold voltage to the negative side. When this is done, a high-level potential (Vg1) is applied to the gate, turning it into the ON state. It shall be so. Also, transistor M3, transistor M3r, transistor M4, and Each of the transistors M4r has a low-level current at the back gate, as explained in Figure 12A. Given a position, when the threshold voltage is shifted to the positive side, a high-level potential is reached at the gate. The transistor is assumed to be in the off state when (Vg1) is applied. M3, transistor M3r, transistor M4, and transistor M4r are each: As explained in Figure 12A, a high-level potential is applied to the back gate, and the threshold voltage is negative. Even if it is shifted to the eggplant side, a low-level potential (Vg2) is applied to the gate. This will cause it to turn off. In that case, transistor M3, transistor M3r, transistor M4, and transistor M4r are each as described in Figure 12A. When a low-level potential is applied to the back gate, the threshold voltage is shifted to the positive side. Even if it were present, applying a low-level potential (Vg2) to the gate would turn it off. It shall be so.

[0218] In other words, in this example, unless otherwise specified, transistor M3, tra Transistor M3r, Transistor M4, and Transistor M4r each have a backgear. When a high-level potential is applied to the tor and a high-level potential is applied to the gate, This state occurs when a low-level potential is applied to at least one of the gate or back gate. This will cause it to turn off. Note that the above-mentioned transistor M3, transistor The operation of transistors M3r, M4, and M4r is an example and represents one aspect of the present invention. The term is not limited to this. For example, transistor M3, transistor M3r, transistor Transistor M4 and transistor M4r each have electricity applied to their gate and back gate. A current of analog value flows according to the voltage (analog voltage or multi-level digital voltage). It could function as a source of water.

[0219] Furthermore, in this specification, etc., transistor M3, transistor M3r, transistor Unless otherwise specified, transistors M4 and M4r will eventually become saturated when in the ON state. This includes cases where the transistor operates in the sum region. That is, each of the transistors mentioned above The gate voltage, source voltage, and drain voltage should be appropriate for the voltages within the operating range in the saturation region. This includes cases where the system is biased. However, one aspect of the present invention is not limited thereto. It cannot be done. In order to reduce the amplitude value of the supplied voltage, transistor M3, transistor Transistors M3r, M4, and M4r may operate in the linear region. Oh, if the weight coefficient is an analog value, then depending on the magnitude of the weight coefficient, for example, Transistor M3, transistor M3r, transistor M4, and transistor M4r are linear. It is acceptable for there to be a mix of cases where the system operates within the region and cases where it operates within the saturated region.

[0220] Furthermore, in this specification and elsewhere, transistors M8 and M8r are particularly distinguished. If there is no exception, the ON state includes cases where it ultimately operates in the linear domain. That is, the gate voltage, source voltage, and drain voltage of each of the transistors mentioned above. The voltage includes cases where it is properly biased to a voltage within the range in which it operates in the linear region. ru.

[0221] Below, we will examine the possible combinations of values ​​for each of the weight coefficients and the neuron signals. Next, we will explain an example of the operation of circuit MP.

[0222] [Condition 1] First, as an example, consider a neuron input to circuit MP with a weight coefficient w of "0". Let's consider the case where the signal (calculated value) is "+1". Figure 13A shows the circuit M in that case. This is the timing chart for P.

[0223] Between time T1 and time T2, wiring IL and wiring ILB each have a hold. To initialize the potential of node nd3 of part HC and the potential of node nd3r of holding part HCr Initialization potential V ini This is the input. Note that in Figure 13A, V ini That's a low-level potential. Although it is shown as a potential that is higher and lower than the high-level potential, V ini low-level potential It may be set to a potential lower than or higher than the high-level potential. Alternatively, V i ni This may be set to the same potential as the low-level potential, or to the same potential as the high-level potential. Furthermore, the initialization potential V applied to wiring IL and wiring ILB, respectively. ini They are different from each other It may also be defined as an electric potential. Furthermore, an initial potential V is set for each of the wirings IL and ILB. ini of You don't need to input anything. In other words, you don't need to specify a period between time T1 and time T2. .

[0224] Furthermore, between time T1 and time T2, a low-level potential is input to the wiring WL. Therefore, transistors M8 and M8r are in the off state. It is.

[0225] Furthermore, between time T1 and time T2, node nd3 and node nd3r The potentials of each node are not specifically defined. In Figure 13A, node nd3 and node nd Each of the 3r potentials is higher than the low-level potential, V ini It is set to a lower potential than .

[0226] Wiring X1L and wiring X2L are each supplied with a low-level potential (Vg2). Note that transistors M3, M4, M3r, and transistor Since the threshold voltage of M4r is determined according to the potential of each back gate, , transistor M3, transistor M4, transistor M3r, and transistor M4r It may be in an on state rather than an off state.

[0227] Next, between time T2 and time T3, a high-level potential is input to the wiring WL. As a result, transistors M8 and M8r are turned ON. , the connection between wiring IL and node nd3 becomes conductive, and the connection between wiring ILB and node nd3r This creates a conductive state. Therefore, the potentials of node nd3 and node nd3r are V, respectively. ini This is the result.

[0228] At this time, transistors M3, M4, M3r, and Each of the M4r's tailgates has a V ini The input is transistor M3. Transistor M4, transistor M3r, and transistor M4r are each, back V at the gate ini The normally off state will be activated when this is input. Therefore, transistor M3, transistor M4, transistor M3r, and transistor Each of the M4r nodes will be in the off state. Note that the potentials of node nd3 and node nd3r are , initialization potential V ini It doesn't have to be that way. In other words, the period between time T2 and time T3 It is not necessary to set it up.

[0229] Between time T3 and time T4, low levels were observed in both the wiring IL and wiring ILB. A potential is applied, and "0" is input as the weighting coefficient w. Wiring WL is before time T3. Because a high-level potential is continuously input, transistor M8 and transistor M8r is in the ON state. Therefore, "0" is input as the weight coefficient w, and the node The potentials at nd3 and node nd3r are both low-level potentials.

[0230] Between time T4 and time T5, a low-level potential is input to the wiring WL. As a result, transistors M8 and M8r are turned off, and the capacitance element The potentials of nodes nd3 and nd3r are maintained by sub-C3 and capacitive element C3r. It is held.

[0231] The operation from time T1 to time T5 sets the weight coefficient of circuit MP to "0". It can be done.

[0232] As a result of the operations so far, transistors M3, M4, and M3r Since the potential of the back gates of transistors M4r and transistor M4r will be at a low level, Transistors M3, M4, M3r, and M4r Each threshold voltage is positive compared to the threshold voltage from time T2 to time T3. It shifts to transistor M3, transistor M4, transistor M3r, and The potential at each of the first terminals of transistor M4r is 0V, and the potential at each gate is... Since it is at a low level potential (Vg2), transistors M3, M4, and Both transistor M3r and transistor M4r are turned off.

[0233] Between time T5 and time T6, for example, wiring IL and wiring ILB will be initialized. Potential V ini This is input. Note that this operation is not particularly necessary, so wiring I Initialization potential V for L and wiring ILB ini You don't have to enter it. In other words, from time T5 It is not necessary to set a period until time T6. Also, for each of the wiring IL and wiring ILB The inputs may be of different potentials.

[0234] From time T6 onward, the input to the circuit MP is the neuron's signal (calculated value) "+1". Then, a high-level potential (Vg1) is input to wiring X1L and a low-level potential (Vg2) is input to wiring X2L. At this time, a high-level potential is applied to the gates of transistors M3 and M3r. (Vg1) is input, and a low level is applied to the gates of transistors M4 and M4r. The potential (Vg2) is input. Transistor M3, Transistor M3r, Transistor M 4. A low-level potential is input to the back gates of transistors M4r. Therefore, transistor M3, transistor M3r, transistor M4, and transistor Each of the M4r switches to the OFF state. In other words, this action causes the circuit MC and wiring OL to switch The circuit MC and the wiring OLB become non-conductive, and the circuit MCr and wiring OL During this time, and between the circuit MCr and the wiring OLB, a non-conductive state is maintained.

[0235] Therefore, in the circuit MC, current flows between wiring OL and wiring OLB and wiring VL. No current flows. In other words, the current I output from node outa of wiring OL. OL , and wiring O Current I output from LB node outb OLB This does not change before or after time T6. As shown, in circuit MCr, the current between wiring OL and wiring OLB and wiring VLr is No current flows. In other words, the current I output from node outa of wiring OL. OL , and wiring OL Current I output from node outb of B OLB However, it does not change around time T6.

[0236] By the way, this condition assumes that the weight coefficient is "0", and the neuron signal input to circuit MP Since we have set it to "+1", using equation (1.1), the product of the weight coefficient and the neuron's signal is The result is "0". The product of the weight coefficient and the neuron's signal being "0" indicates the movement of the circuit MP. In this work, the current I OL and current I OLB If each of them does not change It corresponds to.

[0237] Note that once the weight coefficient w is entered, only the calculated value can be changed without updating the value itself. Multiple sum-of-products operations may be performed. In this case, updating the weight coefficient w is unnecessary. Therefore, power consumption can be reduced. Furthermore, to minimize the updating of the weight coefficient w This requires that the weight coefficient w be maintained for a long period of time. In this case, for example, the OS transistor By using this method, it becomes possible to maintain the weighting coefficient w for a long period of time by taking advantage of the low off-current. ru.

[0238] [Condition 2] Next, as an example, consider a neuron input to circuit MP with a weight coefficient w of "+1". Let's consider the case where the signal (calculated value) is "+1". Figure 13B shows the circuit M in that case. This is the timing chart for P.

[0239] Regarding the operation from time T1 to time T3, the operation from time T1 to time T3 under condition 1 Since it is the same as the original, we will refer to the explanation of the operation from time T1 to time T3 in Condition 1.

[0240] Between time T3 and time T4, a high-level potential occurred in wiring IL, and a low-level potential occurred in wiring ILB. A bell potential is applied, and a weighting coefficient w of "1" is input. Wiring WL is connected from time T3. Because a high level potential is still being input from before, transistor M8 and the transistor The M8r is in the ON state. Therefore, "1" is input as the weight coefficient w, The potential at node nd3 becomes a high-level potential, while the potential at node nd3r becomes a low-level potential.

[0241] Between time T4 and time T5, a low-level potential is input to the wiring WL. As a result, transistors M8 and M8r are turned off, The capacitance element C3 and the capacitance element C3r respectively affect nodes nd3 and nd3r. Each potential is maintained.

[0242] Based on the operation from time T1 to time T5, the weight coefficient of circuit MP is set to "+1". It will be done.

[0243] The operations described so far have resulted in the respective batteries of transistors M3 and M4. The potential of the gate is the high-level potential, and the potentials of transistors M3r and M4r are respectively The potential of the back gate becomes a low level potential. Therefore, transistor M3, Each threshold voltage of station M4 is greater than the threshold voltage from time T2 to time T3. , shifting to the negative side, the thresholds for transistors M3r and M4r The voltage value shifts to the positive side compared to the threshold voltage between time T2 and time T3. Also, transistor M3, transistor M4, transistor M3r, and transistor M4 The potential at each of the first terminals of r is 0V, and the potential at each gate is a low-level potential. (Vg2) Therefore, transistor M3, transistor M4, transistor M3r, and Each of the transistors M4r is in the OFF state.

[0244] Regarding the operation from time T5 to time T6, the operation from time T5 to time T6 under condition 1 Since it is the same as the original, we will refer to the explanation of the operation from time T5 to time T6 in Condition 1.

[0245] From time T6 onward, the input to the circuit MP is the neuron's signal (calculated value) "+1". Then, a high-level potential (Vg1) is input to wiring X1L and a low-level potential (Vg2) is input to wiring X2L. At this time, a high-level potential (Vg1) is input to the gates of transistors M3 and M3r. Therefore, a low-level potential (Vg2) is applied to the gates of transistors M4 and M4r. The input is high. The back gates of transistors M3 and M4 are high A level potential is input, and the respective batteries of transistors M3r and M4r are connected. Since a low-level potential is input to the gate, transistor M3 is in the ON state. Transistor M3r, transistor M4, and transistor M4r are turned off. In other words, This action creates a conductive state between circuit MC and wiring OL, and between circuit MC and wiring OLB. The connection between them becomes non-conductive, and the connection between circuit MCr and wiring OL becomes non-conductive, circuit MC The connection between r and the OLB wiring becomes non-conductive.

[0246] At this time, in circuit MC, transistor M3 is in the ON state, so wiring O Current flows from L to wiring VL. In other words, the output from node outa of wiring OL Current I OL It increases after time T6 has elapsed (in Figure 13B, current I OL The increase It is written as ΔI.) On the other hand, in circuit MC, transistor M4 is in the OFF state. Therefore, no current flows between the wiring OLB and the wiring VL. Also, in circuit MCr And because transistor M3r is in the off state, from wiring OLB to wiring VLr No current flows between them. Also, in circuit MCr, transistor M4r is in the off state. Therefore, no current flows between wiring OL and wiring VLr. Current I output from node outb of B OLB This does not change before or after time T6.

[0247] By the way, this condition assumes that the weight coefficient w is "+1", and the neurons input to circuit MP Since the signal (calculated value) is set to "+1", using equation (1.1), the weight coefficient and the neuron The product of the signals from the neurons is "+1". This is the result where the product of the weight coefficient and the neuron's signal is "1". In the operation of circuit MP, the current I OL As the current I changes OLB That's strange This addresses cases where transformation does not occur.

[0248] [Condition 3] Next, as an example, consider a neuron input to circuit MP with a weight coefficient w of "-1". Let's consider the case where the signal (calculated value) is "+1". Figure 13C shows the circuit M in that case. This is the timing chart for P.

[0249] Regarding the operation from time T1 to time T3, the operation from time T1 to time T3 under condition 1 Since it is the same as the original, we will refer to the explanation of the operation from time T1 to time T3 in Condition 1.

[0250] Between time T3 and time T4, wiring IL has a low potential and wiring ILB has a high potential. A bell potential is applied, and a weighting coefficient w of "-1" is input. At time T3, the wiring WL is connected. Because a high-level potential has been continuously input from earlier, transistor M8 and transistor The ZISTA M8r is in the ON state. Therefore, "-1" is input as the weight coefficient w. The potential at node nd3 becomes a low-level potential, and the potential at node nd3r becomes a high-level potential. ru.

[0251] Between time T4 and time T5, a low-level potential is input to the wiring WL. As a result, transistors M8 and M8r are turned off, Nodes nd3 and nd3 are determined by the capacitance element C3 and the capacitance element C3r, respectively. Each potential of r is maintained.

[0252] Based on the operation from time T1 to time T5, the weight coefficient of circuit MP is set to "-1". It will be done.

[0253] The operations described so far have resulted in the respective batteries of transistors M3 and M4. The potential of the gate is the low-level potential, and the potentials of transistors M3r and M4r are respectively The potential of the back gate becomes a high level potential. Therefore, transistor M3 and the transistor Each threshold voltage of the inverter M4 is calculated from the threshold voltage between time T2 and time T3. Furthermore, it shifts to the positive side, and each of transistors M3r and M4r The threshold voltage is shifted to the positive side compared to the threshold voltage from time T2 to time T3. Also, transistors M3, M4, M3r, and transistors The potential of each first terminal of the M4r is 0V, and the potential of each gate is low level. Since the potential (Vg2), transistor M3, transistor M4, transistor M3 r and transistor M4r are assumed to be in the off state.

[0254] Regarding the operation from time T5 to time T6, the operation from time T5 to time T6 under condition 1 Since it is the same as the original, we will refer to the explanation of the operation from time T5 to time T6 in Condition 1.

[0255] From time T6 onward, the input to the circuit MP is the neuron's signal (calculated value) "+1". Then, a high-level potential (Vg1) is input to wiring X1L and a low-level potential (Vg2) is input to wiring X2L. When this occurs, a high-level potential (Vg) is applied to the gates of transistors M3 and M3r. 1) When input, a low level potential is applied to the gates of transistors M4 and M4r. Vg2) is input. The backgear of transistors M3 and M4 A low-level potential is input to the terminal, affecting transistors M3r and M4r. Because a high-level potential is input to the back gate of each transistor, transistor M3r turns on. The state is such that transistors M3, M4, and M4r are in the off state. In other words, this action causes a non-conductive state between circuit MC and wiring OL, and circuit MC The connection between the circuit and the wiring OLB becomes non-conductive, and the connection between the circuit MCr and the wiring OL becomes non-conductive. As a result, there is electrical conductivity between the circuit MCr and the wiring OLB.

[0256] At this time, in circuit MCr, transistor M3r is in the ON state, Current flows between the line OLB and the wiring VLr. In other words, the current flows from the node outb of the wiring OLB. Current I output from OLB It increases after time T6 has elapsed (in Figure 13C, current I O LB The increase is denoted as ΔI. On the other hand, in circuit MC, transistor M3 Since it is in the OFF state, no current flows between wiring OL and wiring VL. Also, In the MC circuit, transistor M4 is in the OFF state, so wiring OLB to wiring V No current flows between L and the circuit. Also, in circuit MCr, transistor M4r is in the OFF state. Because of this state, no current flows between wiring OL and wiring VLr. Current I output from node outa of line OL OL This does not change before or after time T6.

[0257] By the way, this condition assumes that the weight coefficient w is "-1", and the neurons input to circuit MP Since the signal (calculated value) is set to "+1", using equation (1.1), the weight coefficient and the neuron The product of the signals of the two neurons is "-1". The result is that in the operation of circuit MP, the current I OL If the current I does not change, OLB This handles cases where [something] changes.

[0258] [Condition 4] Under these conditions, as an example, the weight coefficient w is set to "0", and the neuron input to circuit MP... Let's consider the operation of circuit MP when the signal (calculated value) is set to "-1". Figure 14A shows the operation in that case. This is a timing chart for the MP circuit in the combined circuit.

[0259] Regarding the operation from time T1 to time T6, the operation from time T1 to time T6 under condition 1 Since it is the same as the original, we will refer to the explanation of the operation from time T1 to time T6 in Condition 1.

[0260] From time T6 onward, the input to the circuit MP is set to the neuron's signal (calculated value) "-1". Then, a low-level potential (Vg2) is input to wiring X1L and a high-level potential (Vg1) is input to wiring X2L. At this time, a low-level potential is applied to the gates of transistors M3 and M3r. (Vg2) is input, and a high level is applied to the gates of transistors M4 and M4r. A potential (Vg1) is input. Transistor M3, Transistor M3r, Transistor M 4. A low-level potential is input to the back gates of transistors M4r. Therefore, transistor M3, transistor M3r, transistor M4, and transistor Each of the M4r switches to the OFF state. In other words, this action causes the circuit MC and wiring OL to switch The circuit MC and the wiring OLB become non-conductive, and the circuit MCr and wiring OL The circuit MCr and the wiring OLB become non-conductive.

[0261] Therefore, in the circuit MC, current flows between wiring OL and wiring OLB and wiring VL. No current flows. In other words, the current I output from node outa of wiring OL. OL , and wiring O Current I output from LB node outb OLB This does not change before or after time T6. As shown, in circuit MCr, the current between wiring OL and wiring OLB and wiring VLr is No current flows. In other words, the current I output from node outa of wiring OL. OL , and wiring OL Current I output from node outb of B OLB However, it does not change around time T6.

[0262] By the way, this condition assumes that the weight coefficient w is "0", and the signal of the neuron input to circuit MP Since the unit (operational value) is set to "-1", using equation (1.1), the weight coefficient and the neuron The product of the signals is "0". The result of the product of the weight coefficient and the neuron's signal being "0" is In the operation of circuit MP, the current I OL and current I OLB Each of them is different This addresses the case where the circuit does not change, which is consistent with the result of circuit operation under condition 1.

[0263] [Condition 5] Under these conditions, as an example, the weight coefficient w is set to "+1", and the neuron input to circuit MP Let's consider the operation of circuit MP when the signal (calculated value) of n is set to "-1". Figure 14B shows the operation of the circuit MP. This is a timing chart for the circuit MP in the given case.

[0264] Regarding the operation from time T1 to time T6, the operation from time T1 to time T6 under condition 2 Since it is the same as the previous case, we will refer to the explanation of the operation from time T1 to time T6 in condition 2.

[0265] From time T6 onward, the input to the circuit MP is set to the neuron's signal (calculated value) "-1". Then, a low-level potential (Vg2) is input to wiring X1L and a high-level potential (Vg1) is input to wiring X2L. At this time, a low-level potential is applied to the gates of transistors M3 and M3r. (Vg2) is input, and a high level is applied to the gates of transistors M4 and M4r. A potential (Vg1) is input. The respective bars of transistors M3 and M4 A high-level potential is input to the gate, and transistors M3r and M4r Since a low-level potential is input to each of the back gates, transistor M4 ON state, transistors M3, M3r, and M4r are OFF state This means that, as a result of this operation, the circuit MC and the wiring OL become non-conductive, and the rotation The circuit MC and wiring OLB become conductive, while the circuit MCr and wiring OL become non-conductive. As a result, the circuit MCr and the wiring OLB become non-conductive.

[0266] At this time, in circuit MC, transistor M4 is in the ON state, so wiring O Current flows between LB and wiring VL. In other words, current flows from node outb of wiring OLB. Current I OLB It increases after time T6 has elapsed (in Figure 14B, current I OLB of The increase is denoted as ΔI.) On the other hand, in circuit MC, transistor M3 is in the off state. Because of this state, no current flows between wiring OL and wiring VL. Also, circuit MC At r, transistor M3r is in the off state, so the wiring OLB is connected to the wiring VL. No current flows between r and r. Also, in circuit MCr, transistor M4r is in the off state. Because of this state, no current flows between wiring OL and wiring VLr. Current I output from node outa of line OL OL This does not change before or after time T6.

[0267] By the way, this condition assumes that the weight coefficient w is "+1", and the neurons input to circuit MP Since the signal (calculated value) is set to "-1", using equation (1.1), the weight coefficient and the neuron The product of the signals of the two neurons is "-1". The result is that in the operation of circuit MP, the current I OL If the current I does not change, OLB This corresponds to the case where the value changes, which is consistent with the result of the circuit operation under condition 3.

[0268] [Condition 6] Under these conditions, as an example, the weight coefficient w is set to "-1", and the neuron input to circuit MP Let's consider the operation of circuit MP when the signal (calculated value) of n is set to "-1". Figure 14C shows the operation of the circuit MP. This is a timing chart for the circuit MP in the given case.

[0269] Regarding the operation from time T1 to time T6, the operation from time T1 to time T6 under condition 3 Since it is the same as the original, we will refer to the explanation of the operation from time T1 to time T6 in condition 3.

[0270] From time T6 onward, the input to the circuit MP is set to the neuron's signal (calculated value) "-1". Then, a low-level potential (Vg2) is input to wiring X1L and a high-level potential (Vg1) is input to wiring X2L. At this time, a low-level potential is applied to the gates of transistors M3 and M3r. (Vg2) is input, and a high level is applied to the gates of transistors M4 and M4r. A potential (Vg1) is input. The respective bars of transistors M3 and M4 A low-level potential is input to the gate, and transistors M3r and M4r Because a high-level potential is input to the back gate of each transistor M4r When the transistor is ON, transistors M3, M3r, and M4 are OFF. This means that, as a result of this operation, the circuit MC and the wiring OL become non-conductive, and the rotation The connection between circuit MC and wiring OLB becomes non-conductive, while the connection between circuit MCr and wiring OL becomes conductive. As a result, the circuit MCr and the wiring OLB become non-conductive.

[0271] At this time, in circuit MCr, transistor M4r is in the ON state, Current flows between line OL and wiring VLr. That is, from node outa of wiring OL Output current I OL It increases after time T6 has elapsed (in Figure 14C, current I OLB of The increase is denoted as ΔI.) On the other hand, in circuit MC, transistor M3 is in the off state. Because of this state, no current flows between wiring OL and wiring VL. Also, circuit MC At r, transistor M3r is in the off state, so the wiring OLB is connected to the wiring VL. No current flows between r and r. Also, in circuit MCr, transistor M4r is in the off state. Because of this state, no current flows between wiring OL and wiring VLr. Current I output from node outb of the line OLB OLB This does not change before or after time T6. .

[0272] By the way, this condition assumes that the weight coefficient w is "-1", and the neurons input to circuit MP Since the signal (calculated value) is set to "-1", using equation (1.1), the weight coefficient and the neuron The product of the signals of the neurons is "+1". The result is that in the operation of circuit MP, the current I OL As the current I changes OLB but This addresses the case where there is no change, which is consistent with the result of the circuit operation under condition 2.

[0273] [Condition 7] Under these conditions, as an example, the weight coefficient w is "0", and the new input to circuit MP is Let's consider the operation of circuit MP under condition 7, where Ron's signal (calculated value) is "0". (See diagram) 15A is the timing chart for the circuit MP in that case.

[0274] Regarding the operation from time T1 to time T6, the operation from time T1 to time T6 under condition 1 Since it is the same as the original, we will refer to the explanation of the operation from time T1 to time T6 in Condition 1.

[0275] From time T6 onward, the input of the neuron signal (calculated value) "0" to circuit MP is A low-level potential (Vg2) is input to wiring X1L, and a low-level potential (Vg2) is input to wiring X2L. At this time, a low-level potential is applied to the gates of transistors M3 and M3r. Vg2) is input, and low-level current is supplied to the gates of transistors M4 and M4r. The position (Vg2) is input. That is, transistor M3, transistor M3r, transistor Regardless of the back gate potential of transistor M4 and transistor M4r, transistor M3 Transistors M3r, M4, and M4r are each in the OFF state. This results in the following state. In other words, this action creates a connection between circuit MC and wiring OL, between circuit MC and wiring OL The connections between B, between circuit MCr and wiring OL, and between circuit MCr and wiring OLB are non-conductive. This is the state it is in.

[0276] Therefore, in the circuit MC, between wiring OL and either wiring VL or wiring VLr No current flows. In other words, the current I output from node outb of the wiring OLB is not flowing. OLB teeth, It does not change before and after time T6. Similarly, in circuit MCr, from wiring OLB to wiring VL or No current flows between the other end of wiring VLr. In other words, no current flows between the outa node of wiring OL. The output current I OL However, it does not change around time T6.

[0277] By the way, this condition assumes that the weight coefficient w is "0", and the signal of the neuron input to circuit MP Since the unit (operational value) is set to "0", using equation (1.1), the weight coefficient and the neuron The product of the signals is "0". The result when the product of the weight coefficient and the neuron's signal is "0" is: In the operation of circuit MP, the current I OL and current I OLB Each of them changes This corresponds to the case where this does not happen, which is consistent with the results of the circuit operation under conditions 1 and 4.

[0278] [Condition 8] Under these conditions, as an example, the weight coefficient w is "+1", and the input to circuit MP is Let's consider the operation of circuit MP under condition 8, where the signal (calculated value) of -ron is "0". Figure 15B shows the timing chart of the circuit MP in that case.

[0279] Regarding the operation from time T1 to time T6, the operation from time T1 to time T6 under condition 2 Since it is the same as the previous case, we will refer to the explanation of the operation from time T1 to time T6 in condition 2.

[0280] From time T6 onward, the input of the neuron signal (calculated value) "0" to circuit MP is A low-level potential (Vg2) is input to wiring X1L, and a low-level potential (Vg2) is input to wiring X2L. This means that transistors M3, M3r, M4, and Regardless of the back gate potential of transistor M4r, transistor M3, transistor M3r Transistor M4 and transistor M4r each turn off. Therefore, the connection between circuit MC and wiring OL, and between circuit MC and wiring OLB, becomes non-conductive. Therefore, the circuit MCr and wiring OL, and the circuit MCr and wiring OLB, are in a non-conductive state. Therefore, either wiring VL or wiring VLr can be taken from wiring OL or wiring OLB. No current flows between these points, therefore the current I output from node outa of wiring OL is not present. OL , And the current I output from node outb of the wiring OLB OLB Each of these is at time T6 It doesn't change before or after.

[0281] By the way, this condition assumes that the weight coefficient w is "+1", and the neurons input to circuit MP Since the signal (calculated value) is set to "0", using equation (1.1), the weight coefficient and the neuron The product of the signals is "0". The result of the product of the weight coefficient and the neuron's signal being "0" is In the operation of circuit MP, the current I OL and current I OLB Each of them is different This addresses the case where the circuit does not change, which is consistent with the results of the circuit operation under conditions 1, 4, and 7. .

[0282] [Condition 9] Under these conditions, for example, the weight coefficient w is "-1", and the New input to circuit MP Let's consider the operation of circuit MP under condition 9, where Ron's signal (calculated value) is "0". (See Figure) 15C is the timing chart for the circuit MP in that case.

[0283] Regarding the operation from time T1 to time T6, the operation from time T1 to time T6 under condition 3 Since it is the same as the original, we will refer to the explanation of the operation from time T1 to time T6 in condition 3.

[0284] From time T6 onward, the input of the neuron signal (calculated value) "0" to circuit MP is A low-level potential (Vg2) is input to wiring X1L, and a low-level potential (Vg2) is input to wiring X2L. This means that transistors M3, M3r, M4, and Regardless of the back gate potential of transistor M4r, transistor M3, transistor M3r Transistor M4 and transistor M4r are both turned off. Therefore, circuit MC will be in a non-conductive state between either wiring OL or wiring OLB. Therefore, circuit MCr will be in a non-conductive state whether it is between wiring OL or wiring OLB. Therefore, from wiring OL or wiring OLB to either wiring VL or wiring VLr Since no current flows between them, the current I output from node outa of wiring OL is not present. OL , and Current I output from node outb of the wiring OLB. OLB Each of these is around time T6. It doesn't change.

[0285] By the way, this condition assumes that the weight coefficient w is "-1", and the neurons input to circuit MP Since the signal (calculated value) is set to "0", using equation (1.1), the weight coefficient and the neuron The product of the signals is "0". The result of the product of the weight coefficient and the neuron's signal being "0" is In the operation of circuit MP, the current I OL and current I OLB Each of them is different To address the case where this does not occur, this is the result of the circuit operation under conditions 1, 4, 7, and 8. They match.

[0286] The results of the operation examples for conditions 1 through 9 described above are summarized in the table below. Note that in the table below, high level The high potential is indicated as "high," and the low-level potential is indicated as "low."

[0287] [Table 2]

[0288] Here, one circuit MC and one circuit MCr are connected to wiring OL and wiring OLB. This is shown as an example. This is explained in Figures 2, 6, 7, and 8. In addition, multiple circuits MC and MCr are connected to wiring OL and wiring OLB. In this case, the current output from each circuit MC and circuit MCr also conforms to Kirchhoff's current law. Based on this, they will be added together. As a result, the summation operation will be performed. Then, in circuits MC and MCr, a multiplication operation is performed, and multiple circuits MC and MCr... The sum of these currents is calculated by adding them together. As a result, a sum-of-products operation is performed. This will happen.

[0289] By the way, in the operation of the MP circuit, the weight coefficients are limited to only two values, "+1" and "-1". By performing calculations that treat the neuron's signals as only two values, "+1" and "-1", the circuit MP becomes It can perform the same operation as the negation of the exclusive OR (the coincidence circuit).

[0290] Furthermore, in the operation of the MP circuit, the weight coefficients are limited to only two values: "+1" and "0". By performing calculations using only two values ​​for Ron's signal, "+1" and "0", the circuit MP performs logical AND It can perform operations similar to those of a circuit.

[0291] By the way, in this example of operation, the circuit MC of circuit MP, the holding part HC of circuit MCr, and The potential held in the holding part HCr was set to either a high-level potential or a low-level potential, but the holding part The HC and the holding part HCr may hold potentials that represent analog values. For example, weighting coefficients. In the case of a "positive analog value," a high-level analog signal is sent to node nd3 of the holding unit HC. A low-level potential is maintained at node nd3r of the potential-holding part HCr. In the case of a "negative analog value," for example, a low-level potential is applied to node nd3 of the holding unit HC. A high level of analog potential is maintained at node nd3r of the HCr component. And current I OL and current I OLB The magnitude of the current will be proportional to the analog potential. The circuit in Figure 9A shows how the holding parts HC and HCr hold potentials that represent analog values. This may not be limited to the example of MP operation, but may also be applied to other circuit MPs shown in this specification, etc.

[0292] <Configuration Example 2> Next, we will explain an example of a circuit configuration that can be applied to the circuit MP shown in Figures 5C and 5D. .

[0293] The circuit MP shown in Figure 16A is an example of the configuration of the circuit MP in Figure 5C, and the circuit M in Figure 9A is a different circuit from Figure 9A. The difference from P is that wiring IL and wiring ILB are combined into one, and wiring WL is as shown in Figure 9A. The point is that it has wiring W1L and wiring W2L.

[0294] In circuit MP in Figure 16A, the first terminal of transistor M8 and transistor M8r are It is electrically connected to wiring IL. In addition, the gate of transistor M8 is connected to wiring W1L. The gate of transistor M8r is electrically connected to wiring W2L. Note that the connection configuration of circuit MP in Figure 16A and circuit MP in Figure 9A is the same. I will omit the explanation regarding that.

[0295] When setting weighting coefficients for circuit MP in Figure 16A, first, the wiring W1L and wiring W2L are used By changing the supplied potential, transistor M8 is turned ON, and transistor M8r is turned OFF Set to the F state, then supply a potential for holding from the wiring IL to the holding part HC, and the transistor Turn off the M8. Then, change the potential supplied to wiring W1L and wiring W2L. Next, turn transistor M8 to the OFF state and transistor M8r to the ON state, then distribute The wire IL supplies a potential to the holding part HCr for retention, and transistor M8r is turned off. In this way, in the case of circuit MP in Figure 16A, the wiring IL is connected to the retaining part HC, and the retaining part HC By sequentially supplying potential to r, the holding part HC and the holding part HCr are supplied with a weighting coefficient equivalent to the current. It can maintain electrical potential.

[0296] The circuit MP shown in Figure 16B is an example of the configuration of the circuit MP in Figure 5D, and the circuit M in Figure 9A is a different circuit from Figure 9A. The difference from P is that wiring IL and wiring OL are combined into wiring IOL, and wiring ILB and wiring OLB are combined. The key point is that the wiring is consolidated into an IOLB (Internet Load Balance).

[0297] In circuit MP of Figure 16B, the first terminal of transistor M8 is electrically connected to wiring IOL. Connected, transistor M8r is electrically connected to the wiring IOLB. In addition, The second terminal of transistor M3 is electrically connected to the wiring IOL, and the second terminal of transistor M4 The terminal is electrically connected to wiring IOLB, and the second terminal of transistor M3r is connected to wiring IO. The second terminal of transistor M4r is electrically connected to LB, and the wiring IOL is electrically connected to LB. It is configured similarly to the circuit MP in Figure 16B and the circuit MP in Figure 9A. I will omit the explanation for the parts that are present.

[0298] In the circuit MP shown in Figure 16B, the wiring IOL is electrically connected to the retaining part HC, and the retaining part HCr Wiring IOLB is electrically connected, and transistors M8 and M8r are connected to wiring WL. Since each gate is electrically connected, the holding part H is the same as in circuit MP in Figure 9A. The potential corresponding to the weighting coefficient can be simultaneously written to C and the holding part HCr.

[0299] <Configuration Example 3> Unlike the circuit MP in Figure 9A, the circuit MP shown in Figure 17 only has a retaining part HC and a retaining part HCr. Instead, it is a circuit having retaining parts HCs and retaining parts HCsr.

[0300] The circuit MC included in circuit MP in Figure 17 is added to the circuit elements of circuit MP in Figure 9A. Uh, transistor M8s, transistor M5a, transistor M5b, transistor M5 It has sa, transistor M5sb, and capacitive element C3s. It is also included in the circuit MP in Figure 17. The circuit MCr, which is being constructed, has the same circuit elements as the circuit MC, therefore the transistors of the circuit MC Transistor M8s, Transistor M5a, Transistor M5b, Transistor M5sa, Transistor Transistor M8sr, Transistor M5sb, and capacitor C3s, respectively. Transistor M5ar, Transistor M5br, Transistor M5sar, Transistor M5sb It has r and a capacitive element C3sr.

[0301] Note that in this specification, transistor M5a, transistor M5b, and transistor Transistor M5sa, Transistor M5sb, Transistor M5ar, Transistor M5br, The transistors M5sar and M5sbr are in the ON state unless otherwise specified. The case ultimately includes operating in the linear domain. That is, each of the above The gate voltage, source voltage, and drain voltage of the transistor are within the range of operation in the linear region. This includes cases where the voltage is properly biased within the range.

[0302] Next, the configuration of circuit MP in Figure 17 will be explained. Explanations of the parts that have the same configuration as circuit MP in Figure 9A will be omitted.

[0303] The first terminal of transistor M5a is electrically connected to the second terminal of transistor M3. The second terminal of transistor M5a is electrically connected to wiring OL, and the transistor M5a The gate is electrically connected to wiring S1L. The first terminal of transistor M5b is connected to the transistor The second terminal of transistor M4 is electrically connected, and the second terminal of transistor M5b is connected to wiring O The gate of transistor M5b is electrically connected to wiring S1L, and is electrically connected to LB. The first terminal of transistor M5sa is electrically connected to the second terminal of transistor M3s. The second terminal of transistor M5sa is connected to wiring OL, and the transistor The gate of transistor M5sa is electrically connected to wiring S2L. The first terminal is electrically connected to the second terminal of transistor M4s, and transistor M5sb The second terminal is electrically connected to the wiring OLB, and the gate of transistor M5sb is connected to wiring S Electrically connected to 2L. The first terminal of transistor M3s and transistor M4s The first terminal is electrically connected to the wiring VLc, and the gate of transistor M3s is wired The gate of transistor M4s is electrically connected to X1L, and the wire X2L is electrically connected to X1L. It is being done.

[0304] The first terminal of transistor M8 is electrically connected to wiring I1L. The gate of M8s is electrically connected to wiring WL, and the first terminal of transistor M8s is connected to wiring Electrically connected to line I2L, the second terminal of transistor M8s is connected to the first terminal of capacitive element C3s. The terminal, the back gate of transistor M3s, the back gate of transistor M4s, It is electrically connected to the wiring VLcs. The second terminal of the capacitive element C3s is electrically connected to the wiring VLcs. It is being done.

[0305] In circuit MP in Figure 17, circuit MCr has almost the same circuit configuration as circuit MC. Therefore, the circuit elements of circuit MCr are distinguished from the circuit elements of circuit MC. Therefore, the symbol "r" is added.

[0306] Wiring VLc, VLcs, VLcr, and VLcsr are wires VL and VL. Similar to Ls, wiring VLr, and wiring VLsr, it functions as a voltage line that supplies a constant voltage. The constant voltages in question include the low-level potential VSS, other low-level potentials, and the ground potential. This can be done as follows. Furthermore, the constant voltage can be set to VDD, which is a high-level potential. Also, wiring VL, wiring VLs, wiring VLr, wiring VLsr, wiring VLc, wiring V The constant voltages supplied by Lcs, wiring VLcr, and wiring VLcsr are different from each other. They may be identical, or some or all of them may be identical.

[0307] Wiring S1L is for transistors M5a, M5b, M5ar, and The voltage line that supplies the potential to turn transistor M5br on or off is used as the voltage line. It functions and wiring S2L is transistor M5sa, transistor M5sb, transistor The potential required to turn M5sar and transistor M5sbr on or off is supplied. It functions as a voltage supply line.

[0308] The circuit MP shown in Figures 5C and 5D should apply the configuration shown in the circuit MP of Figure 17. This allows for the storage of two weight coefficients. Specifically, the circuit MP in Figure 17 is 1 The potential corresponding to the weight coefficient of the first element is determined by the holding part HC of the circuit MC and the holding part HCr of the circuit MCr. , held in place, the potential corresponding to the second weight coefficient is applied to the holding part HCs of the circuit MC and the circuit MC The holding part HCsr can hold it. Also, the circuit MP in Figure 17 has wiring S1L. The weight coefficients used in the calculation can be switched depending on the potential supplied from wiring S2L. For example, the circuits MP[1,j] to MP[m,j] of the arithmetic circuit 110 contain Each retaining part HC and retaining part HCr has a weighting coefficient w1 (k-1) j (k) Or maybe lol m (k-1 ) j (k) It maintains a potential equivalent to the circuit MP[1,j] of the calculation circuit 110 or circuit MP Each retaining part HCs and HCsr included in [m,j] has a weighting coefficient w1 (k-1) h ( k) Or maybe lol m (k-1) h (k) (Here, h is an integer greater than or equal to 1 and not equal to j.) Maintain the corresponding potential, and connect wiring XLS[1] to wiring XLS[m] (circuit MP in Figure 17) Signal z1 (connected to wiring X1L, wiring X2L) (k-1) ~z m (k-1) The electric potential corresponding to Input. At this time, a high-level potential is applied to the wiring S1L, and transistor M5a, Turn on transistors M5b, M5ar, and M5br, and A low-level potential is applied to the line S2L, and transistors M5sa, M5sb, and By turning off transistors M5sar and M5sbr, the arithmetic circuit Circuits MP[1,j] through MP[m,j] of 110 have a weight coefficient w1 (k-1) j (k ) Or maybe lol m (k-1) j (k) and signal z1 (k-1) ~z m (k-1) Product-sum and activity It is possible to perform calculations on the transformation function. Also, by applying a low-level potential to the wiring S1L, Transistor M5a, Transistor M5b, Transistor M5ar, and Transistor M5br With the switch turned off, a high-level potential is applied to the wiring S2L, and transistor M5sa, Turn on transistors M5sb, M5sar, and M5sbr. By doing so, the circuits MP[1,j] to MP[m,j] of the arithmetic circuit 110 have weight coefficients w 1 (k-1) h (k) Or maybe lol m (k-1) h (k) and signal z1 (k-1) ~z m (k- 1)It is possible to perform sum-of-product and activation function operations with respect to [the specified variable].

[0309] As described above, by applying the circuit MP in Figure 17 to the arithmetic circuit 110, the weight coefficients can be calculated. It can hold two values, and the weight coefficients can be switched to perform sum-of-products and activation function operations. This is possible. The arithmetic circuit 110 that constitutes the circuit MP in Figure 17, for example, the k-th layer - When the number of rons is greater than n, when operations are performed in an intermediate layer different from the kth layer, etc. This is effective. Also, in the circuit MP of Figure 17, the holding part of circuit MC and circuit MCr Each of the above is set to 2, but each of the circuit MC and circuit MCr can be set to 3 depending on the situation. The device may have the above-mentioned retaining parts.

[0310] Furthermore, the circuit MP included in one embodiment of the present invention is not limited to the circuit MP shown in Figure 17. It is not determined. The circuit configuration of circuit MP of a semiconductor device according to one aspect of the present invention is the circuit MP in Figure 17. It can be changed depending on the situation.

[0311] For example, the circuit MP shown in Figure 18 contains the same number of transistors as the circuit MP in Figure 17. The circuit configuration has been modified by changing the number of components. Specifically, circuit MP in Figure 18 is the same as circuit M in Figure 17. P's transistors M5a, M5b, M5ar, and M 5br, transistor M5sa, transistor M5sb, transistor M5sar, and Instead of transistor M5sbr, use transistor M5, transistor M5r, or transistor It has a transistor M5s and a transistor M5sr. The first terminal of transistor M5 is connected to the transistor The first terminal of transistor M3 and the first terminal of transistor M4 are electrically connected, The second terminal of transistor M5 is electrically connected to wiring VL, and the gate of transistor M5 It is electrically connected to wiring S1L. The first terminal of transistor M5s is The first terminal of transistor M3 and the first terminal of transistor M4 are electrically connected, and the transistor The second terminal of transistor M5s is electrically connected to the wiring VLc, and the gate of transistor M5s It is electrically connected to wiring S2L.

[0312] The second terminal of transistor M3 and the second terminal of transistor M3s are electrically connected to wiring OL. The second terminal of transistor M4 and the second terminal of transistor M4s are connected to the wiring O It is electrically connected to LB.

[0313] Note that the circuit MCr of circuit MP in Figure 18 has almost the same circuit configuration as circuit MC. Therefore, the circuit elements of circuit MCr are distinguished from the circuit elements of circuit MC. Therefore, the sign "r" is added. Also, in circuit MCr, the first of transistor M3r Terminal 2 and the second terminal of transistor M3sr are electrically connected to wiring OL, and the transistor The second terminal of transistor M4r and the second terminal of transistor M4sr are electrically connected to the OLB wiring. It continues.

[0314] The circuit MP in Figure 18 can reduce the number of circuit elements compared to the circuit MP in Figure 17. Therefore, by using the circuit MP in Figure 18 for the arithmetic circuit 110, the circuit area of ​​the arithmetic circuit 110 can be reduced. It can be cut.

[0315] Furthermore, for example, circuit MP shown in Figure 19 is a modified version of circuit MP shown in Figure 18, with altered wiring configurations around it. The circuit configuration is as follows. Specifically, circuit MP in Figure 19 has the same wiring as circuit MP in Figure 18. Combine wiring I1L and wiring I2L into wiring IL, and wiring I1LB and wiring I2L of circuit MP in Figure 18. B is combined into wiring ILB, and wiring W1L and W2L are used as wiring WL for circuit MP in Figure 18. The configuration is as follows: Wiring W1L connects the gate of transistor M8 and transistor M The gate of transistor 8r is electrically connected to the wiring W2L, and the gate of transistor M8s is connected to the gate of transistor M8s. It is electrically connected to the gate of transistor M8sr.

[0316] When setting weight coefficients for circuit MP in Figure 19, first, the values ​​for wiring W1L and wiring W2L are set. By changing the potential supplied to them, transistors M8 and M8r are turned on. Set the device to the OFF state, turn off transistors M8s and M8sr, and then wire it up. The IL and wiring ILB each supply the potential necessary for holding the retaining parts HC and HCr. Then, turn off transistors M8 and M8r. After that, wire W1 By changing the potential supplied to L and wiring W2L respectively, transistor M8 and transistor M8 and Turn transistor M8r off, and turn on transistors M8s and M8sr. Next, connect the wiring IL and wiring ILB to the holding parts HCs and HCsr respectively. A potential is supplied to maintain the state, and transistors M8s and M8sr are turned off. To achieve this state, in the case of circuit MP in Figure 19, the holding part HC is reached from wiring IL and wiring ILB. By sequentially supplying potential to HCr, retaining part HCs, and retaining part HCsr, The HC, HCr, holding HCs, and holding HCsr parts maintain a potential corresponding to the weighting coefficient. It is possible.

[0317] <Configuration Example 4> Circuit MP shown in Figure 20A is a circuit that can be applied to circuit MP in Figure 5A, and the holding part HC, Each of the HCr components replaces the capacitive element C3 and the capacitive element C3r in the inverter loop circuit. It differs from circuit MP in Figure 9A in that it has a different configuration.

[0318] In the circuit MC of circuit MP in Figure 20A, the holding part HC is connected to the inverter circuit INV5, It has an inverter circuit INV6. The input terminal of inverter circuit INV5 is an inverter The output terminal of the transistor INV6, the second terminal of transistor M8, and the battery terminal of transistor M3 The back gate of transistor M4 is electrically connected to the back gate of transistor M4. Similar to the explanation for 9A, the second terminal of transistor M8 and the back gate of transistor M3. And the back gate of transistor M4, the input terminal of inverter circuit INV5, and the inverter The electrical connection point between the output terminal of circuit INV6 and the node nd3 is referred to as node nd3. nd3 is not an input terminal for inverter circuit INV5, but an output terminal for inverter circuit INV5. It may be connected to a power terminal.

[0319] Note that circuit MCr of circuit MP in Figure 20A has almost the same circuit configuration as circuit MC. Therefore, the circuit elements of circuit MCr are distinguished from the circuit elements of circuit MC. Therefore, the symbol "r" is added.

[0320] The retaining part HC included in the circuit MC is the inverter circuit INV5 and the inverter circuit I The NV6 and the holding part H included in the circuit MCr form an inverter loop. Cr is an inverter circuit INV5r, an inverter circuit INV6r, and an inverter A loop is formed. In other words, the circuit MP in Figure 20A consists of a holding part HC and a holding part H Each inverter loop of Cr maintains a potential corresponding to the weighting coefficient. can.

[0321] Note that in circuit MP of Figure 20A, inverter circuit INV5 and inverter circuit INV5r The inverter circuits INV6 and INV6r are shown in the diagram, but the inverter circuit Circuit INV5, inverter circuit INV5r, inverter circuit INV6, inverter circuit IN At least one of V6r is a logic that receives an input signal and outputs an inverted signal of that input signal. It may be replaced with a circuit. Examples of such logic circuits include NAND gates, NOR gates, XOR circuits, circuits combining these, etc., can be used. Specifically, inverters When replacing the circuit with a NAND gate, set one of the two input terminals of the NAND gate to a fixed potential. By inputting a high-level potential, the NAND gate can function as an inverter circuit. Yes, it is possible. Also, when replacing an inverter circuit with a NOR circuit, the two input terminals of the NOR circuit By inputting a low-level potential as a fixed potential to one side, the NOR circuit becomes an inverter circuit. It can function in this way. Also, when replacing an inverter circuit with an XOR circuit, XO By inputting a high-level potential as a fixed potential to one of the two input terminals of the R circuit, the XOR circuit is formed. It can function as an inverter circuit.

[0322] As described above, the inverter circuits described in this specification include NAND gates and NOR gates. It can be replaced with logic circuits such as paths, XOR circuits, or circuits that combine these. Therefore, in this specification and elsewhere, the term "inverter circuit" is used instead of "logic circuit". It can be referred to as such.

[0323] Furthermore, the circuit MP in Figure 20A can be modified depending on the situation. Figure 20A An example of a modified circuit MP is shown in Figure 20B. The circuit MP in Figure 20B is the same as the circuit in Figure 20A. The MP has a configuration where the retaining part HCr is removed from the circuit MCr, and the retaining part HC of the circuit MC is the circuit The back gates of transistors M3r and M4r of MCr are electrically connected. It has a well-structured configuration.

[0324] Figure 20B shows the output terminal of inverter circuit INV5 and the input of inverter circuit INV6. The terminal and the electrical connection point are designated as node nd3r. In other words, the terminal of transistor M3r The back gate of transistor M4r and the potential of node nd3r are connected. To be empowered.

[0325] The circuit MP shown in Figure 20B does not include a holding part HCr in the circuit MCr, and is a transistor. The potential applied to the back gate of transistor M3r and the back gate of transistor M4r is the circuit It is held by the MC's holding part HC. The holding part HC is also connected to the inverter circuit INV5. Because it has an inverter loop configuration consisting of an inverter circuit INV6, node nd3 Then either a high-level potential or a low-level potential is maintained, and at node nd3r, the high-level potential is maintained. Alternatively, the other low-level potential is maintained.

[0326] Furthermore, due to the configuration of the inverter loop, the holding section HC is located at node nd3 and node nd3r. It is not possible to maintain the same potential at each of them. Therefore, in circuit MP in Figure 20B This is expressed by maintaining the same potential at node nd3 and node nd3r, respectively. It is not possible to set the weight coefficient. Specifically, in the above example of operation, the transient Each of the transistors M3, M4, M3r, and M4r Because the back gate cannot maintain a low level potential, the weighting coefficient for circuit MP in Figure 20B is set to "0". It is not possible to set this.

[0327] <Configuration Example 5> In Configuration Examples 1 to 4, the weight coefficients held by the circuit MP are "+1", "-1", and "0 The three values ​​of " and the neuron signal corresponding to the potential input from wiring X1L and X2L are "+1 This section describes a circuit MP that can calculate the product of the three values ​​", "-1", and "0". However, in this example configuration, as an example, the weight coefficients are set to three values: "+1", "-1", and "0", and The circuit MP can calculate the product of the two values ​​"+1" and "0" of the euron signal. I will explain.

[0328] The circuit MP shown in Figure 21A is derived from the circuit MP in Figure 9A, with transistor M4 and transistor... This is the circuit with transistor M4r removed. Also, transistors M4 and M4r are removed. Therefore, in Figure 21A, the gates of transistor M4 and transistor M4r are shown. The wiring X2L for inputting potential is also excluded. Furthermore, the wiring corresponding to wiring X1L is, In Figure 21A, the wiring is labeled XL.

[0329] The weight coefficient set in circuit MP in Figure 21A is the high-level electric current at node nd3 of the holding part HC. The value is set to "+1" when a low-level potential is maintained at node nd3r of the holding part HCr. Low-level potential at node nd3 of the retaining part HC, and high-level potential at node nd3r of the retaining part HCr. If the potential is maintained, it is set to "-1", and a low-level potential is set at node nd3 of the holding part HC. This value is set to "0" when a low-level potential is maintained at node nd3r of the holding part HCr.

[0330] Furthermore, the neuron signal input to circuit MP in Figure 21A has a high-level potential in wiring XL. When a voltage is applied, it is set to "+1", and when a low-level potential is applied to wiring XL, Set it to "0".

[0331] For the operation of circuit MP in Figure 21, please refer to the explanation of the operation example in Configuration Example 1.

[0332] In the circuit MP shown in Figure 21, as described above, the weight coefficient and the input neuron signal When defined, for each weight coefficient, the neuron's signal is input to the circuit MP. As a result, the current I output from node outa of wiring OL OL Whether or not there has been a change , and the current I output from node outb of the wiring OLB OLB Whether or not there has been a change is as follows: The table shows the results. In the table below, high-level potentials are denoted as "high" and low-level potentials as "high". It is written as "low".

[0333] [Table 3]

[0334] As shown in the table above, the circuit MP in Figure 21A has three weight coefficients: "+1", "-1", and "0". Then, the product of the neuron's signal, which is either "+1" or "0", can be calculated. The weight coefficients do not have to be 3 values; they can be 2 values ​​or 3 or more values. For example, “+ It can also be a binary value of 1" or "0", or a binary value of "+1" or "-1". Alternatively, it can be a weighting coefficient. This can be an analog value or a multi-bit (multi-level) digital value.

[0335] In this example of operation, the holding parts HC and H of the circuit MC and MCR of the circuit MP are used. The potential held in Cr was set to either a high-level potential or a low-level potential, but the holding part HC and The holding part HCr may hold a potential that shows an analog value. For example, as a weighting coefficient, In the case of a positive analog value, a high level analog potential is applied to node nd3 of the holding unit HC. A low-level potential is maintained at node nd3r of the retaining HCr. A negative a is used as the weighting coefficient. In the case of "analog value", for example, a low-level potential is applied to node nd3 of the holding part HC, and the holding part HC A high level of analog potential is maintained at node nd3r of r. And current I OL Reach current I OLB The magnitude of the current will depend on the analog potential.

[0336] Furthermore, the circuit MP in Figure 21A can be modified depending on the situation. Figure 21A An example of a modified circuit MP is shown in Figure 21B. The circuit MP in Figure 21B is the same as the one in Figure 21A. The electrical connections between the gate and back gate of transistor M3 and transistor M3r are swapped. The configuration is such that the gate potentials of transistor M3 and transistor M3r are The structure is such that it is held by the holding part HC and the holding part HCr. In addition, the circuit MP is The configuration involves applying a potential from line XL to the back gates of transistors M3 and M3r. The potential supplied from wiring XL affects transistor M3, transistor M3 The configuration involves changing the threshold voltage of r to switch between the on and off states. ru.

[0337] Furthermore, in circuit MP in Figure 21B, the change in current flowing through wiring OL and wiring OLB is shown in Figure It can be considered similarly to circuit MP in 21A. Therefore, in circuit MP in Figure 21B The combination of potentials held at node nd3 and node nd3r, and the power supplied by wiring XL The current I output from node outa of wiring OL, determined by position and OL Change The presence or absence of the current I output from node outb of the wiring OLB. OLB Whether or not there is a change, The circuit MP in Figure 21A is explained in the table above.

[0338] Furthermore, as an example of modifying circuit MP in Figure 21A, the wiring IL and are similar to those of circuit MP in Figure 16A. Even if the wiring ILB is combined into a single wire, and the wiring WL is divided into wiring W1L and wiring W2L, Good. Such a circuit configuration is shown in Figure 22A. Circuit MP in Figure 22A is shown in Figure 6 as an example. This can be applied to the calculation circuit 120. Furthermore, regarding the operation method of circuit MP in Figure 22A... Therefore, refer to the description of the operation method of circuit MP in Figure 16A.

[0339] Furthermore, as an example of modifying circuit MP in Figure 22A, wiring XL is divided into wiring X1L and wiring X2L. This configuration is also acceptable. Such a circuit configuration is shown in Figure 22B. Wiring X1L, Wiring X2L Each shall be given either a high-level potential (Vg1) or a low-level potential (Vg2). Therefore, there are four possible combinations of potentials supplied by wiring X1L and wiring X2L. Also, the holding part H At nodes nd3 and nd3r of C and the holding part HCr, respectively, there is a high-level potential or low-level potential. Assuming that the level potential is maintained, the potentials held at nodes nd3 and nd3r are... There are four possible combinations.

[0340] Specifically, a high-level potential is maintained at node nd3, and a high-level potential (V) is maintained at wiring X1L. When g1) is applied, the connection between wiring OL and wiring VL becomes conductive, therefore wiring Current flowing through OL I OL This changes. Also, a high-level potential is maintained at node nd3r. When a high-level potential (Vg1) is applied to wiring X2L, wiring OLB and wiring VL Because a conductive state is created between r and the circuit, the amount of current I flowing through the OLB wiring OLB This changes. Figure 22 In circuit MP of B, the combination of potentials held at node nd3 and node nd3r The potential is determined by the combination of the potentials provided by wiring X1L and wiring X2L. Current I output from node outa of wiring OL OL Whether or not there has been a change, and the wiring OLB Current I output from outb OLB The presence or absence of changes is as shown in the table below. Oh, in the table below, high-level potentials are labeled "high" and low-level potentials are labeled "low". .

[0341] [Table 4]

[0342] In this example, the holding parts HC of circuit MP and circuit MCr are each... The potential held in the holding part HCr was set to either a high-level potential or a low-level potential, but the holding The HC section and the holding section HCr may hold potentials that represent analog values. For example, weighted In the case of a "positive analog value" as a number, a high level of analog is stored in node nd3 of the holding unit HC. A low-level potential is maintained at node nd3r of the holding part HCr. In the case of a "negative analog value," for example, a low-level potential is applied to node nd3 of the holding unit HC. A high level of analog potential is maintained at node nd3r of the holding part HCr. Flow I OL and current I OLB The magnitude of the current will depend on the analog potential.

[0343] This embodiment can be appropriately combined with other embodiments shown herein. ru.

[0344] (Embodiment 3) In this embodiment, the OS transistor applicable to the semiconductor device described in the above embodiment Let's explain an example of the configuration of the TA.

[0345] <Example of semiconductor device configuration> The semiconductor device shown in Figure 23 includes transistor 300, transistor 500, and a capacitive element. It has 600 and . Figure 25A is a cross-sectional view of transistor 500 in the channel length direction. Figure 25B is a cross-sectional view of transistor 500 in the channel width direction, and Figure 25C is a cross-sectional view of transistor 500. This is a cross-sectional view of the ZISTA 300 in the channel width direction.

[0346] Transistor 500 is a transistor (OS) having a metal oxide in the channel formation region. Transistor 500 has a small off-current, so it is used in semiconductor devices. In particular, transistors M3 and M4 of circuit MP included in the arithmetic circuit 110, By using it in transistors such as M8, it is possible to retain written data for a long period of time. This is possible. In other words, the refresh operation is infrequent, or the refresh operation is Since no operation is required, the power consumption of semiconductor devices can be reduced.

[0347] Transistor 500 is located above transistor 300, and capacitive element 600 is located above transistor 300. It is located above the zista 300 and transistor 500. Note that the capacitive element 600 These can be capacitive elements C3, C3r, etc., in the MP circuit.

[0348] The transistor 300 is mounted on the substrate 311 and consists of a conductor 316, an insulator 315, and the substrate A semiconductor region 313 consisting of part of 311, a low-level region that functions as a source region or drain region. It has a resistive region 314a and a low-resistance region 314b. Note that the transistor 300 is an example For example, it can be applied to the transistor in the above embodiment.

[0349] As shown in Figure 25C, transistor 300 is located on the upper surface and channel of semiconductor region 313. The sides in the width direction are covered by the conductor 316 via the insulator 315. In this way, By making the ZISTA 300 a Fin type, the effective channel width is increased. The ON characteristics of the transistor 300 can be improved. Also, the contribution of the electric field of the gate electrode. This allows for an increase in the off-peak characteristics of transistor 300. .

[0350] Note that transistor 300 can be either a p-channel or n-channel type. .

[0351] The region in which the channel of the semiconductor region 313 is formed, the region near it, the source region, or In the low-resistance region 314a and low-resistance region 314b, which are rain regions, silicon It is preferable that it contains semiconductors such as semiconductor systems, and it is preferable that it contains single-crystal silicon. These are Ge (germanium), SiGe (silicon germanium), and GaAs (gallium hydrogen). It may be formed from a material containing (aluminum arsenide), GaAlAs (gallium aluminum arsenide), etc. By applying stress to the crystal lattice and changing the lattice spacing, silicon with controlled effective mass is used. Alternatively, by using GaAs and GaAlAs, transistor 30 0 is HEMT (High Electron Mobility Transistor) ) is also acceptable.

[0352] Low-resistance regions 314a and 314b are semiconductor regions applied to semiconductor region 313. In addition to the main material, elements that impart n-type conductivity, such as arsenic and phosphorus, or p-type conductivity, such as boron. It contains elements that impart conductivity.

[0353] The conductor 316, which functions as a gate electrode, imparts n-type conductivity to arsenic, phosphorus, etc. Semiconductor materials such as silicon containing elements, or elements that impart p-type conductivity, such as boron. Conductive materials such as cellulose, metallic materials, alloy materials, or metal oxide materials can be used.

[0354] Furthermore, since the work function is determined by the material of the conductor, the material of the conductor must be selected accordingly. This allows you to adjust the threshold voltage of the transistor. Specifically, by using nitride in the conductor... It is preferable to use materials such as tan or tantalum nitride. Furthermore, both conductivity and embedding properties are desirable. To achieve this, metal materials such as tungsten and aluminum are used as laminates in the conductive material. This is preferable, and using tungsten is particularly preferable in terms of heat resistance.

[0355] Note that the transistor 300 shown in Figure 23 is just one example, and its structure is not limited to that example. Appropriate transistors should be used depending on the configuration and driving method. For example, a semiconductor device can use an OS transistor. When using a unipolar circuit consisting only of transistors, the configuration of transistor 300 is as shown in Figure 24. The configuration should be the same as that of transistor 500, which uses an oxide semiconductor. Details about the Transistor 500 will be described later.

[0356] The transistor 300 is covered by insulators 320, 322, 324, and The bodies 326 are arranged in a series of stacked units.

[0357] As insulators 320, 322, 324, and 326, for example, oxidative Silicon, silicon oxide nitride, silicon nitride, silicon nitride, aluminum oxide, acid Aluminum nitride, aluminum nitride oxide, aluminum nitride, etc., can be used.

[0358] In this specification, silicon oxidnitride refers to a material whose composition contains more oxygen than nitrogen. It refers to materials with a high content of nitrogen, and silicon nitride, in terms of its composition, contains more nitrogen than oxygen. This indicates a material with a high concentration of [amount]. Furthermore, in this specification, aluminum oxide nitride is defined as [component]. It refers to a material in which the oxygen content is higher than the nitrogen content, and aluminum nitride oxide is a combination of these materials. This refers to materials with a higher nitrogen content than oxygen content.

[0359] The insulator 322 provides a step created by the transistor 300 and the like located below it. It may also function as a planarizing film that flattens the surface. For example, the upper surface of the insulator 322 is To improve flatness, the surface is flattened using a planarization treatment such as chemical mechanical polishing (CMP). It's fine if you do that.

[0360] Furthermore, the insulator 324 receives the transistor from the substrate 311 or the transistor 300, etc. A barrier film is used in the region where the TA500 is provided to prevent the diffusion of hydrogen and impurities. It is preferable that they be present.

[0361] As an example of a film that has barrier properties against hydrogen, for example, silica nitride formed by CVD A semiconductor can be used. Here, a semiconductor having an oxide semiconductor such as transistor 500 can be used. The diffusion of hydrogen into the semiconductor element may degrade the characteristics of that semiconductor element. So, a film that suppresses hydrogen diffusion is placed between transistor 500 and transistor 300. It is preferable to use it. Specifically, a membrane that suppresses hydrogen diffusion is one in which the amount of hydrogen desorption is small. It will be called a membrane.

[0362] The amount of hydrogen desorption can be analyzed, for example, using a thermodynamic desorption gas analysis (TDS) method. Yes, it is possible. For example, the amount of hydrogen desorption from insulator 324 can be determined by TDS analysis when the film surface temperature is In the range of 50°C to 500°C, the amount of desorption converted to hydrogen atoms is the area of ​​the insulator 324. Converted to a single win, 10 x 10 15 atoms / cm 2 The following is preferably 5 × 10 15 a toms / cm 2 The following is acceptable.

[0363] Furthermore, it is preferable that the dielectric constant of the insulator 326 is lower than that of the insulator 324. For example, The relative permittivity of the edge material 326 is preferably less than 4, and more preferably less than 3. Also, for example, an insulator... The relative permittivity of 326 is preferably 0.7 times or less, and preferably 0.6 times or less, than the relative permittivity of the insulator 324. This is more preferable. By using a material with a low dielectric constant as the interlayer film, the parasitic capacitance that occurs between the wiring is reduced. It can be reduced.

[0364] Furthermore, insulators 320, 322, 324, and 326 contain capacitive elements 6 A conductor 328 and a conductor 330, etc., which are connected to transistor 500, are embedded. Furthermore, conductors 328 and 330 have the function of a plug or wiring. Furthermore, a conductor that functions as a plug or wiring may combine multiple structures into a single unit. The symbol may be assigned. Also, in this specification, etc., wiring and plastics that connect to the wiring The and may be a single unit. That is, when a part of the conductor functions as wiring, and In some cases, a portion of the conductive material may function as a plug.

[0365] The materials for each plug and wiring (conductor 328, conductor 330, etc.) are metal materials, composite materials, etc. Conductive materials such as gold, metal nitride, or metal oxide are used in a single layer or in a laminated form. It is possible to have both heat resistance and conductivity with high melting point materials such as tungsten and molybdenum. It is preferable to use a material, and it is preferable to use tungsten. Alternatively, aluminum. It is preferable to form it with a low-resistance conductive material such as copper. This can reduce wiring resistance.

[0366] A wiring layer may be provided on the insulator 326 and the conductor 330. For example, as shown in Figure 23 Insulators 350, 352, and 354 are arranged in a sequential stack. Furthermore, a conductor 356 is formed on insulators 350, 352, and 354. The conductor 356 functions as a plug or wiring to connect to the transistor 300. The conductor 356 is provided using the same material as the conductors 328 and 330. It is possible.

[0367] Furthermore, for example, insulator 350 has a barrier property against hydrogen, similar to insulator 324. It is preferable to use an insulator. Furthermore, the conductor 356 has barrier properties against hydrogen. It is preferable to include a conductor. In particular, it is preferable to include an insulator 350 that has barrier properties against hydrogen. A conductor having a barrier property against hydrogen is formed in the opening. With this configuration, The transistor 300 and the transistor 500 can be separated by a barrier layer. This can suppress the diffusion of hydrogen from transistor 300 to transistor 500.

[0368] For example, tantalum nitride can be used as a conductor that has barrier properties against hydrogen. It would be good to do so. Also, by laminating tantalum nitride and highly conductive tungsten, the wiring can be made It is possible to suppress the diffusion of hydrogen from transistor 300 while maintaining conductivity. In this case, the tantalum nitride layer having barrier properties against hydrogen has barrier properties against hydrogen It is preferable that the structure is in contact with an insulator 350 having the following properties.

[0369] A wiring layer may be provided on the insulator 354 and the conductor 356. For example, as shown in Figure 23 Insulators 360, 362, and 364 are arranged in a sequential stack. Furthermore, a conductor 366 is formed on insulators 360, 362, and 364. Conductor 366 has the function of a plug or wiring. It can be provided using the same material as body 328 and conductor 330.

[0370] Furthermore, for example, insulator 360 has a barrier property against hydrogen, similar to insulator 324. It is preferable to use an insulator. Furthermore, the conductor 366 has barrier properties against hydrogen. It is preferable to include a conductor. In particular, an insulator 360 having barrier properties against hydrogen is preferable. A conductor having a barrier property against hydrogen is formed in the opening. With this configuration, The transistor 300 and the transistor 500 can be separated by a barrier layer. This can suppress the diffusion of hydrogen from transistor 300 to transistor 500.

[0371] A wiring layer may be provided on the insulator 364 and the conductor 366. For example, as shown in Figure 23 Insulators 370, 372, and 374 are arranged in a sequential stack. Furthermore, a conductor 376 is formed on insulators 370, 372, and 374. The conductor 376 functions as a plug or wiring. It can be provided using the same material as body 328 and conductor 330.

[0372] Furthermore, for example, insulator 370, like insulator 324, has barrier properties against hydrogen. It is preferable to use an insulator. Furthermore, the conductor 376 has barrier properties against hydrogen. It is preferable to include a conductor. In particular, an insulator 370 having barrier properties against hydrogen is preferable. A conductor having a barrier property against hydrogen is formed in the opening. With this configuration, The transistor 300 and the transistor 500 can be separated by a barrier layer. This can suppress the diffusion of hydrogen from transistor 300 to transistor 500.

[0373] A wiring layer may be provided on the insulator 374 and the conductor 376. For example, as shown in Figure 23 Insulators 380, 382, ​​and 384 are arranged in a sequential stack. Furthermore, a conductor 386 is formed on insulators 380, 382, ​​and 384. Conductor 386 functions as a plug or wiring. It can be provided using the same material as body 328 and conductor 330.

[0374] For example, insulator 380, like insulator 324, has barrier properties against hydrogen. It is preferable to use an insulator. Furthermore, the conductor 386 has barrier properties against hydrogen. It is preferable to include a conductor. In particular, an insulator 380 having barrier properties against hydrogen is preferable. A conductor having a barrier property against hydrogen is formed in the opening. With this configuration, The transistor 300 and the transistor 500 can be separated by a barrier layer. This can suppress the diffusion of hydrogen from transistor 300 to transistor 500.

[0375] In the above, a wiring layer containing a conductor 356, a wiring layer containing a conductor 366, and a conductor 376 A wiring layer including and a wiring layer including the conductor 386 have been described, but this embodiment is not applicable. The semiconductor device is not limited to this. A wiring layer similar to a wiring layer containing conductor 356 The number of layers may be three or less, or the wiring layers similar to the wiring layer containing the conductor 356 may be made five or more layers. That's good too.

[0376] Insulator 384 has insulators 510, 512, 514, and 516. They are arranged in a stack in order. Insulator 510, insulator 512, insulator 514, and insulation It is preferable that one of the components 516 is a material that has barrier properties against oxygen and hydrogen. .

[0377] For example, the insulator 510 and the insulator 514 are, for example, a substrate 311 or a transistor Hydrogen and impurities spread from the area where transistor 300 is installed to the area where transistor 500 is installed. It is preferable to use a film that has barrier properties to prevent dispersion. Therefore, insulator 324 Similar materials can be used.

[0378] As an example of a film with hydrogen barrier properties, silicon nitride formed by CVD is used. It is possible to have a semiconductor device having an oxide semiconductor such as transistor 500. Furthermore, hydrogen diffusion can degrade the properties of the semiconductor device. Therefore, A film that suppresses hydrogen diffusion is used between the transistor 500 and the transistor 300. This is preferable. Specifically, a membrane that suppresses hydrogen diffusion is a membrane that has a low rate of hydrogen desorption. ru.

[0379] Furthermore, as films having barrier properties against hydrogen, for example, insulator 510 and insulator 5 14 uses metal oxides such as aluminum oxide, hafnium oxide, and tantalum oxide. It is preferable.

[0380] In particular, aluminum oxide is a source of oxygen and hydrogen, which can cause variations in the electrical properties of transistors. It has a high barrier effect that prevents both water and other impurities from passing through the film. Aluminum oxide is susceptible to hydrogen, moisture, and other impurities during and after the transistor manufacturing process. This prevents contamination of the transistor 500 with pure material. This can suppress the release of oxygen from the oxides that make up the transistor 5. It is suitable for use as a protective film for 00.

[0381] Furthermore, for example, the same material as the insulator 320 is used for insulators 512 and 516. It is possible to do so by applying materials with relatively low dielectric constants to these insulators. This can reduce parasitic capacitance between wirings. For example, insulator 512 and insulator For 516, silicon oxide films or silicon oxide nitride films can be used.

[0382] Furthermore, insulators 510, 512, 514, and 516 contain a conductive material 5 18, and a conductor (for example, conductor 503) that constitutes the transistor 500 is embedded. The conductor 518 is connected to the capacitive element 600 or the transistor 300. It functions as a plug or wiring. Conductor 518 is connected to conductor 328 and conductor 3 It can be provided using the same materials as in 30.

[0383] In particular, the conductor 518 in the region in contact with the insulator 510 and the insulator 514 is oxygen, hydrogen, And preferably it is a conductor that has barrier properties against water. With this configuration, The ZISTA 300 and Transistor 500 have barrier properties against oxygen, hydrogen, and water. The layers can be separated, and hydrogen can be diffused from transistor 300 to transistor 500. It can be suppressed.

[0384] A transistor 500 is provided above the insulator 516.

[0385] As shown in Figures 25A and 25B, the transistor 500 is an insulator 514 and an insulating A conductor 503 is arranged to be embedded in the body 516, and the insulator 516 and the conductor 50 An insulator 520 placed on top of 3, an insulator 522 placed on top of insulator 520, and An insulator 524 placed on the edge 522, and an oxide 53 placed on the insulator 524 0a, oxide 530b placed on oxide 530a, and on oxide 530b, Conductors 542a and 542b are positioned separately, and conductor 542a and conductor 54 An insulating layer is placed on 2b and superimposed between the conductor 542a and the conductor 542b, with an opening formed therein. The edge 580, the oxide 530c arranged on the bottom and sides of the opening, and the shape of the oxide 530c An insulator 550 arranged on the forming surface, and a conductor 560 arranged on the forming surface of the insulator 550, It holds.

[0386] Furthermore, as shown in Figures 25A and 25B, oxide 530a, oxide 530b, and conductive An insulator 544 is placed between the body 542a and the conductor 542b and the insulator 580. This is preferable. Also, as shown in Figures 25A and 25B, the conductor 560 is an insulator 5 A conductor 560a is provided inside 50, and is embedded inside the conductor 560a It is preferable to have a conductor 560b provided. Also, see Figures 25A and 25B. As shown, an insulator 574 is placed on top of an insulator 580, a conductor 560, and an insulator 550. It is preferable that it be placed there.

[0387] In the following, oxides 530a, 530b, and 530c are summarized. It is sometimes referred to as oxide 530.

[0388] Furthermore, in transistor 500, in the region where the channel is formed and in its vicinity, acid The following describes a configuration in which three layers of oxide 530a, oxide 530b, and oxide 530c are laminated. However, the present invention is not limited thereto. For example, a single layer of oxide 530b, oxidation Two-layer structure of substance 530b and oxide 530a, two-layer structure of oxide 530b and oxide 530c, Alternatively, a configuration with a stacked structure of four or more layers may be used. In addition, in transistor 500, Although the electric body 560 is shown as a two-layer laminated structure, the present invention is not limited thereto. For example, the conductor 560 may have a single-layer structure or a multilayer structure of three or more layers. Good. Also, the transistor 500 shown in Figures 23 and 25A is just one example, and its structure is not limited to that. It is not necessary to use a specific transistor; instead, an appropriate transistor should be used depending on the circuit configuration and driving method.

[0389] Here, the conductor 560 functions as the gate electrode of the transistor, and the conductor 542a and The conductor 542b functions as either a source electrode or a drain electrode, respectively. Furthermore, the conductor 560 is sandwiched between the opening of the insulator 580 and the conductors 542a and 542b. It is formed to be embedded in the region. Conductor 560, Conductor 542a and Conductor 5 The placement of 42b is self-aligned with the opening of the insulator 580. In the inverter 500, the gate electrode is positioned between the source electrode and the drain electrode in a self-aligned manner. It can be positioned in this way. Therefore, the conductor 560 can be positioned with a margin. Since it can be formed without any issues, the occupied area of ​​transistor 500 can be reduced. This makes it possible to miniaturize and highly integrate semiconductor devices.

[0390] Furthermore, the conductor 560 is self-aligned in the region between conductor 542a and conductor 542b. As a result, the conductor 560 has a region that overlaps with the conductor 542a or the conductor 542b. It does not have. As a result, between the conductor 560 and the conductors 542a and 542b The parasitic capacitance can be reduced. Therefore, the switching speed of transistor 500 This improves the degree of performance and allows for high frequency characteristics.

[0391] The conductor 560 may function as the first gate (also called the top gate) electrode. Furthermore, the conductor 503 functions as a second gate (also called a bottom gate) electrode. There are cases where this is the case. In that case, the potential applied to conductor 503 is the same as the potential applied to conductor 560. By changing them independently and without linking them, the threshold voltage of transistor 500 is controlled. This can be achieved by applying a negative potential to the conductor 503, which allows the transistor 5 It becomes possible to increase the threshold voltage of 00 to greater than 0V and reduce the off-current. However, Therefore, applying a negative potential to conductor 503 is better than not applying a negative potential to conductor 560 The drain current can be reduced when the applied potential is 0V.

[0392] The conductor 503 is arranged so as to overlap with the oxide 530 and the conductor 560. Therefore, when a potential is applied to the conductor 560 and the conductor 503, the conductor 560 generates The electric field and the electric field generated from the conductor 503 connect, and channels are formed in the oxide 530. It can cover the gel-forming region. In this specification, the first gate electrode and the second gate The electric field of the electrode electrically surrounds the channel formation region, creating a transistor structure. This is called a surrounded channel (S-channel) structure.

[0393] Furthermore, the conductor 503 has the same configuration as the conductor 518, and the insulators 514 and 5 A conductor 503a is formed in contact with the inner wall of the 16 openings, and a conductor 503b is formed further inside. This has been done. In addition, in transistor 500, conductors 503a and 503b are combined. Although the present invention describes a layered configuration, it is not limited thereto. For example, conductive Body 503 may be a single layer or a laminated structure of three or more layers.

[0394] Here, the conductor 503a diffuses impurities such as hydrogen atoms, hydrogen molecules, water molecules, and copper atoms. It is preferable to use a conductive material that has the function of suppressing (the above-mentioned impurities are less likely to permeate) It is difficult. Or, it inhibits the diffusion of oxygen (for example, at least one such as an oxygen atom or oxygen molecule). It is preferable to use a conductive material that has a functional property (i.e., one that is impermeable to the above-mentioned oxygen). In this specification, the function of suppressing the diffusion of impurities or oxygen means the above impurities or the above The function is to suppress the diffusion of one or all of the oxygen molecules.

[0395] For example, the conductor 503a has the function of suppressing the diffusion of oxygen, This can suppress the oxidation of b, which reduces its conductivity.

[0396] Furthermore, if the conductor 503 also functions as wiring, the conductor 503b may be tungsten or copper. Alternatively, it is preferable to use a highly conductive material, mainly composed of aluminum. In that case, the conductor 505 does not necessarily have to be provided. Note that the conductor 503b is a single layer. As shown in the illustration, a laminated structure is also possible, for example, titanium or titanium nitride and the above conductive material It may also be a stacked structure.

[0397] Insulators 520, 522, and 524 function as a second gate insulating film. It holds.

[0398] Here, the insulator 524 in contact with the oxide 530 is more abundant than the oxygen that satisfies the stoichiometric composition. It is preferable to use an insulator containing a certain amount of oxygen. In other words, the insulator 524 contains an excess oxygen region. It is preferable that a region is formed. Such an insulator containing excess oxygen is converted to oxide 530. By providing them in contact, oxygen deficiencies in the oxide 530 are reduced, and the signal strength of the transistor 500 is improved. It can improve reliability.

[0399] As an insulator having an excess oxygen region, specifically, an acid in which some of the oxygen is removed by heating. It is preferable to use an oxide material. Oxides that desorb oxygen upon heating include TDS(Th In urinary desorption spectroscopy analysis, oxygen atoms were found to The amount of oxygen removed after conversion is 1.0 × 10⁻⁶ 18 atoms / cm 3 Preferably 1.0 ×10 19 atoms / cm 3 More preferably 2.0 × 10 19 ate / c m 3 Above, or 3.0 × 10 20 atoms / cm 3 The above describes the oxide film. The surface temperature of the film during the above TDS analysis is between 100°C and 700°C, or 100°C. A temperature range of ℃ to 400℃ is preferred.

[0400] Furthermore, the insulator having the excess oxygen region and the oxide 530 are in contact and subjected to heat treatment. The process may be one or more of the following: microwave processing or RF processing. By performing this process, water or hydrogen can be removed from oxide 530. For example, In oxide 530, the VoH bond is broken in a reaction, or in other words, "V O H→V O +H The following reaction occurs, allowing for dehydrogenation. Some of the hydrogen produced at this time is acid It combines with an element to form H2O, and is removed from oxide 530 or the insulator near oxide 530. In some cases, this may occur. Also, some of the hydrogen may diffuse into conductors 542a and 542b. They may be captured (also known as gettering).

[0401] Furthermore, the above microwave processing is performed using, for example, an apparatus having a power supply that generates high-density plasma. Alternatively, it is preferable to use a device that has a power supply that applies RF to the substrate side. For example, acid By using a gas containing elements and employing a high-density plasma, high-density oxygen radicals are generated. This can be achieved by applying RF to the substrate side, generating high-density plasma. Efficiently introduce oxygen radicals into oxide 530 or an insulator near oxide 530. This can be done. Furthermore, the above microwave treatment is performed at a pressure of 133 Pa or higher, preferably 200 Pa. The Pa should be Pa or higher, more preferably 400 Pa or higher. For example, oxygen and argon are used as gases introduced into the apparatus, with an oxygen flow rate ratio (O2 The process should be carried out with (O2+Ar) content of 50% or less, preferably between 10% and 30%.

[0402] Furthermore, during the manufacturing process of transistor 500, the surface of oxide 530 is exposed. Therefore, heat treatment is preferable. This heat treatment is, for example, 100°C to 450°C. Preferably, the heat treatment should be carried out at a temperature of 350°C to 400°C. Furthermore, the heat treatment may be carried out using nitrogen gas. Or an inert gas atmosphere, or an oxidizing gas at 10 ppm or more, 1% or more, or 10 The procedure should be carried out in an atmosphere containing % or more of the substance. For example, heat treatment is preferably carried out in an oxygen atmosphere. Therefore, oxygen is supplied to oxide 530, and oxygen deficiency (V O This can help reduce ) Alternatively, the heat treatment may be carried out under reduced pressure. Or, the heat treatment may be carried out using nitrogen gas or an inert gas. After heat treatment in a gaseous atmosphere, an oxidizing gas is added at 10 ppm to replenish the desorbed oxygen. The above may be carried out in an atmosphere containing 1% or more, or 10% or more. Alternatively, an oxidizing gas may be used. After heat treatment in an atmosphere containing 0 ppm or more, 1% or more, or 10% or more, continuous nitrogen treatment Heat treatment may be carried out in an atmosphere of a primary gas or inert gas.

[0403] Furthermore, by performing an oxygenation treatment on oxide 530, the oxygen deficiencies in oxide 530 are supplied. A reaction that repairs using oxygen, in other words, "V O Promotes the reaction "+O → null". It can be made to react with the oxygen supplied to the hydrogen remaining in oxide 530. By doing so, the hydrogen can be removed as H2O (dehydrated). The hydrogen remaining in oxide 530 recombines with the oxygen vacancy and V O Suppression of H formation It is possible.

[0404] Furthermore, if the insulator 524 has an excess oxygen region, the insulator 522 will have oxygen (for example, It has the function of suppressing the diffusion of oxygen atoms, oxygen molecules, etc. (making it difficult for the above-mentioned oxygen to permeate). This is preferable.

[0405] The insulator 522 has the function of suppressing the diffusion of oxygen and impurities, so the oxide 530 The oxygen present does not diffuse towards the insulator 520, which is preferable. Also, the conductor 503 This suppresses the reaction between the insulator 524 and the oxygen present in the oxide 530.

[0406] The insulator 522 is, for example, aluminum oxide, hafnium oxide, aluminum and haf Oxides containing nium (hafnium aluminate), tantalum oxide, zirconium oxide, Lead zirconate tane (PZT), strontium titanate (SrTiO3), or (Ba Insulators containing so-called high-k materials such as Sr)TiO3(BST) are used in single layers or multi-layered insulators. It is preferable to use it in layers. As transistors become smaller and more integrated, gate insulation Thinning the film can sometimes lead to problems such as leakage current. By using a high-k material as the insulator, the physical film thickness is maintained while the transistor movement This allows for a reduction in the gate potential during operation.

[0407] In particular, it has the function of suppressing the diffusion of impurities and oxygen (the above oxygen is less permeable). Using an insulator containing an oxide of either aluminum or hafnium, or both, which are insulating materials. It would be good to have one. As an insulator containing an oxide of aluminum, hafnium, or both, acid Aluminum oxide, hafnium oxide, aluminum and hafnium oxide (hafnium It is preferable to use materials such as aluminum oxide. When formed, the insulator 522 prevents the release of oxygen from the oxide 530 and the transistor 500 It functions as a layer that suppresses the incorporation of impurities such as hydrogen from the peripheral area into the oxide 530.

[0408] Alternatively, these insulators may contain, for example, aluminum oxide, bismuth oxide, or germanium oxide. M, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, acid Zirconium oxide may be added. Alternatively, these insulators may be nitrided. Silicon oxide, silicon oxide nitride, or silicon nitride may be laminated onto the edge body.

[0409] Furthermore, it is preferable that the insulator 520 is thermally stable. For example, silicon oxide and Silicon oxide nitride is suitable because it is thermally stable. Also, high-k material By combining an insulator with silicon oxide or silicon oxide-nitride, thermal stability can be achieved. This makes it possible to obtain an insulator 520 with a multilayer structure and a high relative permittivity.

[0410] Note that the transistor 500 in Figures 25A and 25B has a three-layer stacked structure. Insulators 520, 522, and 524 are shown as gate insulating films of 2. However, the second gate insulating film may have a single layer, two layers, or a stacked structure of four or more layers. In that case, it is not limited to a laminated structure made of the same material, but is also possible with a laminated structure made of different materials. That's good too.

[0411] Transistor 500 is an oxide semiconductor in oxide 530 including a channel formation region. It is preferable to use a functional metal oxide. For example, as oxide 530, In-M- Zn oxide (element M is aluminum, gallium, yttrium, copper, vanadium, beryllium) Rium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, ra Tantum, cerium, neodymium, hafnium, tantalum, tungsten, or magnesium It is preferable to use one or more metal oxides selected from the above. In particular, oxide 53 The In-M-Zn oxide that can be applied as 0 is CAAC-OS, as described in Embodiment 4. It is preferable that it be CAC-OS. Also, as oxide 530, In-Ga oxide, I n-Zn oxide may also be used.

[0412] Furthermore, it is preferable to use a metal oxide with a low carrier concentration for transistor 500. i. When lowering the carrier concentration of metal oxides, the impurity concentration in the metal oxides should be reduced. The defect level density should be lowered. In this specification, the impurity concentration is low and the defect level density is low. A low level density is referred to as high-purity intrinsic or substantially high-purity intrinsic. Examples of impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, and nickel. Examples include silicone, etc.

[0413] In particular, the hydrogen contained in metal oxides reacts with the oxygen bonded to the metal atoms to form water. In some cases, oxygen vacancies may form in metal oxides. Also, water can form oxygen vacancies in oxide 530. When an element is present, the oxygen deficiency and hydrogen combine to form V O It may form H. O H is Donna It functions as a metal, and electrons, which are carriers, can be generated. Also, some of the hydrogen is metallic. It can combine with oxygen atoms to generate electrons, which are carriers. Therefore, water Transistors using metal oxides that contain many elements exhibit normally-on characteristics. Furthermore, hydrogen in metal oxides is easily moved by stresses such as heat and electric fields. If metal oxides contain a large amount of hydrogen, the reliability of transistors may deteriorate. In one embodiment of the invention, V in oxide 530 O To reduce H as much as possible, and to produce high-purity intrinsic It is preferable to make it substantially high-purity intrinsic. Thus, V O Metals with sufficiently reduced H To obtain an oxide, impurities such as water and hydrogen must be removed from the metal oxide (dehydration, dehydration). This is sometimes referred to as chemical treatment.) This involves supplying oxygen to the metal oxide to compensate for oxygen deficiencies. This (sometimes referred to as oxygenation treatment) is important. V O Sufficient impurities such as H By using metal oxides with reduced levels in the channel formation region of transistors, stable electricity can be produced. It is possible to impart specific properties.

[0414] Defects where hydrogen is present in an oxygen vacancy can function as donors for metal oxides. However, Therefore, it is difficult to quantitatively evaluate the defect. In metal oxides, - In some cases, evaluation is based on carrier concentration rather than concentration. Therefore, in this specification, etc., metal The parameter for the oxide is not the donor concentration, but rather the value assuming a state where no electric field is applied. Carrier concentration may be used. In other words, the "carrier concentration" described in this specification, etc., is "d It can sometimes be rephrased as "ener concentration."

[0415] Therefore, when using metal oxides in oxide 530, the amount of hydrogen in the metal oxide should be kept as low as possible. It is preferable that the amount is reduced. Specifically, in metal oxides, secondary ion mass spectrometry (SIMS: Secondary Ion Mass Spectrometry) The hydrogen concentration obtained is 1 × 10⁻⁶ 20 atoms / cm 3 Less than 1 × 10 19 atoms / cm 3 Less than 5x10 18 atoms / cm 3 Less than, further Preferably 1 × 10 18 atoms / cm 3 Less than. Sufficiently reduced impurities such as hydrogen. By using the metal oxide in the channel formation region of the transistor, stable electrical characteristics are achieved. It can be granted.

[0416] Furthermore, when a metal oxide is used for oxide 530, the channel formation region of the metal oxide The rear concentration is 1 x 10 18 cm -3 The following is preferable: 1 × 10 17 cm -3 Not yet It is more preferable that it be full, 1 × 10 16 cm -3 It is even more preferable that it be less than, 1 x 10 13 cm -3 It is even more preferable that it be less than 1 × 10 12 cm -3 Less than It is even more preferable that the lower limit of the carrier concentration of the metal oxide in the channel-forming region There are no particular limitations regarding this, but for example, 1 x 10 -9 cm -3 It can be done this way.

[0417] Furthermore, when a metal oxide is used for oxide 530, conductors 542a and 542b are When oxide 530 comes into contact with the conductor 542a and conductor 54 It may diffuse into 2b, causing oxidation of conductors 542a and 542b. Conductor 542 As a and conductor 542b oxidize, the conductivity of conductors 542a and 542b There is a high probability that it will decrease. Furthermore, the oxygen in oxide 530 is conductor 542a and conductor 542 The diffusion to b is due to conductors 542a and 542b absorbing oxygen in the oxide 530. This can be rephrased as "to do."

[0418] Furthermore, oxygen in oxide 530 diffuses into conductors 542a and 542b, Between the conductor 542a and the oxide 530b, and between the conductor 542b and the oxide 530b A different layer may be formed between the conductors 542a and 542b. Since it also contains a large amount of oxygen, it is presumed that this different layer has insulating properties. At this time, conductor 54 The three-layer structure of 2a or conductor 542b, the heterogeneous layer, and oxide 530b is a metal-insulator. -It can be considered a three-layer structure made of semiconductors, MIS (Metal-Insulator A diode that primarily uses an r-semiconductor (MIS) structure. It is sometimes called a joint structure.

[0419] The above-mentioned heterogeneous layer is formed between the conductor 542a and conductor 542b and the oxide 530b. It is not limited to this, for example, the different layers are conductor 542a and conductor 542b and oxide 5 When formed between 30c, or between conductor 542a and conductor 542b and oxide 530b In the case where a conductor 542a and conductor 542b are formed between the conductor and the oxide 530c, be.

[0420] In oxide 530, the metal oxide that functions as a channel-forming region is the band gap It is preferable to use one with a voltage of 2 eV or higher, preferably 2.5 eV or higher. By using metal oxides with a large bandgap, the off-current of the transistor can be reduced. It is possible.

[0421] Oxide 530 has oxide 530a beneath oxide 530b, so oxide 530a The diffusion of impurities from structures formed below to oxide 530b can be suppressed. Yes, it is possible. Also, by having oxide 530c on oxide 530b, oxide 530c is more Furthermore, the diffusion of impurities from the structure formed above to the oxide 530b can be suppressed. ru.

[0422] Furthermore, oxide 530 has a layered structure due to oxides with different atomic ratios of each metal atom. It is preferable that the metal oxide used in oxide 530a contains constituent elements The atomic ratio of element M in the oxide is the element of the constituent elements in the metal oxide used in oxide 530b. It is preferable that the ratio is greater than the atomic ratio of element M. Also, the metal oxide used in oxide 530a In this case, the atomic ratio of element M to In is in the metal oxide used in oxide 530b. Furthermore, it is preferable that the atomic ratio of element M to In is greater than that of In. Also, in oxide 530b In the metal oxide used, the atomic ratio of In to element M is used in oxide 530a. It is preferable that the atomic ratio of In to element M in the metal oxide is greater than that of In. Oxide 530c is a metal oxide that can be used in the case of oxide 530a or oxide 530b. It can be used.

[0423] Furthermore, the energy at the lower end of the conduction band of oxide 530a and oxide 530c is It is preferable that the energy of b is higher than the energy of the lower end of the conduction band. In other words, oxide The electron affinity of oxide 530a and oxide 530c is smaller than the electron affinity of oxide 530b. This is preferable.

[0424] Here, at the joint of oxide 530a, oxide 530b, and oxide 530c, The energy levels at the lower end of the guide band change smoothly. In other words, oxide 530a, oxide The energy levels at the lower end of the conduction band at the junction of 530b and oxide 530c are continuous. It can also be said that it changes or becomes a continuous bond. In order to do this, oxide 530 At the interface between a and oxide 530b, and at the interface between oxide 530b and oxide 530c, the shape It is desirable to lower the defect level density of the resulting mixed layer.

[0425] Specifically, oxide 530a and oxide 530b, and oxide 530b and oxide 530c, By having a common element other than oxygen (as the main component), a mixed layer with a low defect level density is formed. It can be done. For example, if oxide 530b is In-Ga-Zn oxide, 530a and oxide 530c are In-Ga-Zn oxide, Ga-Zn oxide, and oxide Using gallium or similar materials would be a good idea.

[0426] In this case, the main carrier pathway is oxide 530b. Oxide 530a, oxide 5 By configuring 30c as described above, the interface between oxide 530a and oxide 530b, and oxidation The defect level density at the interface between material 530b and oxide 530c can be reduced. Therefore, the influence of interfacial scattering on carrier conduction is reduced, and transistor 500 has high On-current can be obtained.

[0427] On the oxide 530b, there is a conductor 542a that functions as a source electrode and a drain electrode. , and a conductor 542b are provided. The conductors 542a and 542b are, Aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tar ngsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium Choose from beryllium, indium, ruthenium, iridium, strontium, and lanthanum. The identified metal element, or an alloy containing the above-mentioned metal element, or a combination of the above-mentioned metal elements It is preferable to use a blended alloy, such as tantalum nitride, titanium nitride, or tungsten. Titanium nitrides containing titanium and aluminum, tantalum nitrides containing tantalum and aluminum, oxides Thenium, ruthenium nitride, oxides containing strontium and ruthenium, lanthanum and nickel It is preferable to use oxides containing Kel. Also, tantalum nitride, titanium nitride, titan Nitrides containing aluminum, nitrides containing tantalum and aluminum, ruthenium oxide , ruthenium nitride, oxides containing strontium and ruthenium, lanthanum and nickel Oxides are conductive materials that are resistant to oxidation, or materials that maintain their conductivity even when absorbing oxygen. Therefore, it is preferable. Furthermore, metal nitride films such as tantalum nitride are suitable for hydrogen or oxygen. It is preferable because it has barrier properties.

[0428] Furthermore, in Figures 25A and 25B, the conductors 542a and 542b are shown as a single-layer structure. As shown above, a laminated structure of two or more layers is also possible. For example, a tantalum nitride film and tungsten film. It is good to laminate the film. Alternatively, a titanium film and an aluminum film may be laminated. A two-layer structure consisting of an aluminum film laminated on a gusten film, and a copper-magnesium-aluminum alloy. A two-layer structure with a copper film laminated on a gold film, a two-layer structure with a copper film laminated on a titanium film, tungsten A two-layer structure in which a copper film is laminated on top of the film may also be used.

[0429] Furthermore, a titanium film or titanium nitride film, and aluminum layered on top of the titanium film or titanium nitride film. A three-layer structure consisting of a laminated titanium film or copper film, with a titanium film or titanium nitride film formed on top of it. A molybdenum film or molybdenum nitride film, and on the molybdenum film or molybdenum nitride film An aluminum film or copper film is laminated on top of it, and then a molybdenum film or molybdenum nitride film is placed on top of that. There are three-layer structures that form a film. Furthermore, there are permeable films containing indium oxide, tin oxide, or zinc oxide. A brightly conductive material may be used.

[0430] Furthermore, as shown in Figure 25A, the oxide 530 has conductor 542a (conductor 542b) and Regions 543a and 543b are formed at and near the interface as low-resistance regions. In some cases, region 543a functions as either the source region or the drain region. Furthermore, region 543b functions as either the source region or the drain region. Also, region 54 A channel-forming region is formed in the area sandwiched between region 3a and region 543b.

[0431] By providing the conductor 542a (conductor 542b) in contact with the oxide 530, The oxygen concentration in region 543a (region 543b) may decrease. Also, region 543a ( In region 543b), the metal contained in conductor 542a (conductor 542b) and oxide 530 A metal compound layer containing the component may be formed. In such cases, region 543a (region The carrier density in region 543b increases, and region 543a (region 543b) becomes a low-resistance region. Yes.

[0432] The insulator 544 is provided so as to cover the conductors 542a and 542b, and the conductor The oxidation of 542a and conductor 542b is suppressed. At this time, the insulator 544 is oxide 5 It may be provided to cover the side of 30 and to be in contact with the insulator 524.

[0433] Insulator 544 includes hafnium, aluminum, gallium, yttrium, and zirconium. Umium, tungsten, titanium, tantalum, nickel, germanium, neodymium, lanthanum Alternatively, a metal oxide containing one or more metals selected from magnesium, etc., can be used. This is possible. Furthermore, silicon nitride or silicon nitride can also be used as the insulator 544. It is possible to be there.

[0434] In particular, as the insulator 544, an oxide of either aluminum or hafnium, or both. The insulators include aluminum oxide, hafnium oxide, aluminum, and hafnium. It is preferable to use an oxide containing (hafnium aluminate), etc. In particular, hafnium Mualuminate has higher heat resistance than hafnium oxide film. Therefore, heat in subsequent processes In processing, it is preferable because it is less likely to crystallize. Note that conductor 542a and conductor 542 If b is an oxidation-resistant material, or if its conductivity does not significantly decrease even when it absorbs oxygen, then The 544 element is not a mandatory component. It can be designed appropriately depending on the desired transistor characteristics. stomach.

[0435] The presence of the insulator 544 allows water and other impurities such as hydrogen contained in the insulator 580 to be acidic. The diffusion of oxide 530c to oxide 530b via insulator 550 is suppressed. Yes, it is possible. Furthermore, the excess oxygen in the insulator 580 suppresses the oxidation of the conductor 560. It is possible.

[0436] The insulator 550 functions as the first gate insulating film. The insulator 550 is made of oxide 530 It is preferable to place it in contact with the inside (top surface and side surface) of c. The insulator 550 is as described above. Similar to insulator 524, an insulator that contains an excess of oxygen and releases oxygen upon heating It is preferable to use this method to form the product.

[0437] Specifically, silicon oxide, silicon oxide nitride, silicon nitride oxide, silicon oxide containing excess oxygen silicon nitride, silicon oxide with added fluorine, silicon oxide with added carbon, carbon, and Silicon oxide with added nitrogen and silicon oxide with voids can be used. Silicon oxide and silicon oxide-nitride are preferred because they are stable to heat.

[0438] An insulator that releases oxygen upon heating is designated as insulator 550, and the oxide 530c is placed on its upper surface. By being installed in contact with each other, the oxide 530b is transmitted from the insulator 550 through the oxide 530c. This allows for effective oxygen supply to the channel formation region. Also, similar to insulator 524. Preferably, the concentration of impurities such as water or hydrogen in the insulator 550 is reduced. The thickness of the edge body 550 is preferably between 1 nm and 20 nm.

[0439] Furthermore, in order to efficiently supply excess oxygen from the insulator 550 to the oxide 530, A metal oxide may be provided between the edge 550 and the conductor 560. The metal oxide is an insulating material. It is preferable to suppress oxygen diffusion from body 550 to conductor 560. By providing a metal oxide, the diffusion of excess oxygen from the insulator 550 to the conductor 560 is suppressed. This means that the decrease in the amount of excess oxygen supplied to oxide 530 can be suppressed. Furthermore, oxidation of the conductor 560 due to excess oxygen can be suppressed. For the insulator 544, any material suitable for use in the insulator 544 may be used.

[0440] Furthermore, the insulator 550 may have a multilayer structure, similar to the second gate insulating film. As DISTRAs become smaller and more highly integrated, the gate insulating film becomes thinner, leading to leakage current and other issues. Because problems may occur, the insulator that functions as the gate insulating film is made of high-k material. By creating a laminated structure of a material and a thermally stable material, the physical film thickness is maintained while preventing traction. This allows for a reduction in gate potential during inverter operation. Furthermore, it offers thermal stability and a high dielectric constant. It can be made into a layered structure.

[0441] The conductor 560, which functions as the first gate electrode, has a two-layer structure in Figures 25A and 25B. Although it is shown as a structure, it may be a single-layer structure or a laminated structure of three or more layers.

[0442] Conductor 560a contains hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, and nitrogen oxide molecules. Conductive material (such as N2O, NO, NO2, etc.) has the function of suppressing the diffusion of impurities such as copper atoms. It is preferable to use a material that contains oxygen (for example, oxygen atoms, oxygen molecules, etc.). It is preferable to use a conductive material that has the function of suppressing the diffusion of (1). Conductor 56 Because 0a has the function of suppressing oxygen diffusion, the oxygen contained in the insulator 550 This can suppress the oxidation of the conductor 560b and the resulting decrease in conductivity. Oxygen diffusion Examples of conductive materials that have the function of suppressing this include tantalum, tantalum nitride, and ruthenium. It is preferable to use um or ruthenium oxide. Also, as the conductor 560a, An oxide semiconductor applicable to oxide 530 can be used. In that case, conductor 560 By depositing b using the sputtering method, the electrical resistance of the conductor 560a is reduced, thus improving conductivity. It can be incorporated into the body. This is called an OC (Oxide Conductor) electrode. It is possible.

[0443] Furthermore, the conductive material 560b is a conductive material whose main components are tungsten, copper, or aluminum. It is preferable to use the material. Also, since the conductor 560b also functions as wiring, It is preferable to use a highly conductive material. For example, tungsten, copper, or aluminum. A conductive material mainly composed of um can be used. In addition, the conductor 560b has a laminated structure. This may also be done, for example, by forming a laminated structure of titanium or titanium nitride and the above-mentioned conductive material. .

[0444] The insulator 580 is provided on the conductors 542a and 542b via the insulator 544. It is possible. The insulator 580 preferably has an excess oxygen region. For example, insulator 58 As 0, silicon oxide, silicon oxide nitride, silicon oxide nitride, silicon nitride, fluorine silicon oxide with added carbon, silicon oxide with added carbon, and silicon oxide with added nitrogen. It is preferable that the material contains silicon, porous silicon oxide, or resin. In particular, acid Silicon oxide and silicon oxide-nitride are preferred because they are thermally stable. In particular, silicon oxide Silicon oxide with voids can easily form excess oxygen regions in subsequent processes. This is preferable because it allows for this.

[0445] The insulator 580 preferably has an excess oxygen region. Oxygen is released upon heating. By placing the insulator 580 in contact with the oxide 530c, the oxygen in the insulator 580 is oxidized. It can be efficiently supplied to the oxide 530 through material 530c. It is preferable that the concentration of impurities such as water or hydrogen in 80 is reduced.

[0446] The opening in the insulator 580 is formed superimposed on the region between the conductor 542a and the conductor 542b. This allows the conductor 560 to pass through the opening of the insulator 580, and the conductor 542a and the conductor. It is formed in a way that it is embedded in the region sandwiched between 542b.

[0447] When miniaturizing semiconductor devices, it is necessary to shorten the gate length, but the conductor 5 It is necessary to prevent the conductivity of 60 from decreasing. To that end, the film thickness of conductor 560 is increased. As a result, the conductor 560 can have a shape with a high aspect ratio. In this embodiment, In order to embed the body 560 into the opening of the insulator 580, the conductor 560 is aspect ratio Even when forming a shape with a high ratio, it is possible to form the conductive material 560 without causing it to collapse during the process. Cut.

[0448] The insulator 574 is located on the upper surface of the insulator 580, the upper surface of the conductor 560, and the upper surface of the insulator 550. It is preferable that it be provided in contact with the insulator 574. This allows for the...

Claims

[Claim 1] Having a first circuit, The first circuit comprises a first transistor, a second transistor, and a first capacitive element. The first transistor has a first gate and a second gate, The first gate of the first transistor is electrically connected to the first input wiring. The second gate of the first transistor is electrically connected to the first terminal of the second transistor and the first terminal of the first capacitive element. The first circuit is, By turning off the second transistor, the first potential of the first terminal of the first capacitive element and the second gate of the first transistor is maintained. The first transistor has a function to turn on or off depending on the first potential and the second potential input to the first input wiring, The first potential is an analog value, A semiconductor device through which an analog current flows when the first transistor is in the ON state.

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