A signal generator that provides timing signals for the control of quantum computer systems.

Abstract

To provide a signal generator for generating a plurality of timing signals required by a quantum computing system.SOLUTION: A signal generator 1 is provided, comprising a timer configured to execute a predetermined session N times upon detection of a pulse of a first trigger signal and output a signal generation start signal having one or more pulses in each said session, a channel signal generation unit 200 configured to generate a timing signal having one or more pulses upon detection of a pulse of the signal generation start signal.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to a signal generator that generates timing signals required for quantum computer control.

Background Art

[0002] A quantum computer system should include a signal generator that generates synchronization signals and TTL pulses necessary for accurate qubit control. Such a signal generator generates timing signals used throughout the quantum computer system and must distribute each generated timing signal (20) to each of a plurality of individual devices belonging to the entire quantum computer system. Therefore, there is a need for a technology that independently generates and provides timing signals suitable for each of the individual devices.

Summary of the Invention

Problems to be Solved by the Invention

[0003] An object of the present invention is to provide a new signal generator that provides timing signals for controlling a quantum computer system.

Means for Solving the Problems

[0004] According to an embodiment of the present invention, a signal generator (1) that generates a plurality of timing signals required for a quantum computing system can be provided.

[0005] The timing signals can be synchronization signals and / or TTL pulses required for a quantum computing system for accurate qubit control.

[0006] The signal generator generates timing signals used throughout the quantum computer system and distributes each generated timing signal (20) to each of a plurality of individual devices belonging to the entire quantum computer system.

[0007] The signal generator may include multiple signal generation channels, each used to generate multiple timing signals. For example, a first signal generation channel may generate a first timing signal to drive a laser, a second signal generation channel may generate an equipment drive signal (second timing signal) for qubit operation, and a third signal generation channel may generate a synchronization signal (third timing signal) that includes a function to be executed multiple times at precise timings as a detector drive signal for light source detection.

[0008] The signal generator can generate precisely synchronized TTL pulses by generating the rising and falling edges of the TTL pulses at timings desired by the user. For example, it can generate up to 1024 TTL pulses.

[0009] In one embodiment, the signal generator may include a total of 12 channels, from the first channel (CH01) to the twelfth channel (CH12). Each of these channels can adjust the timing of the rising / falling edges of the TTL pulse with a resolution of 5 ns.

[0010] The signal generator may include a channel signal generator (200) corresponding to each of the multiple channels. For example, if there are a total of 12 channels, the signal generator may include a total of 12 channel signal generators.

[0011] A predetermined delay chain part may be connected to the output terminal of each channel signal generation unit. The settings of each delay chain part can be made independently of each other. By using the delay chain part, a relative delay with a resolution of 10 ps can be created between two selected channels from the plurality of channels.

[0012] Each of the plurality of channel signal generators receives a signal generation start signal (110) provided by a predetermined timer (100) included in the signal generator. For example, the first channel signal generator may be provided with a first signal generation start signal provided by the timer, and the second channel signal generator may be provided with a second signal generation start signal provided by the timer. For example, using an event in which the first signal generation start signal changes from a first level to a second level as a trigger signal, the first channel signal generator can generate and output a first timing signal according to a predetermined rule.

[0013] The signal generator can accept an external trigger-in signal (N-channel trigger input signal) (10) provided from outside the signal generator and generate a plurality of timing signals in synchronization with the external trigger-in signal (N-channel trigger input signal).

[0014] The signal generator can generate and output a trigger-out signal (N-channel trigger output signal) (30) based on the external trigger-in signal (N-channel trigger input signal). The trigger-out signal (N-channel trigger output signal) can be used to generate a combined signal by performing an AND logic operation or an OR logic operation between selected timing signals from among the plurality of timing signals.

[0015] According to one aspect of the present invention, a signal generating device is provided that includes a timer (100) which, upon detecting a pulse of a first trigger signal (410), executes a predetermined session N times, and outputs a signal generation start signal (110) having one or more pulses in each session; and a channel signal generation unit (200) which, upon detecting a pulse of the signal generation start signal, generates a timing signal (20) having one or more pulses.

[0016] In this case, the timer may further include a control unit (300) that provides a predetermined execution period and the value of N, and when the timer detects a pulse of the first trigger signal, it may execute the session, which is repeated N times, according to the execution period.

[0017] In this configuration, the channel signal generation unit includes a memory (210) and a generation unit (220), and a series of natural numbers can be recorded in a series of addresses in the memory. The generation unit generates and outputs an output signal (221) having either a first level or a second level, and reads out the first natural number and the second natural number from the series of natural numbers. The level of the output signal is controlled so that it has the first level for a first time corresponding to the value of the first natural number, and after the first time has elapsed, the level of the output signal is controlled so that it has the second level for a second time corresponding to the value of the second natural number.

[0018] In this case, the generation unit is configured to read the second natural number after reading the first natural number, and to read the first natural number before the start of the first time period corresponding to the value of the first natural number, and to read the second natural number before the start of the second time period corresponding to the value of the second natural number.

[0019] In this case, if the first natural number is read from the first address of the memory, the generation unit may be configured to read the second natural number from the second address, which is the address immediately following the first address.

[0020] In this configuration, the channel signal generation unit includes a memory (210) and a generation unit (220), and a series of natural numbers can be recorded in a series of addresses in the memory. The generation unit generates and outputs an output signal (221) having alternating first and second levels, and the output signal consists of a plurality of consecutive sequential time intervals divided based on the boundary time between the first and second levels, and the length of each of the series of sequential time intervals can correspond to the values ​​of the series of natural numbers.

[0021] At this time, the generation unit sequentially reads out the series of natural numbers, and the length of each of the sequential time intervals can be sequentially corresponding to the values ​​of the sequentially read-out series of natural numbers.

[0022] In this case, the signal generating device may further include a control unit (300), and the control unit may prepare and provide the series of natural numbers to the channel signal generating unit so that the channel signal generating unit can record the series of natural numbers in the memory.

[0023] In this case, the channel signal generation unit may further include a session selection unit (230) configured to receive the output signal and mask a portion of the output signal. The session selection unit may output the output signal as a timing signal provided by the channel signal generation unit during the sessions that are pre-selected from the N repeated sessions, and output a signal fixed to a specific level as the timing signal during the remaining sessions of the N repeated sessions, excluding the pre-selected sessions.

[0024] In this case, the channel signal generation unit may further include a session selection unit (230) configured to receive the output signal and mask a portion of the output signal. The signal generation device may further include a control unit (300) configured to provide the session selection unit with a current identifier, which is an identifier for the current session among the N repeated sessions, and one or more selection identifiers, which are identifiers indicating the pre-selected sessions. The session selection unit may output the output signal as a timing signal provided by the channel signal generation unit if any one of the one or more selection identifiers is the same as the current identifier. The session selection unit may output a signal fixed to a specific level as the timing signal if the current identifier is not included in the one or more selection identifiers.

[0025] In this case, the channel signal generation unit may further include a session selection unit (230) configured to receive the output signal and mask a portion of the output signal, and a delay unit (700). The session selection unit may output the output signal during the sessions that are pre-selected from the N repeated sessions, and output a signal fixed at a specific level during the remaining sessions that are not the pre-selected sessions. The delay unit may output a delayed signal, which is the signal output by the session selection unit delayed by a predetermined time, as a timing signal provided by the channel signal generation unit.

[0026] According to another aspect of the present invention, when a pulse of a first trigger signal (410) is detected, a predetermined session is repeated N times, and in each said session, a first signal generation start signal having one or more pulses, and a timer (100) adapted to output a second signal generation start signal having one or more pulses; a first channel signal generation unit (201) adapted to generate a first timing signal having one or more pulses when a pulse of the first signal generation start signal is detected; and a second channel signal generation unit (202) adapted to generate a second timing signal having one or more pulses when a pulse of the second signal generation start signal is detected; A signal generation device may be provided. At this time, the time axis profile of the first timing signal is different from the time axis profile of the second timing signal.

[0027] According to still another aspect of the present invention, the signal generation device; and a quantum computing device including any one of a laser device adapted to receive the timing signal generated by the signal generation device, a qubit operation device adapted to receive the timing signal, and a photodetection device adapted to receive the timing signal may be provided.

Advantages of the Invention

[0028] According to the present invention, a new signal generation device for providing a timing signal for controlling a quantum computer system can be provided.

Brief Description of the Drawings

[0029] [Figure 1] It is a diagram showing the configuration of a signal generation device provided according to an embodiment of the present invention. [Figure 2] It is a diagram showing the state machine of a timer provided according to an embodiment of the present invention. [Figure 3] It is a diagram showing an example of data provided by a control unit and a method of recording the data in a memory according to an embodiment of the present invention. [Figure 4a] This figure shows the process of generating an output signal in a channel signal generator provided according to one embodiment of the present invention. [Figure 4b] This figure shows an example of an output signal generated by the channel signal generation unit shown in Figure 4a. [Figure 5] This figure shows the internal configuration of a signal generator provided according to one embodiment of the present invention. [Figure 6] This figure shows a method for generating timing signals provided according to another embodiment of the present invention. [Figure 7] This is a flowchart showing a timing signal generation method provided according to one embodiment of the present invention. [Figure 8] This figure illustrates the signal patterns and states in one operating mode of a signal generator provided according to one embodiment of the present invention. [Modes for carrying out the invention]

[0030] Embodiments of the present invention will be described below with reference to the accompanying drawings. However, the present invention is not limited to the embodiments described herein and can be embodied in various other forms. The terms used herein are for the purpose of aiding the understanding of the embodiments and are not intended to limit the scope of the present invention. Furthermore, singular forms used herein also include plural forms unless the context clearly indicates otherwise.

[0031] Figure 1 shows the configuration of a signal generator provided according to one embodiment of the present invention.

[0032] The signal generator (1) may include a timer (100), a channel signal generator (200), a control unit (300), an input trigger synthesizer (400), and an output trigger generator (500).

[0033] The signal generator (1) may include a plurality of channel signal generators (200). For example, the signal generator (1) may include a first channel signal generator (200

[01] ) to a twelfth channel signal generator (200

[12] ).

[0034] The timer (100) receives a timer trigger signal (410) that is generated based on an external trigger-in signal (10) and an internal trigger (320), and can generate a signal generation start signal (STrig.) (110) based on the input external trigger-in signal (10) or internal trigger (320) and provide it to the channel signal generation unit (200). For example, the timer (100) can generate a first signal generation start signal (110

[01] ) to a twelfth signal generation start signal (110

[12] ) and provide them to the first channel signal generation unit (200

[01] ) to the twelfth channel signal generation unit (200

[12] ), respectively.

[0035] The control unit (300) can provide the timer (100) with a predetermined execution period and a session repetition count. The execution period is information indicating the time interval between two sessions executed consecutively by the timer (100), and the session repetition count may be a value indicating the total number of repetitions of a session executed when the timer (100) detects a timer trigger signal (410).

[0036] The control unit (300) can provide the channel signal generation unit (200) with the waveform data (310) required by each channel signal generation unit (200). For example, the control unit (300) can generate first data (310

[01] ) to twelfth data (310

[12] ) and provide them to the first channel signal generation unit (200

[01] ) to twelfth channel signal generation unit (200

[12] ), respectively.

[0037] The control unit (300) can provide an internal trigger (320).

[0038] The input trigger synthesizer (400) can provide the timer (100) with a timer trigger signal (TTrig.) (410) generated by synthesizing an external trigger-in signal (10) input from outside the signal generator (1) and an internal trigger (320). This allows the timer (100) to receive either the external trigger-in signal (10) or the internal trigger (320). Here, the synthesis may mean performing an OR operation on the external trigger-in signal (10) and the internal trigger (320).

[0039] Each channel signal generator (200) can generate a timing signal (20) based on the signal generation start signal (110) and waveform data (310) input to it. For example, the first channel signal generator (200

[01] ) to the twelfth channel signal generator (200

[12] ) can generate the first timing signal (20

[01] ) to the twelfth timing signal (20

[12] ), respectively.

[0040] Each of the aforementioned timing signals (20) can be used individually, or they can be used in combination with each other.

[0041] The output trigger generation unit (500) can generate a trigger out signal (30) by combining two or more timing signals (20) selected from among a plurality of timing signals (20). In this case, the combination may include operations that add or multiply the two or more selected timing signals (20) together.

[0042] Therefore, the control unit (300) can generate a timing signal selection and calculation rule signal (340) based on the external trigger-in signal (10) and provide it to the output trigger generation unit (500). Based on the timing signal selection and calculation rule signal (340), the output trigger generation unit (500) can select two or more timing signals (20) from among a plurality of timing signals (20), perform calculations on the selected timing signals (20) using the calculation rules received from the control unit (300), and generate a trigger-out signal (30).

[0043] In one preferred embodiment, the external trigger-in signal (10), timing signal (20), trigger-out signal (30), internal trigger (320), execution cycle and session repeat count (330), signal generation start signal (110), waveform data (310), and timing signal selection and calculation rule signal (340) may each be a TTL signal having one of either a first-level or second-level voltage value.

[0044] The first and second levels described above may be a HIGH level signal and a LOW level signal, respectively, or vice versa.

[0045] When the signal output by the input trigger synthesizer (400) is a HIGH level signal, the timer (100) can generate and output multiple signal generation start signals (110) to be provided to the multiple channel signal generation units (200).

[0046] In this case, generating and outputting the signal generation start signal (110) may mean changing the level of the signal generation start signal (110) according to a specific rule. For example, the timer (100) can basically maintain the value of the signal generation start signal (110) at a LOW level and change it to a HIGH level at the point when the channel signal generation unit (200) is to generate the timing signal (20). In this case, the channel signal generation unit (200) can start the process of generating the timing signal (20) from the point when the value of the signal generation start signal (110) changes to a HIGH level.

[0047] Before the signal generator (1) outputs the timing signal (20), as a kind of preliminary operation, the control unit (300) can transfer waveform data (310), which is information necessary for the channel signal generator (200) to generate the timing signal (20), to the channel signal generator (200). The channel signal generator (200) may include RAM for storing the transferred waveform data (310).

[0048] The waveform data (310) may include information regarding the timing of the rising and falling edges of the timing signal (20) to be generated by the channel signal generation unit (200). The timing of the rising and falling edges may be, for example, times determined relatively with respect to the time when the timer (100) generates and outputs the signal generation start signal (110).

[0049] The timing signal selection and calculation rule signal (340) may be a signal generated and output by the control unit (300). In this case, the specific value of the timing signal selection and calculation rule signal (340) may be a value set by the user using the signal generator (1) and input to the control unit (300).

[0050] The signal generator (1) can be applied to various types of quantum computing systems, but the timing signal selection and operation rule signals (340) may be set differently from each other depending on the specific configuration and / or requirements of the quantum computing system to which the signal generator (1) is applied.

[0051] The operation of the timer (100) may be carried out by an algorithm embodied according to a state machine provided according to one embodiment of the present invention.

[0052] In one embodiment of the present invention, one or more of the timer (100), channel signal generation unit (200), control unit (300), input trigger synthesis unit (400), and output trigger generation unit (500) can be implemented by an FPGA.

[0053] Figure 2 shows a timer state machine provided according to one embodiment of the present invention.

[0054] The timer (100) may be configured to operate based on the first state machine (641). Therefore, the timer (100) may include a circuit that executes an algorithm according to the first state machine (641).

[0055] The first state machine (641) includes four states and can utilize a timer trigger signal (410) input to a timer (100) and information regarding the number of session repetitions for at least one state transition. The timer trigger signal (410) is provided by an input trigger synthesizer (400), and the information regarding the number of session repetitions may be included in the execution cycle and the number of session repetitions (330) provided to the control unit (300). The number of session repetitions may be an integer. In one embodiment, if the number of session repetitions is 0, this may mean that the session will be repeated indefinitely until other predetermined conditions are met.

[0056] The first state machine (641) has four states: idle [IDLE], continuous operation [OPER_C], session operation [OPER_S], and completion [COMP].

[0057] The timer (100) can be in an idle state [IDLE] when the timer trigger signal (410) is 0. When the timer (100) detects that the timer trigger signal (410) has changed to 1, it can transition to a continuous operation state [OPER_C] or a session operation state [OPER_S] depending on the specific value of the session repetition count received from the control unit (300).

[0058] If the timer trigger signal (410) is 1 and the value of the session repetition count is greater than 0, the system can transition from the idle state [IDLE] to the session operation state [OPER_S]. In this case, if the value of the session repetition count is N, the timer (100) can execute a predetermined session N times in the session operation state [OPER_S].

[0059] In contrast, if the timer trigger signal (410) is 1 and the value of the session repetition count is 0, the system can transition from the idle state [IDLE] to the continuous operation state [OPER_C]. Here, the fact that the value of the session repetition count is always 0 indicates that the number of repetitions for a given session is not defined, and it can be replaced with any other value that is not 0, for example, -1, if it can be defined in the same sense.

[0060] While the timer (100) is in the continuous operation state [OPER_C], if it detects that the timer trigger signal (410) has changed to 0, it transitions from the continuous operation state [OPER_C] to the idle state [IDLE]. In one embodiment, in the continuous operation state [OPER_C], the timer (100) can repeat a predetermined session without restriction until the timer trigger signal (410) changes to 0.

[0061] While the timer (100) is in the session operation state [OPER_S], if the session is executed for the specified number of session repetitions, it can transition to the completion state [COMP].

[0062] While the timer (100) is in the completed state [COMP], if the timer trigger signal (410) is detected to have a value of 0, the system can transition from the completed state [COMP] to the idle state [IDLE].

[0063] In each of the sessions described above, the timer (100) can generate and output a signal generation start signal (110) according to a predetermined rule. Different signal generation start signals (110) generated for different channels may be generated independently of each other. Therefore, different signal generation start signals (110) may have different shapes.

[0064] In this state, in continuous operation [OPER_C], the timer (100) can repeat and execute sessions according to the execution cycle communicated by the control unit (300) through the execution cycle and the number of session repetitions (330).

[0065] In this session operation state [OPER_S], the timer (100) can execute the session N times in accordance with the execution cycle communicated by the control unit (300) through the execution cycle and the number of session repetitions (330).

[0066] For each session, the timer (100) can provide the channel signal generator (200) with a predetermined signal generation start signal (STrig.) (110).

[0067] In one embodiment of the present invention, a channel signal generator (200) can operate according to a second state machine (642) provided in accordance with one embodiment of the present invention. The second state machine (642) requests predetermined information for its operation. Such information can be stored in the channel signal generator (200), and for this reason, the channel signal generator (200) can include a memory (210) for storing the information.

[0068] In one embodiment, the memory (210) may be RAM.

[0069] The information stored in the memory (210) may be waveform data (310) provided by the control unit (300).

[0070] Figure 3 shows an example of data provided by a control unit and a method by which the data is recorded in memory, according to one embodiment of the present invention.

[0071] The control unit (300) can generate waveform data (310) containing {Data1, Data2, Data3, ...} which is information to be stored in the memory (210), and provide it to the channel signal generation unit (200).

[0072] {Data1, Data2, Data3, ...} may be values ​​set by the user for the quantum computer system in which the signal generator (1) is used. Data1, Data2, and Data3, etc., may each be natural numbers.

[0073] When the channel signal generator (200) receives waveform data (310), it can store {Data1, Data2, Data3, ...} in memory (210). At this time, {Data1, Data2, Data3, ...} may be stored in {Add1, Add2, Add3, ...} of memory (210), respectively. In this case, Add1, Add2, and Add3, etc., may each represent different addresses in memory (210) that have continuously increasing values.

[0074] In one embodiment, the channel signal generation unit (200) and the memory (210) can also be pre-set as {0, 1, 2, ...} for {Add1, Add2, Add3, ...}.

[0075] In other embodiments, the waveform data (310) may further include information specifying concrete values ​​for {Add1, Add2, Add3, ...} that store {Data1, Data2, Data3, ...} respectively.

[0076] Figure 4a shows the process of generating an output signal in a channel signal generator provided according to one embodiment of the present invention.

[0077] The channel signal generator (200) may be configured to operate based on a second state machine (642). Therefore, the channel signal generator (200) may include a circuit that executes an algorithm according to the second state machine (642).

[0078] The second state machine (642) includes two states and can utilize a signal generation start signal (110) input to the channel signal generation unit (200) for at least one state transition.

[0079] The second state machine (642) has two states: the idle state [IDLE] and the start state [START].

[0080] While the channel signal generator (200) is in the idle state [IDLE], if the signal generation start signal (110) received from the timer (100) is 1 and the value of a predetermined parameter Size is 2 or greater, it can transition to the start state [START].

[0081] Here, the value of Size may be a value that the control unit (300) has provided to the channel signal generation unit (200) in advance.

[0082] Alternatively, the Size value may be a value pre-stored in the channel signal generation unit (200).

[0083] In one embodiment of the present invention, the value of Size may represent the total number of data items in the memory (210) that the channel signal generation unit (200) should read during one session.

[0084] During the transition from the idle state [IDLE] to the start state [START], the channel signal generator (200) provides the memory (210) with en=1 and Add=Add1=0, allowing it to read Data1 recorded in Add1 of the memory (210). The memory (210) is RAM included in each channel signal generator (200). Here, en means enable and Add means address. During this process, the channel signal generator (200) can initialize a predetermined Cnt prepared for the second state machine (642) to 0.

[0085] Here, providing Add=Add1=0 could mean providing the address where the first data to be read by the second state machine (642) is recorded in memory (210). In some concrete examples, Add1 may not be 0.

[0086] The value of Data1 recorded in memory (210) may be information transmitted as part of the waveform data (310) transferred by the control unit (300) to the channel signal generation unit (200).

[0087] In the START state, if the value of internal Cnt is smaller than the value of Data1 read from memory (210) according to the operating clock of the second state machine (642), Cnt can be increased by 1 (Cnt++). For example, if the value of Data1 read during the transition from the IDLE state to the START state is 10, then after 10 operating clock cycles of the second state machine (642), Cnt may become 10.

[0088] In the start state [START], if the value of Data1 read from memory (210) and the value of Cnt are equal, the memory (210) is provided with en=1 and Add++=Add2, and Data2 recorded in Add++=Add2 in memory (210) can be read. Here, Add++ means the value of Add updated by adding the unit address size to the existing Add1. The channel signal generator (200) can then initialize Cnt, which has been prepared for the second state machine (642), back to 0. The channel signal generator (200) can then change the value of the output signal (Sig) generated by the second state machine (642) from the first level to the second level, or from the second level to the first level. That is, the value of the output signal can be inverted (Sig=~Sig). The output signal may be the signal output from the output port (PortO) of the generator (220), which will be described later in Figure 5.

[0089] In the START state, if the updated Add value is greater than or equal to Size-1, the system can transition to the IDLE state.

[0090] By repeatedly executing this second state machine (642), the occurrence of rising and falling edges of the output signal (Sig) can be controlled based on the data stored in memory (210).

[0091] If the operating clock is 200MHz, an output signal (Sig) with a resolution of 5ns can be generated.

[0092] The output signal (Sig) can be used directly as the timing signal (20) output by the channel signal generator (200). Alternatively, the timing signal (20) may be provided with a portion of the output signal (Sig) masked by the session selection unit (230), which will be described later in Figure 5.

[0093] Figure 4b shows an example of the output signal (Sig) generated by the channel signal generator shown in Figure 4a.

[0094] As shown at the top of Figure 4b, we will explain assuming that the values ​​of the data stored at memory addresses "0" (=Add1), "1" (=Add2), "2" (=Add3), "3" (=Add4), "4" (=Add5), and "5" (=Add6) are "5" (=Data1), "3" (=Data2), "5" (=Data3), "1" (=Data4), "10" (=Data5), and "5" (=Data6), respectively.

[0095] The lower part of Figure 4b shows the waveform of the output signal (Sig) generated by the second state machine (642) shown in Figure 4a after reading the data stored in the memory (210).

[0096] In the example in Figure 4b, the operating clock of the second state machine (642) is a clock having a period that changes at a rate that includes a total of five pulses from time (t0) to time (t1), for example. The second state machine (642) resets the value of Cnt to 0 at each of the multiple time points indicated by "*" in Figure 4b. Each time the value of Cnt is reset to 0, the second state machine (642) increments the value of the address and reads the data stored at the incremented address. Then, the value of Cnt is increased according to the operating clock, and when the value of Cnt becomes the same as the value of the data read out, the level of the waveform of the output signal (Sig) is inverted, and Cnt is reset to 0 again. Therefore, the time length of each pulse of the output signal (Sig) and the time length between each pulse can be determined according to the value of the data recorded in memory (210).

[0097] Figure 5 shows the internal configuration of a signal generator (1) provided according to one embodiment of the present invention.

[0098] The control unit (300) can be configured to control the number of session repetitions performed by the timer (100).

[0099] Furthermore, the control unit (300) can specify which sessions each channel signal generator (200) should disable or select from the sessions executed by the timer (100). That is, the control unit (300) can determine and provide to the channel signal generator (200) the current session (Cur_Session) (350), which is the session currently being executed by the timer (100), and the selected session (Sel_Session) (360), which is the session that the channel signal generator (200) should select. The selected session (360) may be determined automatically or by the user depending on the specific settings and configuration of the quantum computer system to which the signal generator (1) is applied.

[0100] In this specification, the current session (Cur_Session)(350) may mean the ID of the current session that distinguishes the current session from other sessions. The selected session (Sel_Session)(360) may mean the ID of a session that can identify one or more selected sessions. Here, the ID of the current session and the ID of the session may be numbers assigned in the order in which the sessions are executed when a series of sessions are executed by the first state machine (641) in Figure 2. For example, assuming that a total of 10 sessions are repeatedly executed by the first state machine (641), the ID of the current session and the ID of the specific session included in the selected session may be any natural number from 1 to 10.

[0101] The channel signal generator (200) can output a timing signal (20) that is valid only in the selected session, and can output the timing signal (20) at a fixed level for the time intervals of the remaining sessions.

[0102] For example, if the number of session repetitions is N, the first channel signal generator (200, 201) can be configured to select only the k1th session, and the second channel signal generator (200, 202) can be configured to select only the k2nd to k3rd sessions.

[0103] The timer (100) can generate a signal generation start signal (110) corresponding to the session being executed, according to the number of session repetitions set by the control unit (300), and provide it to the channel signal generation unit (200). An example of this specific method is shown in Figures 1 and 2.

[0104] The timer (100) can run one or more sessions and can provide one or more trigger signals to the channel signal generator (200) for each session.

[0105] The channel signal generation unit (200) may include a memory (210), a generation unit (220), and a session selection unit (230).

[0106] The generation unit (220) can receive a clock (clk) provided from an external source and operate according to the clock (clk).

[0107] The control unit (300) can provide the generation unit (220) with the total number (size) of data that the generation unit (220) should read from the memory (210) when the timer (100) is in the idle state [IDLE], that is, before it generates the signals for the entire session. The session data (310) and the number (size) can be set, and a trigger signal can be given to transition to the start state [START]. Based on the total number (size), the channel signal generation unit (200) can generate and output timing signals (20) that should be output during one session.

[0108] The generation unit (220) can be reset by a reset provided by the control unit (300).

[0109] The second state machine (642) shown in Figure 4a may be executed in the generation unit (220) of the channel signal generation unit (200).

[0110] When the generation unit (220) receives multiple trigger signals (STrig.) from the timer (100) corresponding to the number of session repetitions, the second state machine (642) shown in Figure 4a is executed multiple times, thereby enabling the output signal (Sig) (221) to be output through the output port (Port0).

[0111] If the channel signal generation unit (200) does not include a session selection unit (230), the output signal (Sig) (221) can be output as is as the timing signal (20). However, in the example in Figure 5, a portion of the output signal (Sig) (221) corresponding to a certain session may be masked by the session selection unit (230), and the masked result may be output as the timing signal (20).

[0112] As described above, the memory (210) receives and stores data from the control unit (300), and can provide some or all of the data to the generation unit (220) at the required time according to the operation of the second state machine (642) shown in Figure 4a. In this case, the memory (210) may have a first port (Port A) and a second port (Port B) as data input / output interfaces. In this case, the data transmitted from the control unit (300) to the memory (210) may be recorded in the memory (210) through the second port (Port B), and the data transmitted from the memory (210) to the generation unit (220) may be read from the memory (210) through the first port (Port A).

[0113] The session selection unit (230) can receive a value indicating the current session (Cur_Session) (350) and a value indicating the selected session (Sel_Session) (360) from the control unit (300).

[0114] The value representing the current session (Cur_Session) (350) may change in real time when the ID of the running session changes. In contrast, the value representing the selected session (Sel_Session) (360) may remain unchanged for at least the duration of the time interval from one idle state [IDLE] to the next idle state [IDLE] in Figure 2.

[0115] The control unit (300) knows the session repetition count, which is the total number of sessions that the timer (100) executes when it detects a timer trigger signal (410) once, and knows information regarding the ID of the session that the channel signal generator (200) should select.

[0116] Furthermore, the control unit (300) knows the ID of the session currently running in real time. In contrast, the channel signal generator (200) cannot know what the ID of the current session is on its own, so in order to find out, it needs to obtain a value indicating the current session (Cur_Session) (350) from the control unit (300).

[0117] The session selection unit (230) can either output the output signal (Sig) (221) output by the generation unit (220) as the timing signal (20) via the output terminal (PortO), or ignore the value of the output signal (Sig) (221) output by the generation unit (220) and output a signal fixed to a specific level as the timing signal (20).

[0118] If the value of the current session (Cur_Session) (350) received by the session selection unit (230) from the control unit (300) is the same as the value included in the information indicated by the selected session (Sel_Session) (360) received from the control unit (300), the session selection unit (230) can output the output signal (Sig) (221) output by the generation unit (220) as the timing signal (20).

[0119] In contrast, if the value of the current session (Cur_Session) (350) received by the session selection unit (230) from the control unit (300) is not included in the information indicated by the selected session (Sel_Session) (360) received from the control unit (300), the session selection unit (230) can ignore the value of the output signal (Sig) (221) output by the generation unit (220) and output a signal fixed to a specific level as the timing signal (20).

[0120] The control unit (300) can set and provide a selection session (Sel_Session) (360) as an independent value for each of the multiple channel signal generators (200). Therefore, the specific values ​​of the selection sessions (360) provided to different channel signal generators (200) may be different from each other or may be the same.

[0121] Figure 6 shows a method for generating a timing signal (20) provided according to another embodiment of the present invention.

[0122] In Figure 5, the signal output by the output port (PortO) of the session selection unit (230) is provided as the timing signal (20) of the channel signal generation unit (200).

[0123] In contrast, as shown in Figure 6(a), the channel signal generation unit (200) may further include a predetermined delay unit (700) connected to the output port (PortO) of the session selection unit (230). In this case, the channel signal generation unit (200) can provide the output signal of the delay unit (700) as a timing signal (20).

[0124] In this case, the delay unit (700) can delay the input signal and output it with a time resolution of, for example, 10 ps.

[0125] In the modified embodiment, if the channel signal generation unit (200) does not include a session selection unit (230), the signal output by the output port (Port0) of the generation unit (220) may be provided as the timing signal (20) of the channel signal generation unit (200).

[0126] In a further modified embodiment, as shown in Figure 6(b), the channel signal generation unit (200) may further include a predetermined delay unit (700) connected to the output port (Port0) of the generation unit (220).

[0127] In this case, the delay unit (700) can delay the input signal and output it with a time resolution of, for example, 10 ps.

[0128] By using any one of the configurations shown in Figure 6, as described above, the channel signal generation unit (200) of each channel included in the signal generator (1) can generate a timing signal (20) having rising edge / falling edge controlled with a 5ns resolution, and in this case, the delay of the timing signal (20) can be controlled in units of 10ps.

[0129] Figure 7 is a flowchart showing a timing signal generation method provided according to one embodiment of the present invention.

[0130] In step (S100), the control unit (300) can reset the signal generator (1) to an idle state (State=IDLE).

[0131] In step (S110), the control unit (300) can set the execution cycle and session repetition count information and provide the set execution cycle and session repetition count information to the timer (100).

[0132] In step (S120), the control unit (300) can set up the signal generator (1).

[0133] In step (S130), the control unit (300) can set the total number (size) of data to be read during one session and provide it to the channel signal generator (200).

[0134] In step (S140), the control unit (300) can set the channel data and provide it to the memory (210) of the channel signal generation unit (200).

[0135] In step (S150), the signal generator (1) can transition to the start state [START] and provide a timer trigger signal (410) to the timer (100) (State[1:0]=START).

[0136] Figure 8 illustrates the signal patterns and states in one operating mode of a signal generator provided according to one embodiment of the present invention.

[0137] Figure 8(a) shows an example of a timer trigger signal (TTrig.)(410) input to the timer (100).

[0138] Figure 8(b) shows the state changes of timer (100).

[0139] Figure 8(c) shows a session that is executed by timer (100) according to a predetermined number of session repetitions.

[0140] In this example, the case where the session repetition count set by the control unit (300) is defined as 1 or greater is shown. When the timer trigger signal (TTrig.) (410) changes to "1", the timer (100) exits the idle state [IDLE]. Since the value of the session repetition count is defined as 3, which is a value greater than 0, the timer (100) enters the session operation state [OPER_S]. When the session has been executed a total of 3 times, the timer (100) enters the completed state [COMP]. In the completed state [COMP], since the timer trigger signal (TTrig.) (410) is "0", the timer (100) enters the idle state [IDLE] again.

[0141] Figure 8(d) shows the signal generation start signal (STrig.)(110) generated by the timer (100) in each session.

[0142] In the example shown in Figure 8(d), the signal generation start signal (STrig.)(110) is configured to have only one pulse in a single session, but the number of pulses can be designed to be greater, and the intervals between pulses can also be designed in various patterns.

[0143] Furthermore, the signal generation start signals (STrig.)(110) output by the timers (100) in different sessions may have the same time pattern, or they may be designed to have different time patterns.

[0144] Figure 8(e) illustrates a timing signal (20) generated by the channel signal generator (200). This shows the case where the selected session (Sel_Session) (360) provided to the session selection unit (230) is limited to the first session only. In this case, in the first session, the channel signal generator (200) outputs the signal (221) output by the generator (220) as the timing signal (20). However, in the second and third sessions, the channel signal generator (200) does not output the signal (221) output by the generator (220) as the timing signal (20), but outputs a predetermined masked signal as the timing signal (20). For example, in the second and third sessions, the timing signal (20) output by the channel signal generator (200) can always have a first level (e.g., LOW level).

[0145] For example, in time intervals not separately indicated in Figure 8(e), the timing signal (20) may be designed to always have a first level (e.g., LOW level). In intervals indicated as “Set Timing Signal” in Figure 8(e), the timing signal (20) may be designed to contain one or more pulses. In intervals indicated as “Masked Timing Signal” in Figure 8(e), the timing signal (20) may be designed to always have a first level (e.g., LOW level).

[0146] Although the present invention has been described above using embodiments of the present invention, the present invention is not limited to the above embodiments, and those skilled in the art within the scope of the present invention will be able to make various changes and modifications without departing from the essential characteristics of the present invention. The content of each claim may be combined with other claims that are not related by reference as can be understood through this specification. [Explanation of symbols]

[0147] 1: Signal generator 10: External trigger-in signal 20: Timing signal 30: Trigger Out Signal 100: Timer 110: Signal generation start signal 200: Channel signal generation unit 210: Memory (RAM) 220: Generation part 230: Session Selection Section 300: Control Unit 310: Waveform data 320: Internal trigger 330: Execution cycle and session repetition count 340: Timing signal selection and arithmetic rule signals 400: Input trigger synthesis unit 410: Timer trigger signal 500: Output trigger generation unit 641: First State Machine 642: Second State Machine 700: Delay section

Claims

1. A timer (100) is configured to execute a predetermined session N times upon detecting a pulse of a first trigger signal (410), and to output a signal generation start signal (110) having one or more pulses in each session; A channel signal generation unit (200) is configured to generate a timing signal (20) having one or more pulses when it detects a pulse of the signal generation start signal; A signal generating device characterized by including [a specific component].

2. A signal generating device according to claim 1, The timer further includes a control unit (300) that provides a predetermined execution period and the value of N, The signal generator is characterized in that, upon detecting a pulse of the first trigger signal, the timer executes the session, which is repeated N times, according to the execution cycle.

3. A signal generating device according to claim 1, The channel signal generation unit includes a memory (210) and a generation unit (220), A series of natural numbers are recorded in the series of addresses of the aforementioned memory. The generating unit is The device generates and outputs an output signal (221) having either a first level or a second level. The system is configured to select the first natural number and the second natural number from the aforementioned series of natural numbers. The level of the output signal is controlled such that the output signal has the first level for a first time period corresponding to the value of the first natural number. A signal generator characterized in that, after the first time has elapsed, the level of the output signal is controlled so that the output signal has the second level for a second time corresponding to the value of the second natural number.

4. A signal generating device according to claim 3, The signal generating device is characterized in that the generating unit reads out the first natural number and then reads out the second natural number, and reads out the first natural number before the start of the first time period corresponding to the value of the first natural number, and reads out the second natural number before the start of the second time period corresponding to the value of the second natural number.

5. A signal generating device according to claim 3, A signal generator characterized in that, when the first natural number is read from the first address of the memory, the generation unit reads the second natural number from the second address, which is the address immediately following the first address.

6. A signal generating device according to claim 1, The channel signal generation unit includes a memory (210) and a generation unit (220), A series of natural numbers are recorded in the series of addresses of the aforementioned memory. The generation unit generates and outputs an output signal (221) having a first level and a second level alternately. The output signal is composed of a plurality of consecutive sequential time intervals that are divided based on the boundary time between the first level and the second level. A signal generator characterized in that the length of each of the series of sequential time intervals corresponds to the values ​​of the series of natural numbers.

7. A signal generating device according to claim 6, The generation unit is configured to sequentially read out the series of natural numbers. A signal generator characterized in that the length of each of the series of sequential time intervals corresponds sequentially to the values ​​of the series of natural numbers read out sequentially.

8. A signal generating device according to any one of claims 3 to 7, The system further includes a control unit (300), A signal generating device characterized in that the control unit prepares and provides the series of natural numbers to the channel signal generating unit so that the channel signal generating unit can record the series of natural numbers in the memory.

9. A signal generating device according to claim 3 or claim 6, The channel signal generation unit further includes a session selection unit (230) configured to receive the output signal and mask a portion of the output signal, The signal generator is characterized in that the session selection unit outputs the output signal as a timing signal provided by the channel signal generation unit during the sessions that are pre-selected from the N repeated sessions, and outputs a signal fixed to a specific level as the timing signal during the remaining sessions that are not the pre-selected sessions from the N repeated sessions.

10. A signal generating device according to claim 3 or claim 6, The channel signal generation unit further includes a session selection unit (230) configured to receive the output signal and mask a portion of the output signal, The signal generator further includes a control unit (300) which provides the session selection unit with a current identifier, which is an identifier for the current session among the N repeated sessions, and one or more selection identifiers, which are identifiers indicating the pre-selected sessions. The session selection unit outputs the output signal as a timing signal provided by the channel signal generation unit if any one of the one or more selection identifiers is the same as the current identifier. The signal generator is characterized in that the session selection unit outputs a signal fixed to a specific level as the timing signal if the current identifier is not included in the one or more selection identifiers.

11. A signal generating device according to claim 3 or claim 6, The channel signal generation unit further includes a session selection unit (230) configured to receive the output signal and mask a portion of the output signal, and a delay unit (700), The session selection unit outputs the output signal during the sessions that are pre-selected from the N repeated sessions, and outputs a signal fixed at a specific level during the remaining sessions that are not the pre-selected sessions from the N repeated sessions. The signal generating device is characterized in that the delay unit outputs a delayed signal, which is obtained by delaying the signal output by the session selection unit by a predetermined time, as a timing signal provided by the channel signal generating unit.

12. A timer (100) is configured to execute a predetermined session N times when it detects a pulse of a first trigger signal (410), and to output a first signal generation start signal having one or more pulses in each session, and a second signal generation start signal having one or more pulses in each session; A first channel signal generation unit (201) is configured to generate a first timing signal having one or more pulses when it detects a pulse of the first signal generation start signal; and A second channel signal generation unit (202) is configured to generate a second timing signal having one or more pulses when it detects a pulse of the second signal generation start signal; Includes, A signal generator characterized in that the time-axis profile of the first timing signal is different from the time-axis profile of the second timing signal.

13. A signal generator according to claim 1; and A laser device to which the timing signal generated by the signal generator is input, a qubit operation device to which the timing signal is input, and any one of the photodetector devices to which the timing signal is input. A quantum computing device characterized by including [a certain component].

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