Switching regulator

Abstract

Provided is a switching regulator that generates a comparison result signal relating to an input / output voltage difference even when there is no terminal for monitoring an output voltage. The switching regulator of the present invention comprises: a switching circuit that switches an input voltage on the basis of a predetermined gate control signal to output a switching voltage; a voltage difference detector that outputs a comparison result signal by comparing the switching voltage with a threshold value depending on the input voltage; and a control circuit that generates a gate control signal on the basis of an output voltage to which the switching voltage is fed back after being smoothed and the comparison result signal and outputs the gate control signal to the switching circuit. The voltage difference detector comprises: an integration circuit that generates and outputs a pseudo-output voltage that is the voltage obtained by integrating the switching voltage with respect to time and substantially equal to the output voltage; and a comparator circuit that outputs a comparison result signal by comparing the pseudo-output voltage with a threshold value depending on a power supply voltage.

Description

Technical Field

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[0005] ,

[0001] The present invention relates to a switching regulator applied to, for example, a power conversion device or the like.

Background Art

[0002] Conventionally, in a switching regulator, it has already been known to use a specific sequence when the difference between the input and output voltages is small, such as in battery-through mode.

[0003] For example, in Patent Document 1, a conventional switching converter for improving the conversion efficiency during DC-DC conversion is disclosed, in which drive units are provided for a plurality of switches respectively, and each switch is controlled according to the load current, input voltage, output voltage, and input / output voltage difference.

[0004] When the conventional switching converter synchronously rectifies by alternately turning on a plurality of first switches and a plurality of second switches, the plurality of first switches are repeatedly driven to be in an on or off state according to the required output respectively, the plurality of second switches are driven to be in an on or off state in synchronization with the first switches respectively, and the driving of some of the plurality of first switches and the driving of some or all of the plurality of second switches are stopped according to the load current, output voltage, input voltage, or input / output voltage difference.

Prior Art Documents

Patent Documents

[0005]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0006] However, conventional input / output voltage monitoring circuits using voltage detection circuits require the acquisition and comparison of power supply voltage and output voltage, and external output voltage adjustment circuits where the feedback rate can be arbitrarily set by the customer have the problem of not being able to monitor the output voltage.

[0007] In the conventional switching converters described above, a configuration is disclosed in which the power supply voltage and output voltage are monitored for the purpose of switching control based on the input / output voltage difference. However, the problem that it cannot handle cases where there is no terminal to monitor the output voltage has not been resolved.

[0008] The objective of the present invention is to solve the above problems and to provide a switching regulator that can generate a comparison result signal regarding the input / output voltage difference even when there is no terminal to monitor the output voltage in the switching regulator. [Means for solving the problem]

[0009] A switching regulator according to one aspect of the present invention is A switching circuit that switches the input voltage and outputs a switching voltage based on a predetermined gate control signal, A voltage difference detector that outputs a comparison result signal by comparing the switching voltage with a threshold voltage dependent on the input voltage, A switching regulator comprising a control circuit that generates the gate control signal based on the output voltage, which is a smoothed switching voltage that is fed back, and the comparison result signal, and outputs it to the switching circuit, The voltage difference detector is An integrating circuit that generates and outputs a pseudo-output voltage which is substantially equal to the output voltage, obtained by integrating the switching voltage over time, The system includes a comparator circuit that compares the pseudo-output voltage with a threshold voltage dependent on the power supply voltage and outputs a comparison result signal. [Effects of the Invention]

[0010] Therefore, according to the switching regulator of the present invention, a comparison result signal is generated by comparing the voltage obtained by time integration of the switching voltage with a threshold voltage dependent on the power supply voltage. Thus, even if there is no terminal to monitor the output voltage, a comparison result signal regarding the input / output voltage difference can be generated. [Brief explanation of the drawing]

[0011] [Figure 1] This is a circuit diagram showing an example configuration of the switching regulator 1 according to Embodiment 1. [Figure 2] Figure 1 is a circuit diagram of an example configuration showing the operation of the voltage difference detector 20 of the switching regulator 1. [Figure 3] Figure 1 shows the timing chart of each signal when the PWM method is used in switching regulator 1. [Figure 4] Figure 1 shows the timing chart of each signal when the PFM method is used in switching regulator 1. [Figure 5] This is a circuit diagram showing an example configuration of the voltage difference detector 20A according to Modification 1. [Figure 6] This is a circuit diagram showing an example configuration of the voltage difference detector 20B according to Modification 2. [Figure 7] This is a circuit diagram showing an example configuration of the voltage difference detector 20C according to Modification 3. [Figure 8] This is a circuit diagram showing an example configuration of the voltage difference detector 20D according to Modification 4. [Figure 9] This is a circuit diagram showing an example configuration of the voltage difference detector 20E according to Modification 5. [Figure 10] This is a circuit diagram showing an example configuration of the switching regulator 1A according to Embodiment 2. [Figure 11] This is a circuit diagram showing an example configuration of the switching regulator 1D according to Embodiment 3. [Figure 12] This is a circuit diagram showing an example configuration of the switching regulator 1E according to Embodiment 4. [Figure 13] This is a circuit diagram showing an example configuration of the switching regulator 1F according to Embodiment 5. [Figure 14] This is a circuit diagram showing a configuration example of the switching regulator 1G according to Embodiment 6. [Figure 15] This is a circuit diagram showing a configuration example of the switching regulator 1H according to Embodiment 7. [Figure 16] This is a circuit diagram showing a configuration example of the switching regulator 1I according to Embodiment 8. [Figure 17] This is a circuit diagram showing a configuration example of the switching regulator 1J according to Embodiment ⑨. [Figure 18] This is a circuit diagram showing a configuration example of the switching regulator 1K according to Embodiment 10. [Figure 19] This is a circuit diagram showing a configuration example of the switching regulator 1L according to Embodiment 11. [Figure 20] This is a circuit diagram showing the configuration of the input / output voltage monitoring circuit 101 according to Comparative Example 1. [Figure 21] This is a circuit diagram showing the configuration of the input / output voltage monitoring circuit 102 according to Comparative Example 2. [Figure 22] This is a circuit diagram showing the configuration of the switching regulator 103 according to Comparative Example 3. [Figure 23] This is a circuit diagram showing the configuration of the switching regulator 104 according to Comparative Example 4.

Modes for Carrying Out the Invention

[0012] Hereinafter, embodiments and modifications according to the present invention will be described with reference to the drawings. Note that the same or similar components are denoted by the same reference numerals.

[0013] (Findings of the Inventor)

[0014] (Comparative Example 1) FIG. 20 is a circuit diagram showing the configuration of the input / output voltage monitoring circuit 101 according to Comparative Example 1. In FIG. 20, the input / output voltage monitoring circuit 101 includes two differential amplifiers 111 and 112 and a selector 113.

[0015] In the input / output voltage monitoring circuit 101 configured as described above, the input voltage VIN, which is the power supply voltage input to input terminal T1, is input to the non-inverting input terminal of differential amplifier 111. The differential amplifier 111 amplifies the difference voltage between the input voltage VIN and the first reference voltage Vre1 from the reference voltage source 121 and outputs it to the selector 113. On the other hand, the output voltage VOUT is input to the non-inverting input terminal of differential amplifier 112. The differential amplifier 112 amplifies the difference voltage between the output voltage VOUT and the second reference voltage Vre2 from the reference voltage source 122 and outputs it to the selector 113. The selector 113 selects one of the two input voltages according to predetermined selection conditions and outputs the selected voltage as the comparison result voltage COMP.

[0016] (Comparative Example 2) Figure 21 is a circuit diagram showing the configuration of the input / output voltage monitoring circuit 102 according to Comparative Example 2. In Figure 21, the input / output voltage monitoring circuit 102 is configured with four resistors R91 to R94 and a comparator 114.

[0017] In the input / output voltage monitoring circuit 102 configured as described above, the input voltage VIN, which is the power supply voltage input to input terminal T1, is divided by voltage divider resistors R91 and R92, and the divided voltages are input to the non-inverting input terminal of comparator 114. On the other hand, the output voltage VOUT is divided by voltage divider resistors R93 and R94, and the divided voltages are input to the inverting input terminal of comparator 114. Comparator 114 generates and outputs a comparison result signal COMP for each divided voltage.

[0018] As explained above, when generating a comparison result signal related to the input-output voltage difference, a circuit such as a comparator 114 that takes in and compares the input voltage VIN and the output voltage VOUT is usually required, which increases the circuit area. In the circuit of Patent Document 1 mentioned above, differential amplifiers 111, 112 and a selector 113 are required, as shown in Figure 20. Furthermore, when using a voltage detector, a voltage divider circuit that takes in the input voltage VIN and the output voltage VOUT, and a comparator 114 that compares the two obtained divided voltages are required.

[0019] (Comparative Example 3) Figure 22 is a circuit diagram showing the configuration of a switching regulator 103 according to Comparative Example 3. In Figure 22, the switching regulator 103 is configured to include terminals T1 to T4, voltage divider resistors R95 and R96, a differential amplifier 11, a comparator 12, a reference voltage source 21, a triangular wave oscillator 22, a control circuit 10 that generates gate control signals S1 and S2 having at least different levels from each other at a predetermined period, MOS transistors Q1 and Q2 which are switching elements, and a voltage difference detector 20F.

[0020] As described above, the switching output voltage from terminal T4 of the switching regulator 103 is smoothed by the output inductor Lout and the smoothing capacitor Cout to obtain the output voltage VOUT, which is then fed back to the feedback terminal T3. Here, terminal T4 is the switching output voltage terminal (SW), and terminal T3 is the feedback terminal (FB).

[0021] The output voltage VOUT, input to terminal T3, is input to the voltage difference detector 20F and is divided by the voltage divider resistors R95 and R96. The divided voltages are input to the differential amplifier 11, which uses the reference voltage from the reference voltage source 21 to amplify the difference voltages and output them to the comparator 12. The comparator 12 compares the amplified error voltage with the triangular wave voltage from the triangular wave oscillator 22 to generate a comparison result signal (synchronous control signal) for generating gate control signals S1 and S2, and outputs it to the control circuit 10. If the comparator 12 is a PWM type comparator, it generates a comparison result pulse signal with a narrower pulse width as the output voltage VOUT becomes lower than the reference voltage, based on the amplified error voltage. Meanwhile, the voltage difference detector 20F detects the difference between the two input voltages and outputs the voltage difference error signal to the control circuit 10. The control circuit 10 generates gate control signals S1 and S2 based on the voltage difference error signal and the comparison result pulse signal, as is well known, and applies them to the gates of the MOS transistors Q1 and Q2, respectively, thereby controlling the on / off state of the MOS transistors Q1 and Q2.

[0022] (Comparative Example 4) Figure 23 is a circuit diagram showing the configuration of the switching regulator 104 according to Comparative Example 4. In Figure 23, the switching regulator 104 differs from the switching regulator 103 in Figure 22 in the following respects. (1) The voltage divider resistors R95 and R96 were replaced with variable resistors VR1 and VR2 located outside the switching regulator 104.

[0023] As shown in Figure 22 of Comparative Example 3, if the output voltage VOUT is fed back into the circuit, it is possible to monitor the output voltage VOUT. However, as shown in Figure 23 of Comparative Example 4, if the output voltage VOUT is adjusted externally using variable resistors VR1 and VR2, there is no longer a monitoring target, so it becomes necessary to add an unnecessary terminal T5 (VOUT).

[0024] In an embodiment of the present invention, a switching regulator is provided that can generate a comparison result signal regarding the input-output voltage difference even when there is no terminal to monitor the output voltage. Specifically, when detecting the input-output voltage difference in a circuit where the output voltage VOUT cannot be acquired, the voltage obtained by time integration of the switching voltage is detected using a power supply voltage-dependent threshold.

[0025] (Embodiment 1) Figure 1 is a circuit diagram showing an example configuration of the switching regulator 1 according to Embodiment 1. Figure 2 is a circuit diagram showing an example configuration of the operation of the voltage difference detector 20 of the switching regulator 1 in Figure 1.

[0026] In Figure 1, the switching regulator 1 comprises terminals T1 to T4, variable resistors VR1 and VR2, a differential amplifier 11, a comparator 12, a reference voltage source 21, a triangular wave oscillator 22, a control circuit 10 that generates gate control signals S1 and S2 having at least different levels from each other at a predetermined period, MOS transistors Q1 and Q2 which are switching elements and constitute a switching circuit, and a voltage difference detector 20. In Figure 2, the voltage difference detector 20 comprises an integrating circuit 25 including a resistor R1 and a capacitor C1, a comparator circuit 27 including MOS transistors Q11 and Q12, and an inverter INV1. Here, MOS transistor Q1 is a P-channel MOS transistor (PMOSFET), and MOS transistor Q2 is an N-channel MOS transistor (NMOSFET).

[0027] The comparator circuit 27 is configured by connecting a P-channel MOS transistor (PMOS transistor) Q11 and an N-channel MOS transistor (NMOS transistor) Q12 in series between the input voltage VIN, which is the power supply voltage VDD, and ground. It outputs a comparison result signal by comparing the output voltage of the integrating circuit 25 using a threshold value that depends on the power supply voltage VDD.

[0028] As described above, the output voltage from terminal T4 of the switching regulator 1 is smoothed by the output inductor Lout and the smoothing capacitor Cout to become the output voltage VOUT, which is then fed back to the feedback terminal T3 via the variable resistor VR1. The voltage obtained by resistively dividing the output voltage VOUT is input to the differential amplifier 11 via terminal T3, and the differential amplifier 11 amplifies the difference voltage between the divided voltage and the reference voltage and inputs it to the non-inverting input terminal of the comparator 12. The comparator 12 compares the amplified error voltage with the triangular wave voltage from the triangular wave oscillator 22 to generate a comparison result signal (synchronous control signal) for generating gate control signals S1 and S2, and outputs it to the control circuit 10. If the comparator 12 is a PWM type comparator, it generates a comparison result pulse signal with a narrower pulse width as the output voltage VOUT becomes lower than the reference voltage, based on the amplified error voltage. On the other hand, the voltage difference detector 20 receives the input voltage VIN, which is the power supply voltage VDD input to terminal T1, and the output voltage from terminal T4. The voltage difference detector 20 integrates the output voltage of terminal T4 over time using the integration circuit 25, and then outputs it to the control circuit 10 via the comparator circuit 27 and inverter INV1, and terminal T13, which perform the comparison operation. Based on the comparison result signal from the voltage difference detector 20 and the comparison result pulse signal from the comparator 12, the control circuit 10 generates gate control signals S1 and S2 as is well known and applies them to the gates of MOS transistors Q1 and Q2, respectively, thereby controlling the on / off state of MOS transistors Q1 and Q2.

[0029] Here, the integration constant is set so that the output voltage VOUTa of the integrating circuit 25 substantially matches the output voltage VOUT. The comparator circuit 27 operates using the input voltage VIN as the power supply voltage, and the threshold duty cycle of the comparator circuit 27 is determined by the ratio of the gate size of the PMOS transistor Q11 to the gate size of the NMOS transistor Q12. Here, since the output voltage VOUTa of the integrating circuit 25 substantially matches the output voltage VOUT, it can be called a "pseudo-output voltage".

[0030] As explained above, the switching regulator 1 in Figure 1 monitors the SW voltage at terminal T4 without adding an output voltage VOUT terminal when there is no terminal to monitor the output voltage VOUT. The voltage difference detector 20 in Figure 2 generates a pseudo output voltage (false output voltage) VOUTa after integrating the SW voltage over time, and the comparator circuit 27 generates and outputs a comparison result signal by comparing the pseudo output voltage VOUTa with a threshold dependent on the power supply voltage VDD.

[0031] Figure 3 is a timing chart of each signal showing the operation when the PWM method is used in the switching regulator 1 of Figure 1. In Figure 3, the voltage VOUTa generated from a SW voltage separate from the input voltage VIN and the voltage difference detection signal OUT are shown. The ripple voltage of the voltage VOUTa in Figure 3 is several mV to several tens of mV. Here, when the PN ratio (gate size ratio of PMOS transistor Q11 and NMOS transistor Q12) is adjusted so that the threshold of the comparator circuit 27 is 75%, the detection signal is configured to rise from L level to H level when the output voltage VOUT exceeds 75% of the power supply voltage VDD.

[0032] Figure 4 shows the timing charts of each signal when the PFM method is used in the switching regulator 1 of Figure 1. In addition to the continuous operation PWM method of Figure 3, detection is also possible with the skip operation PFM method. The ripple voltages of the voltages VOUT and VOUTa in Figure 4 are approximately a few mV to several tens of mV.

[0033] The integral multiplier (time constant) of the integrating circuit 25 can be optimized to a multiplier corresponding to the oscillation frequency of the switching regulator 1. Furthermore, even if there is an output voltage VOUT terminal, changing the application of the SW voltage to the application of the output voltage VOUT is effective in reducing the circuit area.

[0034] As described above, according to Embodiment 1, a switching regulator can generate a comparison result signal regarding the input-output voltage difference even when there is no terminal to monitor the output voltage.

[0035] Next, several modified examples of the voltage difference detector 20 will be described below.

[0036] (Variation 1) Figure 5 is a circuit diagram showing an example configuration of the voltage difference detector 20A according to Modification 1. The voltage difference detector 20A in Figure 5 differs from the voltage difference detector 20 in Figure 2 in the following ways. (1) Instead of MOS transistors Q11 and Q12, the device is equipped with four MOS transistors Q21 to Q24 connected in series, and MOS transistors Q25 and Q26 for generating hysteresis characteristics. Here, MOS transistors Q21, Q22, and Q25 are P-channel MOS transistors (PMOSFETs), and MOS transistors Q23, Q24, and Q26 are N-channel MOS transistors (NMOSFETs).

[0037] (Modification 2) Figure 6 is a circuit diagram showing an example configuration of the voltage difference detector 20B according to Modification 2. The voltage difference detector 20B in Figure 6 differs from the voltage difference detector 20 in Figure 2 in the following ways. (1) Instead of MOS transistors Q11 and Q12, a delay-generating inverter INV2 and a capacitor C2 are provided.

[0038] (Variation 3) Figure 7 is a circuit diagram showing an example configuration of the voltage difference detector 20C according to Modification 3. The voltage difference detector 20C in Figure 7 differs from the voltage difference detector 20 in Figure 2 in the following ways. (1) Instead of MOS transistors Q11, Q12 and inverter INV1, the circuit is equipped with voltage divider resistors R11, R12 and a comparator 13. Here, the voltage divider resistors R11, R12 apply the divided voltage of the input voltage VIN to the inverting input terminal of the comparator 13. The output voltage of the integrating circuit 25 is applied to the non-inverting input terminal of the comparator 13. The comparator 13 outputs a comparison result signal from terminal T13, which is obtained by comparing these two voltages.

[0039] (Modification 4) Figure 8 is a circuit diagram showing an example configuration of the voltage difference detector 20D according to Modification 4. The voltage difference detector 20D in Figure 8 differs from the voltage difference detector 20 in Figure 2 in the following ways. (1) Instead of MOS transistors Q11, Q12 and inverter INV1, an input-referred comparator 13 with a level shifter is provided. Here, the input voltage VIN is applied to the inverting input terminal of the comparator 13, and the output voltage of the integrating circuit 25 is applied to the non-inverting input terminal of the comparator 13.

[0040] (Variation 5) Figure 9 is a circuit diagram showing an example configuration of the voltage difference detector 20E according to Modification 5. The voltage difference detector 20E in Figure 9 further includes the following components compared to the voltage difference detector 20 in Figure 2. (1) A constant current source CI1 connected between the input voltage VIN terminal T11 and the gates of MOS transistors Q11 and Q12; (2) Constant current source CI2 connected between the source and ground of MOS transistor Q12; and (3) A MOS transistor Q13 inserted between the integrating circuit 25 and the comparator circuit 27.

[0041] Here, the circuit between the integrating circuit 25 and the inverter INV1 constitutes a constant current inverter circuit.

[0042] (Embodiment 2) Figure 10 is a circuit diagram showing an example configuration of the switching regulator 1A according to Embodiment 2. The switching regulator 1A in Figure 10 differs from the switching regulator 1 in Figure 1 in the following ways. (1) A Noah gate 14 is provided instead of the control circuit 10.

[0043] Here, the output voltage of the voltage difference detector 20 is input to the first input terminal of the Norr gate 14, and the output voltage of the comparator 12 is input to the second input terminal of the Norr gate 14. The Norr gate 14 applies the output voltage as a gate control signal S1 to the gates of MOS transistors Q11 and Q12. This constitutes a voltage-controlled switching regulator 1A.

[0044] As described above, according to Embodiment 2, a switching regulator can generate a comparison result signal regarding the input-output voltage difference even when there is no terminal to monitor the output voltage.

[0045] The differential amplifier 11, comparator 12, reference voltage source 21, and triangular wave oscillator 22 may be combined and formed into a switching modulation circuit block. The same applies to the following embodiments.

[0046] (Embodiment 3) Figure 11 is a circuit diagram showing an example configuration of the switching regulator 1D according to Embodiment 3. The switching regulator 1D in Figure 11 has the same internal circuitry as the switching regulator 1A in Figure 10, except for the connections of terminals T1 and T5, but differs in the following points. (1) The input voltage VIN of terminal T1 is input from terminal T4 via input inductor Lout and is also input to the voltage difference detector 20. (2) The drain voltage of MOS transistor Q1 is output to the voltage difference detector 20 and also to the voltage divider resistors VR1 and VR2 via the output capacitor Cout as the output voltage VOUT.

[0047] This configures a switching regulator in boost mode.

[0048] As described above, according to Embodiment 3, even if there is no terminal to monitor the output voltage in the switching regulator, a comparison result signal regarding the input / output voltage difference can be generated.

[0049] (Embodiment 4) Figure 12 is a circuit diagram showing an example configuration of the switching regulator 1E according to Embodiment 4. The switching regulator 1E in Figure 12 differs from the switching regulator 1A in Figure 10 in the following ways. (1) Instead of the comparator 12 having a triangular wave oscillator 22, comparators 12A and 12B, each having a triangular wave oscillator 22A and 22B, are provided. (2) Noah gate 14 is replaced with Noah gates 14A and 14B. (3) MOS transistors Q33 and Q34 are provided between the output inductor Lout and the output capacitor Cout. (4) Connect terminal T5 to terminal T12 of the voltage difference detector 20 instead of terminal T4.

[0050] Here, MOS transistors Q31 and Q34 are P-channel MOS transistors (PMOSFETs), and MOS transistors Q32 and Q33 are N-channel MOS transistors (NMOSFETs).

[0051] In Figure 12, the output voltage from the differential amplifier 11 is input to the inverting input terminals of comparators 12A and 12B. The comparison result signals from comparators 12A and 12B are output to the gates of MOS transistors Q31 and Q32, and MOS transistors Q33 and Q34, respectively, via Norgates 14A and 14B. Here, the source of MOS transistor Q31 is connected to terminal T1 of the input voltage VIN and the voltage difference detector 20. The connection points of the drains of MOS transistors Q31 and Q32 are connected to the connection point of the drain of MOS transistor Q33 and the source of Q34 via terminal T6, connecting capacitor Lcn, and terminal T7. The connection points of the sources of MOS transistors Q32 and Q33 are grounded. The drain of MOS transistor Q34 is connected to terminal T5, and the output voltage VOUT from terminal T5 is connected to voltage divider resistors VR1 and VR2 via output capacitor Cout.

[0052] Here, terminal T6 is the step-down switching voltage terminal (BUSW), and terminal T7 is the step-up switching voltage terminal (BOSW).

[0053] The switching regulator 1E configured as described above operates in buck-boost mode.

[0054] As described above, according to Embodiment 4, a switching regulator can generate a comparison result signal regarding the input-output voltage difference even if there is no terminal to monitor the output voltage.

[0055] (Embodiment 5) Figure 13 is a circuit diagram showing an example configuration of the switching regulator 1F according to Embodiment 5. The switching regulator 1F in Figure 13 differs from the switching regulator 1 in Figure 1 in the following ways. (1) Voltage regulator 30, diode D1, and boost terminal T8 It also features a boost capacitor Cbst.

[0056] In Figure 13, the input voltage VIN is input to the voltage regulator 30 and the voltage difference detector 20. The voltage regulator 30 adjusts the input voltage VIN to a predetermined voltage, then outputs it to the control circuit 10 via diode D1, and also outputs the output voltage VOUT via boost terminal T8, boost capacitor Cbst, output inductor Lout, and output capacitor Cout. The other configurations are the same as in Figure 1, and this constitutes a so-called NN type (N-channel-N-channel type) bootstrap switching regulator.

[0057] As described above, according to Embodiment 5, a switching regulator can generate a comparison result signal regarding the input-output voltage difference even when there is no terminal to monitor the output voltage.

[0058] Next, the voltage difference detector 20 has a different application than described above and is suitable for electronic circuits that monitor the power supply voltage and output voltage to control a switching regulator, as described below.

[0059] (Embodiment 6) Figure 14 is a circuit diagram showing an example configuration of switching regulator 1G according to Embodiment 6. In Figure 14, the following points differ from the switching regulator 1A in Figure 10. (1) Instead of the differential amplifier 11, comparator 12, reference voltage source 21, and triangular wave oscillator 22, the system is equipped with a comparator 12, reference voltage source 21, pulse oscillator 26, and set-reset flip-flop 16. (2) The comparison result signal from the voltage difference detector 20 is input to the first input terminal of the Noah gate 14. The output signal from the set-reset flip-flop 16 is output to the gate of the MOS transistor Q1 as a gate control signal S1 via the inverter INV11. (3) The output signal of inverter INV11 is output to the second input terminal of the Noah gate 14 via inverter INV12. (4) The output signal of the Noah gate 14 is applied to the gate of the MOS transistor Q2 as the gate control signal S2.

[0060] In Figure 14, the comparator 12 compares the divided voltage of the output voltage VOUT with a reference voltage source from the reference voltage source 21, and outputs the comparison result signal to the set terminal of the set-reset flip-flop 16 and the control terminal of the pulse oscillator 26. The pulse oscillator 26 generates a pulse signal synchronized with the comparison result signal and outputs it to the reset terminal of the set-reset flip-flop 16. The switching regulator 1C configured as described above operates using a so-called hysteresis control method.

[0061] In the switching regulator 1G configured as described above, the inclusion of a voltage difference detector 20 and a Norgate 14 reduces the peak value of the inductor current in low input / output voltage conditions, and prevents reverse current when there is a concern about reverse current.

[0062] As described above, according to Embodiment 6, a switching regulator can generate a comparison result signal regarding the input-output voltage difference even when there is no terminal to monitor the output voltage.

[0063] (Embodiment 7) Figure 15 is a circuit diagram showing an example configuration of the switching regulator 1H according to Embodiment 7. In Figure 15, the switching regulator 1H in Figure 15 differs from the switching regulator 1G in Figure 14 in the following respects. (1) A zero-crossing detector 40 was inserted between the voltage difference detector 20 and the input terminal of the Norgate 14. (2) A current detector 2 was inserted between terminal T4 and the output inductor Lout.

[0064] Here, the zero-crossing detector 40 outputs an H-level detection signal to the Norr gate 14 when the current value from the current detector 2 crosses zero, or when the voltage difference from the voltage difference detector 20 is within a predetermined voltage range.

[0065] In the switching regulator 1H configured as described above, the inclusion of a voltage difference detector 20, a zero-crossing detector 40, and a Norgate 14 reduces the peak value of the inductor current in low input / output voltage conditions, and prevents reverse current when there is a concern about reverse current.

[0066] As described above, Embodiment 7 According to this, even in a switching regulator, a comparison result signal regarding the input-output voltage difference can be generated even if there is no terminal to monitor the output voltage.

[0067] (Embodiment 8) Figure 16 is a circuit diagram showing an example configuration of the switching regulator 1I according to Embodiment 8. The switching regulator 1I in Figure 16 differs from the switching regulator 1A in Figure 10 in the following ways. (1) Replace the Noahgate 14 with an inverter INV11. (2) The comparison result signal from the voltage difference detector 20 is input to the pulse oscillator 26.

[0068] In the switching regulator 1I configured as described above, the pulse oscillator 26 synchronizes with the comparison result signal, or generates a pulse signal when the comparison result signal is within a predetermined voltage range, and outputs it to the reset terminal of the set-reset type flip-flop 16.

[0069] In the switching regulator 1I configured as described above, the comparison result signal from the voltage difference detector 20 is input to the pulse oscillator 26, so that the timer time can be varied while the comparison result signal is within a predetermined voltage range. This allows adjustment of the control time related to the gate control of the switching element.

[0070] (Embodiment 9) Figure 17 is a circuit diagram showing an example configuration of the switching regulator 1J according to Embodiment 9. The switching regulator 1J in Figure 17 differs from the switching regulator 1A in Figure 10 in the following ways. (1) A current detector 2 is inserted between terminal T4 and output inductor Lout to detect the inductor current and output the detected current value to peak current detector 50. (2) The comparison result signal from the voltage difference detector 20 is input to the peak current detector 50. (3) When the comparison result signal is within a predetermined voltage range, the peak current detector 50 detects the peak current based on the inductor current detected by the current detector 2 and outputs the detection signal to the reset terminal of the set-reset type flip-flop 15. (4) The comparison result signal from the comparator 12 is output to the set terminal of the set-reset flip-flop 15.

[0071] With the switching regulator 1J configured as described above, the current detection threshold can be adjusted by resetting the switching operation when a predetermined peak current is reached.

[0072] In the switching regulator 1J configured as described above, the comparison result signal from the voltage difference detector 20 is: Peak current detector 50Since it is input to the set-reset flip-flop, the comparison result signal is within a predetermined voltage range, and a pulse signal is generated. 15 This allows you to reset the switching operation threshold related to the gate control of the switching element.

[0073] As described above, according to Embodiment 9, a switching regulator can generate a comparison result signal regarding the input-output voltage difference even when there is no terminal to monitor the output voltage.

[0074] (Embodiment 10) Figure 18 is a circuit diagram showing an example configuration of the switching regulator 1K according to Embodiment 10. The switching regulator 1K in Figure 18 differs from the switching regulator 1G in Figure 14 in the following respects. (1) The comparison result signal from the voltage difference detector 20 is input to the soft start circuit 60. (2) The output signal of the soft-start circuit 60 is input to the non-inverting input terminal of the comparator 12.

[0075] In the switching regulator 1K configured as described above, the comparison result signal from the voltage difference detector 20 is input to the soft-start circuit 60. When the comparison result signal is within a predetermined voltage range, it is soft-started with a predetermined time delay using the reference voltage from the reference voltage source 21 to generate a predetermined trigger signal, which is input to the inverting input terminal of the comparator 12. As a result, the set-reset type flip-flop 16 can be reset and then set by the H-level set signal from the comparator 12 and the trigger signal to the pulse oscillator 26. This makes it possible to soft-start the gate control signal related to the gate control of the switching element.

[0076] As described above, according to Embodiment 10, a switching regulator can generate a comparison result signal regarding the input-output voltage difference even when there is no terminal to monitor the output voltage. (Embodiment 11) Figure 19 is a circuit diagram showing an example configuration of the switching regulator 1L according to Embodiment 11. The switching regulator 1L in Figure 19 differs from the switching regulator 1E in Figure 12 in the following ways. (1) Inverters INV21 and INV22 are provided in place of the Noahgate 14A and 14B, respectively. (2) Comparators 12C and 12D are provided instead of comparators 12A and 12B, respectively. The comparison result signal from the voltage difference detector 20 is input to the control terminal of comparator 12C via inverter INV31, and also to the control terminal of 12D. Here, when the comparison result signal falls within a predetermined first voltage range, comparator 12C is operated, while when the comparison result signal falls within a second voltage range different from the first voltage range, comparator 12D is operated.

[0077] With the switching regulator 1L configured as described above, the operation of comparators 12C and 12D can be selectively switched according to the voltage difference from the voltage difference detector 20.

[0078] As described above, according to Embodiment 11, a switching regulator can generate a comparison result signal regarding the input-output voltage difference even when there is no terminal to monitor the output voltage.

[0079] (Other variations) In the embodiments and modifications described above, the MOS transistors Q1 to Q31, which are switching elements, are provided within the circuits of the switching regulators 1, 1A to 1L. However, the present invention is not limited to this, and the transistors may be provided outside the circuits of the switching regulators 1, 1A to 1L. [Industrial applicability]

[0080] As described in detail above, the switching regulator according to the present invention generates a comparison result signal by comparing the voltage obtained by time integration of the switching voltage with a threshold voltage dependent on the power supply voltage. Therefore, even if there is no terminal to monitor the output voltage, a comparison result signal regarding the input / output voltage difference can be generated. [Explanation of symbols]

[0081] 1.1A~1L Switching Regulator 10 Control circuits 11 Differential amplifier 12, 12A~12D Comparator 13 Comparator 14, 14A, 14B Noahgate 16-set reset flip-flops 20, 20A~20F Voltage Difference Detector 21 Reference voltage source 22, 22A, 22B Triangular Wave Oscillator 23 Adder 25 Integrator circuit 26. Pulse Oscillator 27 Comparator Circuit 30 Voltage Regulator 50 Peak current detector 60 Soft-start circuit 101,102 Input / Output Voltage Monitoring Circuit 103-104 Switching Regulator 111,112 Differential amplifier 113 Selector 114 Comparator 121,122 Reference voltage source CI1,CI2 Constant current source Cbst Boost Capacitor Ccn connected capacitor Cout output capacitor D1 diode INV1~INV31 Inverter Lcn connecting inductor Lout output inductor Q1-Q34 MOS transistors R1~R96 Resistors C1 Capacitor VR1~VR2 Variable resistors T1~T13 terminals

Claims

1. A switching circuit that switches the input voltage and outputs a switching voltage based on a predetermined gate control signal, A voltage difference detector that outputs a comparison result signal by comparing the switching voltage with a threshold voltage dependent on the input voltage, A switching regulator comprising a control circuit that generates the gate control signal based on the output voltage, which is a smoothed switching voltage that is fed back, and the comparison result signal, and outputs it to the switching circuit, The voltage difference detector is An integrating circuit that generates and outputs a pseudo-output voltage which is substantially equal to the output voltage, obtained by integrating the switching voltage over time, The system includes a comparator circuit that compares the pseudo-output voltage with a threshold voltage dependent on the power supply voltage and outputs a comparison result signal. Switching regulator.

2. The aforementioned comparator circuit includes two MOS transistors connected in series. A switching regulator according to claim 1.

3. The comparator circuit has hysteresis characteristics and includes four MOS transistors connected in series. A switching regulator according to claim 1.

4. The comparator circuit includes an inverter and an output capacitor connected downstream of the inverter. A switching regulator according to claim 1.

5. The comparator circuit includes a comparator that compares the voltage corresponding to the input voltage with the time-integrated voltage and outputs a comparison result signal. A switching regulator according to claim 1.

6. The voltage corresponding to the input voltage is a voltage obtained by level-shifting the input voltage. The switching regulator according to claim 5.

7. The comparator circuit includes a constant current inverter circuit. A switching regulator according to claim 1.

8. The switching regulator is a switching regulator using a voltage control method, a current control method, or a hysteresis control method. A switching regulator according to claim 1.

9. The switching regulator is a boost-type or buck-boost switching regulator. A switching regulator according to claim 1.

10. The switching regulator monitors the input voltage and the output voltage to control the operation of the switching regulator. A switching regulator according to claim 1.

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