Semiconductor chip and failure detection system

Abstract

The present invention provides a technology for improving the accuracy of failure detection and failure prediction. According to the present technology, provided is a semiconductor chip that, in order to detect and predict failure of an internal circuit, monitors at least one of a current and a voltage flowing therein and outputs a failure detection signal or a failure prediction signal on the basis of the monitoring result. Further provided is a failure detection system comprising a semiconductor chip and a host device, wherein: the semiconductor chip, in order to detect and predict a failure of an internal circuit, monitors at least one of a current and a voltage flowing therein and outputs a failure detection signal or a failure prediction signal on the basis of the monitoring result; and the host device determines whether or not to stop the system on the basis of the failure detection signal or the failure prediction signal.

Description

Semiconductor Chip and Fault Detection System

[0001] This technology relates to a semiconductor chip and a fault detection system.

[0002] In recent years, with the requirements for higher performance and higher reliability of electronic devices, the importance of fault detection technology has been increasing. For example, Patent Document 1 describes a method for analyzing the cause of a fault in a device based on operation state signals acquired under different operating conditions of the diagnostic target device.

[0003] Japanese Patent Application Laid-Open No. 2005-309078

[0004] In the conventional technology, it is common to monitor current and voltage outside the semiconductor chip, and it has been difficult to obtain accurate data due to the influence of external loads (for example, parasitic inductance and stabilizing capacitance of the substrate). Therefore, it has been impossible to accurately detect abnormalities in the semiconductor chip, which has been a factor妨碍ing the improvement of the accuracy of fault detection and fault prediction.

[0005] Therefore, the main object of this technology is to provide a technology that eliminates the constraints associated with conventional external monitoring and improves the accuracy of fault detection and fault prediction.

[0006] It should be noted that there is an incorrect character "妨碍" in the original text. I have translated it as "hindering" in the English version while keeping the overall context. If this is a special term or needs to be corrected, please let me know.This technology provides a semiconductor chip that monitors at least one of the current and voltage flowing internally for fault detection and fault prediction of the internal circuit, and outputs a fault detection signal or a fault prediction signal based on the monitoring results. The monitored current and voltage may include both digital and analog signals. The semiconductor chip may store the monitored current and voltage as the maximum or minimum value within a predetermined period, and output the fault detection signal or the fault prediction signal based on the maximum value and at least one of the maximum value. The semiconductor chip may calculate an average value based on the maximum and minimum values ​​and output the fault detection signal or the fault prediction signal based on the average value. The semiconductor chip may calculate the rate of change over time of the monitored current and voltage, and output the fault detection signal or the fault prediction signal based on the rate of change over time. Based on the monitoring results, the semiconductor chip may output the fault detection signal if a threshold is exceeded, and output the fault prediction signal if the fluctuation is within a predetermined range. The threshold may be set based on simulation or evaluation tests and stored internally. The semiconductor chip may store the monitoring results on a recording medium, evaluate the tendency for anomalies to occur by comparing the stored data with past data, and output the fault detection signal or the fault prediction signal based on the evaluation results. The semiconductor chip may use a learning model that has learned the current and voltage patterns under normal conditions, and output the fault detection signal or the fault prediction signal by comparing it with the monitoring results. The learning model may be constructed based on data of current and voltage patterns under normal conditions aggregated on the cloud. The fault detection signal or fault prediction signal may be transmitted to an external host device. The semiconductor chip may be applied to an imaging device. The semiconductor chip may be applied to an in-vehicle imaging device. The semiconductor chip may be applied to a power supply IC.Furthermore, this technology provides a fault detection system comprising a semiconductor chip and a host device, wherein the semiconductor chip monitors at least one of the current and voltage flowing internally for fault detection and fault prediction of internal circuits, outputs a fault detection signal or a fault prediction signal based on the monitoring results, and the host device determines whether or not to shut down the system based on the fault detection signal or the fault prediction signal. The host device may send an alert to the user based on the fault detection signal or the fault prediction signal, enabling the user to decide whether to shut down the system. The host device may determine a course of action based on the fault detection signal or the fault prediction signal. The host device may estimate a maintenance timing based on the fault detection signal or the fault prediction signal. The semiconductor chip may classify the cause when an abnormality occurs based on the monitoring results, transmit the classification results to the host device, and the host device may analyze the scope of the abnormality's impact based on the classification results and determine whether or not to shut down the system.

[0007] This is a circuit diagram showing an example of a digital circuit constituting a semiconductor chip. This is a circuit diagram showing the internal configuration of a CMOS inverter constituting the combinational logic circuit LC shown in Figure 1. This is a graph showing the change in current waveform. This is a graph showing the change in voltage waveform. This is a circuit diagram showing the current monitoring location. This is a graph showing a comparison of the results of monitoring current inside and outside the semiconductor chip. This is a block diagram showing an example of the configuration of a semiconductor chip 1 according to one embodiment of this technology. This is a flowchart showing an example of the operation process of a semiconductor chip 1 according to one embodiment of this technology. This is a waveform diagram showing the monitoring results of the current inside the semiconductor chip 1 according to one embodiment of this technology. This is a waveform diagram showing the monitoring results of the current inside the semiconductor chip 1 according to one embodiment of this technology. This is a waveform diagram showing the monitoring results of the voltage inside the semiconductor chip 1 according to one embodiment of this technology. This is a waveform diagram showing the monitoring results of the voltage inside the semiconductor chip 1 according to one embodiment of this technology. This is a flowchart showing an example of the processing flow of a semiconductor chip 1 according to one embodiment of this technology. This is a flowchart showing an example of the processing flow of a threshold determination circuit 16 according to one embodiment of this technology. This is a flowchart showing an example of the process of constructing a learning model used by the threshold determination circuit 16 according to one embodiment of this technology. This is a block diagram showing an example of the configuration of a fault detection system 100 according to one embodiment of this technology. This is a flowchart showing an example of the processing flow of a host device 101 according to one embodiment of this technology. This is a block diagram showing an example configuration of an imaging device 2 to which the semiconductor chip 1 of this technology is applied. This is a block diagram showing an example configuration of a power supply IC 3 to which the semiconductor chip 1 of this technology is applied. This is a block diagram showing an example of a schematic configuration of a vehicle control system. This is an explanatory diagram showing an example of the installation location of the external information detection unit and the imaging unit.

[0008] Hereinafter, preferred embodiments for implementing this technology will be described with reference to the drawings. The embodiments described below are merely examples of typical embodiments of this technology and do not limit the scope of this technology. Furthermore, this technology can be implemented by combining any of the following embodiments and their modifications.

[0009] In the following description of the embodiments, the configuration may be described using terms with "approximately" attached, such as "approximately parallel" and "approximately orthogonal." For example, "approximately parallel" means not only that they are perfectly parallel, but also that they are substantially parallel, that is, that is, that they are deviated from a perfectly parallel state by, for example, a few percent. The same applies to other terms with "approximately." Also, each figure is a schematic diagram and is not necessarily a strictly accurate representation.

[0010] Unless otherwise specified, in drawings, "up" means the upper direction or upper side in the drawing, "down" means the lower direction or lower side in the drawing, "left" means the left direction or left side in the drawing, and "right" means the right direction or right side in the drawing. In addition, in drawings, the same or equivalent elements or components are denoted by the same reference numeral, and redundant explanations are omitted.

[0011] The explanation will proceed in the following order: 1. First Embodiment (Example 1 of a Semiconductor Chip) (1) Current and Voltage Monitoring Locations (2) Overall Configuration (3) Semiconductor Chip Operation (4) Current Monitoring Circuit (5) Voltage Monitoring Circuit (6) Data Processing Circuit (7) Threshold Judgment Circuit (8) Memory Circuit (9) Error Report Circuit (10) Host Interface (11) Effects 2. Second Embodiment of the Technology (Example 2 of a Semiconductor Chip) 3. Third Embodiment of the Technology (Example of a Fault Detection System) (1) Overall Configuration (2) System Stop Judgment Function (3) Alert Transmission Function (4) Countermeasure Judgment Function (5) Maintenance Timing Estimation Function (6) Impact Scope Analysis Function 4. Application Example to Imaging Devices 5. Application Example to Automotive Imaging Devices 6. Application Example to Power ICs 7. Application Example to Mobile Devices

[0012] [1. First Embodiment (Example 1 of a Semiconductor Chip)] [(1) Current and Voltage Monitoring Locations] The necessity of monitoring the current or voltage flowing through the internal circuitry of a semiconductor chip will be explained with reference to Figures 1 to 6. Figure 1 is a circuit diagram showing an example of a digital circuit constituting a semiconductor chip. This circuit receives input data (IN_DATA), performs predetermined logic processing, and generates output data (OUT_DATA).

[0013] The input data (IN_DATA) is input to the first flip-flop (Type D flip-flop) F1 in synchronization with the clock signal (CLK). The first flip-flop temporarily holds the input data and supplies its output to a combinational logic circuit LC. This combinational logic circuit LC is composed of a combination of components such as a CMOS inverter, NAND gate, and NOR gate, and realizes the desired logic processing. The output of this combinational logic circuit LC is supplied to the second flip-flop F2, which generates the final output data (OUT_DATA).

[0014] Figure 2 is a circuit diagram showing the internal configuration of the CMOS inverter that constitutes the combinational logic circuit LC shown in Figure 1. The CMOS inverter has a structure in which two MOSFETs, a P-type MOS transistor (PMOS) and an N-type MOS transistor (NMOS), are connected in series. The source terminal of the PMOS transistor is connected to the power supply voltage (VDD), and the source terminal of the NMOS transistor is connected to ground (VSS). The drain terminals of both are connected to a common output terminal, and the inverter's output signal is taken from this output terminal.

[0015] Such MOSFETs may experience aging degradation such as NBTI (Negative Bias Temperature Instability) degradation and HCI (Hot Carrier Injection) degradation. These degradation phenomena can reduce the current supply capability of the MOSFET.

[0016] This will be explained with reference to Figures 3 and 4. Figure 3 is a graph showing the change in the current waveform. The vertical axis represents the current value I, and the horizontal axis represents time t, comparing the difference in voltage waveforms before and after aging.

[0017] In waveform W1, before aging degradation, the MOSFET maintains its normal current supply capability, resulting in a high peak value for current consumption and a waveform with sharp rise and fall times. On the other hand, in waveform W2, after aging degradation, the current supply capability of the MOSFET has decreased due to the aging phenomenon. As a result, the slope of the current consumption becomes gentler, and the peak value of the current consumption decreases.

[0018] Figure 4 is a graph showing the change in voltage waveform. The vertical axis represents the voltage value V, and the horizontal axis represents time t, showing the difference in voltage drop before and after aging degradation.

[0019] In waveform W1, before aging degradation, the MOSFET maintains normal operation, resulting in a deep instantaneous voltage drop and small fluctuation range. It can also be seen that the voltage quickly returns to the VDD value. On the other hand, in waveform W2, after aging degradation, the depth of the voltage drop decreases, the time it takes for the voltage to return to the VDD value increases, and the slope during the voltage drop becomes gentler.

[0020] These effects may reduce the operating speed of the combinational logic circuit LC shown in Figure 1. As a result, a setup error may occur in the second flip-flop F2, potentially leading to a malfunction of the semiconductor chip.

[0021] To prevent this, it is preferable to monitor at least one of the current and voltage flowing through the internal circuitry of the semiconductor chip. The reason for this will be explained with reference to Figure 5. Figure 5 is a circuit diagram showing the current monitoring location. This figure shows an example of current monitoring between the semiconductor chip 1, the package 41, and the PCB substrate (printed circuit board) 42.

[0022] A digital circuit 1d is configured within the semiconductor chip 1, and a current i flows from VDD to VSS.

[0023] Package 41 plays the role of connecting the semiconductor chip 1 and the PCB substrate 42, providing a path for signal transmission and power supply. Parasitic components such as inductance (L) and capacitance (C) may be present in this part, which can affect the frequency characteristics of the current.

[0024] A bypass capacitor 421 is placed on the PCB board to stabilize the power supply voltage. Current monitoring on the PCB board is important for understanding the total system current consumption, but when monitoring the current outside of the semiconductor chip 1, the parasitic LC configuration present in the package 41 and PCB board 42 acts as a low-pass filter, attenuating high-frequency current components. This makes it difficult to accurately monitor the current waveform generated at the end of the semiconductor chip 1.

[0025] This will be explained with reference to Figure 6. Figure 6 is a graph showing a comparison of the results of monitoring current inside and outside the semiconductor chip. The vertical axis represents the current value I, and the horizontal axis represents time t. The solid line shows the monitoring results inside the semiconductor chip, and the dashed line shows the monitoring results outside the semiconductor chip.

[0026] The solid lines show the monitoring results inside the semiconductor chip, reflecting accurate current waveforms that include high-frequency components. This makes it possible to understand the detailed changes in current in real time in response to the operating state of the digital circuit and load fluctuations.

[0027] On the other hand, the monitoring results outside the semiconductor chip, shown by the dashed line, reveal that the high-frequency components of the current waveform are significantly attenuated. This is because the LC circuit parasitic between the semiconductor chip 1 and the PCB substrate 42 acts as a low-pass filter, reducing the high-frequency components. As a result, the current waveform becomes smoother and does not accurately reflect the actual current fluctuations occurring within the semiconductor chip 1.

[0028] This comparison clearly shows that current monitoring outside the semiconductor chip is difficult due to the loss of high-frequency components. In particular, direct monitoring within the semiconductor chip is essential for detecting the effects of circuit aging and other factors. While this example uses current, the same principle applies to voltage.

[0029] This technology employs current and voltage monitoring techniques within the semiconductor chip, enabling accurate measurement of waveforms, including high-frequency components. This improves the operational reliability of the circuit.

[0030] [(2) Overall Configuration] This technology provides a semiconductor chip that monitors at least one of the current and voltage flowing inside the chip for fault detection and fault prediction of the internal circuit, and outputs a fault detection signal or a fault prediction signal based on the monitoring results.

[0031] An example of the configuration of a semiconductor chip according to one embodiment of this technology will be described with reference to Figure 7. Figure 7 is a block diagram showing an example of the configuration of a semiconductor chip 1 according to one embodiment of this technology.

[0032] As shown in Figure 7, the semiconductor chip 1 includes, for example, current monitoring circuits (analog circuit current monitoring circuit 11 and digital circuit current monitoring circuit 12), voltage monitoring circuits (analog circuit voltage monitoring circuit 13 and digital circuit voltage monitoring circuit 14), data processing circuit 15, threshold determination circuit 16, error reporting circuit 17, memory circuit 18, and host interface 19.

[0033] The analog circuit current monitor circuit 11 is a circuit that detects the switching current flowing through the analog circuit 1a with high precision. The analog circuit current monitor circuit 11 monitors the current flowing through the analog circuit 1a in real time and outputs the value as a current waveform.

[0034] The digital circuit current monitor circuit 12 is a circuit that detects switching current and other currents flowing through the digital circuit 1d with high precision. The digital circuit current monitor circuit 12 monitors the current flowing through the digital circuit 1d in real time and outputs the value as a current waveform.

[0035] The analog circuit current monitor circuit 11 is optimized to accurately capture relatively low-frequency switching currents, while the digital circuit current monitor circuit 12 is designed to detect high-frequency current fluctuations corresponding to high-speed clocks.

[0036] The above describes the components related to electric current. A similar configuration applies to voltage.

[0037] The analog circuit voltage monitor circuit 13 is a circuit that detects gradual voltage fluctuations and sudden spike voltages in the analog circuit 1a with high precision. The analog circuit voltage monitor circuit 13 monitors the voltage in the analog circuit 1a in real time and outputs the value as a voltage waveform.

[0038] The digital circuit voltage monitor circuit 14 is a circuit that detects sharp voltage fluctuations caused by high-speed clock and switching operations in the digital circuit 1d. The digital circuit voltage monitor circuit 14 monitors the voltage in the digital circuit 1d in real time and outputs the value as a voltage waveform.

[0039] This configuration allows the semiconductor chip 1 to monitor at least one of the current and voltage flowing inside it. The monitored current and voltage include both digital and analog signals.

[0040] The data processing circuit 15 is a central processing circuit that analyzes signals transmitted from the current monitoring circuit and the voltage monitoring circuit and detects abnormalities. This circuit performs tasks such as calculating the rate of change over time and extracting the maximum and minimum values.

[0041] The threshold determination circuit 16 is a module that determines whether or not there is an abnormality based on the analysis results of the data calculation circuit 15. This circuit compares the value with a reference value (threshold) and sends a signal to the subsequent circuit if an abnormality is detected.

[0042] The error reporting circuit 17 is a circuit that generates a fault detection signal or a fault prediction signal based on the signal from the threshold determination circuit 16. The generated signal is transmitted to an external host device. In other words, the error reporting circuit 17 outputs a fault detection signal or a fault prediction signal based on the monitoring results.

[0043] The memory circuit 18 stores reference values, profile data, and analysis results used for signal analysis and judgment. This stored data is used for data processing and threshold determination.

[0044] The host interface 19 is a module that manages communication between the semiconductor chip 1 and an external host device. This interface receives abnormality notifications and external control signals, and ensures the cooperation of the entire chip.

[0045] [(3) Operation of the Semiconductor Chip] Fig. 8 is a flowchart showing an example of the operation process of the semiconductor chip 1 according to an embodiment of the present technology. Based on this flowchart, the operation in which the semiconductor chip 1 monitors current and voltage and outputs a fault detection signal or a fault prediction signal will be described in detail below.

[0046] First, at step S11, monitoring of current and voltage is performed. The current monitor circuit and the voltage monitor circuit operate to monitor the current and voltage of the analog circuits and digital circuits inside the semiconductor chip 1 in real time. The monitored signal is converted from analog to digital and transmitted to the data arithmetic circuit 15.

[0047] Next, at step S12, data arithmetic operation is performed. The data arithmetic circuit 15 calculates the monitored data and calculates the maximum value, minimum value, average value, rate of change over time (di / dt, dv / dt), etc. of the current and voltage. These data are transmitted to the threshold determination circuit 16 to determine the presence or absence of an abnormality.

[0048] Next, at step S13, threshold determination is performed. The threshold determination circuit 16 determines how much the monitored value deviates from the reference value based on the analysis result. This determination may be made based on, for example, a set first threshold (omen level) and a second threshold (serious abnormality level). The determination result is transmitted to the error report circuit 17 as a fault prediction signal in the case of the omen level and as a fault detection signal in the case of a serious abnormality.

[0049] Finally, at step S14, the error report circuit 17 generates a notification signal based on the determination result. This notification signal is transmitted to the external host device via the host interface 19.

[0050] [(4) Current monitoring circuit] Returning to the explanation of Figure 7, the current monitoring circuit monitors fluctuations in the current flowing inside the semiconductor chip 1 in real time and generates basic data for analysis by the data calculation circuit 15.

[0051] The analog circuit current monitor circuit 11 is designed to accurately measure switching current and gradual current changes associated with the operation of the analog circuit, and includes components such as a mutual inductance structure 111, an amplification circuit 112, and an A / D conversion circuit 113.

[0052] The mutual inductance structure 111 consists of a low-inductance primary coil connected in series with the power line of the analog circuit, and a secondary coil that generates an induced electromotive force. The primary coil generates a magnetic field associated with continuous current changes, and the secondary coil senses this change and outputs an induced signal.

[0053] The amplification circuit 112 amplifies the weak induced electromotive force generated in the secondary coil and converts it into a signal level that can be processed by the subsequent circuit.

[0054] The A / D conversion circuit 113 converts analog signals into digital data. This circuit has a configurable sampling rate and resolution, generating accurate digital data of current waveforms. For analog circuits, it operates at a relatively low sampling frequency (tens of megasamples per second) to accurately capture gradual current fluctuations. The generated data is then sent to subsequent processing circuits.

[0055] The current monitoring circuit can be realized, for example, by applying and improving the technology disclosed in the non-patent document "Toru Nagura, Makoto Ikeda, Kunihiro Asada, "Di / dt Measurement Circuit Core for LSI Power Supply" (URL: http: / / silicon.u-tokyo.ac.jp / ~nakura / pdfFiles / ipaward05proc.pdf)".

[0056] The current monitoring circuit 12 for digital circuits is designed to detect sharp current fluctuations caused by high-speed switching and includes components such as a mutual inductance structure 121, an amplification circuit 122, and an A / D conversion circuit 123.

[0057] The mutual inductance structure 121 consists of a high-inductance primary coil connected in series with the power supply line of the digital circuit, and a secondary coil that generates an induced electromotive force. To improve high-frequency response, it is preferable to design the structure to minimize the effects of parasitic inductance and capacitance.

[0058] The amplification circuit 122 is a circuit that amplifies the signal from the secondary coil, and uses an operational amplifier or similar device with high-speed response capabilities.

[0059] The A / D conversion circuit 123 converts analog signals into digital data. This circuit has a configurable sampling rate and resolution, and generates accurate digital data of voltage waveforms. It is preferable to employ an A / D conversion circuit with a sampling frequency that supports high-speed operation.

[0060] [(5) Voltage monitoring circuit] The voltage monitoring circuit monitors voltage fluctuations inside the semiconductor chip 1 in real time and generates basic data for analysis by the data calculation circuit 15.

[0061] The analog circuit voltage monitor circuit 13 includes a probing circuit 131, a voltage amplification circuit 132, a filter circuit 133, an A / D conversion circuit 134, a timing generation circuit 135, and a data buffer 136, among others.

[0062] The probing circuit 131 employs a high-impedance design to faithfully acquire the input voltage and incorporates a source follower circuit. This makes it possible to minimize the load while maintaining signal accuracy.

[0063] The voltage amplification circuit 132 amplifies the voltage signal acquired by the probing circuit 131, and employs a low-noise amplifier with high linearity. This makes it possible to accurately detect even minute voltage fluctuations.

[0064] The filter circuit 133 removes, for example, high-frequency noise. The cutoff frequency can be adjusted according to the characteristics of the analog circuit, and by effectively removing unwanted high-frequency components, it improves signal quality.

[0065] The A / D conversion circuit 134 uses a high-resolution (e.g., 16-bit) conversion accuracy to convert analog signals into accurate digital data. This enables high-precision signal supply to the data processing circuit 15.

[0066] The timing generation circuit 135 generates a highly accurate timing signal and achieves equally spaced sampling. The timing resolution is, for example, 5 picoseconds, allowing for precise tracking of gradual fluctuations within the analog circuit.

[0067] The data buffer 136 temporarily stores the data output from the A / D conversion circuit 134, enabling efficient data transmission to the data processing circuit 15.

[0068] Similarly, the voltage monitor circuit 14 for digital circuits also includes a probing circuit 141, a voltage amplification circuit 142, a filter circuit 143, an A / D conversion circuit 144, a timing generation circuit 145, and a data buffer 146.

[0069] The probing circuit 141 employs a low-impedance structure capable of handling steep switching voltages. This structure makes it possible to accurately capture the high-speed voltage changes characteristic of digital circuits. For analog circuits, a source follower circuit may be used in the probing circuit to faithfully reflect the input voltage.

[0070] The voltage amplification circuit 142 employs a wideband amplifier to achieve high-speed operation. This allows for amplification and detection of rapid voltage fluctuations caused by high-speed clock operation.

[0071] The filter circuit 143 includes a low-pass filter that allows for precise adjustment of high-frequency components. The cutoff frequency is optimized according to the switching characteristics of the digital circuit to remove noise associated with high-speed operation.

[0072] The A / D conversion circuit 144 is designed to achieve high-speed sampling (e.g., several hundred MS / s). This allows for real-time digitization of sharp voltage changes within the digital circuit, improving the accuracy of fault detection.

[0073] To accommodate high-speed switching voltages, the timing generation circuit 145 has an extremely short timing resolution (e.g., 1 picosecond). This makes it possible to track the high-speed operation unique to digital circuits.

[0074] The data buffer 146 temporarily stores the high-speed data transmitted from the A / D conversion circuit 144 and supplies it stably to the data processing circuit 15, thereby preventing data loss.

[0075] The voltage monitoring circuit can be realized, for example, by applying and improving the technology disclosed in the non-patent document "Takushi Hashida, Makoto Nagata, "An On-Chip Waveform Capturer and Application to Diagnosis of Power Delivery in SoC Integration," IEEE Journal of Solid-State Circuits, vol. 46, no. 4, pp. 789-796, April 2011."

[0076] [(6) Data Calculation Circuit] The data calculation circuit 15 analyzes the data sent from the current monitor circuit and the voltage monitor circuit. Based on the time-series data of current and voltage, the data calculation circuit 15 calculates the maximum value, minimum value, and average value.

[0077] In the data processing circuit 15, current and voltage signals transmitted from the monitor circuit are collected at predetermined intervals (for example, several clock cycles, several seconds, or 1 hour period). The maximum and minimum values ​​are extracted from the data recorded within this period and stored in the memory circuit 18, which is the recording medium. Furthermore, a process is performed to calculate the average value based on these maximum and minimum values.

[0078] This will be explained with reference to Figure 9. Figure 9 is a waveform diagram showing the results of monitoring the current inside a semiconductor chip 1 according to one embodiment of this technology. This waveform diagram visually shows the maximum, minimum, average, and rate of change over time of the monitored value within a predetermined period. The vertical axis represents the value of the monitored current (unit: milliamperes). The horizontal axis represents time (unit: seconds), and shows the fluctuations within the predetermined period during which monitoring was performed. The solid line in the figure shows the real-time fluctuation of the current monitored within the predetermined period, and the amplitude and shape of the waveform reflect the load conditions and switching state during circuit operation.

[0079] Figure 9A shows the waveform of semiconductor chip 1 at the time of shipment, and Figure 9B shows the waveform after aging. In Figure 9A, the peak values ​​within a predetermined period are 100mA, 101mA, 102mA, and 99mA. The data calculation circuit 15 extracts the maximum value of 102mA from these peak values ​​and further calculates 101mA as the average of these peak values. This maximum value is calculated, for example, at a point in the waveform where the time change is close to zero.

[0080] Furthermore, the trough values ​​within a predetermined period are 11 mA, 12 mA, 13 mA, and 10 mA. The data calculation circuit 15 extracts the minimum value of 10 mA from these trough values ​​and then calculates 12 mA as the average value of these trough values. This minimum value is calculated, for example, at a point in the waveform where the time change is close to zero.

[0081] Furthermore, the data calculation circuit 15 has the function of calculating the rate of change of current over time (di / dt) based on the acquired waveform data. The time interval for calculating the rate of change over time, i.e., the sampling time, can be set in the range of, for example, tens of picoseconds to several nanoseconds. This high-precision sampling makes it possible to capture minute changes and signs of abnormalities.

[0082] On the other hand, in the waveform after aging degradation shown in Figure 9B, the peak values ​​within a predetermined period are 80 mA, 81 mA, 83 mA, and 82 mA. The data calculation circuit 15 extracts the maximum value of 83 mA from these peak values ​​and then calculates 81 mA as the average of these peak values.

[0083] Furthermore, the trough values ​​within the predetermined period are 8mA, 8mA, 9mA, and 8mA. The data calculation circuit 15 extracts the minimum value of 8mA from these trough values ​​and then calculates 8mA as the average value of these trough values. This decrease in the maximum, minimum, and average values ​​reflects changes in load conditions and circuit characteristics due to aging.

[0084] Other monitoring results will be explained with reference to Figure 10. Figure 10 is a waveform diagram showing the current monitoring results inside the semiconductor chip 1 according to one embodiment of this technology. Figure 10A shows the waveform of the semiconductor chip 1 under normal conditions, and Figure 10B shows the waveform when affected by external noise.

[0085] In Figure 10A, the peak values ​​within a predetermined period are 100 mA, 101 mA, 102 mA, and 99 mA. The data calculation circuit 15 extracts the maximum value of 102 mA from these peak values, and then calculates 101 mA as the average of these peak values.

[0086] Furthermore, the trough values ​​within the predetermined period are 11 mA, 12 mA, 13 mA, and 10 mA. The data calculation circuit 15 extracts the minimum value of 10 mA from these trough values, and then calculates 12 mA as the average value of these trough values.

[0087] On the other hand, in the waveform affected by disturbance noise shown in Figure 10B, the peak values ​​within a predetermined period are 133 mA, 101 mA, 110 mA, and 102 mA. The data calculation circuit 15 extracts the maximum value of 133 mA from these peak values, and then calculates 108 mA as the average of these peak values.

[0088] Furthermore, the trough values ​​within the predetermined period are 11 mA, 12 mA, 13 mA, and 10 mA. The data calculation circuit 15 extracts the minimum value of 10 mA from these trough values ​​and then calculates 12 mA as the average value of these trough values.

[0089] Based on these results, the significant increase in the peak value in Figure 10B (maximum value of 133 mA) is estimated to be due to the influence of disturbance noise. By comparing it with a threshold, it becomes possible to quantitatively evaluate the influence of disturbance noise on the current characteristics. Such analysis results are used as important information for fault detection and fault prediction.

[0090] Figures 9 and 10 show waveforms of current monitoring results, and the same can be said for voltage. Figure 11 is a waveform diagram showing the voltage monitoring results inside a semiconductor chip 1 according to one embodiment of this technology. The vertical axis represents the voltage value (unit: millivolts) being monitored. The horizontal axis represents time (unit: seconds), showing fluctuations within a predetermined period during which monitoring was performed. Figure 11A shows the waveform of the semiconductor chip 1 at the time of shipment, and Figure 11B shows the waveform after aging.

[0091] In Figure 11A, the peak values ​​within a predetermined period are 1101 mV, 1104 mV, 1095 mV, and 1098 mV. The data calculation circuit 15 extracts the maximum value of 1104 mV from these peak values ​​and then calculates 1100 mV as the average of these peak values.

[0092] Furthermore, the trough values ​​within the predetermined period are 1001 mV, 1003 mV, 1011 mV, and 1009 mV. The data calculation circuit 15 extracts the minimum value of 1001 mV from these trough values ​​and then calculates 1006 mV as the average value of these trough values.

[0093] Furthermore, the data calculation circuit 15 has the function of calculating the rate of change of voltage over time (dv / dt) based on the acquired waveform data. The time interval for calculating the rate of change over time, i.e., the sampling time, can be set in the range of, for example, tens of picoseconds to several nanoseconds. This high-precision sampling makes it possible to capture minute changes and signs of abnormalities.

[0094] On the other hand, in the waveform after aging degradation shown in Figure 11B, the peak values ​​within a predetermined period are 1201 mV, 1204 mV, 1195 mV, and 1198 mV. The data calculation circuit 15 extracts the maximum value of 1204 mV from these peak values ​​and further calculates 1200 mV as the average of these peak values.

[0095] Furthermore, the trough values ​​within the predetermined period are 1099 mV, 1102 mV, 1093 mV, and 1096 mV. The data calculation circuit 15 extracts the minimum value of 1093 mV from these trough values ​​and then calculates 1098 mV as the average value of these trough values.

[0096] Changes in these values ​​reflect changes in load conditions and circuit characteristics due to aging. As aging occurs, phenomena such as a decrease in the drive current of a MOSFET can be observed. This decrease in drive current means that the current value within the circuit becomes smaller, which reduces the voltage drop due to the resistance components of the wiring and connections. In other words, the voltage is maintained within a predetermined range without dropping significantly.

[0097] Other monitoring results will be explained with reference to Figure 12. Figure 12 is a waveform diagram showing the voltage monitoring results inside the semiconductor chip 1 according to one embodiment of this technology. Figure 12A shows the waveform of the semiconductor chip 1 under normal conditions, and Figure 12B shows the waveform when affected by external noise.

[0098] In Figure 12A, the peak values ​​within a predetermined period are 1201 mV, 1204 mV, 1195 mV, and 1198 mV. The data calculation circuit 15 extracts the maximum value of 1204 mV from these peak values ​​and then calculates 1200 mV as the average of these peak values.

[0099] Furthermore, the trough values ​​within the predetermined period are 1099 mV, 1102 mV, 1093 mV, and 1096 mV. The data calculation circuit 15 extracts the minimum value of 1093 mV from these trough values ​​and then calculates 1098 mV as the average value of these trough values.

[0100] On the other hand, in the waveform affected by disturbance noise shown in Figure 12B, the peak values ​​within a predetermined period are 1201 mV, 1204 mV, 1195 mV, and 1198 mV. The data calculation circuit 15 extracts the maximum value of 1204 mV from these peak values ​​and further calculates 1200 mV as the average of these peak values.

[0101] Furthermore, the trough values ​​within the predetermined period are 960mV, 1090mV, and 1110mV. The data calculation circuit 15 extracts the minimum value of 960mV from these trough values ​​and then calculates 1040mV as the average value of these trough values.

[0102] Based on these results, the significant decrease in the trough value in Figure 12B (minimum value 960 mV) is estimated to be due to the influence of disturbance noise. By comparing it with a threshold, it becomes possible to quantitatively evaluate the effect of disturbance noise on the current characteristics. Such analysis results are used as important information for fault detection and fault prediction.

[0103] The analysis results described above provide crucial information for detecting aging degradation and external noise, enabling reliable fault detection and prediction. This data is used in subsequent processing to generate fault detection signals and fault prediction signals.

[0104] The data processing circuit 15 can be designed as a dedicated digital circuit, but it can also be implemented in software using an FPGA or microcontroller.

[0105] [(7) Threshold determination circuit] The threshold determination circuit 16 is a circuit for determining the presence and nature of an abnormality based on the analysis data transmitted from the data calculation circuit 15. This analysis data includes the maximum, minimum, and average values ​​of current and voltage, or the rate of change over time.

[0106] The threshold determination circuit 16 compares the received analysis data with a reference value (hereinafter also referred to as the "threshold") in real time and determines an anomaly based on the result. This reference value is optimized based on simulation or evaluation tests according to the design specifications and operating conditions of the semiconductor chip and is stored in the memory circuit 18.

[0107] The threshold determination circuit 16 performs fault detection and fault prediction based on the current and voltage monitoring results.

[0108] Thresholds are set based on simulations or evaluation tests and stored within the semiconductor chip. For threshold setting, for example, the semiconductor chip is operated before shipment, and voltage and current profiles are obtained using current and voltage monitoring circuits. Based on these profiles, thresholds are set by taking into account the allowable fluctuations (e.g., values ​​obtained from simulations during design, or values ​​based on malfunctions and operating speed degradation). In this case, the specified fluctuation amount may be set based on values ​​predicted during design (e.g., 8% to 20%). Furthermore, for instantaneous voltage fluctuations, the allowable voltage fluctuation amount specified in the semiconductor chip's specifications (e.g., VDD = 1.1V to 1.2V) can be used as a reference.

[0109] Regarding the determination of an anomaly, the threshold determination circuit 16 compares the maximum value and at least one of the maximum values ​​transmitted from the data calculation circuit 15 with a threshold value to determine whether a fault has been detected or predicted. Alternatively, the threshold determination circuit 16 compares the average value calculated based on the maximum and minimum values ​​with a threshold value to determine whether a fault has been detected or predicted. Alternatively, the threshold determination circuit 16 compares the rate of change over time with a threshold value to determine whether a fault has been detected or predicted.

[0110] The threshold determination circuit 16 determines that a fault is detected if the analysis data exceeds a threshold, and determines that a fault is predicted if the fluctuation is within a predetermined range. Fault detection is determined when the analysis data exceeds a set predetermined amount of fluctuation. Fault prediction is determined when a fluctuation is observed that is smaller than the fluctuation amount defined for fault detection (for example, a range of about 1% to 2% smaller).

[0111] Figure 13 is a flowchart showing an example of the processing flow of a semiconductor chip 1 according to one embodiment of this technology. This flowchart includes monitoring processing and threshold determination processing during the operation of the semiconductor chip 1, and visually represents the fault detection and fault prediction processes.

[0112] First, in step S21, the semiconductor chip 1 is started up. In this step, the monitor circuit is set to an operational state.

[0113] Next, in step S22, current and voltage monitoring is performed for one cycle. The current and voltage values ​​during this cycle are monitored in real time and used for subsequent processing.

[0114] Next, in step S23, the monitored current or voltage value is compared with the stored value (e.g., maximum or minimum value) stored in the memory circuit 18. If updating the stored value is necessary, the maximum or minimum value is updated in step S24. Specifically, if the current monitored value is greater than the stored value, the maximum value is updated; if it is smaller, the minimum value is updated. If updating the stored value is not necessary, the maximum or minimum value is not updated.

[0115] Next, in step S25, a comparison is performed between the stored value and the set threshold. The maximum and minimum values ​​stored in the memory circuit 18 are compared with the set threshold. In the comparison process, the difference between the maximum or minimum value stored in the memory circuit 18 and the threshold is calculated, and it is determined whether the difference falls within a predetermined range.

[0116] If it is determined that a signal output is necessary, a signal output is performed in step S27. Fault detection signals and fault prediction signals are generated according to the set conditions and notified to an external host device. These signals are used by the external system to monitor the operating status of the semiconductor chip in real time.

[0117] For example, if the difference is less than 8% of the threshold, neither the fault prediction signal nor the fault detection signal will be output. If the difference is between 8% and 10% of the threshold, the fault prediction signal will be output, but the fault detection signal will not. If the difference is 10% or more of the threshold, the fault prediction signal will not be output, but the fault detection signal will be output.

[0118] If it is determined in step S25 that a signal output is not needed, the process transitions to the next cycle of current monitoring in step S26. Once the current monitoring process for one cycle is completed, the process proceeds to the next cycle. This enables real-time monitoring of current fluctuations within a certain period. The processes in steps S22 to S26 are repeatedly executed over a predetermined period.

[0119] While this flowchart explains the maximum and minimum values ​​of current and voltage, it also applies to average values ​​and rates of change over time.

[0120] The threshold determination circuit 16 can be configured with multiple threshold levels, and three or more threshold levels may be set. In that case, for example, the first threshold may be set as the upper limit of the normal range, the second threshold as the warning level, and the third threshold as the severe abnormality level. This enables fine-grained determination according to the severity of the abnormality, and operations such as the following can be realized.

[0121] If the value is below the first threshold, the system will continue normal operation and no anomaly detection will be performed.

[0122] If the reading exceeds the first threshold but falls below the second threshold, it is judged to be a warning level. At this stage, it is determined that there is no serious abnormality, but the operating status needs to be continuously monitored.

[0123] If the value exceeds the second threshold but falls below the third threshold, an anomaly is detected, and a fault prediction signal is generated. This increases the likelihood of avoiding serious failures by taking preventative measures.

[0124] If the level exceeds the third threshold, a serious anomaly is detected, and a fault detection signal is immediately generated. This signal triggers emergency responses such as system shutdown or transition to protection mode.

[0125] By setting thresholds in this multi-stage manner, the threshold determination circuit 16 enhances the reliability of the system and enables a quick and appropriate response in the event of an abnormality.

[0126] Furthermore, the threshold determination circuit 16 can compare the monitoring results stored on the recording medium with past data to evaluate the tendency for abnormalities to occur, and make a determination as fault detection or fault prediction based on the evaluation result. This function contributes to the early detection of faults and the realization of preventive maintenance.

[0127] The processing of the threshold determination circuit 16 will be explained with reference to Figure 14. Figure 14 is a flowchart showing an example of the processing flow of the threshold determination circuit 16 according to one embodiment of this technology.

[0128] As shown in Figure 14, first, in step S31, the threshold determination circuit 16 selects the target period. The threshold determination circuit 16 extracts data from the data stored on the recording medium for the period necessary to evaluate the abnormal trend. This period is set to a time width suitable for analyzing the abnormal trend (for example, the most recent few minutes or a few hours).

[0129] Next, in step S32, the threshold determination circuit 16 calculates feature quantities (maximum value, minimum value, average value, and rate of change over time) based on the extracted data.

[0130] Finally, in step S33, the threshold determination circuit 16 compares the current data with past data and analyzes the trend of change. In this analysis, for example, calculations of moving averages or trend lines for time series data are applied.

[0131] Regarding the calculation of the moving average, the threshold determination circuit 16 calculates the moving average for the time series data at regular intervals of a certain number of samples. This moving average is used to smooth out short-term fluctuations and visualize the overall trend. For example, if the window width of the moving average is set to 10 samples, the average value of the most recent 10 points at each sample point is calculated sequentially.

[0132] The threshold determination circuit 16 may generate a trend line by applying linear regression analysis or the like based on the results of the moving average. This trend line quantitatively shows the overall increase or decrease trend of the time series data. If the slope (gradient) of the trend line is positive, it is judged that the value is increasing, and if it is negative, it is judged that the value is decreasing.

[0133] Alternatively, the threshold determination circuit 16 can compare the current data with past data and evaluate the characteristics of the fluctuations. For example, if the data shows a periodic waveform, it can analyze the change in that periodicity.

[0134] This function allows for accurate assessment of the occurrence trend before an anomaly progresses. In particular, if a continuous increase in the maximum value or rate of change over time, or a change exceeding a baseline value is observed, it becomes possible to detect early signs of anomalies. By continuously monitoring the occurrence trend, this technology prevents serious failures and significantly improves the reliability and safety of the system.

[0135] Let's explain an example of operation. For example, if the normal current value is a maximum of 102 mA, a minimum of 10 mA, and an average of 101 mA, the system will determine whether there is an abnormality based on a set threshold (for example, a 20% fluctuation tolerance). If the measured value exceeds the threshold due to aging degradation or external noise, it will be treated as a fault detection. On the other hand, if the fluctuation falls within the predetermined range, it will be processed as a fault prediction.

[0136] The threshold determination circuit 16 can be designed as a dedicated digital circuit, but it can also be implemented in software using an FPGA or microcontroller.

[0137] [(8) Memory Circuit] The memory circuit 18 is a circuit for temporarily or permanently recording and storing the operation data and analysis data of the semiconductor chip 1. Specifically, the memory circuit 18 records analysis data such as the maximum value, minimum value, average value, and rate of change over time transmitted from the current monitor circuit and the voltage monitor circuit. Fault detection and fault prediction results generated by the data calculation circuit 15 and the threshold determination circuit 16 may also be recorded.

[0138] Furthermore, the memory circuit 18 stores the reference value (threshold) used in the threshold determination circuit 16. This reference value is optimized based on evaluation tests and simulation results performed before shipment and is set within the circuit. In addition, a configuration can be adopted that allows the threshold data to be updated via an external host device, taking into account aging degradation and environmental changes.

[0139] The memory circuit 18 records the voltage and current profiles during normal operation and may be used to set reference values ​​and improve the accuracy of anomaly detection. This allows for comparison between monitoring results and stored data, improving the accuracy of fault detection and prediction.

[0140] The memory circuit 18 may record and retain past operating data. This allows for the evaluation of trends in abnormal occurrences and signs of aging deterioration by comparing them with current data, enabling future preventive maintenance.

[0141] The memory circuit 18 provides data to the data processing circuit 15 and the threshold determination circuit 16 in real time, and may overwrite existing data with new data as needed.

[0142] The memory circuit 18 is implemented using a storage medium such as volatile memory or non-volatile memory. Volatile memory (e.g., SRAM, DRAM) is used as a temporary storage area where high-speed data access is required. Non-volatile memory (e.g., flash memory, MRAM) is used to retain data even when the power supply is interrupted.

[0143] [(9) Error Report Circuit] The error report circuit 17 is a circuit that generates a fault detection signal or a fault prediction signal based on the signal transmitted from the threshold determination circuit 16 and notifies an external host device.

[0144] The error reporting circuit 17 generates a fault detection signal based on the signal from the threshold determination circuit 16 when the abnormality exceeds a threshold. This signal is used to promptly notify of serious system abnormalities.

[0145] The error reporting circuit 17 generates a fault prediction signal when the abnormality fluctuates within a predetermined range. This enables the detection of potential problems during system operation and facilitates preventive maintenance.

[0146] The generated signal may include additional information such as the type of anomaly (e.g., overcurrent, overvoltage), maximum and minimum values, rate of change over time, and average value. This information, which is communicated to external devices, is used for system analysis and maintenance.

[0147] The error reporting circuit 17 can be designed as a dedicated digital circuit, but it can also be implemented in software using an FPGA or microcontroller.

[0148] [(10) Host Interface] The host interface 19 is a module for managing communication between the semiconductor chip 1 and an external host device, and is equipped with the function of receiving abnormality notifications and control signals from the outside.

[0149] The host interface 19 transmits fault detection signals and fault prediction signals generated by the error reporting circuit 17 to an external host device. The host interface 19 can also transmit monitoring results (e.g., maximum value, minimum value, average value, or rate of change over time) as needed.

[0150] The host interface 19 can also receive configuration change commands and reset commands from an external host device, and can switch the operating mode within the semiconductor chip. This includes, for example, updating thresholds and changing data acquisition intervals.

[0151] The host interface 19 can also notify the host device of detailed information (type of anomaly, time of occurrence, scope of impact, etc.) if an anomaly is detected. The error report may consist of data in text format or bit string format.

[0152] The host interface 19 can be designed as a dedicated digital circuit, but it can also be implemented in software using an FPGA or microcontroller.

[0153] [(11) Effects] The semiconductor chip using this technology can monitor instantaneous fluctuations in current and voltage with high precision, improving the accuracy of fault detection and fault prediction. In particular, it can quickly identify the effects of aging degradation and external noise, preventing serious failures that would cause system downtime.

[0154] This technology enables highly accurate fault prediction of semiconductor chips based on maximum, minimum, and average values ​​of current and voltage, as well as their time-dependent changes (di / dt, dv / dt). By notifying an external host device of the fault prediction signal, early maintenance can be performed, contributing to improved system uptime.

[0155] This technology enables the quantitative evaluation of the progression of degradation over time by continuously recording and analyzing the current and voltage waveforms within the semiconductor chip. This makes it possible to predict the appropriate maintenance timing based on the degradation status.

[0156] This technology enables semiconductor chips to notify external host devices of fault detection and prediction results, improving the overall system's anomaly monitoring capabilities. This collaboration with external host devices allows for rapid response in the event of an anomaly, reducing system downtime.

[0157] Semiconductor chips utilizing this technology precisely monitor the effects of noise, overcurrent, and overvoltage from the external environment within their internal circuits, enabling rapid response in the event of an anomaly. This is particularly beneficial for applications with harsh electromagnetic environments, such as automotive applications, improving the overall system stability.

[0158] Semiconductor chips utilizing this technology can record monitoring data and anomaly occurrence history in a memory circuit, enabling comparison with past data and analysis of long-term operational data. Analyzing anomaly trends based on the stored data can be useful for further technological improvements and the development of design guidelines.

[0159] The semiconductor chip based on this technology, equipped with current monitoring and voltage monitoring circuits, is applicable to both analog and digital circuits and can be mounted on a variety of semiconductor chips. Furthermore, it can be used in a wide range of applications, including imaging devices and power supply ICs (PMICs).

[0160] This technology enables flexible communication with external host devices via a host interface, allowing for rapid fault detection and configuration changes. By supporting standard communication protocols, it can be easily integrated while maintaining compatibility with existing systems.

[0161] This technology enables high-precision fault detection and prediction on semiconductor chips, improving the reliability, stability, and efficiency of the entire system. Due to the wide range of effects described above, it can be applied in various fields, including automobiles and industrial equipment, providing a high-value-added technological foundation.

[0162] The effects described herein are not necessarily limited and may be any of the effects described in this disclosure. Furthermore, the effects described herein will also occur in other embodiments described later.

[0163] The above description of the semiconductor chip according to the first embodiment of this technology can be applied to other embodiments of this technology, unless there are any particular technical inconsistencies.

[0164] [2. Second Embodiment of the Technology (Example 2 of a Semiconductor Chip)] The threshold determination circuit 16 has the function of determining fault detection or fault prediction by comparing it with the monitoring results using a learning model that has learned the current and voltage patterns under normal conditions. This learning model is built on operating data under normal conditions and improves the accuracy of fault detection and fault prediction performed by the threshold determination circuit 16. The learning model reflects the fluctuation patterns of current and voltage under normal conditions and includes features such as maximum value, minimum value, average value, and rate of change over time (di / dt and dv / dt).

[0165] The learning model is constructed based on a large amount of normal operation data aggregated on a cloud platform. Specifically, it is constructed based on the process shown in Figure 15. Figure 15 is a flowchart showing an example of the process for constructing a learning model used by a threshold determination circuit 16 according to one embodiment of this technology.

[0166] First, in the data acquisition step S41, current and voltage data are collected during normal operation of the semiconductor chip. Feature quantities are then extracted for each product group and operating condition.

[0167] Next, in the data aggregation step S42, the collected data is aggregated on the cloud to build a broad dataset that can handle different environments and load conditions.

[0168] Finally, in learning step S43, a machine learning algorithm is used to model normal operating patterns. Parameter optimization is performed to improve the accuracy of anomaly detection and prediction.

[0169] There are several specific implementation methods for the learning model used in the threshold determination circuit 16, and each model is applied according to specific applications and requirements. Examples of learning models that can be used in this technology are as follows.

[0170] First, there is a statistically based model. This model is built on statistical features such as the maximum, minimum, mean, and standard deviation of current and voltage recorded under normal conditions. This allows for the definition of normal baseline values ​​and the detection of abnormalities by comparing them with real-time monitoring results. Because this model employs a simple calculation algorithm, it is suitable for situations requiring real-time performance.

[0171] Next, there are time-series prediction models. These models predict trends based on past current and voltage data, and then predict anomalies and failures by comparing the predicted values ​​with current measurements. Specifically, methods such as moving averages and autoregressive models may be used. This method is suitable for more precise analysis of patterns that change over time.

[0172] Furthermore, machine learning-based models can also be applied. These models learn current and voltage data during normal operation as training data and detect anomalies by comparing them with new data. For example, algorithms such as support vector machines (SVMs) and random forests can be used to analyze the complex interrelationships of features. In addition, deep learning models using neural networks enable more advanced pattern recognition, improving the accuracy of fault prediction.

[0173] Furthermore, dynamic threshold models can also be utilized. This model dynamically adjusts the threshold based on the trend of measurement fluctuations and environmental conditions, rather than using a fixed threshold setting. This method is suitable for detecting anomalies while considering the influence of the actual operating environment, such as power supply conditions and temperature fluctuations.

[0174] These models can be flexibly selected and applied depending on their characteristics and applications. In particular, this technology combines simple statistical models with advanced cloud-learning and machine learning-based models to achieve both accuracy and flexibility in fault detection and prediction. This significantly improves the reliability of semiconductor chips.

[0175] The threshold determination circuit 16 analyzes the monitoring results in real time while referring to the learned model. It compares the feature quantities (maximum value, minimum value, average value, rate of change over time, etc.) with the normal pattern of the learned model and determines whether or not there is an abnormality according to the degree of agreement or deviation. If the deviation exceeds the threshold, it is determined to be a fault detection, and if the deviation is confirmed to be within a predetermined range, it is determined to be a fault prediction.

[0176] With this configuration, the threshold determination circuit 16 can perform fault detection and fault prediction quickly and with high accuracy by comparing the normal operating pattern with monitor data collected in real time. Furthermore, because the learning model is built on data aggregated on the cloud, it has versatility to handle different products and operating conditions.

[0177] The above description of the semiconductor chip according to the second embodiment of this technology can be applied to other embodiments of this technology, unless there are any particular technical inconsistencies.

[0178] [3. Third Embodiment of the Technology (Example of a Fault Detection System)] [(1) Overall Configuration] The technology provides a fault detection system comprising a semiconductor chip and a host device, wherein the semiconductor chip monitors at least one of the current and voltage flowing inside for fault detection and fault prediction of the internal circuit, outputs a fault detection signal or a fault prediction signal based on the monitoring results, and the host device determines whether or not to shut down the system based on the fault detection signal or the fault prediction signal.

[0179] The fault detection system of this technology will be described with reference to Figure 16. Figure 16 is a block diagram showing an example configuration of a fault detection system 100 according to one embodiment of this technology.

[0180] As shown in Figure 16, the fault detection system 100 includes a semiconductor chip 1 and a host device 101.

[0181] The semiconductor chip 1 monitors at least one of the current and voltage flowing inside it for fault detection and fault prediction of its internal circuits, and outputs a fault detection signal or a fault prediction signal based on the monitoring results. The internal structure of the semiconductor chip 1 may be as shown in Figure 7, for example.

[0182] The host device 101 performs various processes to ensure the safety of the system based on fault detection signals or fault prediction signals.

[0183] The semiconductor chip 1 can also transmit the internally analyzed monitoring results and processed data to the host device 101 as output data. For example, waveform data of current and voltage acquired by the current monitoring circuit and voltage monitoring circuit, or analysis results from the data calculation circuit, can be transmitted.

[0184] Furthermore, the semiconductor chip 1 has the function of receiving input signals from the host device 101, and the operation of the semiconductor chip 1 is controlled based on these input signals. Specifically, it is possible to switch the operating modes of the current monitor circuit and the voltage monitor circuit, or update the reference value (threshold) of the threshold determination circuit, through the input signals. This control allows the semiconductor chip to flexibly adapt to different applications and operating conditions.

[0185] Furthermore, communication with the host device 101 can be configured to be performed via wired communication or wireless communication. Also, the communication interface can use a general-purpose protocol (for example, I). ２ C, SPI, UART, etc., or dedicated protocols can be applied, and the most suitable communication method is selected according to the application.

[0186] The host device 101 can be configured as dedicated hardware integrating a signal receiving circuit and notification interface, for example, with an MPU (Micro Processing Unit) or FPGA at its core. In this case, real-time processing capabilities are enhanced, enabling rapid anomaly detection and system control.

[0187] Furthermore, the host device 101 may be implemented by software running on a general-purpose processor. In this case, the analysis algorithm and notification logic are designed as software, enabling the construction of a highly flexible system.

[0188] Alternatively, a configuration in which some of the notification and analysis functions of the host device 101 are executed on the cloud is also conceivable. In this case, abnormal data can be sent to the cloud, and more accurate countermeasures and maintenance timing estimates can be made based on large-scale data analysis.

[0189] [(2) System shutdown decision function] The host device 101 has a function to analyze the received signal and decide whether or not to shut down the system. This decision process is designed with the safety and efficiency of the system as the top priority and is realized by the processing flow shown in Figure 17, for example. Figure 17 is a flowchart showing an example of the processing flow of the host device 101 according to one embodiment of this technology.

[0190] First, in the "received signal classification" step S51, the host device 101 analyzes the signal received from the semiconductor chip 1 and determines whether it is a fault detection signal or a fault prediction signal.

[0191] Next, in step S52, "Evaluation of Anomaly Type and Severity," the host device 101 evaluates the severity of the anomaly based on the data associated with the signal (type of anomaly, location, time of occurrence, etc.). Anomaly types include overcurrent, overvoltage, overheating, and communication errors. Anomaly locations include specific circuit blocks or components that may have an impact. Anomaly time includes whether the anomaly is momentary or continuous.

[0192] Finally, in the "system shutdown determination" step S53, the host device 101 determines whether to continue or shut down the system based on the severity of the abnormality, etc.

[0193] For example, if the severity is "minor anomaly (such as a temporary overcurrent)," the host device 101 continues to operate the system and monitors the anomaly for its continuation. In this case, the host device 101 issues a warning to the user as needed.

[0194] If the severity is "moderate abnormality (such as repeated overvoltage)," the host device 101 temporarily suspends the system and attempts to recover. If recovery is unsuccessful, the host device 101 notifies the user.

[0195] If the severity level is "critical anomaly (such as overheating or short circuit)," the host device 101 prioritizes safety and immediately shuts down the system. The host device 101 generates a control signal to cut off the power supply to the entire system or disable specific components. This control signal is output at the timing necessary to protect semiconductor chips and peripheral circuits.

[0196] When the system shuts down, the host device 101 saves data about the incident to a recording medium. This record includes the signal value at the time of the incident, a timestamp, and details of the shutdown process. The recorded data is used for troubleshooting and maintenance planning after the system is restored.

[0197] After the system shuts down, the host device 101 notifies the user of the fact of the shutdown and its cause. The notification is made by various means, such as displaying a message on the display or by remote notification (e.g., push notification to a smartphone). The notification content includes the type of abnormality that led to the shutdown, the scope of the impact, and the recommended next action (e.g., attempting a restart, requesting maintenance, etc.).

[0198] [(3) Alert transmission function] The host device 101 can also send an alert to the user based on a fault detection signal or fault prediction signal, enabling the user to determine whether the system should shut down. This alert function is intended to ensure the safety of the entire system and to enable a rapid response, and includes a variety of means and configurations as follows:

[0199] The host device 101 outputs an alert sound using its built-in speaker or a connected external audio device. The type of alert sound varies depending on the severity of the anomaly; for example, a simple beep may be used for minor anomalies, while a continuous tone or high-frequency warning sound may be used for serious anomalies. This allows the user to immediately recognize the importance of the anomaly.

[0200] Furthermore, a detailed message regarding the anomaly can be displayed on the host device 101's display or a connected monitor. The message content includes the type of anomaly (e.g., overcurrent, overvoltage, overheating), the location where it occurred (e.g., a specific circuit block), the severity (e.g., minor, moderate, critical), and the recommended course of action (e.g., restart, component replacement, system shutdown). This allows the user to accurately understand the situation.

[0201] Alternatively, the host device 101 may also have the functionality to send anomaly information to remote devices (e.g., smartphones, tablets, PCs) via the cloud. This notification can be made via a dedicated app, email, SMS, etc. For example, based on anomaly data uploaded to the cloud, a push notification can be sent to a smartphone app, allowing the user to recognize the anomaly even when remote and consider appropriate action.

[0202] These notifications are not merely announcements of anomalies, but are designed to provide users with sufficient information to decide whether to shut down the system or continue operation. For example, if the anomaly is minor, the notification may include advice such as, "This will not affect the system's operation, but please check again during the next maintenance." On the other hand, if a serious anomaly is detected, an emergency response such as, "Immediately shut down the system and ensure safety" will be prompted.

[0203] [(4) Action Plan Determination Function] The host device 101 has a function to determine an action plan based on a fault detection signal or a fault prediction signal. This action plan determination is intended to ensure the safety and efficient operation of the entire system.

[0204] The host device 101 analyzes the content of the received signal to identify the type and severity of the anomaly. For example, it determines whether the current or voltage anomaly is due to overcurrent or overvoltage, or to the deterioration of circuit components. Based on this analysis, potential countermeasures are extracted, such as instructions to restart the system, suggestions for replacing specific components, or recommendations for maintenance of the entire system or a part of it.

[0205] If the abnormality is caused by deterioration or damage to a specific component, the host device 101 identifies that component and suggests replacing it. This process provides information such as the part number and location of the component that needs replacing, the tools and procedures required for component replacement, and whether re-diagnosis is necessary after component replacement. For example, if a capacitor in the power supply circuit is exhibiting abnormal behavior exceeding a specified value, the host device 101 suggests replacing that capacitor.

[0206] The implemented countermeasures and their results are stored on a recording medium within the host device 101 and can be used as reference in the event of subsequent malfunctions. This record includes, for example, the type of countermeasure, the date and time of implementation, and the system status after implementation.

[0207] [(5) Maintenance timing estimation function] The host device 101 has a function to estimate the maintenance timing for the entire system or specific components based on fault detection signals or fault prediction signals. This estimation is achieved by analyzing the collected monitoring results.

[0208] The host device 101 records and analyzes the frequency of specific anomalies. This analysis considers factors such as the interval between anomalies, the type of anomaly, and its severity. The host device 101 analyzes the time intervals between anomalies and determines that maintenance is approaching if anomalies occur frequently in a short period. For minor anomalies, the host device 101 observes the long-term trend, while prioritizing a rapid response for serious anomalies. For example, if an overcurrent occurs in a specific component five or more times, it is determined that there is a high probability that the component will need to be replaced soon.

[0209] The host device 101 determines whether a specific parameter is degrading based on the current and voltage fluctuation data obtained as monitoring results. Methods such as time series analysis, moving averages, and comparison with thresholds are used to analyze this degradation trend. Time series analysis is a method that analyzes current and voltage values ​​along a time axis to detect continuous increases or decreases. Moving average analysis is a method that smooths short-term fluctuations to identify long-term trends and evaluate the degree of degradation. Comparison with thresholds is a method that determines degradation is progressing if the values ​​exceed the acceptable range set in evaluation tests or simulations. For example, if a trend of the capacitor voltage dropping by more than 10% from the design value is observed, it is estimated that its replacement time is approaching.

[0210] The estimated maintenance timing is output through methods such as user notification, cloud integration, and logging. User notification displays the estimated maintenance timing and recommended work for each component on the display. Cloud integration sends the estimation results to the cloud, enabling remote verification and analysis. Logging records the estimated maintenance timing within the host device 101 and utilizes it for subsequent maintenance planning. For example, the user is provided with specific instructions such as "Perform the next maintenance within 90 days" for the cooling system.

[0211] [(6) Impact Scope Analysis Function] Based on the monitoring results, the semiconductor chip 1 classifies the cause when an abnormality occurs and transmits the classification result to the host device 101. Based on the classification result, the host device 101 analyzes the scope of the abnormality's impact and decides whether or not to shut down the system.

[0212] Semiconductor chip 1 analyzes the current and voltage monitoring results for fault detection and prediction of internal circuit failures, and if an abnormality is detected, it classifies the cause. This classification includes the type of abnormality, the location where the abnormality occurred, and the severity of the abnormality.

[0213] Types of anomalies include overcurrent, overvoltage, voltage drops, and current spikes. The location of the anomaly is identified as the specific circuit area where it occurred, such as analog circuits, digital circuits, or power supply circuits. The severity of the anomaly is ranked as "minor anomaly," "warning level," or "major anomaly" based on the scope of its impact and frequency of occurrence.

[0214] The classification results are transmitted to the host device 101 in data format. This transmission ensures that detailed information about the anomaly is conveyed quickly and accurately, allowing the host device 101 to take appropriate action based on this information.

[0215] The host device 101 receives the classification results transmitted from the semiconductor chip 1 and performs an analysis to evaluate the impact on the entire system. This analysis identifies the extent of the impact that a faulty circuit or component may have on other circuits and the entire system. For example, if an overvoltage occurs in the power supply circuit, the analysis determines the potential for that impact to cause malfunctions in other circuits and identifies the extent of that impact.

[0216] If the abnormality is limited to a specific component, the host device 101 will consider disconnecting that component. On the other hand, if a serious abnormality is detected, safety will be given top priority, and it will be determined that the entire system must be shut down, and the shutdown process will be executed immediately. For example, if an overcurrent is detected in the power supply circuit, the system will need to be shut down.

[0217] In the case of minor malfunctions, if the malfunction is limited to a part of the system, the host device 101 can disconnect the affected circuit or component and continue operation. Furthermore, in the case of predictable malfunctions, the host device 101 provides notification based on fault prediction, helping users and maintenance systems prepare appropriate responses.

[0218] Through this series of processes, the semiconductor chip 1 and the host device 101 work together to ensure the safety of the entire system, while also achieving efficient operation and improved reliability. By quickly and accurately classifying anomalies and analyzing the scope of their impact, it is possible to minimize system downtime and optimize responses to anomalies.

[0219] This technology enables real-time monitoring of the operating status of the internal circuits of the semiconductor chip 1, thereby improving the reliability of the entire system through fault detection and prediction. Furthermore, by utilizing abnormal signals from the host device 101, it is possible to determine the appropriate timing for system shutdown, notify users of alerts, propose countermeasures, estimate maintenance timing, and analyze the scope of impact, thus improving safety and operational efficiency.

[0220] The above description of the fault detection system according to the third embodiment of this technology can be applied to other embodiments of this technology, unless there are any particular technical inconsistencies.

[0221] [4. Examples of Application to Imaging Devices] Imaging devices are used in a wide range of fields, including cameras, surveillance systems, medical imaging devices, and automotive driver assistance systems. Their basic role is to convert light into electronic signals and provide high-precision image information. However, conventional imaging devices have had the following problems.

[0222] Due to aging degradation such as NBTI degradation and HCI degradation in the image sensor and peripheral circuit MOSFETs, the operating speed may decrease, and normal image processing may become impossible. In particular, aging degradation is often not immediately detected, and problems are only discovered when the failure becomes apparent.

[0223] Furthermore, imaging devices are susceptible to external noise such as electromagnetic waves, overcurrents, and overvoltages, which can cause distortion or loss in parts of the acquired image. This effect is particularly pronounced in imaging devices used in harsh electromagnetic environments such as automobiles.

[0224] Therefore, the semiconductor chip based on this technology can be applied to an imaging device. An example of the configuration of an imaging device to which the semiconductor chip of this technology is applied will be explained with reference to Figure 18. Figure 18 is a block diagram showing an example of the configuration of an imaging device 2 to which the semiconductor chip 1 of this technology is applied.

[0225] As shown in Figure 18, the imaging device 2 includes an image sensor 21, a lens unit 22, an analog signal processing circuit 23, an A / D conversion circuit 24, a digital signal processing circuit 25, a memory circuit 26, an output interface 27, a power supply circuit 28, and a control circuit 28, among others.

[0226] The image sensor 21 is a sensor for converting incident light into an electronic signal, and can be a CMOS sensor or a CCD sensor. The image sensor 21 includes a photoelectric conversion unit, a signal amplification unit, and a charge transfer unit. The semiconductor chip of this technology can be configured as this image sensor 21.

[0227] The lens unit 22 focuses light onto the image sensor 21. The lens unit 22 may also have a focus adjustment function and an optical zoom function.

[0228] The analog signal processing circuit 23 is a circuit that appropriately adjusts the analog signal output from the image sensor 21. The analog signal processing circuit 23 performs noise reduction, signal amplification, and color filtering.

[0229] The A / D conversion circuit 24 is a circuit that converts analog signals into digital signals. In order to efficiently process high-resolution image data, the A / D conversion circuit 24 is equipped with an appropriate sampling frequency and resolution.

[0230] The digital signal processing circuit 25 is a circuit that processes the A / D converted digital signal as image data. The digital signal processing circuit 25 performs white balance adjustment, compression, noise reduction, and image quality correction.

[0231] The memory circuit 26 is a memory for temporarily storing imaging data and processing results, and uses DRAM or flash memory. The memory circuit 26 also functions as a buffer for processed image data.

[0232] The output interface 27 is an interface for transmitting the processed image data to an external source. For example, USB or Ethernet can be used as the output interface 27.

[0233] The control circuit 28 is a circuit that manages the operation of the entire imaging device 2, and includes focus control, exposure control, and data transfer control.

[0234] The power supply circuit 29 is a circuit that supplies stable power to the entire imaging device 2. The power supply circuit 29 monitors the internal power consumption and maintains an appropriate power supply.

[0235] This technology allows for real-time monitoring of the current and voltage of analog and digital circuits within the imaging device, enabling rapid detection of abnormalities caused by external noise and power supply fluctuations. This improves the overall stability of the device and enhances the reliability of image acquisition.

[0236] [5. Examples of Application to In-Vehicle Imaging Devices] In the past, in-vehicle imaging devices have been used in autonomous driving and advanced driver-assistance systems (ADAS). In-vehicle imaging devices are susceptible to electromagnetic waves and noise inside the vehicle, which can cause partial image loss or misrecognition. In particular, in electric vehicles and hybrid vehicles, noise from motors and inverters creates a harsh environment that adversely affects the operation of the entire device.

[0237] Furthermore, in an in-vehicle environment, temperature changes and vibrations can easily cause deterioration of the electronic circuits inside the imaging device over time. This can lead to a decrease in MOSFET operation, potentially worsening the circuit's switching speed and signal processing capabilities.

[0238] Therefore, the semiconductor chip based on this technology can be applied to an in-vehicle imaging device. The configuration of an in-vehicle imaging device to which the semiconductor chip of this technology is applied may be as shown in Figure 18, for example.

[0239] Automotive imaging devices are crucial components of autonomous driving and advanced driver-assistance systems (ADAS). The current and voltage monitoring circuits integrated into the semiconductor chip of this technology can detect abnormalities in real time in response to external noise and power supply fluctuations specific to the automotive environment. This enables early detection of malfunctions in the imaging device, allowing for the avoidance of hazards while driving.

[0240] Furthermore, in automotive environments, temperature changes, vibrations, and electromagnetic noise frequently occur. These factors can cause fluctuations in the current and voltage inside the imaging device, posing a risk of disrupting normal operation. This technology includes a function to monitor these fluctuations in real time and notify an external host device of a fault detection signal or fault prediction signal. This makes it possible to maintain the reliability of the imaging device even in harsh environments.

[0241] Furthermore, in-vehicle imaging devices require high image quality to accurately recognize road conditions and surrounding objects. This technology minimizes the effects of noise and prevents image distortion and loss by monitoring the current and voltage stability of the analog and digital circuits within the imaging device.

[0242] [6. Examples of applications to power supply ICs] Power supply ICs (Integrated Circuit for Power Management) are widely used to manage power supply in various electronic devices and systems.

[0243] Traditionally, power supply ICs have been used in electronic devices such as smartphones, laptops, and tablet devices to ensure stable power supply and efficient energy management. Power supply ICs are also used in industrial equipment, automotive systems, medical devices, communication equipment, and servers.

[0244] Power supply ICs can experience rapid fluctuations in voltage and current due to variations in the connected load or external noise, which can cause malfunctions in the entire system.

[0245] Furthermore, internal components such as MOSFETs and capacitors may deteriorate over time, leading to a decrease in the efficiency of the power supply IC and potentially resulting in a loss of voltage supply stability.

[0246] Therefore, semiconductor chips based on this technology can be applied to power supply ICs. An example of the configuration of a power supply IC to which the semiconductor chip of this technology is applied will be explained with reference to Figure 19. Figure 19 is a block diagram showing an example of the configuration of a power supply IC 3 to which the semiconductor chip 1 of this technology is applied.

[0247] As shown in Figure 19, the power supply IC 3 comprises a semiconductor chip 1, an input voltage terminal 31, an output voltage terminal 32, a voltage regulator 33, a control circuit 34, a protection circuit 35, and a clock generation circuit 36.

[0248] The input voltage terminal 31 is a terminal that receives input voltage from the external power supply of the power supply IC 3. The voltage supplied from the external power supply is adjusted and stabilized by the subsequent circuit.

[0249] The output voltage terminal 32 is a terminal for supplying a stabilized voltage to a load (such as an external electronic device or circuit). A constant voltage is supplied from this terminal.

[0250] The voltage regulator 33 is a circuit that stabilizes the input voltage and outputs a constant voltage according to the load. Linear regulators and switching regulators are used for the voltage regulator 33.

[0251] The control circuit 34 is the central circuit that controls the voltage regulator 33 and the protection circuit 35. The control circuit 34 performs dynamic voltage and current control in response to load fluctuations, ensuring output stability.

[0252] The protection circuit 35 is a circuit that has the function of shutting off or limiting the output in the event of an abnormality such as overvoltage, overcurrent, or overheating. The operation of the protection circuit 35 is controlled based on a signal from the semiconductor chip 1.

[0253] The clock generation circuit 36 ​​is a circuit that generates an operating clock used inside the power supply IC 3. The clock generation circuit 36 ​​is used to ensure synchronization of the internal circuits of the semiconductor chip 1.

[0254] Power supply ICs incorporating this semiconductor chip technology improve power supply stability by enabling real-time fault detection and prediction. Furthermore, by streamlining monitoring of aging degradation and preventative maintenance, it extends the lifespan of power supply ICs and reduces operating costs. As a result, power supply ICs are expected to contribute to improved reliability in a wide range of fields, including industrial, medical, and communication equipment.

[0255] [7. Examples of Application to Mobile Devices] This technology can be applied to a variety of products. For example, this technology may be implemented as a device mounted on any type of mobile device, such as automobiles, electric vehicles, hybrid electric vehicles, motorcycles, bicycles, personal mobility devices, airplanes, drones, ships, and robots.

[0256] Figure 20 is a block diagram showing a schematic configuration example of a vehicle control system, which is an example of a mobile control system to which the technology described herein may be applied.

[0257] The vehicle control system 12000 comprises a plurality of electronic control units connected via a communication network 12001. In the example shown in Figure 20, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an external information detection unit 12030, an internal information detection unit 12040, and an integrated control unit 12050. The functional configuration of the integrated control unit 12050 is shown in the figure, which includes a microcomputer 12051, an audio / image output unit 12052, and an in-vehicle network interface 12053.

[0258] The drivetrain control unit 12010 controls the operation of devices related to the vehicle's drivetrain according to various programs. For example, the drivetrain control unit 12010 functions as a control device for a drivetrain generating device that generates driving force for the vehicle, such as an internal combustion engine or a drive motor; a drivetrain transmission mechanism that transmits driving force to the wheels; a steering mechanism that adjusts the steering angle of the vehicle; and a braking device that generates braking force for the vehicle.

[0259] The body system control unit 12020 controls the operation of various devices mounted on the vehicle body according to various programs. For example, the body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, a power window system, or various lamps such as headlights, reverse lights, brake lights, turn signals, or fog lights. In this case, the body system control unit 12020 may receive radio waves transmitted from a portable device that replaces a key or signals from various switches. The body system control unit 12020 receives these radio waves or signals and controls the vehicle's door lock system, power window system, lamps, etc.

[0260] The external information detection unit 12030 detects information from outside the vehicle equipped with the vehicle control system 12000. For example, an imaging unit 12031 is connected to the external information detection unit 12030. The external information detection unit 12030 causes the imaging unit 12031 to capture images of the outside of the vehicle and receives the captured images. Based on the received images, the external information detection unit 12030 may perform object detection processing such as detecting people, cars, obstacles, signs, or characters on the road surface, or distance detection processing.

[0261] The imaging unit 12031 is a light sensor that receives light and outputs an electrical signal corresponding to the amount of light received. The imaging unit 12031 can output the electrical signal as an image or as distance measurement information. The light received by the imaging unit 12031 may be visible light or invisible light such as infrared light.

[0262] The in-vehicle information detection unit 12040 detects information inside the vehicle. The in-vehicle information detection unit 12040 is connected to, for example, a driver status detection unit 12041 that detects the driver's state. The driver status detection unit 12041 includes, for example, a camera that captures images of the driver, and the in-vehicle information detection unit 12040 may calculate the driver's level of fatigue or concentration, or determine whether the driver is drowsy, based on the detection information input from the driver status detection unit 12041.

[0263] The microcomputer 12051 can calculate control target values ​​for the drive force generator, steering mechanism, or braking device based on information inside and outside the vehicle acquired by the external information detection unit 12030 or the internal information detection unit 12040, and output control commands to the drive system control unit 12010. For example, the microcomputer 12051 can perform cooperative control aimed at realizing ADAS (Advanced Driver Assistance System) functions, including collision avoidance or impact mitigation, following driving based on distance between vehicles, maintaining vehicle speed, vehicle collision warning, or vehicle lane departure warning.

[0264] Furthermore, the microcomputer 12051 can perform cooperative control for purposes such as autonomous driving, where the vehicle drives autonomously without driver intervention, by controlling the drive force generating device, steering mechanism, or braking device, etc., based on information about the vehicle's surroundings acquired by the external information detection unit 12030 or the internal information detection unit 12040.

[0265] Furthermore, the microcomputer 12051 can output control commands to the body system control unit 12020 based on external information acquired by the external information detection unit 12030. For example, the microcomputer 12051 can control the headlights according to the position of a preceding or oncoming vehicle detected by the external information detection unit 12030, and perform coordinated control aimed at reducing glare, such as switching from high beams to low beams.

[0266] The audio-image output unit 12052 transmits at least one of audio and image output signals to an output device capable of visually or audibly notifying information to the vehicle's occupants or to those outside the vehicle. In the example shown in Figure 20, the output devices are exemplified as an audio speaker 12061, a display unit 12062, and an instrument panel 12063. The display unit 12062 may include, for example, at least one of an onboard display and a head-up display.

[0267] Figure 21 shows an example of the installation position of the imaging unit 12031.

[0268] In Figure 21, the imaging unit 12031 includes imaging units 12101, 12102, 12103, 12104, and 12105.

[0269] The imaging units 12101, 12102, 12103, 12104, and 12105 are installed, for example, on the front nose, side mirrors, rear bumper, back door, and the upper part of the windshield inside the vehicle 12100. The imaging unit 12101 installed on the front nose and the imaging unit 12105 installed on the upper part of the windshield inside the vehicle mainly acquire images of the front of the vehicle 12100. The imaging units 12102 and 12103 installed on the side mirrors mainly acquire images of the sides of the vehicle 12100. The imaging unit 12104 installed on the rear bumper or back door mainly acquires images of the rear of the vehicle 12100. The imaging unit 12105 installed on the upper part of the windshield inside the vehicle is mainly used for detecting preceding vehicles, pedestrians, obstacles, traffic lights, traffic signs, or lanes.

[0270] Figure 21 shows an example of the imaging range of imaging units 12101 to 12104. Imaging range 12111 indicates the imaging range of imaging unit 12101 located on the front nose, imaging ranges 12112 and 12113 indicate the imaging ranges of imaging units 12102 and 12103 located on the side mirrors, respectively, and imaging range 12114 indicates the imaging range of imaging unit 12104 located on the rear bumper or back door. For example, by superimposing the image data captured by imaging units 12101 to 12104, an overhead view image of the vehicle 12100 can be obtained.

[0271] At least one of the imaging units 12101 to 12104 may have a function for acquiring distance information. For example, at least one of the imaging units 12101 to 12104 may be a stereo camera consisting of multiple image sensors, or an image sensor having pixels for phase difference detection.

[0272] For example, the microcomputer 12051, based on distance information obtained from the imaging units 12101 to 12104, can determine the distance to each object within the imaging range 12111 to 12114 and the temporal change of this distance (relative speed to the vehicle 12100). In particular, it can extract the closest object on the vehicle 12100's path that is traveling in approximately the same direction as the vehicle 12100 at a predetermined speed (e.g., 0 km / h or more) as the preceding vehicle. Furthermore, the microcomputer 12051 can set a predetermined distance to be maintained before the preceding vehicle and perform automatic braking control (including follow-and-stop control) and automatic acceleration control (including follow-and-start control), etc. In this way, cooperative control aimed at autonomous driving, where the vehicle drives autonomously without driver intervention, can be performed.

[0273] For example, the microcomputer 12051 can use distance information obtained from imaging units 12101 to 12104 to classify and extract three-dimensional object data related to three-dimensional objects, such as motorcycles, passenger cars, large vehicles, pedestrians, utility poles, and other three-dimensional objects, and use this data for automatic obstacle avoidance. For example, the microcomputer 12051 identifies obstacles around the vehicle 12100 into obstacles that are visible to the driver of the vehicle 12100 and obstacles that are difficult to see. The microcomputer 12051 then determines the collision risk, which indicates the degree of risk of collision with each obstacle. If the collision risk is above a set value and there is a possibility of collision, the microcomputer 12051 can provide driving assistance to avoid collisions by outputting a warning to the driver via the audio speaker 12061 or the display unit 12062, or by performing forced deceleration or evasive steering via the drive system control unit 12010.

[0274] At least one of the imaging units 12101 to 12104 may be an infrared camera that detects infrared light. For example, the microcomputer 12051 can recognize pedestrians by determining whether or not pedestrians are present in the images captured by the imaging units 12101 to 12104. Such pedestrian recognition is performed, for example, by a procedure to extract feature points from the images captured by the imaging units 12101 to 12104 as infrared cameras, and a procedure to perform pattern matching on a series of feature points that indicate the contour of an object to determine whether or not it is a pedestrian. When the microcomputer 12051 determines that a pedestrian is present in the images captured by the imaging units 12101 to 12104 and recognizes a pedestrian, the audio-image output unit 12052 controls the display unit 12062 to superimpose a rectangular contour line for emphasis on the recognized pedestrian. The audio-image output unit 12052 may also control the display unit 12062 to display an icon indicating a pedestrian at a desired position.

[0275] The above describes an example of a vehicle control system to which this technology may be applied. This technology can be applied to, for example, the imaging unit 12031, among the configurations described above.

[0276] Furthermore, the embodiments relating to this technology are not limited to the embodiments described above, and various modifications are possible without departing from the gist of this technology.

[0277] Furthermore, this technology can also take the following configurations: [1] A semiconductor chip that monitors at least one of the current and voltage flowing inside for fault detection and fault prediction of the internal circuit, and outputs a fault detection signal or a fault prediction signal based on the monitoring results. [2] The semiconductor chip according to [1], wherein the monitored current and voltage include both digital and analog signals. [3] The semiconductor chip according to [1] or [2], which stores the monitored current and voltage as the maximum or minimum value within a predetermined period, and outputs the fault detection signal or the fault prediction signal based on the maximum value and at least one of the maximum value. [4] The semiconductor chip according to [3], which calculates an average value based on the maximum and minimum values, and outputs the fault detection signal or the fault prediction signal based on the average value. [5] The semiconductor chip according to [3] or [4], which calculates the rate of change over time of the monitored current and voltage, and outputs the fault detection signal or the fault prediction signal based on the rate of change over time. [6] A semiconductor chip according to any one of [1] to [5], wherein, based on the monitoring results, it outputs the fault detection signal when a threshold is exceeded and outputs the fault prediction signal when the fluctuation is within a predetermined range. [7] A semiconductor chip according to [6], wherein the threshold is set based on a simulation or evaluation test and stored internally. [8] A semiconductor chip according to any one of [1] to [7], wherein the monitoring results are stored on a recording medium, the stored data is compared with past data to evaluate the tendency for abnormalities to occur, and the fault detection signal or the fault prediction signal is output based on the evaluation results. [9] A semiconductor chip according to any one of [1] to [8], wherein it uses a learning model that has learned the current and voltage patterns under normal conditions and outputs the fault detection signal or the fault prediction signal by comparing it with the monitoring results.

[10] A semiconductor chip according to [9], wherein the learning model is constructed based on data of current and voltage patterns under normal conditions aggregated on the cloud.

[11] A semiconductor chip according to any one of [1] to

[10] , wherein the fault detection signal or fault prediction signal is transmitted to an external host device.

[12] A semiconductor chip according to any one of [1] to

[11] , applicable to an imaging device.

[13] A semiconductor chip according to

[12] , applicable to an in-vehicle imaging device.

[14] A semiconductor chip according to any one of [1] to

[13] , applicable to a power supply IC.

[15] A fault detection system comprising a semiconductor chip and a host device, wherein the semiconductor chip monitors at least one of the current and voltage flowing inside for fault detection and fault prediction of the internal circuit, outputs a fault detection signal or a fault prediction signal based on the monitoring results, and the host device determines whether or not to shut down the system based on the fault detection signal or the fault prediction signal.

[16] The fault detection system according to

[15] , wherein the host device sends an alert to a user based on the fault detection signal or the fault prediction signal, enabling the user to decide whether or not to shut down the system.

[17] The fault detection system according to

[15] or

[16] , wherein the host device determines a course of action based on the fault detection signal or the fault prediction signal.

[18] A fault detection system according to any one of

[15] to

[17] , wherein the host device estimates the maintenance timing based on the fault detection signal or the fault prediction signal.

[19] A fault detection system according to any one of

[15] to

[18] , wherein the semiconductor chip classifies the cause when an abnormality occurs based on the monitoring results, transmits the classification result to the host device, and the host device analyzes the scope of the abnormality's impact based on the classification result and determines whether or not to shut down the system.

[0278] 1. Semiconductor chip 11. Current monitoring circuit for analog circuits 12. Current monitoring circuit for digital circuits 13. Voltage monitoring circuit for analog circuits 14. Voltage monitoring circuit for digital circuits 15. Data calculation circuit 16. Threshold determination circuit 17. Error reporting circuit 18. Memory circuit 19. Host interface 2. Imaging device 3. Power supply IC 100. Fault detection system 101. Host device

Claims

1. A semiconductor chip that monitors at least one of the current and voltage flowing inside for fault detection and fault prediction of the internal circuit, and outputs a fault detection signal or a fault prediction signal based on the monitoring results.

2. The semiconductor chip according to claim 1, wherein the monitored current and voltage include both digital and analog signals.

3. The semiconductor chip according to claim 1, which stores the monitored current and voltage as the maximum or minimum value within a predetermined period, and outputs the fault detection signal or the fault prediction signal based on the maximum value and at least one of the maximum values.

4. The semiconductor chip according to claim 3, which calculates an average value based on the maximum and minimum values ​​and outputs the fault detection signal or the fault prediction signal based on the average value.

5. The semiconductor chip according to claim 3, which calculates the time rate of change of the monitored current and the voltage, and outputs the fault detection signal or the fault prediction signal based on the time rate of change.

6. The semiconductor chip according to claim 1, which outputs the fault detection signal when a threshold is exceeded based on the monitoring results, and outputs the fault prediction signal when the fluctuation is within a predetermined range.

7. The semiconductor chip according to claim 6, wherein the threshold is set based on a simulation or evaluation test and stored internally.

8. The semiconductor chip according to claim 1, which stores the monitoring results on a recording medium, evaluates the tendency for anomalies to occur by comparing the stored data with past data, and outputs the fault detection signal or the fault prediction signal based on the evaluation results.

9. The semiconductor chip according to claim 1, which uses a learning model that has learned the current and voltage patterns under normal conditions and outputs the fault detection signal or the fault prediction signal by comparing it with the monitoring results.

10. The semiconductor chip according to claim 9, wherein the learning model is constructed based on data of normal current and voltage patterns aggregated on the cloud.

11. The semiconductor chip according to claim 1, wherein the fault detection signal or fault prediction signal is transmitted to an external host device.

12. The semiconductor chip according to claim 1, applicable to an imaging device.

13. The semiconductor chip according to claim 12, applicable to an in-vehicle imaging device.

14. The semiconductor chip according to claim 1, applicable to a power supply IC.

15. A fault detection system comprising a semiconductor chip and a host device, wherein the semiconductor chip monitors at least one of the current and voltage flowing inside for fault detection and fault prediction of the internal circuitry, outputs a fault detection signal or a fault prediction signal based on the monitoring results, and the host device determines whether or not to shut down the system based on the fault detection signal or the fault prediction signal.

16. The fault detection system according to claim 15, wherein the host device sends an alert to a user based on the fault detection signal or the fault prediction signal, enabling the user to determine whether to shut down the system.

17. The fault detection system according to claim 15, wherein the host device determines a course of action based on the fault detection signal or the fault prediction signal.

18. The fault detection system according to claim 15, wherein the host device estimates the maintenance timing based on the fault detection signal or the fault prediction signal.

19. The fault detection system according to claim 15, wherein the semiconductor chip classifies the cause of an abnormality when it occurs based on the monitoring results, transmits the classification results to the host device, and the host device analyzes the scope of the abnormality's impact based on the classification results and determines whether or not to shut down the system.

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