Switching regulator

Abstract

A switching regulator according to the present invention comprises: a comparator that compares a switching voltage corresponding to an inductor current flowing from the switching regulator to an inductor with a prescribed reference voltage, and outputs a comparison result signal; a monitoring circuit that generates a current for generating a monitoring voltage that monitors the switching voltage; a reference voltage circuit that generates a current for generating the reference voltage; and a control circuit that outputs a plurality of selection signals indicating a plurality of mutually different timings to at least one of the monitoring circuit and the reference voltage circuit. At least one of the monitoring circuit and the reference voltage circuit changes the generated current according to the plurality of timings, and at least one of the monitoring circuit and the reference voltage circuit is shared for the plurality of timings.

Description

Technical Field

[0001] The present invention relates to a switching regulator.

Background Art

[0002] In a switching regulator according to the prior art, in order to reduce the mounting area, it has already been known that an integrated circuit (IC) is also required to be miniaturized.

[0003] For example, in Patent Document 1, in order to operate a plurality of abnormality detection functions of a switching regulator with low power consumption and to reduce the occupied area in a semiconductor device, a switching regulator according to a conventional example has been invented. The switching regulator includes a comparison circuit, a plurality of switch circuits, and a switch control circuit, and is characterized in that the plurality of switch circuits are switched by a plurality of control signals of the switch control circuit, and a plurality of abnormality detection functions are realized by one comparison circuit.

[0004] That is, in Patent Document 1, in order to reduce the chip area, for example, a technique is disclosed in which the reference voltage and the monitoring voltage of a plurality of detection circuits having different operation timings are switched, and one comparator circuit is used in common.

Prior Art Documents

Patent Documents

[0005]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0006] However, conventional analog switching regulators require circuits to compensate for manufacturing variations in electrical characteristics and specific accuracy in order to maintain high and stable quality, which makes it difficult to reduce the circuit area. In particular, the invention described in Patent Document 1 does not resolve the problem that circuits to compensate for manufacturing variations are required for each application.

[0007] The objective of the present invention is to solve the above problems and to provide a switching regulator that can reduce the circuit area compared to the conventional technology while maintaining high and stable quality. [Means for solving the problem]

[0008] A switching regulator according to one aspect of the present invention is A switching regulator comprising a pair of switch elements connected in series with each other, A comparator that compares the switching voltage corresponding to the inductor current flowing from the switching regulator to the inductor with a predetermined reference voltage and outputs a comparison result signal, A monitoring circuit that generates a current for generating a monitoring voltage to monitor the switching voltage, A reference voltage circuit that generates a current for generating the aforementioned reference voltage, The system includes a control circuit that outputs multiple selection signals indicating multiple different timings to at least one of the monitoring circuit and the reference voltage circuit, At least one of the monitoring circuit and the reference voltage circuit changes the generated current according to the plurality of timings, At least one of the monitoring circuit and the reference voltage circuit is shared for the plurality of timings. [Effects of the Invention]

[0009] Accordingly, according to one aspect of the present invention, a switching regulator can reduce the circuit area compared to the prior art while maintaining high and stable quality. [Brief explanation of the drawing]

[0010] [Figure 1] This is a block diagram showing the configuration of the switching regulator 1 related to the basic circuit. [Figure 2] Figure 1 is a block diagram showing the configuration of the zero-crossing detector 11. [Figure 3] Figure 1 shows a timing chart of each signal illustrating an example of the operation of the switching regulator 1. [Figure 4] This is a block diagram showing the configuration of the current monitor circuit 11A according to modified example 1. [Figure 5] Figure 4 shows a timing chart of each signal illustrating an example of the operation of a switching regulator including the current monitoring circuit 11A. [Figure 6] This is a block diagram showing the configuration of the current monitor circuit 11B according to modified example 2. [Figure 7] Figure 6 shows a timing chart of each signal illustrating an example of the operation of a switching regulator including the current monitoring circuit 11B. [Figure 8] This is a block diagram showing the configuration of the current monitor circuit 11C according to modified example 3. [Figure 9] Figure 8 shows a timing chart of each signal illustrating an example of the operation of a switching regulator including the current monitor circuit 11C. [Figure 10] This is a block diagram showing the configuration of the current monitor circuit 11D according to modified example 4. [Figure 11] Figure 10 shows a timing chart of each signal illustrating an example of the operation of a switching regulator including the current monitoring circuit 11D. [Figure 12] This is a block diagram showing the configuration of the current monitor circuit 11E in the comparative example. [Figure 13] Figure 12 is a block diagram showing a part of the configuration of the current monitor circuit 11E. [Figure 14] Figure 13 shows a timing chart of each signal illustrating an example of the operation of a switching regulator including the current monitor circuit 11E. [Figure 15] It is a block diagram showing a partial configuration of the current monitor circuit 11E in FIG. 12. [Figure 16] It is a timing chart of each signal showing an operation example of a switching regulator including the current monitor circuit 11E in FIG. 15. [Figure 17] It is a block diagram showing a configuration example of a switching regulator including the current monitor circuit 11F according to Embodiment 1. [Figure 18] It is a block diagram showing a configuration example of a switching regulator including the current monitor circuit 11G according to Embodiment 2. [Figure 19] It is a block diagram showing a configuration example of a switching regulator including the current monitor circuit 11H according to Embodiment 3. [Figure 20] It is a block diagram showing a configuration example of a switching regulator including the current monitor circuit 11I according to Embodiment 4. [Figure 21] It is a block diagram showing a configuration example of a switching regulator including the current monitor circuit 11J according to Embodiment 5. [Figure 22] It is a block diagram showing a configuration example of a switching regulator including the current monitor circuit 11K according to Embodiment 6. [Figure 23] It is a block diagram showing a configuration example of a switching regulator including the current monitor circuit 11L according to Embodiment 7. [Figure 24] It is a block diagram showing a configuration example of a switching regulator including the current monitor circuit 11M according to Embodiment 8.

Embodiments for Carrying Out the Invention

[0011] Hereinafter, embodiments and modifications according to the present invention will be described with reference to the drawings. The same or similar components are denoted by the same reference numerals.

[0012] (Findings of the Inventor) First, in order to explain the problems of the present invention, the basic circuit will be described below.

[0013] (Basic circuit) Figure 1 is a block diagram showing the configuration of the switching regulator 1 related to the basic circuit. In Figure 1, the switching regulator 1 consists of a switching modulation circuit 10 and an inverter INV1. of It is composed of an agate NOR1, a zero-crossing detector 11, a pair of switching elements which are MOS transistors Q1 and Q2, and terminals T1 to T4.

[0014] In Figure 1, the switching modulation circuit 10 generates, for example, a PWM signal to switch the MOS transistors Q1 and Q2 that constitute the inverter circuit, based on the output voltage Vout fed back to terminal T4, so that the output voltage Vout becomes a predetermined value. This signal is output to the gate of MOS transistor Q1 via inverter INV1 and to the gate of MOS transistor Q2 via Nor gate NOR1, thereby switching MOS transistors Q1 and Q2. The power supply voltage Vdd is grounded via terminal T1, the source and drain of MOS transistor Q1, the drain and source of MOS transistor Q2, and terminal T2. The output voltages from the drains of MOS transistors Q1 and Q2 are output as output voltage Vout to the output capacitor Cout via terminal T3, current detector 12, and inductor Ind. Here, the output voltage Vout is fed back to terminal T4.

[0015] The current signal corresponding to the inductor current Iind detected by the current detector 12 is input to the zero-cross detector 11. Each time the zero cross detector crosses zero, the zero-cross detector 11 generates a high-level zero-cross detection signal ZCDET and outputs it to the Nor gate NOR1.

[0016] The basic circuit shown in Figure 1, configured as described above, is a diagram illustrating the basic operation of monitoring the inductor current Iind. As illustrated, the basic circuit isIn particular, the zero-crossing detector 11 is characterized by its ability to detect when the inductor current during rectification becomes zero and control the switching operation. Specifically, in Figure 1, in response to the H-level zero-crossing detection signal ZCDET, the switching operation is stopped to prevent reverse current flow.

[0017] Next, a modified version of the basic circuit will be described below.

[0018] (Variation 1) Figure 2 is a block diagram showing the configuration of the zero-crossing detector 11 in Figure 1, and Figure 3 is a timing chart of each signal showing an example of operation of the switching regulator 1 in Figure 1. In Figure 2, the zero-crossing detector 11 is configured to include a "current monitoring circuit" which includes a comparator 13.

[0019] In Figure 2, the switching voltage Vsw at the connection point between the drains of MOS transistor Q1 and MOS transistor Q2 is applied to the non-inverting input terminal of comparator 13, and the ground voltage of the source of MOS transistor Q2 is applied to the inverting input terminal of comparator 13. Comparator 13 outputs the comparison result signal as the zero-crossing detection signal ZCDET.

[0020] The zero-cross detector 11 configured as described above can detect "0A" by comparing the voltage across the MOS transistor Q2, since the drain-source voltage Vds of the MOS transistor Q2 becomes 0V when the inductor current Iind becomes "0A". However, as shown in Figure 3, there was a problem in that a reverse current Iind was generated due to the delay time tdelay.

[0021] Therefore, a current monitor circuit 11A (included in the zero-cross detector 11) according to the following modified example 1 has been proposed.

[0022] (Variation 1) Figure 4 is a block diagram showing the configuration of the current monitor circuit 11A according to Modification 1. Figure 5 is a timing chart of each signal showing an example of operation of a switching regulator including the current monitor circuit 11A of Figure 4. The current monitor circuit 11A of Figure 4 differs from the current monitor circuit 11 of Figure 2 in the following respects. (1) A constant current source IS1 was inserted between the power supply voltage Vdd and the non-inverting input terminal of comparator 13. (2) A MOS transistor Q3 with the power supply voltage Vdd applied to its gate was inserted between the non-inverting input terminal of comparator 13 and the drain of MOS transistor Q2.

[0023] With the switching regulator including the current monitor circuit 11A configured as described above, as shown in Figure 5, the switching voltage Vsw can be detected earlier by the delay time by comparing the voltage Vmoni, which is obtained by level-shifting the switching voltage Vsw by a predetermined voltage, with the ground voltage.

[0024] The detection voltage of comparator 13 is expressed by the following formula.

[0025] 0V<0V-Vdsdrv+Vdsmoni

[0026] Here, Vdsdrv is the voltage across MOS transistor Q2, and Vdsmoni is the voltage across MOS transistor Q3. The inductor current Iind, which is the DC detection current, is expressed by the following equation.

[0027] Iind = (On-resistance of Q3) × (Bias current due to IS1) ÷ (On-resistance of Q2)

[0028] Furthermore, the AC detection current considering the delay time tdelay is expressed by the following equation.

[0029] AC detection current = DC detection current - Vout × tDelay ÷ Ind Vdsdrv = (On-resistance of Q2) × (Current of Q2 Iind) Vdsmoni = (On-resistance of Q3) × (Bias current due to IS1)

[0030] Next, the current monitoring circuit that detects currents other than zero will be described below.

[0031] (Modification 2) Figure 6 is a block diagram showing the configuration of the current monitor circuit 11B according to modified example 2. Figure 7 is a timing chart of each signal showing an example of operation of a switching regulator including the current monitor circuit 11B of Figure 6. The current monitor circuit 11B of Figure 6 differs from the current monitor circuit 11A of Figure 4 in the following respects. (1) Instead of constant current source IS1, a constant current source IS12 is provided, thereby making the voltage Vdsmoni larger than that when zero is detected in Figure 4, so that the comparator 13 detects a current value larger than "0A". (2) The comparator 13 outputs the voltage VCDET of the comparison result signal.

[0032] (Variation 3) Figure 8 is a block diagram showing the configuration of the current monitor circuit 11C according to modified example 3. Figure 9 is a timing chart of each signal showing an example of operation of a switching regulator including the current monitor circuit 11C of Figure 8. The current monitor circuit 11C of Figure 8 differs from the current monitor circuit 11B of Figure 6 in the following respects. (1) Constant current source IS2 is provided instead of constant current source IS1A. Here, the power supply voltage Vdd is connected to the inverting input terminal of comparator 13 via constant current source IS2. (2) The switching voltage Vsw is applied to the non-inverting input terminal of the comparator 13. (3) A MOS transistor Q4 with the power supply voltage Vdd applied to its gate is inserted between the inverting input terminal (reference voltage Vref) of the comparator 13 and the ground voltage.

[0033] In the current monitoring circuit 11C configured as described above, the comparator 13 is characterized by detecting a current that has flowed backward by an amount equal to the voltage Vdsref.

[0034] (Modification 4) Figure 10 is a block diagram showing the configuration of the current monitor circuit 11D according to modified example 4. Figure 11 is a timing chart of each signal showing an example of operation of a switching regulator including the current monitor circuit 11D of Figure 10.

[0035] In Figure 10, the current monitor circuit 11D comprises three constant current sources IS1, IS2, and IS12, MOS transistors Q3 to Q5, switches SW1 to SW6, and a comparator 13. Switches SW1 and SW2 are turned on or off based on the selection signal RCSEL, switches SW3 and SW4 are turned on or off based on the selection signal VCSEL, and switches SW5 and SW6 are turned on or off based on the selection signal ZCSEL, so that one pair of switches is turned on. The comparator 13 outputs a comparison result signal voltage LSCDET.

[0036] The current monitoring circuit 11D configured as described above is an example of a circuit in which three types of inductor currents are detected by a single comparator 13.

[0037] (Comparative example) Figure 12 is a block diagram showing the configuration of a current monitor circuit 11E according to a comparative example disclosed in Patent Document 1.

[0038] In Figure 12, the current monitor circuit 11E is comprised of three variable constant current sources VIS1 to VIS3, MOS transistors Q3 to Q5, switches SW1 to SW6, and a comparator 13. Switches SW1 and SW2 are turned on or off based on the selection signal RCSEL, switches SW3 and SW4 are turned on or off based on the selection signal VCSEL, and switches SW5 and SW6 are turned on or off based on the selection signal ZCSEL, so that one pair of switches is turned on. The comparator 13 outputs a comparison result signal voltage LSCDET.

[0039] The following describes the problems 1 to 3 with the current monitor circuit 11E configured as described above.

[0040] (Task 1) When monitoring multiple detection values ​​such as zero inductor current Iind, positive overcurrent, and reverse overcurrent, even if the input-referred offset voltage Voffset of the shared comparator 13 is the same, the reference voltage Vrefr and monitoring voltages Vmoniz and Vmoniv will vary, requiring correction such as trimming to adjust the voltages generated by MOS transistors Q3 to Q5 individually. This increases the number of correction items in mass production and increases the chip area due to the correction circuit (Figure 12).

[0041] Figure 13 is a block diagram showing a part of the configuration of the current monitor circuit 11E in Figure 12. Figure 14 is a timing chart of each signal showing an example of operation of a switching regulator including the current monitor circuit in Figure 13.

[0042] (Task 2) Since both the reference voltage and the monitoring voltage have finite impedance, there was a concern that when the switching switches SW1 to SW6 were opened or closed, noise via parasitic capacitances C1 and C2 would be superimposed on the differential input and generated voltage of the comparator 13, leading to false detection (Figures 13 and 14).

[0043] Figure 15 is a block diagram showing the configuration of the current monitor circuit 11E in Figure 12. Figure 16 is a timing chart of each signal showing an example of operation of a switching regulator including the current monitor circuit in Figure 15.

[0044] (Challenge 3) When switching SW1 to SW6, there was a concern that simultaneous switching due to timing differences in the control signals of each SW1 to SW6 could cause interference between the reference voltage and monitoring voltage, leading to false detections (Figures 15 and 16).

[0045] The following describes embodiments for solving the above problems 1 to 3.

[0046] (Embodiment 1) Figure 17 is a block diagram showing an example configuration of a switching regulator including a current monitor circuit 11F according to Embodiment 1.

[0047] In Figure 17, the current monitor circuit 11F is comprised of four constant current sources IS21 to IS24, switches SW11 and SW12, MOS transistors Q3 and Q4, and a comparator 13. The switching regulator, including the current monitor circuit 11F, also includes a switching modulation circuit 10, which is a control circuit.

[0048] The power supply voltage Vdd is connected to the inverting input terminal of comparator 13 via a constant current source IS21, and also to the inverting input terminal of comparator 13 via a switch SW11, which is controlled on / off by a selection signal RCSEL, and a constant current source IS22. The power supply voltage Vdd is also connected to the non-inverting input terminal of comparator 13 via a constant current source IS23, and also to the non-inverting input terminal of comparator 13 via a switch SW12, which is controlled on / off by a selection signal VCSEL, and a constant current source IS24. Here, a MOS transistor Q3 with the power supply voltage Vdd applied to its gate is inserted between the non-inverting input terminal of comparator 13 and the switching voltage Vsw. In addition, a MOS transistor Q4 with the power supply voltage Vdd applied to its gate is inserted between the inverting input terminal of comparator 13 and the ground voltage.

[0049] The non-inverting input terminal of comparator 13 is the point of generation of the monitoring voltage Vmoni, and its inverting input terminal is the point of generation of the reference voltage Vref, and the comparator 13 compares these voltages and outputs the comparison result signal voltage LSCDET. In other words, the constant current sources IS21 and IS22 and switch SW11 constitute a reference voltage circuit for generating the reference voltage Vref, and the constant current sources IS23 and IS24 and switch SW12 constitute a monitoring circuit for generating the monitoring voltage Vmoni for monitoring the switching voltage Vsw.

[0050] In Figure 17, the switching modulation circuit 10 generates, for example, a PWM signal to switch the MOS transistors Q1 and Q2 that constitute the inverter circuit, based on the output voltage Vout fed back to terminal T4, so that the output voltage Vout becomes a predetermined value, thereby switching the MOS transistors Q1 and Q2. In addition, as described above, the switching modulation circuit 10 generates selection signals RCSEL and VCSEL at different timings and outputs them to the control terminals of switches SW11 and SW12, respectively, thereby controlling the on or off state of switches SW11 and SW12.

[0051] As described above, the current monitor circuit 11F in Figure 17 does not generate and switch the reference voltage Vref and the monitoring voltage Vmoni separately. Instead, the voltages generated by MOS transistor Q3 and MOS transistor Q4 are changed at different timings. By changing the reference voltage Vref or the monitoring voltage Vmoni, the three problems 1 to 3 in the comparative example in Figure 12 can be solved. Furthermore, by unifying the reference voltage circuit and the monitoring circuit, the chip area can be reduced and the circuit current consumption can be lowered.

[0052] (Solution to Problem 1) In response to problem 1 of the comparative example described above, by using the same MOS transistor Q4 that generates the reference voltage Vref and its bias current (IS21, IS22), and the same MOS transistor Q3 that generates the monitoring voltage and its bias current (IS23, IS24), correcting one of the three detection currents will also correct the other detection values.

[0053] In the current monitoring circuit 11E shown in Figure 12, if the on-resistance of MOS transistor Q5 is smaller than the design value and the on-resistance of MOS transistor Q3 is larger than the design value, the monitoring voltages Vmoniz and Vmoniv need to be corrected in opposite directions. In contrast, in the current monitoring circuit 11F shown in Figure 17, since the circuit is shared as described above and the variation in finished products is the same, the correction can be completed by simply trimming the input-referred offset, on-resistance, bias current, etc. of the comparator 13 once. This solves the aforementioned problem 1.

[0054] (Solution to Problem 2) Problem 2 can be solved by concealing the direct parasitic capacitance of switches SW11 and SW12 at the reference voltage Vref node and the monitoring voltage Vmoni node.

[0055] (Solution to Problem 3) Whether the current is zero or positive overcurrent (switch SW12 is turned on and switch SW11 is turned off by the selection signal VCSEL), or whether the current is zero or negative overcurrent (switch SW11 is turned on and switch SW12 is turned off by the selection signal RCSEL), both switches SW11 and SW12 can be turned on with a single switch in each case, eliminating the need to adjust the control timing. This solves the aforementioned problem 3.

[0056] As described above, according to Embodiment 1, not only is the comparator 13 shared, but the monitoring circuit and the reference voltage circuit are also shared, so manufacturing variations of multiple detection circuits can be corrected all at once. Furthermore, there is no need to adjust the control timing, and since no direct parasitic capacitance is visible at the input terminal of the comparator 13, false detections can be avoided.

[0057] (Embodiment 2) Figure 18 is a block diagram showing an example configuration of a switching regulator including a current monitor circuit 11G according to Embodiment 2. The current monitor circuit 11G in Figure 18 differs from the current monitor circuit 11F in Figure 17 in the following ways. (1) A constant current source IS22 was inserted between the switch SW11 and the inverting input terminal of the comparator 13. (2) A constant current source IS24 was inserted between the switch SW11 and the inverting input terminal of the comparator 13. The differences are explained below.

[0058] There are multiple embodiments of the method or technique for generating the reference voltage Vref or monitoring voltage Vmoni, and Embodiment 2 in Figure 18 is one example. This is an example in which switches SW11 and SW12 are placed downstream of the current of constant current sources IS22 and IS24, for example when the impedance of the reference voltage Vref or monitoring voltage Vmoni is low, or when the parasitic capacitance of switches S11 and SW12 is small.

[0059] According to Embodiment 2 configured as described above, in addition to the effects and advantages mentioned above, it has the same effects and advantages as Embodiment 1.

[0060] (Embodiment 3) Figure 19 is a block diagram showing an example configuration of a switching regulator including a current monitor circuit 11H according to Embodiment 3. The current monitor circuit 11H in Figure 19 differs from the current monitor circuit 11F in Figure 17 in the following respects. (1) Replace the MOS transistor Q3 with a resistor Rmoni. (2) Replace the MOS transistor Q4 with a resistor Rref. The differences are explained below.

[0061] The current monitor circuit 11H in Figure 19 is an example in which the reference voltage Vref or monitoring voltage Vmoni is generated using resistors Rmoni and Rref instead of MOS transistors Q3 and Q4. This allows the reference voltage Vref or monitoring voltage Vmoni to be changed by the resistance value rather than the on-resistance of the MOS transistors.

[0062] Embodiment 3, configured as described above, has the same effects and advantages as Embodiment 1.

[0063] (Embodiment 4) Figure 20 is a block diagram showing an example configuration of a switching regulator including a current monitor circuit 11I according to Embodiment 4. The current monitor circuit 11I in Figure 20 differs from the current monitor circuit 11F in Figure 17 in the following ways. (1) Instead of switch SW12, constant current source IS24, and MOS transistor Q3, a MOS transistor Q3A is provided. (2) Instead of switch SW11, constant current source IS22, and MOS transistor Q4, a MOS transistor Q4A is provided. The differences are explained below.

[0064] In Figure 20, MOS transistors Q3A and Q4A are each composed of, for example, multiple MOS transistors connected in series. By short-circuiting some of these MOS transistors based on the selection signals VCSEL and RCSEL, the effective transistor size is changed, thereby altering the resistance between the source and drain of MOS transistors Q3A and Q4A, and thus changing the current flowing through them. This, in turn, changes the monitoring voltage Vmoni and the reference voltage Vref. Note that instead of MOS transistors Q3A and Q4A, which consist of multiple MOS transistors connected in series, a circuit consisting of, for example, multiple resistors connected in series may also be used.

[0065] According to Embodiment 4 configured as described above, in addition to the effects and advantages mentioned above, it has the same effects and advantages as Embodiment 1.

[0066] (Embodiment 5) Figure 21 is a block diagram showing an example configuration of a switching regulator including a current monitor circuit 11J according to Embodiment 5. The current monitor circuit 11J in Figure 21 differs from the current monitor circuit 11F in Figure 17 in the following respects. (1) Switch SW11 and constant current source IS22 were removed. The differences are explained below.

[0067] In the current monitoring circuit 11J shown in Figure 21, configured as described above, the current for generating the monitoring voltage Vmoni may be switched between two values: a predetermined current value I11 and a predetermined current value I12. This allows the monitoring voltage Vmoni to be switched between two values: a predetermined voltage value V11 and a predetermined voltage value V12.

[0068] According to Embodiment 5 configured as described above, in addition to the effects and advantages mentioned above, it has the same effects and advantages as Embodiment 1.

[0069] (Embodiment 6) Figure 22 is a block diagram showing an example configuration of a switching regulator including a current monitor circuit 11K according to Embodiment 6. The current monitor circuit 11K in Figure 22 differs from the current monitor circuit 11F in Figure 17 in the following ways. (1) Switch SW12 and constant current source IS24 were removed. The differences are explained below.

[0070] In the current monitor circuit 11K shown in Figure 22, configured as described above, the current for generating the reference voltage Vref may be switched between two values, between a predetermined current value I11 and a predetermined current value I12, thereby switching the reference voltage Vref between two values, a predetermined voltage value V11 and a predetermined voltage value V12.

[0071] According to Embodiment 6 configured as described above, in addition to the effects and advantages mentioned above, it has the same effects and advantages as Embodiment 1.

[0072] (Embodiment 7) Figure 23 is a block diagram showing an example configuration of a switching regulator including a current monitor circuit 11L according to Embodiment 7. The current monitor circuit 11L in Figure 23 differs from the current monitor circuit 11F in Figure 17 in the following ways. (1) Switch SW11, constant current sources IS21 and IS22, and MOS transistor Q4 were removed. (2) The inverting input terminal of comparator 13 was grounded.

[0073] Embodiment 7, configured as described above, has the same effects and advantages as Embodiment 1.

[0074] (Embodiment 8) Figure 24 is a block diagram showing an example configuration of a switching regulator including a current monitor circuit 11M according to Embodiment 8. The current monitor circuit 11M in Figure 24 is configured to include a comparator 13, constant current sources IS31 and IS32, a switch SW21, and a MOS transistor Q3a.

[0075] In Figure 24, the power supply voltage Vdd is connected to the non-inverting input terminal of comparator 13 via a gate-grounded MOS transistor Q3a. The non-inverting input terminal of comparator 13 is grounded via a constant current source IS31, and also grounded via switch SW21 and constant current source IS32. Switch SW21 is turned on or off based on an overcurrent selection signal.

[0076] In the current monitor circuit 11M shown in Figure 24, configured as described above, switching the switch SW21 on or off changes the current from the MOS transistor Q3a at the non-inverting input terminal of the comparator 13, thereby changing the reference voltage Vref. The comparator 13 compares the switching voltage Vsw with the reference voltage Vref and outputs a comparison result signal HSCDET.

[0077] The current monitoring circuit 11M in Figure 24 is characterized by monitoring the inductor current Iind when the current passes through the MOS transistor Q1, which is the high-side driver element.

[0078] According to Embodiment 8 configured as described above, it has the same effects and advantages as Embodiment 1, except for the effects and advantages mentioned above.

[0079] (Other variations) In embodiments 1 to 8 described above, the pair of switching elements, MOS transistors Q1 and Q2, are placed outside the current monitoring circuits 11F to 11M. However, the present invention is not limited to this arrangement, and the transistors may be integrated into the current monitoring circuits 11F to 11M. [Industrial applicability]

[0080] As described in detail above, the switching regulator according to the present invention makes it possible to reduce the circuit area compared to the conventional technology while maintaining high and stable quality in the switching regulator. [Explanation of symbols]

[0081] 1. Switching Regulator 10 Switching Modulation Circuit 11 Zero-crossing detectors 11A~11M Current Monitor Circuit 12 Current detector 13 Comparator C1~C2 Parasitic capacitance Cout output capacitor Ind Inductor INV1 Inverter IS1~IS32,IS1A Constant current source NOR1 Noahgate Q1-Q5, Q3A, Q5A MOS transistors Rload Load resistance Rref Reference Resistor SW1~SW21 Switches T1~T4 terminals VIS1~VIS3 Variable Current Source

Claims

1. A switching regulator comprising a pair of switch elements connected in series with each other, A comparator that compares the switching voltage corresponding to the inductor current flowing from the switching regulator to the inductor with a predetermined reference voltage and outputs a comparison result signal, A monitoring circuit that generates a current for generating a monitoring voltage to monitor the switching voltage, A reference voltage circuit that generates a current for generating the aforementioned reference voltage, The system includes a control circuit that generates multiple selection signals indicating multiple different timings and outputs them to at least one of the monitoring circuit and the reference voltage circuit, At least one of the monitoring circuit and the reference voltage circuit changes the generated current according to the plurality of timings, At least one of the monitoring circuit and the reference voltage circuit is shared for the plurality of timings. Switching regulator.

2. At least one of the monitoring circuit and the reference voltage circuit includes a circuit in which a first constant current source and a second constant current source and a switch are connected in series are connected in parallel. A switching regulator according to claim 1.

3. The reference voltage of the aforementioned reference voltage circuit is generated at a point where the reference voltage is grounded via a MOS transistor to which a predetermined voltage is applied to the gate. The switching regulator according to claim 2.

4. The reference voltage of the aforementioned reference voltage circuit is determined by the point at which the reference voltage is generated being grounded via a resistor. The switching regulator according to claim 2.

5. The reference voltage of the aforementioned reference voltage circuit is determined when the point of generation of the reference voltage is grounded. The switching regulator according to claim 2.

6. The monitoring circuit and the reference voltage circuit each include a first constant current source and a MOS transistor to which a predetermined voltage is applied, connected to the point where the monitoring voltage or the reference voltage is generated. By applying the selection signal to the back gate of the MOS transistor, the resistance value of the MOS transistor is changed, thereby changing the monitoring voltage or the reference voltage. A switching regulator according to claim 1.

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