Hybrid fan-out hybrid density interconnect architecture

Abstract

The semiconductor module includes two or more semiconductor dies and an interconnect structure coupled to the two or more semiconductor dies, the interconnect structure implementing a plurality of inter-die connection paths having a first density and a plurality of fan-out rewiring paths having a second density different from the first density.

Description

Background Art

[0001] A system-on-a-chip (SoC) integrates multiple functional nodes into a single integrated circuit. For example, an SoC can include one or more processor cores, a memory interface, a network interface, an optical interface, a digital signal processor, a graphics processor, telecommunications components, and the like. Conventionally, each of the nodes is generated within a monolithic die. However, for various reasons such as increasing the yield of functional chips or reducing design complexity and cost, it is becoming increasingly common to separate these nodes into individual dies and reconfigure them on a wafer. In order to achieve the efficiency and performance of a monolithic die, these individual dies must be highly interconnected. As the die size shrinks and / or the number of input / output pins increases, it is becoming increasingly difficult to scale this connectivity.

Brief Description of the Drawings

[0002] [Figure 1] FIG. 13 is a block diagram of an exemplary semiconductor device implementing a mixed density interconnect architecture that utilizes hybrid fanout, according to an embodiment of the present disclosure. [Figure 2] FIG. 14 is a block diagram of an exemplary semiconductor module for a mixed density interconnect architecture that utilizes hybrid fanout, according to some embodiments of the present disclosure. [Figure 3] FIG. 15 is a block diagram of a semiconductor die interface for a mixed density interconnect architecture that utilizes hybrid fanout, according to some embodiments of the present disclosure. [Figure 4A] FIG. 16 shows a portion of an exemplary process flow for manufacturing a mixed density interconnect architecture that utilizes hybrid fanout, according to some embodiments. [Figure 4B]This figure shows a portion of an exemplary process flow for manufacturing a mixed-density interconnect architecture utilizing hybrid fan-out, according to several embodiments. [Figure 4C] This figure shows a portion of an exemplary process flow for manufacturing a mixed-density interconnect architecture utilizing hybrid fan-out, according to several embodiments. [Figure 4D] This figure shows a portion of an exemplary process flow for manufacturing a mixed-density interconnect architecture utilizing hybrid fan-out, according to several embodiments. [Figure 4E] This figure shows a portion of an exemplary process flow for manufacturing a mixed-density interconnect architecture utilizing hybrid fan-out, according to several embodiments. [Figure 4F] This figure shows a portion of an exemplary process flow for manufacturing a mixed-density interconnect architecture utilizing hybrid fan-out, according to several embodiments. [Figure 5] This is a block diagram of an exemplary semiconductor module for a mixed-density interconnect architecture utilizing hybrid fan-out, according to some embodiments of the present disclosure. [Figure 6A] This figure shows a portion of an exemplary process flow for manufacturing a mixed-density interconnect architecture utilizing hybrid fan-out, according to several embodiments. [Figure 6B] This figure shows a portion of an exemplary process flow for manufacturing a mixed-density interconnect architecture utilizing hybrid fan-out, according to several embodiments. [Figure 6C] This figure shows a portion of an exemplary process flow for manufacturing a mixed-density interconnect architecture utilizing hybrid fan-out, according to several embodiments. [Figure 6D] This figure shows a portion of an exemplary process flow for manufacturing a mixed-density interconnect architecture utilizing hybrid fan-out, according to several embodiments. [Figure 6E] This figure shows a portion of an exemplary process flow for manufacturing a mixed-density interconnect architecture utilizing hybrid fan-out, according to several embodiments. [Figure 7] This is a block diagram of an exemplary semiconductor device for a mixed-density interconnect architecture utilizing hybrid fan-out, according to some embodiments of the present disclosure. [Figure 8A] This figure shows a portion of an exemplary process flow for manufacturing a mixed-density interconnect architecture utilizing hybrid fan-out, according to several embodiments. [Figure 8B] This figure shows a portion of an exemplary process flow for manufacturing a mixed-density interconnect architecture utilizing hybrid fan-out, according to several embodiments. [Figure 8C] This figure shows a portion of an exemplary process flow for manufacturing a mixed-density interconnect architecture utilizing hybrid fan-out, according to several embodiments. [Figure 8D] This figure shows a portion of an exemplary process flow for manufacturing a mixed-density interconnect architecture utilizing hybrid fan-out, according to several embodiments. [Figure 8E] This figure shows a portion of an exemplary process flow for manufacturing a mixed-density interconnect architecture utilizing hybrid fan-out, according to several embodiments. [Figure 8F] This figure shows a portion of an exemplary process flow for manufacturing a mixed-density interconnect architecture utilizing hybrid fan-out, according to several embodiments. [Figure 9] This is a block diagram of an exemplary semiconductor device for a mixed-density interconnect architecture utilizing hybrid fan-out, according to some embodiments of the present disclosure. [Figure 10A] This figure shows a portion of an exemplary process flow for manufacturing a mixed-density interconnect architecture utilizing hybrid fan-out, according to several embodiments. [Figure 10B] This figure shows a portion of an exemplary process flow for manufacturing a mixed-density interconnect architecture utilizing hybrid fan-out, according to several embodiments. [Figure 10C] This figure shows a portion of an exemplary process flow for manufacturing a mixed-density interconnect architecture utilizing hybrid fan-out, according to several embodiments. [Figure 10D] This figure shows a portion of an exemplary process flow for manufacturing a mixed-density interconnect architecture utilizing hybrid fan-out, according to several embodiments. [Figure 11] This is a flowchart illustrating an exemplary method for manufacturing a mixed-density interconnect architecture utilizing hybrid fanout, according to several embodiments. [Modes for carrying out the invention]

[0003] One approach to SoC design and component reuse is the concept of "chiplets." A chiplet is a semiconductor die containing one or more nodes, such as functional circuit blocks or intellectual property (IP) blocks, specifically designed to work together with other chiplets to form larger and more complex chips. To modularize system designs and reduce complexity, these chiplets often contain reusable IP blocks. Integrating various heterogeneous chiplets into a single system can be challenging. For example, different types of chiplets may have different connectivity density requirements and / or capabilities.

[0004] One approach to chiplet integration is to place chiplets within a 2.5D package using a silicon interposer. However, the design and manufacture of silicon interposers are expensive and unsuitable for conventional applications and modularization.

[0005] Another approach to chiplet integration can be to use die-first fan-out packaging (e.g., integrated fan-out) where the inter-die connections are created after the dies are reconfigured. However, such packages are not compatible with external stacked devices such as high-bandwidth memory modules.

[0006] Yet another approach to chiplet integration can be to use die-last fan-out packaging (e.g., chip-on-wafer-on-substrate) where the inter-die connections are created on the wafer before the dies are reconfigured. However, this approach is limited in both input / output connection density and cost.

[0007] Yet another approach to chiplet integration can be to use silicon bridge dies (e.g., high-density cross-links or embedded interconnect bridges) between the dies. However, power delivery to the bridge die can be challenging, similar to the scalability to bump pitches less than 35 μm.

[0008] To address these issues, various embodiments according to the present disclosure provide a mixed density of inter-die connections that allow some chiplets to be tightly coupled with ultra-high density connection paths for improved input / output performance, while other chiplets may not be as tightly coupled with high-density connection paths for scalability and compatibility with external devices.

[0009] One embodiment according to the present disclosure relates to a semiconductor module including two or more semiconductor dies and an interconnect structure coupled to the two or more semiconductor dies to implement a plurality of die connection paths having a first density and a plurality of fan-out re-wiring paths having a second density different from the first density.

[0010] In some examples, the interconnect structure includes a redistribution layer fabricated on two or more dies. In other examples, the interconnect structure includes a redistribution layer fabricated on an interposer coupled to two or more dies.

[0011] In some examples, each of the two or more dies includes a die interface that includes a mixed density of input / output interconnects. In these examples, the plurality of interconnects for the die-to-die connection paths may have a pitch that is substantially finer than the pitch of the plurality of interconnects for the fan-out redistribution paths.

[0012] In some examples, at least a portion of the fan-out redistribution paths terminate in a module interconnect structure that is adapted to connect the semiconductor module to another device.

[0013] One embodiment according to the present disclosure relates to a semiconductor device including a semiconductor module including a first interconnect structure implementing a first plurality of connection paths connecting a first die to a second die, the first plurality of connection paths having a first density. The semiconductor device also includes a second interconnect structure connecting the semiconductor module to at least one peripheral component, the second interconnect structure implementing a second plurality of connection paths between the first die and the peripheral component, the second plurality of connection paths having a second density different from the first density.

[0014] In some examples, the first interconnect structure includes a redistribution layer fabricated on the first die, the second die, and a molding layer supporting the first die and the second die. In other examples, the first interconnect structure includes a redistribution layer fabricated on an interposer coupled to the first die and the second die. In some examples, at least the first die includes a die interface that includes a mixed density of input / output interconnects.

[0015] In some examples, multiple interconnections for inter-die connection paths may have a substantially finer pitch than multiple interconnections for a second set of connection paths. In some examples, the second interconnection structure includes interconnect dies within the second set of connection paths. In some examples, the interconnect dies are connected to semiconductor modules and peripheral modules through a redistribution layer formed on the surface of the second interconnection structure. In some examples, the second interconnection structure includes a wafer-level fan-out redistribution structure fabricated on an interposer.

[0016] Another embodiment of the present disclosure relates to a method for a hybrid fanout-based mixed-density interconnect architecture, comprising: coupling a first die to a second die using a first plurality of interconnects having a first density; and coupling a first die to a peripheral module using a second plurality of interconnects having a second density different from the first density.

[0017] In some examples, coupling a first die to a second die using a first plurality of interconnects having a first density includes using a hybrid bond to bond the first die and the second die to the redistribution layer of an interposer. In some examples, coupling a first die to a second die using a first plurality of interconnects having a first density includes manufacturing a redistribution layer on the first die and the second die. In some examples, coupling a first die to a peripheral module using a second plurality of interconnects having a second density different from the first density includes coupling the interconnect die to the first die and the peripheral module. In some examples, coupling a first die to a peripheral module using a second plurality of interconnects having a second density different from the first density includes using a wafer-level fan-out structure of the interposer to couple the first die to the peripheral module. In various examples, at least the first die includes a die interface with a mixed density of input / output interconnects.

[0018] Figure 1 is a block diagram showing exemplary architectures of a semiconductor device (100) according to various embodiments of the present disclosure. In some examples, the exemplary semiconductor device (100) may be a system-in-a-package (SiP) device or a semiconductor package of other advanced technology. The semiconductor device (100) may include multiple heterogeneous components, including a processor module and a memory module, integrated into a single package. In the example of Figure 1, the semiconductor device (100) includes multiple solder structures (158) (e.g., solder bumps) disposed on the surface of an interconnect structure (120), and the multiple solder structures (158) are exposed for connection to a substrate, printed circuit board (PCB), card, or other external components. The exemplary semiconductor device (100) is implemented in a variety of computing devices, including mobile devices, personal computers, peripheral hardware components, gaming devices, set-top boxes, and the like.

[0019] In the example shown in Figure 1, the semiconductor device (100) includes a semiconductor module (140) comprising two or more semiconductor dies (141, 143), such as semiconductor chips or chiplets. For example, the semiconductor module (140) may be a multi-die package or a similar semiconductor package. The semiconductor module (140) also includes a module-level interconnect structure (145) which includes connections between the two or more semiconductor dies (141, 143), and connections between the two or more semiconductor dies (141, 143) and a solder structure (147) disposed on the outward-facing surface of the interconnect structure (145) to connect the semiconductor module (140) to the interconnect structure (120). In one example, the semiconductor module (140) is a hybrid fan-out package in which the package is treated as if it were a single die, its connection to the interconnect structure (145), while the interconnect structure (145) tightly integrates the connections between the semiconductor dies (141, 143). As will be described in more detail below, in some examples the interconnect structure (145) may include a redistribution layer formed after two or more semiconductor dies (141, 143) have been reconfigured and formed, while in other examples the interconnect structure may include a redistribution layer on the interposer wafer. As will be described in more detail below the interconnect structure (145) includes mixed-density connections such that the connections between the two semiconductor dies (141, 143) have a higher connection density than the connections between each semiconductor die (141, 143) and the solder structure (147). The interconnect structure (145) may utilize fan-out of conductive traces into the region of the interconnect structure (145) where the solder structure (147) is disposed.

[0020] In the example shown in Figure 1, the semiconductor device (100) includes one or more peripheral modules (150, 152). In various examples, the peripheral modules (150, 152) may include memory modules, accelerators, PCIe or other fabric interfaces, optical modules, other package components, or combinations thereof. In one example, the peripheral modules (150, 152) are memory interface modules such as high-bandwidth memory modules (HBM), which include memory interface dies (e.g., chiplets) and stacked memory devices. The peripheral modules (150, 152) may include various dies, integrated circuits, memory devices, passive components, interconnects, buses, etc., which are not shown. In the example shown, the peripheral modules (150, 152) are electrically and physically coupled to the package-level interconnect structure (120) by solder structures (154, 156), such as solder bumps.

[0021] In the example shown in Figure 1, the interconnect structure (120) connects two or more semiconductor dies (141, 143) of a semiconductor module (140) to two or more peripheral modules (150, 152). The example in Figure 1 shows that the integrated circuit (141) is connected to the peripheral module (150) through the interconnect structure (120), and that the integrated circuit (143) is connected to the peripheral module (152) through the interconnect structure (120), but it will be understood that other layouts may be used. For example, each die may be connected to one or more other integrated circuits and one or more peripheral modules. In one example, the interconnect structure (120) includes a fan-out redistribution layer structure to which the semiconductor module (140) and peripheral modules (150, 152) are joined, as will be described in more detail below. In another example, the interconnection structure (120) includes a silicon bridge die coupled to the die of the semiconductor module (140) and the peripheral modules (150, 152) through a redistribution layer to which the semiconductor module (140) and peripheral modules (150, 152) are joined, as will be described in more detail below. In some examples, the interconnection structure (120) includes a solder structure (158) for coupling a semiconductor device (100) to another device, wafer, substrate or circuit board.

[0022] For further explanation, Figure 2 shows a cross-sectional view of an exemplary implementation example of a semiconductor module (200) according to various embodiments of the present disclosure. In some examples, the exemplary implementation example of the semiconductor module (200) shown in Figure 2 can be used as the semiconductor module (140) in Figure 1. The exemplary semiconductor module (200) in Figure 2 comprises two or more dies (240, 250) disposed on an interposer (260) and encapsulated within an inorganic encapsulation layer (270), the inorganic encapsulation layer may, in some examples, be capped with a silicon cap wafer (280). The exemplary semiconductor module (200) in Figure 2 may be produced by a “die-last” manufacturing process in which, for example, connection routing in the redistribution layer of the interposer (260) is completed before the dies (240, 250) are bonded to the interposer (260), and the encapsulation layer (270) and cap wafer (280) are added before dicing, as will be described in more detail below.

[0023] In the example shown in Figure 2, each of the two or more dies (240, 250) may be constructed from silicon, germanium, or other types of semiconductor material and includes a substrate (242, 252) containing various functional logic blocks, logic gates, clocks, buses, and other elements formed within the substrate, as can be understood by those skilled in the art. Each of the two or more dies (240, 250) also includes a die interface (244, 254) containing a metallization layer and an interlevel dielectric layer, as well as conductor structures such as vias, traces, and pads (e.g., die-level build-up structures such as a back-end of line (BEOL) layer generated during die manufacturing). Each of the die interfaces (244, 254) includes several metal contacts for transmitting power, ground, input signals, and output signals, which can be joined to corresponding metal contacts disposed on the surface of the interposer (260). For example, each of the die interfaces (244, 254) includes a group of metal contacts which are input / output signal pads (247, 249, 257, 259) (hereinafter referred to as “I / O pads”) having a finer pitch (e.g., less than 10 μm) for die-to-die connections, and a group of I / O pads having a coarser pitch (45 μm to 55 μm) for die-to-peripheral connections, thus enabling a density of die-to-die connections higher than the density of connections between each die and the interconnection structure (285) of the interposer (260) on the outward-facing surface of the semiconductor module (200), as will be further described below. The reader will understand that the terms “fine” or “finer” and “coarse” or “coarser” are used herein as relative terms to compare the pitches of I / O pads and should not be interpreted as assigning a specific pitch or range of pitches, or giving an absolute value.

[0024] In the example shown in Figure 2, the interposer (260) implements a redistribution layer structure including a metallization layer and an interlevel dielectric layer. For example, the interposer (260) may be a wafer-level build-up structure such as a BEOL layer generated during interposer wafer manufacturing, and the silicon of the interposer wafer is removed so that only the interposer (260) remains. The redistribution layer structure of the interposer (260) may include multiple layers of conductor structures (262), such as traces, pads, vias, and other types of conductor structures suitable for manufacturing, and multiple interlevel dielectric layers (264). In various examples, the conductor structures (262) consist of copper, aluminum, gold, platinum, palladium, or a combination of other conductors, and are manufactured using well-known material deposition techniques such as plating, sputtering, chemical vapor deposition, or a combination thereof, and may be patterned using well-known photolithography and directional etching techniques as needed. The interlevel dielectric layer (264) may be composed of glass such as SiOx or other types of interlevel dielectric layer materials.

[0025] In some examples, multiple metal contacts formed at corresponding pitches are arranged on the inner surface of the interposer (260), including signal pads (263, 265, 267, 269) aligned opposite the I / O pads (247, 249, 257, 259) of the die interface (244, 254). In one example, the conductor structure (262) is manufactured with a fine line width and spacing of approximately 1.0 μm or less, thereby providing a high-density interconnection path between relatively fine-pitch signal pads. In this example, some conductor structures can fan out and interconnect lower-density paths from relatively coarser-pitch signal pads, thereby allowing the interconnection path to scale out to accommodate connections to the interconnection structure (285). In these examples, some of the interposer's conductive structures (262) implement high-density connections between groups of higher-density, finer-pitch I / O pads (247, 257) on semiconductor dies (240, 250), and lower-density connections between lower-density, coarser-pitch I / O pads (249, 259) and interconnect structures (285) on opposing surfaces of the interposer (260) for connecting the semiconductor module (240) to a substrate, wafer, package, or other component. In the exemplary implementation shown in Figure 2, the interposer (260) may be used as a module-level interconnect structure (145) for the exemplary semiconductor device (100) shown in Figure 1.

[0026] In some examples, semiconductor dies (240, 250) are electrically and physically coupled to an interposer (260) by hybrid bonding technology. In one example, a dielectric junction (e.g., an oxide junction) is formed between each semiconductor die (240, 250) and the interposer (260) by applying a dielectric between them. In this example, when heat is applied, the metal contacts of each semiconductor die (240, 250) (e.g., I / O pads (247, 249, 257, 259)) and the metal contacts of the interposer (260) (e.g., signal pads (263, 265, 267, 269)) expand. When the metal interconnects of each semiconductor die (240, 250) and the interposer (260) are aligned, their expansion causes the aligned metal interconnects to contact and bond, thereby forming the metal interconnect junction of the hybrid bonding. In this way, a junction is formed by the dielectric and the expanded and joined metal interconnects. The space between and around the semiconductor die can be filled with an oxide filler material that forms an encapsulation material layer (270).

[0027] In another example of a hybrid junction, the interconnection between each semiconductor die (240, 250) and the interposer (260) consists of a metallurgical junction between the die's I / O pads (247, 249, 257, 259) and the interposer's signal pads (263, 265, 267, 269). In addition, an insulating junction layer bonds each semiconductor die (240, 250) to the interposer (260) and includes a glass layer such as SiOx on the die and another glass layer such as silicon oxynitride on the interposer. The I / O pads (247, 249, 257, 259) and signal pads (263, 265, 267, 269) are metallurgically bonded by an annealing process. In this regard, each semiconductor die (240, 250) is lowered onto the interposer structure or otherwise positioned such that the glass layer of each semiconductor die (240, 250) is on or very close to the silicon oxynitride layer, and the I / O pads (247, 249, 257, 259) are on or very close to the signal pads (263, 265, 267, 269). Subsequently, an annealing process is performed to induce transient thermal expansion of the I / O pads (247, 249, 257, 259) and signal pads (263, 265, 267, 269), bringing these structures into physical contact and forming a metallurgical bond between them that persists after cooling. The areas between and around the semiconductor dies may be filled with oxide packing material to form an encapsulation material layer (270).

[0028] For further reference, Figure 3 shows exemplary configurations (300) of the exemplary die interface (245, 254) of Figure 2 according to various embodiments of the present disclosure. In one example, each I / O pad of the die interface (244, 254) includes, among other things, one or more ultra-high density arrays (310, 320) of I / O pads (312, 322) for die-to-die connections and one or more high density arrays (330, 340) of I / O pads (332, 342) for die-to-peripheral connections. In this example, the array (310) of I / O pads (312) includes several pads arranged around the semiconductor chip die (240) in close proximity to the opposing semiconductor die (250) to transmit input signals to and output signals from the semiconductor die (250). In this example, the array (320) of I / O pads (322) includes several pads arranged around the semiconductor die (250) in close proximity to the opposing semiconductor die (240) to transmit input signals to and output signals from the semiconductor die (240). In this example, the array (330, 340) of I / O pads (332, 342) includes several pads arranged around the semiconductor dies (240, 250) to transmit external input signals to and output signals from the semiconductor module (200). Although only I / O pads are shown, the reader will understand that other pads may exist for transmitting power, ground, or other signals.

[0029] In some examples, the pitch of ultra-high-density I / O pads (312, 322) is substantially finer than the pitch of high-density I / O pads (332, 342). In some examples, the pitch of I / O pads (312, 322) in the first and second arrays (310, 320) can be 5 μm to 10 μm. In some examples, the pitch of I / O pads (332, 342) in the high-density array (330, 340) can be 45 μm to 55 μm. The reader will understand that ultra-high-density arrays (310, 320) enable a higher connection density for inter-chip communication, while high-density arrays can be adapted to a lower connection density for connecting semiconductor modules to wafer-level fan-out structures (e.g., through solder bumps). In this way, the integrated fan-out interconnect between semiconductor dies (240, 250) can be used in conjunction with wafer-level fan-out to support interconnection of the semiconductor dies (240, 250) within the module (200) to peripheral components (e.g., high-bandwidth memory modules).

[0030] For further explanation, Figures 4A to 4F show exemplary process flows for constructing a semiconductor module, such as exemplary implementation examples of the semiconductor module (200) shown in Figure 2, according to various embodiments. For example, the exemplary process flows shown in Figures 4A to 4F may be “die lasts,” in which multiple dies are packaged on an interposer, and the packages are then diced into individual packages, each containing a die or a group of dies. In some examples, the dies may be grouped such that each group contains the same set of dies. In these examples, to facilitate the dicing process, groups of dies may be clustered such that the physical distance between each die within a group (e.g., 20–50 μm) is shorter than the distance between two groups of dies.

[0031] Starting from Figure 4A, at 410, the dies (412, 413, 414, 415) are bonded to the interposer wafer (422). In one example, bonding the dies (412, 413, 414, 415) to the interposer wafer (422) is performed by turning the dies (412, 413, 414, 415) over so that the die interfaces (452, 453, 454, 455) are in contact with the interposer layer (423) of the interposer wafer (422), and then performing the hybrid bonding technique described above. The inter-die connection is achieved by a fine wire connection path within the interposer layer (423). As described above, among the other bonding interconnection structures, the fine-pitch I / O pad groups (412, 413, 414, 415) are bonded to the corresponding signal pads on the interposer layer (423), and the coarse-pitch I / O pad groups are bonded to the corresponding signal pads on the interposer layer (423). The interposer layer (423) includes a redistribution layer structure formed during the wafer manufacturing process. One advantage of manufacturing the interposer layer (423) on the interposer wafer (422), separate from and in addition to the initial manufacturing of the semiconductor dies (412, 413, 414, 415), is that the redistribution layer structure can be larger than the footprint of the dies (412, 413, 414, 415).

[0032] Moving to Figure 4B, in step 420, device thinning and gap filling are performed. In one example, device thinning and gap filling are performed by grinding the silicon substrate of the dies (412, 413, 414, 415) to reduce the height in the z direction and by filling the areas between the dies (412, 413, 414, 415) with an inorganic encapsulation material (425) (e.g., silicon oxide). The encapsulation material (425) is deposited on the semiconductor dies (412, 413, 414, 415) and other otherwise exposed portions of the interposer layer (423).

[0033] Moving to Figure 4C, in step 430, surface planarization and capping are performed. In one example, surface planarization and capping are performed by smoothing the surface of the encapsulation material (425) and bonding the silicon cap wafer (435) to the surface of the encapsulation material. The encapsulation material (425) is thinned (for example by chemical mechanical polishing, CMP) so that a thin portion of the material remains above the semiconductor dies (412, 413, 414, 415). The interposer wafer (522) provides mechanical support and protection, for example, during both the grinding and CMP processes.

[0034] Moving to Figure 4D, in step 440, the interposer layer (423) is exposed. In one example, the exposure of the interposer layer (423) is performed by grinding or etching the silicon of the interposer wafer (422) until the metallization layer of the interposer layer (423) is exposed. The grinding process removes most of the interposer wafer (422).

[0035] Moving to Figure 4E, step 450 involves redistribution layer processing and bumping. In one example, redistribution layer processing and bumping are performed by processing the redistribution layer structure and terminal metal on the exposed surface of the interposer layer (423) and attaching conductive interconnect structures (e.g., solder bumps) to the redistribution layer structure. In this example, an etch-back process can be used to expose a portion of the bottom metallization layer of the interposer layer (423) in preparation for the attachment of interconnects (485), such as the interconnect structure (285) shown in Figure 2. For example, etch-back may be performed as a dry etch with plasma enhancement. Directional etching may be desirable to establish relatively vertical sidewalls for any openings leading to the bottom metallization of the interposer (260). In these examples, the interconnects (485) are attached to the redistribution layer structure using a cap wafer (435) that provides support. In some examples, attachment may involve or be performed in conjunction with the fabrication of underbump metallization (UBM).

[0036] Moving to Figure 4F, in step 460, dicing is performed. In one example, dicing is carried out by a fragmentation process in which the cap wafer (435) and individual groupings of semiconductor dies (412, 413) and (414, 415) undergo fragmentation, resulting in fan-out packages (461) and another fan-out package (462) consisting of semiconductor dies and their associated interposer / redistribution layer structures. At this point, the fan-out packages (461) and (462) can be attached to a circuit board, wafer, package, or other interconnection structure.

[0037] For further explanation, Figure 5 shows a cross-sectional view of an exemplary implementation of a semiconductor module (500) according to the present disclosure. In some implementations, the exemplary implementation of the semiconductor module (500) shown in Figure 5 can be used as the semiconductor module (140) in Figure 1. The exemplary semiconductor module (500) in Figure 5 includes two or more integrated circuits, namely two or more dies (540, 550) encapsulated in an inorganic encapsulation material layer (570) on which a fab-like redistribution layer structure (560) is disposed, all of which are supported by a carrier (580) (e.g., a glass carrier). The exemplary semiconductor module (500) in Figure 5 may be produced by a “die-first” manufacturing process in which the connection routing within the redistribution layer structure (560) is completed after the dies (540, 550) are reconfigured, and the encapsulation material layer (570) and carrier (580) are added after dicing, for example, as will be described in more detail below.

[0038] In the example shown in Figure 5, each of the two or more dies (540, 550) may be configured similarly to the two or more dies (240, 250) shown in Figure 2. Furthermore, each of the two or more dies (540, 550) may include substrates (542, 552) that may be configured similarly to the substrates (242, 252) shown in Figure 2. Furthermore, each of two or more dies (540, 550) may include a die interface (544, 554) that includes a die interface (544, 554) with a relatively fine pitch (e.g., less than 10 μm) for inter-die connections, which is finer (e.g., less than 10 μm) than a group of I / O pads (549, 559) having a relatively coarser pitch (e.g., 45 μm to 55 μm) for die-to-peripheral connections, as will be further described below. Thus, the die interface (544, 554) may be configured similarly to the die interface (244, 254) shown in Figure 2, in that it enables a density of inter-die connections higher than the density of connections between each die and the interconnection structure (585) of the redistribution layer structure (560) on the outward-facing surface of the semiconductor module (500).

[0039] In the example shown in Figure 5, the redistribution layer structure (560) includes a metallization layer and an interlevel dielectric layer. For example, the redistribution layer structure (560) may be a build-up structure formed on the surface of an encapsulation material layer (570) including dies (540, 550) such that the surface of the encapsulation material structure is the exposed active surface of the die on the same plane. The redistribution layer structure (560) may include multiple layers of conductor structures (562), such as traces, pads, vias, and other types of conductor structures suitable for manufacture, and multiple interlevel dielectric layers (564). In various examples, the conductor structures (562) consist of copper, aluminum, gold, platinum, palladium, or combinations of other conductors, and are manufactured using well-known material deposition techniques such as plating, sputtering, chemical vapor deposition, or combinations thereof, and may be patterned using well-known photolithography and directional etching techniques as needed. The interlevel dielectric layers (564) may consist of glass such as SiOx or other types of interlevel dielectric layer materials. The reader will understand that the redistribution layer structure (560) differs from the interposer (260) in that the redistribution layer structure (560) is not formed on the carrier or interposer wafer, but instead is formed directly on the surface of the die and encapsulation material.

[0040] In some examples, multiple metal contacts are arranged on the inner surface of the redistribution layer structure (560), including signal pads (563, 565, 567, 569) that are in electrical contact with the I / O pads (547, 549, 557, 559) of the die interface (544, 554), and are formed with corresponding pitches. In one example, the conductor structure (562) is manufactured with a fine line width and spacing of about 1.0 μm or less, thereby providing a high-density interconnection path between relatively fine-pitch signal pads. In this example, some conductor structures can fan out and interconnect lower-density paths from relatively coarser-pitch signal pads, thereby enabling the interconnection path to scale out to accommodate connections to the interconnection structure (585). In these examples, some of the conductor structures (562) of the redistribution layer implement high-density connections between groups of higher-density, finer-pitch I / O pads (547, 557) on semiconductor dies (540, 550), and lower-density connections between lower-density, coarser-pitch I / O pads (549, 559) and interconnect structures (585) on the opposing surface of the redistribution layer structure (560) for connecting the semiconductor module (540) to a substrate, wafer, package, or other component. Vias (not shown) within the redistribution layer structure (560) connect interconnect paths from the I / O pads (549, 559) to interconnect structures (585) (e.g., solder bumps) on the outward-facing surface of the redistribution layer structure. In the exemplary implementation shown in Figure 5, the redistribution layer structure (560) may be used as a module-level interconnect structure (145) for the exemplary semiconductor device (100) shown in Figure 1.

[0041] For further explanation, Figures 6A–6E show exemplary process flows for constructing a semiconductor module, such as exemplary mounting examples of the semiconductor module (500) shown in Figure 5, according to various embodiments. Starting with Figure 6A, in step 610, the diced and sorted dies (640, 650) are reconfigured on a carrier (660). In one example, the reconfiguration of the dies (640, 650) can be performed by attaching the die interfaces (641, 651) of the dies (640, 650) to the carrier (660) by various well-known bonding techniques. The carrier wafer may include a delamination layer (not shown) for later removal. The carrier (660) provides mechanical support for the dies (640, 650) and may be composed of glass or other suitable material.

[0042] Moving to Figure 6B, in step 620, device thinning and gap filling are performed. In one example, device thinning and gap filling are performed by grinding the silicon substrate of the die (640, 650) to reduce the height in the z direction and filling the region between the die (640, 650) with an inorganic encapsulation material (625) (e.g., silicon oxide). The encapsulation material (625) is deposited on the semiconductor die (640, 650) and the carrier (660) in any other way exposed portion.

[0043] Moving to Figure 6C, in step 630, the support (660) is removed, exposing the coplanar surfaces of the die interfaces (641, 651) and the encapsulation material (625). In one example, the removal of the support (660) is performed by adding an upper support (670) to the upper (back) side of the encapsulation material (625) to support the encapsulation material (625) and the die (640, 650) during further processing, and by removing the support (660) by activating a release layer to detach the support (660) from the encapsulation material (625) and the die (640, 650), for example. For example, the upper support (670) may be a glass support.

[0044] Moving to Figure 6D, in step 640, a redistribution layer structure (690) is processed on the exposed surfaces of the dies (640, 650) and the encapsulation material (625). As described above with reference to Figure 5, the redistribution layer structure (690) may be generated to form interconnection paths between the dies (640, 650) and between each die and external interconnection structures such as interconnection structures (585), and to include multiple levels of metallization of the dielectric layer. Die-to-die interconnection is achieved by high-density fine-wire connection paths within the redistribution layer structure (690) that connect the fine-pitch (e.g., ultra-fine-pitch) I / O pads of each die (640, 650). Die-to-package interconnection is achieved by lower-density connection paths between groups of coarser-pitch (e.g., fine-pitch) I / O pads to interconnection structures such as bumps or pillars.

[0045] Moving to Figure 6E, in step 650, the interconnect structure (685) is formed on the exposed surface of the redistribution layer structure (690). In one example, forming the interconnect structure on the exposed surface of the redistribution layer structure (690) is done by attaching solder bumps to the redistribution layer structure (690). In some examples, the attachment may be accompanied by or performed in conjunction with underbump metallization (UBM) fabrication. At this point, the fan-out package (495) may be attached to the circuit board, wafer, package, or other interconnect structure.

[0046] For further explanation, Figure 7 shows a cross-sectional view of an exemplary implementation example of a semiconductor device (700) according to various embodiments of the present disclosure. In one example, the semiconductor device (700) includes a fan-out multi-chip / multi-die semiconductor module (702), such as the semiconductor module (140) shown in Figure 1, the semiconductor module (200) shown in Figure 2, or the semiconductor module (500) shown in Figure 5. The semiconductor module (702) implements ultra-high density I / O connection paths between two or more dies (721, 722), while implementing lower density I / O connection paths within a fan-out structure that can be implemented by a module-level interconnect structure (724), such as any of the module-level interconnect structures described above. In this example, the semiconductor device (700) includes a peripheral module (704) (e.g., a memory module) coupled to one of the dies in the semiconductor module (702) through an interconnect structure (706), but the reader will understand that additional (heterogeneous or homogeneous) peripheral modules may be included for connection to other dies in the semiconductor module. Continuing this example, the semiconductor module (702) and peripheral module (704) are connected to a device substrate (708) through the interconnect structure (706). In some examples, an underfill material is interposed between the interconnect structure (706) and the substrate (708). In one example, the semiconductor module (702) and peripheral module (704) are coupled to the interconnect structure by conductive bumps (795, 796).

[0047] In the exemplary implementation shown in Figure 7, the interconnect structure (706) includes a redistribution layer (761) formed on an encapsulation material layer (762) into which a plurality of conductive pillars (763) and interconnect dies (764) are embedded. In some examples, the redistribution layer (761) includes, among other things, connection paths for routing I / O signals between the interconnect dies (764) and the semiconductor module (702), and between the interconnect dies (764) and peripheral modules (704). The redistribution layer (761) implements high-density I / O connection paths between the high-density integrated fan-out interconnect of the semiconductor module (702) and the interconnect die (764). The redistribution layer (761) also implements high-density I / O connection paths between the high-density interconnect of the peripheral modules (704) and the interconnect die (764). The redistribution layer (761) may include multiple layers of conductive structures (not shown), such as traces, pads, vias, and other types of conductive structures suitable for manufacturing, and multiple interlevel dielectric layers (not shown). In one example, the conductive structures are manufactured with fine line widths and spacing of about 1.0 μm or less, thereby providing high-density interconnection paths between signal pads with relatively fine pitches. In various examples, the conductive structures are composed of copper, aluminum, gold, platinum, palladium, or a combination of other conductors, and are manufactured using well-known material deposition techniques such as plating, sputtering, chemical vapor deposition, or a combination thereof, and may be patterned using well-known photolithography and directional etching techniques as needed. The interlevel dielectric layers may be composed of glass such as SiOx or other types of interlevel dielectric layer materials.

[0048] In some examples, the interconnect die (764) is designed to provide a high-density crosslink between the semiconductor module (702) and the peripheral module (704) for high-speed signal transmission, also via the redistribution layer (761). The interconnect die (764) includes an interconnect structure (767) which includes traces and vias bridging the area of ​​the redistribution layer (761).

[0049] In some examples, the encapsulation material layer (762) is composed of an epoxy or other polymer material that exhibits a suitable viscosity at the applicable molding temperature and has a molding temperature lower than the melting point of any of the solder structures present during the molding process. In some examples, a similar encapsulation material layer (773) is molded over the exposed portions of the semiconductor module (702), peripheral module (704), and redistribution layer (761).

[0050] In some examples, conductive pillars (763) provide conductive paths to the redistribution layer (761) and therefore to the semiconductor module (702), peripheral module (704), and interconnect die (764). The conductive pillars (763) may be made of a conductive metal such as copper or another conductive metal. Conductive bumps (765) are applied to the conductive pillars (763). The conductive bumps (765) provide solderable connection points for bonding to the substrate (708). For example, the conductive bumps (765) include copper, a tin-silver alloy, or another conductive material suitable for solderable connections. Thus, the conductive bumps (765) and conductive pillars (763) provide conductive paths from the surface of the substrate (708) to the redistribution layer (761) which connects the semiconductor module (702), peripheral module (704), and interconnect die (764) to provide the transmission of input / output signals, power, and ground to these components.

[0051] The reader will understand that the mixed-density interconnect architecture utilizing the hybrid fan-out described above provides high-density connectivity paths between individual dies of a multi-die module and peripheral modules such as memory interfaces, while still achieving ultra-high-density inter-die connectivity within the multi-die module through the use of mixed-density I / O pitch and high-density cross-link dies.

[0052] For further explanation, Figures 8A to 8E show exemplary process flows for constructing semiconductor devices, such as exemplary mounting examples of the semiconductor device (700) shown in Figure 7, according to various embodiments. Starting from Figure 8A, in step 810, conductive pillars (863) are generated on a carrier (812). Generating conductive pillars (863) on the carrier (812) can be carried out by various well-known techniques. In one example, generating conductive pillars (863) on the carrier (812) is carried out by depositing a stripping layer (not shown) and a plating seed layer (not shown), and then performing a plating process to plate the conductive pillars (863) using a photoresist mask which is subsequently removed. In some examples, the conductive pillars (863) are made of copper. In some examples, the carrier (812) is a glass carrier.

[0053] Moving to Figure 8B, in step 820, an interconnecting die (864) including an interconnecting structure (867) is attached to the carrier (812). In one example, the attachment of an interconnecting die (864), such as an interconnecting die (764), is performed by attaching the interconnecting die (864) using a die attach film that contacts the release layer of the carrier (812).

[0054] Moving to Figure 8C, in step 830, the encapsulation material layer (862) is deposited. In one example, depositing the encapsulation material layer (862) is performed by forming a suitable encapsulation material on the conductive pillar (863) and interconnecting die (864) with the carrier (812) in a predetermined position, and by grinding or etching the encapsulation material to expose the upper part of the conductive pillar and the interconnecting structure (867) of the interconnecting die (864).

[0055] Moving to Figure 8D, in step 840, the redistribution layer (861) is fabricated on top of the interconnect structure (867) of the encapsulation material layer (862), the exposed conductive pillars (863), and the interconnect die (864). In one example, the fabrication of the redistribution layer (861) is carried out such that the various conductive structures of the redistribution layer (861) are fabricated in metallurgical contact with the interconnect structure (867) of the conductive pillars (863) and the interconnect die (864). The redistribution layer (861) can be constructed using the fabrication techniques described above.

[0056] Moving to Figure 8E, in step 850, the semiconductor module (802) and peripheral module (804) are mounted on the redistribution layer (861). In one example, mounting the semiconductor module (802) and peripheral module (804) onto the redistribution layer (861) is performed by bonding the interconnects (886, 887) of the semiconductor module (802) and peripheral module (804) to the redistribution layer (861) by a preferred bonding technique. Next, a molded layer (873) is formed on and around the semiconductor module (802) and peripheral module (804).

[0057] Moving to Figure 8F, in step 860, the interconnect (885) is attached to the conductive pillar (863). In one example, attaching the interconnect (885) to the conductive pillar (863) is performed by peeling off the carrier (812) (for example, by activating the peel layer) and attaching the interconnect (885) (for example, a solder bump) to the conductive pillar.

[0058] For further explanation, Figure 9 shows a cross-sectional view of an exemplary implementation example of a semiconductor device (900) according to various embodiments of the present disclosure. In one example, the semiconductor device (900) includes a fan-out multi-chip / multi-die semiconductor module (902), such as the semiconductor module (140) shown in Figure 1, the semiconductor module (200) shown in Figure 2, or the semiconductor module (500) shown in Figure 5. The semiconductor module (902) implements ultra-high density I / O connection paths between two or more dies (921, 922), while implementing lower density I / O connection paths in a fan-out structure that may be implemented by a module-level interconnection structure (924), such as any of the module-level interconnection structures described above. In this example, the semiconductor device (900) includes a peripheral module (904) (e.g., a memory module) connected to one of the dies in the semiconductor module (902) through a redistribution layer structure (906), but the reader will understand that additional (different or similar) peripheral modules may be included for connection to other dies in the semiconductor module. In one example, the semiconductor module (902) and the peripheral module (904) are coupled to an interconnect structure by conductive bumps (995, 996). In some examples, an encapsulation material layer (973) is molded over the exposed portions of the semiconductor module (902), peripheral module (904), and redistribution layer structure (906). The encapsulation material layer (762) may consist of an epoxy or other polymer material that exhibits a suitable viscosity at an applicable molding temperature and has a molding temperature lower than the melting point of any solder structure present during the molding process.

[0059] In the exemplary implementation shown in Figure 9, the redistribution layer structure (906) includes connection paths for routing I / O signals between a semiconductor module (902) and a peripheral module (904). The redistribution layer structure (906) implements a high-density wafer-level fan-out I / O connection path between the integrated high-density fan-out interconnect of the semiconductor module (902) and the high-density interconnect of the peripheral module (904). The redistribution layer structure (906) may include multiple layers of conductive structures (not shown), such as traces, pads, vias, and other types of conductive structures suitable for manufacturing, and multiple interlevel dielectric layers (not shown). In one example, the conductive structures are manufactured with fine line widths and spacing of approximately 1.0 μm or less, thereby providing high-density interconnection paths between signal pads with relatively fine pitches. In various examples, the conductive structure consists of copper, aluminum, gold, platinum, palladium, or a combination of other conductors, and is manufactured using well-known material deposition techniques such as plating, sputtering, chemical vapor deposition, or a combination thereof, and may be patterned using well-known photolithography and directional etching techniques as needed. The interlevel dielectric layer may consist of glass such as SiOx or other types of interlevel dielectric layer materials. In some examples, interconnection structures (985) (e.g., solder bumps) are disposed on the redistribution layer structure (906) by various well-known techniques and are electrically coupled to the metallization layer within the redistribution layer structure (906). In some examples, the interconnection structure (985) provides a connection path between the above-specified components of the semiconductor device (900) and a substrate, card, wafer, or other circuit board (not shown).

[0060] The reader will understand that the mixed-density interconnect architecture utilizing the hybrid fan-out described above provides high-density connectivity paths between individual dies of a multi-die module and peripheral modules such as memory interfaces, while still achieving ultra-high-density inter-die connectivity within the multi-die module through the use of mixed-density I / O pitch and wafer-level fan-out redistribution layers.

[0061] For further explanation, Figures 10A to 10D show exemplary process flows for constructing semiconductor devices, such as exemplary mounting examples of the semiconductor device (900) shown in Figure 9, according to various embodiments. Starting with Figure 10A, in step 1010, a redistribution layer (1006) is generated on a carrier (1012). In one example, the wafer-level fan-out structure is generated within various metallization layers by various techniques for constructing the redistribution layer as described above. The carrier (1012) may consist of glass or another preferred material to support the redistribution layer (1006) and may include a release layer (not shown).

[0062] Moving to Figure 10B, in step 1020, the semiconductor module (1002) (for example, semiconductor module (902) and peripheral module (1004)) is mounted on the redistribution layer (1006). In one example, mounting the semiconductor module (1002) and peripheral module (1004) onto the redistribution layer (1006) is performed by bonding the interconnections (1086, 1087) of the semiconductor module (1002) and peripheral module (1004) to the redistribution layer (1006) by a suitable bonding technique.

[0063] Moving to Figure 10C, in step 1030, the encapsulation material layer (1062) is deposited. In one example, the deposition of the encapsulation material layer (1062) is performed by forming a suitable encapsulation material on and around the semiconductor module (1002) and peripheral module (1004), as well as on the exposed portions of the redistribution layer (1006).

[0064] Moving to Figure 10D, in step 1040, the interconnect (1085) is attached to the redistribution layer (1006). In one example, attaching the interconnect (885) to the conductive pillar (863) is performed by peeling off the carrier (1012) (e.g., by activating a delamination layer) or by other means (e.g., by grinding), and attaching the interconnect (1085) (e.g., a solder bump) to a conductive pad in the redistribution layer (1006), for example, using the techniques described above.

[0065] For further explanation, Figure 11 shows a flowchart illustrating an exemplary method for a mixed-density interconnect architecture utilizing hybrid fan-out, including coupling a first die to a second die (1102) using a first plurality of interconnects having a first density. In one example, coupling a first die to a second die (1102) using a first plurality of interconnects having a first density is performed by coupling the first die and the second die to a redistribution layer of an interposer using a hybrid bond. In this example, coupling a first die to a second die (1102) using a first plurality of interconnects having a first density can be performed through the exemplary process flow shown in Figures 4A to 4F. In another example, coupling a first die to a second die (1102) using a first plurality of interconnects having a first density is performed by manufacturing a redistribution layer on top of the first die and the second die. In this example, coupling a first die to a second die using a first set of interconnections having a first density (1102) can be performed through the exemplary process flow shown in Figures 6A to 6D.

[0066] Furthermore, the exemplary method in Figure 11 includes coupling the first die to a peripheral module (1104) using a second plurality of interconnects having a second density different from the first density (for example, the second density is less than the first density). In one example, coupling the first die to a peripheral module (1104) using a second plurality of interconnects having a second density different from the first density is performed by coupling the interconnect die to the first die and the peripheral module. In this example, coupling the first die to a peripheral module (1104) using a second plurality of interconnects having a second density different from the first density can be performed through the exemplary process flow shown in Figures 8A to 8F. In another example, coupling the first die to a peripheral module (1104) using a second plurality of interconnects having a second density different from the first density is performed by coupling the first die to a peripheral module using a wafer-level fan-out structure of the interposer. In this example, coupling the first die to a peripheral module (1104) using a second set of interconnects having a second density different from the first density can be performed through the exemplary process flow shown in Figures 10A to 10D.

[0067] Considering the above explanation, readers will recognize that the advantages of a hybrid fan-out mixed-density interconnect architecture include improved input / output performance by providing a mixed density of interconnects that allows some dies to be tightly coupled to ultra-high density connection paths, improved scalability and compatibility with external devices by providing a mixed density of interconnects that allows some dies to be less tightly coupled to high density connection paths, and enhanced integration of heterogeneous dies within a single package.

[0068] It will be understood from the above description that modifications and changes can be made to various embodiments of this disclosure. The statements herein are for illustrative purposes only and should not be construed as restrictive. The scope of this disclosure is limited only by the following claims.

Claims

1. It is a semiconductor device, Semiconductor modules and One or more peripheral components outside the semiconductor module, The semiconductor module is further comprising a second interconnection structure for connecting one or more peripheral components, The aforementioned semiconductor module is Two or more semiconductor dies, each semiconductor die having a mixed density input / output interconnect on its die surface, the mixed density input / output interconnect includes a first group interconnect and a second group interconnect, and the first group interconnect has a different density from the second group interconnect, and The system comprises a first interconnection structure coupled to two or more semiconductor dies, The first interconnection structure implements a plurality of die-to-die connection paths having a first density and a plurality of fan-out rerouting paths having a second density different from the first density, The multiple inter-die connection paths and the multiple fan-out rewiring paths are formed together within the same rewiring layer structure. The plurality of inter-die connection paths directly connect the interconnection of the first group of the first semiconductor die among the two or more semiconductor dies to the interconnection of the first group of the second semiconductor die among the two or more semiconductor dies. The plurality of fan-out rerouting paths connect the interconnections of the second group of the first semiconductor die to one or more package interconnections. The second interconnection structure includes interconnection dies connected to the plurality of fan-out rewiring paths, Semiconductor devices.

2. The aforementioned redistribution layer structure is manufactured on the two or more semiconductor dies. A semiconductor device according to claim 1.

3. The redistribution layer structure is manufactured on an interposer coupled to two or more semiconductor dies. A semiconductor device according to claim 1.

4. Each of the two or more semiconductor dies includes a die interface that includes a mixed density input / output interconnection, A semiconductor device according to claim 1.

5. The plurality of interconnections for the inter-die connection path have a finer pitch than the plurality of interconnections for the fan-out rewiring path. The semiconductor device according to claim 4.

6. At least a portion of the fan-out rewiring path terminates at a module interconnect structure, which is adapted to connect the semiconductor module to another device. A semiconductor device according to claim 1.

7. It is a semiconductor device, A semiconductor module including a first interconnection structure that implements a first plurality of connection paths connecting a first die to a second die, wherein the first plurality of connection paths have a first density, A second interconnection structure for connecting the semiconductor module to at least one peripheral component, wherein the second interconnection structure implements a second plurality of connection paths between the first die and the peripheral component, and the second plurality of connection paths have a second density different from the first density, The second interconnection structure includes a wafer-level fan-out redistribution structure manufactured on the interposer. Semiconductor devices.

8. The first interconnection structure includes a redistribution layer manufactured on the first die, the second die, and a mold layer supporting the first die and the second die. The semiconductor device according to claim 7.

9. The first interconnection structure includes a redistribution layer manufactured on an interposer coupled to the first die and the second die. The semiconductor device according to claim 7.

10. The first die includes a die interface that includes a mixed density input / output interconnect, The semiconductor device according to claim 7.

11. The plurality of interconnections for the first plurality of connection paths have a finer pitch than the pitch of the plurality of interconnections for the second plurality of connection paths. A semiconductor device according to claim 10.

12. The second interconnection structure includes interconnection dies within the second plurality of connection paths. The semiconductor device according to claim 7.

13. The interconnect die is connected to the semiconductor module and the peripheral components through a redistribution layer formed on the surface of the second interconnect structure. A semiconductor device according to claim 12.

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