Electronic devices

Abstract

In terms of extending the lifespan of non-volatile memory, there is room for improvement in the frequency of data writing to non-volatile memory. [Solution] The electronic device 10 includes a first memory 11, a second memory 12 which has a slower writing speed than the first memory 11 and is non-volatile, an arithmetic unit 13 which can read and write data to the first memory 11 via a bus 15, and a memory control unit 14 which can read data from the first memory 11 and write data to the second memory 12. The second memory 12 is configured to allow data to be written and erased in predetermined capacity increments. The memory control unit 14 is configured to transfer data from the first memory 11 to the second memory 12 when the amount of data written to the first memory 11 exceeds a set capacity which has a capacity that is an integer multiple of the predetermined capacity.

Description

Technical Field

[0004] , ,

[0005] , , ,

[0001] The present disclosure relates to an electronic device.

Background Art

[0002] Patent Document 1 discloses an example of a technique for writing data into a non-volatile memory by a microcomputer (hereinafter referred to as a microcontroller).

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] In Patent Document 1, various data are written into a non-volatile memory. Since there is a limit to the number of writeable times in the non-volatile memory, when the frequency of writing increases, the life of the non-volatile memory becomes shorter. There is room for improvement in the frequency of writing data into the non-volatile memory in terms of extending the life of the non-volatile memory.

Means for Solving the Problems

[0005] An electronic device according to a first aspect for solving the above problems includes a first memory, a second memory having a slower writing speed and being non-volatile than the first memory, an arithmetic unit capable of reading and writing data to and from the first memory via a bus, and a memory control unit capable of reading data from the first memory and writing data to the second memory. The second memory is configured to be able to write and erase data in a predetermined capacity unit, and when the data capacity written in the first memory exceeds a set capacity that is an integer multiple of the predetermined capacity, the memory control unit is configured to transfer data from the first memory to the second memory.

[0006] According to the above configuration, by temporarily storing data in the first memory, the frequency of writing data to the second memory can be reduced. Therefore, the lifespan of the second memory can be improved.

[0007] The electronic device of the second perspective is the electronic device of the first perspective in which the predetermined capacity is the minimum erase data capacity of the second memory, and the set capacity has a capacity equal to that of the predetermined capacity.

[0008] According to the above configuration, the set capacity corresponds to the minimum amount of data that can be erased from the second memory. Therefore, the electronic device can reduce the frequency of writing data to the second memory and shorten the time required to complete writing data to the second memory.

[0009] The electronic device of the third aspect is configured such that, in the electronic device of the first or second aspect, the memory control unit transfers data from the first memory to the second memory, regardless of the amount of data written to the first memory, based on a signal output from the arithmetic unit or an external terminal, which includes a command to transfer data from the first memory to the second memory.

[0010] According to the above configuration, the memory control unit can retain data by transferring data from the first memory to the second memory when output from the arithmetic unit or an external terminal.

[0011] In the electronic device of the fourth aspect, the signal is output from the arithmetic unit or the external terminal to the memory control unit based on the interruption of the power supply to the electronic device in the electronic device of the third aspect.

[0012] With the above configuration, the memory control unit can retain data even when the power supply to the electronic device is interrupted.

[0013] In the fifth aspect of the electronic device, the memory control unit is configured to detect the signal from the arithmetic unit or the external terminal by rising edge detection or falling edge detection, in the third or fourth aspect of the electronic device.

[0014] According to the above configuration, the memory control unit can suitably detect signals from the arithmetic unit or external terminals.

[0015] In the sixth aspect of the electronic device, in any one of the first to fifth aspects of the electronic device, the arithmetic unit is configured to change the settings of the memory control unit via the bus.

[0016] According to the above configuration, the arithmetic unit can change the settings of the memory control unit.

[0017] The electronic device of the seventh aspect is an electronic device of any one of the first to sixth aspects in which the memory control unit has an address boundary to the first memory corresponding to the set capacity, and is configured to transfer data from the first memory to the second memory based on the address of the first memory to which the arithmetic unit next writes data exceeding the address boundary, and the arithmetic unit is configured to be able to set the address boundary.

[0018] According to the above configuration, the memory control unit can suitably transfer data from the first memory to the second memory based on the setting of the address boundary.

[0019] The electronic device of the eighth aspect is configured such that, in any one of the electronic devices of the first to seventh aspects, the memory control unit transfers data from the first memory to the second memory without going through the bus.

[0020] With the above configuration, the memory control unit transfers data from the first memory to the second memory without going through the bus, thus reducing the load on the arithmetic unit.

[0021] In the electronic device according to the ninth aspect, in the electronic device according to the eighth aspect, the memory control unit is configured to execute the erasure sequence and the write sequence for the second memory by itself without the arithmetic unit executing them.

[0022] According to the above configuration, normally, the erasure sequence and the write sequence for the second memory are executed by the arithmetic unit via the bus, but since the memory control unit can execute the erasure sequence and the write sequence for the second memory without passing through the bus, the load on the arithmetic unit can be reduced.

[0023] In the electronic device according to the tenth aspect, in the electronic device according to the first or second aspect, the arithmetic unit is configured to read the data written in the second memory via the bus.

[0024] According to the above configuration, the arithmetic unit can confirm the data transferred from the first memory by reading the data in the second memory.

[0025] In the electronic device according to the eleventh aspect, in any one of the electronic devices according to the first to tenth aspects, the arithmetic unit is configured to confirm the data to be transferred from the first memory to the second memory by accessing the address of the first memory to be transferred from the first memory to the second memory.

[0026] According to the above configuration, the arithmetic unit can suitably confirm the data to be transferred from the first memory to the second memory.

[0027] The electronic device according to the 12th aspect for solving the above problems includes a first memory, a second memory having a slower writing speed than the first memory and being non-volatile, and an arithmetic unit capable of reading and writing data to the first memory via a bus. The second memory is configured to be able to write and erase data in predetermined capacities. When the data capacity written in the first memory exceeds a set capacity having a capacity that is an integral multiple of the predetermined capacity, the arithmetic unit is configured to transfer data from the first memory to the second memory.

[0028] According to the above configuration, by temporarily storing data in the first memory, the frequency of writing data to the second memory can be reduced. Therefore, the life of the second memory can be improved.

[0029] The electronic device according to the 13th aspect is the electronic device according to the 12th aspect, wherein the predetermined capacity is the minimum erasure data capacity of the second memory, and the set capacity has a capacity that is an equal multiple of the predetermined capacity.

[0030] According to the above configuration, the set capacity corresponds to the minimum erasure data capacity that can be erased from the second memory. Therefore, the electronic device can reduce the frequency of writing data to the second memory and can shorten the time until the writing of data to the second memory is completed.

Brief Description of Drawings

[0031] [Figure 1] It is a schematic diagram of an outdoor unit for a refrigeration device according to the first embodiment. [Figure 2] It is a block diagram showing the electrical configuration of the electronic device in FIG. 1. [Figure 3] It is a conceptual diagram of a bus connecting an arithmetic unit and a first memory. [Figure 4] It is a flowchart of a process for setting an address boundary to the first memory of a memory control unit executed by the arithmetic unit in FIG. 2. [Figure 5]Figure 2 is a flowchart of the process of transferring data from the first memory to the second memory, which is executed by the memory control unit. [Figure 6] This block diagram shows the electrical configuration of the electronic device according to the second embodiment. [Figure 7] Figure 6 is a flowchart of the process of setting the address boundary to the first memory of the arithmetic unit, which is executed by the arithmetic unit. [Figure 8] Figure 6 is a flowchart of the process of transferring data from the first memory to the second memory, which is executed by the arithmetic unit. [Figure 9] This is a block diagram of the modified electronic device. [Figure 10] This is a block diagram of the modified electronic device. [Modes for carrying out the invention]

[0032] <First Embodiment> The electronic device 10 will be described with reference to Figures 1 to 5.

[0033] Figure 1 shows an outdoor unit 1 for a refrigeration system. In this embodiment, the refrigeration system is an air conditioner. The air conditioner is configured to cool or heat the space inside a living room. The air conditioner may be a cooling-only unit, a heating-only unit, or a cooling and heating unit that can switch between cooling and heating. The outdoor unit 1 is connected to the indoor unit of the air conditioner by refrigerant piping.

[0034] The outdoor unit 1 includes a casing 2. The shape of the casing 2 is not particularly limited. In this embodiment, the casing 2 is, for example, a horizontally elongated rectangular parallelepiped.

[0035] The outdoor unit 1 comprises a fan 3 and an electrical component housing 4. The fan 3 and the electrical component housing 4 are housed in a casing 2. The electrical component housing 4 houses a printed circuit board 5 on which a power supply circuit, electronic devices 10, etc. are mounted, and wiring that is electrically connected to the printed circuit board 5.

[0036] <Electronic Devices> The electronic device 10 is a microcontroller. The microcontroller in this embodiment is a semiconductor chip configured to control the electrical circuits and mechanical parts of the outdoor unit 1.

[0037] As shown in Figures 2 and 3, the electronic device 10 comprises a first memory 11, a second memory 12, an arithmetic unit 13, and a memory control unit 14.

[0038] The first memory 11 has a fast write speed and is volatile. The first memory 11 is directly accessible from the arithmetic unit 13 and the memory control unit 14. The first memory 11 includes, for example, RAM (Random Access Memory). In this embodiment, the first memory 11 includes SRAM (Static Random Access Memory). The first memory 11 may also include DRAM (Dynamic Random Access Memory). Information such as what happens when the power supply to the outdoor unit 1 is interrupted and information necessary for the maintenance of the outdoor unit 1 is written to the first memory 11 from the arithmetic unit 13.

[0039] The first memory 11 has a data capacity of at least twice the minimum erase data capacity of the second memory 12, which will be described later. The first memory 11 has, for example, a first surface and a second surface. The first memory 11 has a physical storage medium on each of the first and second surfaces. The two physical storage mediums are integrated as a single memory area. The data capacity that can be stored on each of the first and second surfaces is equal. Each of the first and second surfaces has a data capacity equal to the set capacity. Each of the first and second surfaces has a data capacity equal to the minimum erase data capacity of the second memory 12. Data written from the arithmetic unit 13 to the first memory 11 is written alternately to the first and second surfaces. If data has already been written to the first and second surfaces, it is overwritten.

[0040] The second memory 12 has a slower write speed than the first memory 11 and is non-volatile. The second memory 12 is directly accessible from the arithmetic unit 13 and the memory control unit 14. The second memory 12 includes flash memory. The flash memory in this embodiment is a NOR type flash memory. The second memory 12 may also include EEPROM (Electrically Erasable Programmable Read-Only Memory).

[0041] The second memory 12 has multiple blocks that equally partition the data area of ​​the second memory 12. Each block is assigned an address. Each block has the same data capacity. The data capacity of each block corresponds to the minimum erase data capacity of the second memory 12.

[0042] The second memory 12 is configured to allow data to be written to and erased in predetermined capacity increments. The predetermined capacity is set to an integer multiple of the minimum erase data capacity of the second memory 12. In this embodiment, the predetermined capacity is set to be equal to the minimum erase data capacity of the second memory 12. That is, the predetermined capacity is the minimum erase data capacity of the second memory 12.

[0043] The arithmetic unit 13 is configured to execute a predetermined control program. The arithmetic unit 13 includes, for example, a CPU (Central Processing Unit) or an MPU (Micro Processing Unit). The arithmetic unit 13 is connected to the first memory 11, the second memory 12, and the memory control unit 14 by a bus 15.

[0044] The arithmetic unit 13 is configured to read and write data to the first memory 11 via the bus 15. The arithmetic unit 13 is configured to read data written to the second memory 12 via the bus 15. The arithmetic unit 13 is configured to check the data to be transferred from the first memory 11 to the second memory 12 by accessing the address of the first memory 11 that is scheduled to be transferred from the first memory 11 to the second memory 12.

[0045] Bus 15 includes a data bus, an address bus, and a control bus. The arithmetic unit 13 is configured to send and receive data to and from the first memory 11, the second memory 12, and the memory control unit 14 via the data bus. The arithmetic unit 13 is configured to specify the addresses of the first memory 11, the second memory 12, and the memory control unit 14 via the address bus. The arithmetic unit 13 transmits signals related to the processing to be performed at the locations specified by the address bus via the control bus.

[0046] Figure 3 conceptually shows the data bus, address bus, and control bus of the bus 15 connecting the arithmetic unit 13 and the first memory 11. When the arithmetic unit 13 writes data to the first memory 11 via the bus 15, the arithmetic unit 13 specifies the address of the write area of ​​the first memory 11 via the address bus. The arithmetic unit 13 transmits a signal related to data writing via the control bus. The arithmetic unit 13 transmits data via the data bus. Based on the signal related to data writing, the data received by the arithmetic unit 13 is written to the specified write area of ​​the first memory 11.

[0047] When the arithmetic unit 13 reads data from the first memory 11 via the bus 15, the arithmetic unit 13 specifies the address of the area in the first memory 11 from which it wants to read data via the address bus. The arithmetic unit 13 transmits a signal related to data reading via the control bus. When the first memory 11 receives the signal related to data reading, it transmits the data to be stored in the specified area to the arithmetic unit 13 via the data bus. By receiving the data stored in the specified area, the data in the specified reading area of ​​the first memory 11 is read by the arithmetic unit 13.

[0048] The memory control unit 14 shown in Figure 2 is configured to execute predetermined processes composed of digital circuits. The memory control unit 14 is configured to execute processes set by the arithmetic unit 13.

[0049] The memory control unit 14 can read data from the first memory 11 and write data to the second memory 12. The memory control unit 14 is configured to perform erase and write sequences to the second memory 12 itself, without having the arithmetic unit 13 perform them. Normally, processing including erase and write sequences to the second memory 12 is performed by the arithmetic unit 13 accessing the second memory 12. In this embodiment, the memory control unit 14 can perform processing to the second memory 12 without the arithmetic unit 13 directly performing processing to the second memory 12.

[0050] When the data transfer from the first memory 11 to the second memory 12 is complete, the memory control unit 14 performs an erase process on the next write area of ​​the second memory 12. The erase process is performed when the write area of ​​the second memory 12 becomes empty after transferring data from the first memory 11 to the second memory 12. The erase process is performed starting with the oldest data stored in the second memory 12.

[0051] The memory control unit 14 is configured to transfer data from the first memory 11 to the second memory 12 without going through the bus 15. The memory control unit 14 is configured to transfer data from the first memory 11 to the second memory 12 when the amount of data written to the first memory 11 exceeds a set capacity which has an integer multiple of a predetermined capacity. The set capacity has an equal capacity to the predetermined capacity. In other words, the set capacity is the minimum erase data capacity of the second memory 12.

[0052] The memory control unit 14 has an address boundary to the first memory 11 corresponding to the set capacity. The address boundary is, for example, a threshold for transferring data from the first memory 11 to the second memory 12. The memory control unit 14 is configured to transfer data from the first memory 11 to the second memory 12 based on whether the address of the first memory 11 to which data will be written next from the arithmetic unit 13 exceeds the address boundary. Specifically, the memory control unit 14 obtains the address of the first memory 11 to which data will be written next from the arithmetic unit 13 and determines whether the obtained address exceeds the address boundary which is the threshold. If the memory control unit 14 determines that the address of the first memory 11 to which data will be written next from the arithmetic unit 13 exceeds the address boundary, it transfers data from the first memory 11 to the second memory 12.

[0053] The arithmetic unit 13 is configured to change the settings of the memory control unit 14 via the bus 15. The arithmetic unit 13 sets the minimum erase data capacity of the second memory 12 as the set capacity and determines the address boundary of the memory control unit 14 to the first memory 11 corresponding to the set capacity. In this embodiment, writing to the first memory 11 proceeds to writing to the second surface after completion of writing to the first surface, and then to writing to the first surface after completion of writing to the second surface. The arithmetic unit 13 determines the address boundary based on the boundary of the surface transition between the first surface and the second surface of the first memory 11. The arithmetic unit 13 is configured to set the determined address boundary in the memory control unit 14.

[0054] As shown in Figure 3, the memory control unit 14 monitors the address bus of the bus 15 connecting the arithmetic unit 13 and the first memory 11. The memory control unit 14 is configured to transfer data from the first memory 11 to the second memory 12 when the address of the first memory 11 to which data is to be written crosses an address boundary.

[0055] Referring to Figures 2 and 4, an example of the process by which the arithmetic unit 13 sets the address boundary to the first memory 11 of the memory control unit 14 will be described. In this example, the process by which the arithmetic unit 13 sets the address boundary to the first memory 11 of the memory control unit 14 is executed each time the second memory 12 is replaced. The arithmetic unit 13 determines the address boundary based on the set capacity and sets the determined address boundary in the memory control unit 14.

[0056] In step S11, the arithmetic unit 13 obtains information regarding the minimum erase data capacity from the second memory 12 and proceeds to step S12. In step S12, the arithmetic unit 13 sets the minimum erase data capacity of the second memory 12 as the set capacity, determines the address boundary of the memory control unit 14 to the first memory 11 corresponding to the set capacity, and proceeds to step S13.

[0057] In step S13, the arithmetic unit 13 sets an address boundary to the first memory 11 of the memory control unit 14 via the bus 15 and terminates processing. In step S13, if an address boundary to the first memory 11 has already been set in the memory control unit 14, the arithmetic unit 13 changes the old address boundary to the new address boundary.

[0058] As shown in Figure 2, the electronic device 10 is equipped with an external terminal 16. The external terminal 16 is electrically connected to the memory control unit 14. Signals input to the electronic device 10 from an external device are input to the memory control unit 14 via the external terminal 16.

[0059] The memory control unit 14 is configured to transfer data from the first memory 11 to the second memory 12, regardless of the amount of data written to the first memory 11, based on a signal output from the arithmetic unit 13 or the external terminal 16. The signal output from the arithmetic unit 13 or the external terminal 16 includes a command to transfer data from the first memory 11 to the second memory 12. In this embodiment, the signal output from the arithmetic unit 13 or the external terminal 16 is described as the first transfer signal. For example, when the power supply to the electronic device 10 is interrupted due to a power outage, the arithmetic unit 13 or the external terminal 16 transfers the first transfer signal to the memory control unit 14.

[0060] The memory control unit 14 is configured to detect the first transfer signal by detecting the rising edge or the falling edge. When the memory control unit 14 detects the first transfer signal by detecting the rising edge, it detects the first transfer signal when the first transfer signal changes from a low level to a high level. When the memory control unit 14 detects the first transfer signal by detecting the falling edge, it detects the first transfer signal when the first transfer signal changes from a high level to a low level.

[0061] The first transfer signal is output from the arithmetic unit 13 or external terminal 16 to the memory control unit 14 based on the fact that the power supply to the electronic device 10 is interrupted due to a power outage or the like. The power supply circuit provided on the printed circuit board 5 includes an AC-DC converter, a power factor correction capacitor, and other capacitors. Even when the power supply to the electronic device 10 is interrupted, the power supply circuit continues to supply current for a certain period of time using the charge stored in the capacitors, etc. In this embodiment, when the power supply to the electronic device 10 is interrupted, the memory control unit 14 transfers data from the first memory 11 to the second memory 12 using the power stored in the capacitors, etc.

[0062] Referring to Figures 2 and 5, an example of the process by which the memory control unit 14 transfers data from the first memory 11 to the second memory 12 will be explained.

[0063] In step S21, the memory control unit 14 determines whether or not it has received a first transfer signal from the arithmetic unit 13 or the external terminal 16. If the memory control unit 14 has received a first transfer signal from the arithmetic unit 13 or the external terminal 16, it proceeds to step S22. In step S22, regardless of the amount of data written to the first memory 11, the memory control unit 14 transfers the data from the first memory 11 to the second memory 12 and terminates the process.

[0064] If the memory control unit 14 does not receive a first transfer signal from the arithmetic unit 13 or the external terminal 16 in step S21, it proceeds to step S23. In step S23, the memory control unit 14 determines whether the address of the first memory 11 to which the arithmetic unit 13 will next write data has crossed an address boundary. If the memory control unit 14 determines that the address of the first memory 11 to which the arithmetic unit 13 will next write data has not crossed an address boundary, it terminates the process.

[0065] In step S23, if the address of the first memory 11 to which data is to be written next from the arithmetic unit 13 exceeds an address boundary, the memory control unit 14 proceeds to step S24. In step S24, the memory control unit 14 transfers data from the first memory 11 to the second memory 12 without going through the bus 15, and proceeds to step S25.

[0066] In step S25, the memory control unit 14 executes the erase process for the next write area of ​​the second memory 12 and terminates the process. Preferably, the memory control unit 14 executes step S25 after the data transfer from the first memory 11 to the second memory 12 is completed. If the data transfer from the first memory 11 to the second memory 12 is not completed after a predetermined time has elapsed, the memory control unit 14 may omit step S25 and terminate the process. If there is still writable area remaining in the second memory 12, the memory control unit 14 may omit step S25 and terminate the process.

[0067] <Operation of the First Embodiment> The operation of the first embodiment will now be explained. The electronic device 10 of the first embodiment can reduce the frequency of writing data to the second memory 12 by temporarily storing data in the first memory 11.

[0068] In the first embodiment, when the power supply to the electronic device 10 is interrupted, the electronic device 10 transfers data from the first memory 11 to the second memory 12, regardless of the amount of data written to the first memory 11. Therefore, it is possible to suppress the loss of data stored in the first memory 11.

[0069] <Effects of the First Embodiment> The effects of the first embodiment will be explained. (1-1) The electronic device 10 includes a first memory 11, a second memory 12 which has a slower write speed than the first memory 11 and is non-volatile, an arithmetic unit 13 which can read and write data to the first memory 11 via a bus 15, and a memory control unit 14 which can read data from the first memory 11 and write data to the second memory 12. The second memory 12 is configured to allow data to be written and erased in predetermined capacity increments. The memory control unit 14 is configured to transfer data from the first memory 11 to the second memory 12 when the amount of data written to the first memory 11 exceeds a set capacity which has a capacity that is an integer multiple of the predetermined capacity.

[0070] According to the above configuration, by temporarily storing data in the first memory 11, the frequency of writing data to the second memory 12 can be reduced. Therefore, the lifespan of the second memory 12 can be improved.

[0071] (1-2) The predetermined capacity is the minimum erase data capacity of the second memory 12, and the set capacity has a capacity equal to the predetermined capacity.

[0072] According to the above configuration, the set capacity corresponds to the minimum amount of data that can be erased from the second memory 12. Therefore, the electronic device 10 can reduce the frequency of writing data to the second memory 12 and shorten the time required to complete writing data to the second memory 12.

[0073] (1-3) The memory control unit 14 is configured to transfer data from the first memory 11 to the second memory 12, regardless of the amount of data written to the first memory 11, based on a signal output from the arithmetic unit 13 or an external terminal 16 that includes a command to transfer data from the first memory 11 to the second memory 12.

[0074] According to the above configuration, the memory control unit 14 can retain data by transferring data from the first memory 11 to the second memory 12 when output from the arithmetic unit 13 or the external terminal 16.

[0075] (1-4) A signal including a command to transfer data from the first memory 11 to the second memory 12 is output to the memory control unit 14 from the arithmetic unit 13 or external terminal 16 based on the fact that the power supply to the electronic device 10 is cut off.

[0076] According to the above configuration, the memory control unit 14 can retain data even when the power supply to the electronic device 10 is interrupted.

[0077] (1-5) The memory control unit 14 is configured to detect signals from the arithmetic unit 13 or external terminal 16 that include a command to transfer data from the first memory 11 to the second memory 12 by detecting rising edge or falling edge.

[0078] With the above configuration, the memory control unit 14 can suitably detect signals from the arithmetic unit 13 or the external terminal 16.

[0079] (1-6) The arithmetic unit 13 is configured to change the settings of the memory control unit 14 via the bus 15.

[0080] According to the above configuration, the arithmetic unit 13 can change the settings of the memory control unit 14.

[0081] (1-7) The memory control unit 14 has an address boundary to the first memory 11 corresponding to the set capacity, and is configured to transfer data from the first memory 11 to the second memory 12 based on the address of the first memory 11 to which data is next written by the arithmetic unit 13 exceeding the address boundary. The arithmetic unit 13 is configured to be able to set the address boundary.

[0082] According to the above configuration, the memory control unit 14 can suitably transfer data from the first memory 11 to the second memory 12 based on the setting of address boundaries.

[0083] (1-8) The memory control unit 14 is configured to transfer data from the first memory 11 to the second memory 12 without going through the bus 15.

[0084] With the above configuration, the memory control unit 14 transfers data from the first memory 11 to the second memory 12 without going through the bus 15, thus reducing the load on the arithmetic unit 13.

[0085] (1-9) The memory control unit 14 is configured to perform the erase sequence and write sequence for the second memory 12 itself, without having the arithmetic unit 13 perform them.

[0086] With the above configuration, normally the erase and write sequences for the second memory 12 are executed by the arithmetic unit 13 via the bus 15, but the memory control unit 14 can execute the erase and write sequences for the second memory 12 without going through the bus 15, thus reducing the load on the arithmetic unit 13.

[0087] (1-10) The arithmetic unit 13 is configured to read data written to the second memory 12 via the bus 15.

[0088] According to the above configuration, the arithmetic unit 13 can verify the data transferred from the first memory 11 by reading the data from the second memory 12.

[0089] (1-11) The arithmetic unit 13 is configured to check the data to be transferred from the first memory 11 to the second memory 12 by accessing the address of the first memory 11 that is scheduled to be transferred from the first memory 11 to the second memory 12.

[0090] With the above configuration, the arithmetic unit 13 can suitably confirm the data to be transferred from the first memory 11 to the second memory 12.

[0091] <Second Embodiment> The electronic device 20 of the second embodiment will be described with reference to Figures 6 to 8. Components in this embodiment that are common with the first embodiment are denoted by the same reference numerals as in the first embodiment, and redundant explanations are omitted.

[0092] The electronic device 20 of the second embodiment is provided on a printed circuit board 5. The electronic device 20 comprises a first memory 11, a second memory 12, and an arithmetic unit 21. The arithmetic unit 21 can read and write data to the first memory 11 via a bus 15. The arithmetic unit 21 is configured to transfer data from the first memory 11 to the second memory 12 when the amount of data written to the first memory 11 exceeds a set capacity which has an integer multiple of a predetermined capacity. The predetermined capacity is the minimum erase data capacity of the second memory 12. The set capacity is, for example, an equal multiple of the predetermined capacity.

[0093] The electronic device 20 further includes an interrupt controller 22. The interrupt controller 22 is a hardware circuit that notifies the arithmetic unit 21 that an interrupt has occurred. The interrupt controller 22 is connected to an external terminal 16. The interrupt controller 22 relays interrupt request signals received from an external device via the external terminal 16 to the arithmetic unit 21.

[0094] The electronic device 20 further includes a DMA (Direct Memory Access) controller 23. The DMA controller 23 is connected to the arithmetic unit 21 via a bus 15. The arithmetic unit 21 is configured to change the settings of the DMA controller 23. When the DMA controller 23 receives a signal from the arithmetic unit 21 to initiate a DMA transfer, it is configured to perform memory transfers independently of the arithmetic unit 21.

[0095] The arithmetic unit 21 has an address boundary to the first memory 11 corresponding to the set capacity. The arithmetic unit 21 determines the address boundary of the memory control unit 14 to the first memory 11 corresponding to the set capacity, using the minimum erase data capacity of the second memory 12 as the set capacity. Based on the determined address boundary, the arithmetic unit 21 transfers data from the first memory 11 to the second memory 12.

[0096] The arithmetic unit 21 is configured to transfer data from the first memory 11 to the second memory 12 based on the address of the first memory 11 to which data is to be written next exceeding an address boundary. In this embodiment, when the address of the first memory 11 to which data is to be written next exceeds an address boundary, the arithmetic unit 21 sends a signal to the DMA controller 23 to start a DMA transfer. When the DMA controller 23 receives the signal to start a DMA transfer, it causes the data to be transferred from the first memory 11 to the second memory 12.

[0097] Referring to Figures 6 and 7, an example of the process by which the arithmetic unit 21 determines the address boundary to the first memory 11 will be explained. In this example, the process by which the arithmetic unit 21 determines the address boundary to the first memory 11 is executed each time the second memory 12 is replaced.

[0098] In step S31, the arithmetic unit 21 obtains information regarding the minimum erase data capacity from the second memory 12 and proceeds to step S32. In step S32, the arithmetic unit 13 sets the minimum erase data capacity of the second memory 12 as the set capacity, determines the address boundary of the memory control unit 14 to the first memory 11 corresponding to the set capacity, and terminates the process.

[0099] The arithmetic unit 21 is configured to transfer data from the first memory 11 to the second memory 12 based on a signal output from the external terminal 16, regardless of the amount of data written to the first memory 11. The signal output from the external terminal 16 includes a command to transfer data from the first memory 11 to the second memory 12. In this embodiment, the signal output from the external terminal 16 will be described as the second transfer signal.

[0100] The arithmetic unit 21 is configured to detect the second transfer signal by detecting the rising edge or the falling edge. When the arithmetic unit 21 detects the second transfer signal by detecting the rising edge, the arithmetic unit 21 detects the second transfer signal when it changes from a low level to a high level. When the arithmetic unit 21 detects the second transfer signal by detecting the falling edge, the arithmetic unit 21 detects the second transfer signal when it changes from a high level to a low level.

[0101] The second transfer signal is output from the external terminal 16 to the arithmetic unit 21 based on the interruption of power supply to the electronic device 20, such as in a power outage. In this embodiment, when the arithmetic unit 21 receives the second transfer signal from the external terminal 16, it sends a signal to the DMA controller 23 to start a DMA transfer. The arithmetic unit 21 may be configured to detect when power supply to the electronic device 20 is interrupted, such as in a power outage, and send a signal to the DMA controller 23 to start a DMA transfer.

[0102] The power supply circuit provided on the printed circuit board 5 includes an AC-DC converter, a power factor correction capacitor, and other capacitors. Even when the power supply to the electronic device 20 is interrupted, the power supply circuit continues to supply current for a certain period of time using the charge stored in the capacitors, etc. In this embodiment, when the power supply to the electronic device 20 is interrupted, the arithmetic unit 21 transfers data from the first memory 11 to the second memory 12 using the power stored in the capacitors, etc.

[0103] Referring to Figures 6 and 8, an example of the process by which the arithmetic unit 21 transfers data from the first memory 11 to the second memory 12 will be explained.

[0104] In step S41, the arithmetic unit 21 determines whether or not it has received a second transfer signal from the external terminal 16. If the arithmetic unit 21 has received a second transfer signal from the external terminal 16, it proceeds to step S42. In step S42, the arithmetic unit 21 transfers data from the first memory 11 to the second memory 12, regardless of the amount of data written to the first memory 11, and terminates the process. In this embodiment, in step S42, the arithmetic unit 21 sends a signal to the DMA controller 23 to start a DMA transfer, causing the DMA controller 23 to transfer data from the first memory 11 to the second memory 12.

[0105] If the arithmetic unit 21 does not receive a second transfer signal from the external terminal 16 in step S41, it proceeds to step S43. In step S43, the arithmetic unit 21 determines whether the address of the first memory 11 to which the next data is to be written has crossed an address boundary. If the address of the first memory 11 to which the next data is to be written has not crossed an address boundary, the arithmetic unit 21 terminates the process.

[0106] In step S43, if the address of the first memory 11 to which data is to be written next exceeds an address boundary, the arithmetic unit 21 proceeds to step S44. In step S44, the arithmetic unit 21 transfers data from the first memory 11 to the second memory 12 via the bus 15 and proceeds to step S45. In this embodiment, in step S44, the arithmetic unit 21 sends a signal to the DMA controller 23 to start a DMA transfer, causing the DMA controller 23 to transfer data from the first memory 11 to the second memory 12.

[0107] In step S45, the arithmetic unit 21 performs an erase operation on the next write area of ​​the second memory 12 and terminates the process. Preferably, the arithmetic unit 21 executes step S45 after the data transfer from the first memory 11 to the second memory 12 is completed. If the data transfer from the first memory 11 to the second memory 12 is not completed even after a predetermined time has elapsed, the arithmetic unit 21 may omit step S45 and terminate the process.

[0108] <Effects of the second embodiment> The effects of the second embodiment will be explained. (2-1) The electronic device 20 includes a first memory 11, a second memory 12 which has a slower writing speed than the first memory 11 and is non-volatile, and an arithmetic unit 21 which can read and write data to the first memory 11 via the bus 15. The second memory 12 is configured to allow data to be written and erased in predetermined capacity increments. The arithmetic unit 21 is configured to transfer data from the first memory 11 to the second memory 12 when the amount of data written to the first memory 11 exceeds a set capacity which has a capacity that is an integer multiple of the predetermined capacity.

[0109] According to the above configuration, by temporarily storing data in the first memory 11, the frequency of writing data to the second memory 12 can be reduced. Therefore, the lifespan of the second memory 12 can be improved.

[0110] (2-2) The predetermined capacity is the minimum erase data capacity of the second memory 12, and the set capacity has a capacity equal to the predetermined capacity.

[0111] According to the above configuration, the set capacity corresponds to the minimum amount of data that can be erased from the second memory 12. Therefore, the electronic device 20 can reduce the frequency of writing data to the second memory 12 and shorten the time required to complete writing data to the second memory 12.

[0112] <Example of changes> In addition to the embodiments described above, the electronic devices of this disclosure may also be, for example, in the form of the modifications shown below and a combination of at least two non-inconsistent modifications.

[0113] As shown in Figure 9, the electronic device 10 of the first embodiment may include an external memory 30 instead of the second memory 12. In this modified example, the electronic device 10 further includes an external memory control unit 31 configured to control the external memory 30. The external memory control unit 31 is configured to execute predetermined processes composed of digital circuits. The external memory control unit 31 is configured to execute processes set by the arithmetic unit 13.

[0114] As shown in Figure 10, the electronic device 20 of the second embodiment may include an external memory 30 instead of the second memory 12. In this modified example, the electronic device 20 further includes an external memory control unit 31 configured to control the external memory 30. The external memory control unit 31 is configured to execute predetermined processes composed of digital circuits. The external memory control unit 31 is configured to execute processes set by the arithmetic unit 21.

[0115] The memory control unit 14 may transfer data from the first memory 11 to the second memory 12 using an auxiliary power supply if the power supply to the electronic device 10 is interrupted. The auxiliary power supply includes, for example, an externally provided auxiliary battery circuit, an electrolytic capacitor such as an EDLC (Electric Double Layer Capacitor), and a lithium-ion battery.

[0116] In the second embodiment, if the power supply to the electronic device 20 is interrupted, the arithmetic unit 21 may transfer data from the first memory 11 to the second memory 12 using an auxiliary power supply. The auxiliary power supply includes, for example, an externally provided auxiliary battery circuit, an electrolytic capacitor such as an EDLC (Electric Double Layer Capacitor), and a lithium-ion battery.

[0117] In the second embodiment, the arithmetic unit 21 may be configured to transfer data from the first memory 11 to the second memory 12 based on the interruption of power supply to the electronic device 20. In this modified example, the arithmetic unit 21 is configured to detect when power supply to the electronic device 20 is interrupted.

[0118] The predetermined capacity and the set capacity are not limited to the examples shown in the first and second embodiments. For example, the predetermined capacity may be the minimum erase data capacity of the second memory 12 and the set capacity may be an integer multiple of the predetermined capacity, or the predetermined capacity may be an integer multiple of the minimum erase data capacity of the second memory 12 and the set capacity may be an equal multiple of the predetermined capacity.

[0119] Although various embodiments of the electronic device have been described above, it should be understood that a wide range of modifications to the form and details are possible without departing from the spirit and scope of the electronic device described in the claims. [Explanation of Symbols]

[0120] 10...Electronic device, 11...First memory, 12...Second memory, 13...Arithmetic unit, 14...Memory control unit, 15...Bus, 16...External terminals.

Claims

1. A first memory (11) and A second memory (12) has a slower write speed than the first memory (11) and is non-volatile, An arithmetic unit (13) that can read and write data to the first memory (11) via a bus (15), The system includes a memory control unit (14) that can read data from the first memory (11) and write data to the second memory (12), The data writable capacity of the first memory (11) is greater than or equal to a predetermined capacity. The second memory (12) is configured to allow data to be written and erased in predetermined amounts. The memory control unit (14) It has an address boundary to the first memory (11) corresponding to the set capacity, When the address of the first memory (11) to which data is next written from the arithmetic unit (13) exceeds the address boundary, and the amount of data written to the first memory (11) exceeds the set capacity which has an integer multiple of the predetermined capacity, the system is configured to transfer data from the first memory (11) to the second memory (12). The arithmetic unit (13) is configured to be able to set the address boundary. Electronic devices.

2. The predetermined capacity is the minimum erase data capacity of the second memory (12), The set capacity has a capacity equal to the predetermined capacity. The electronic device according to claim 1.

3. The memory control unit (14) is configured to transfer data from the first memory (11) to the second memory (12) regardless of the amount of data written to the first memory (11), based on a signal output from the arithmetic unit (13) or an external terminal (16) that includes a command to transfer data from the first memory (11) to the second memory (12). The electronic device according to claim 1 or 2.

4. The aforementioned signal is output from the arithmetic unit (13) or the external terminal (16) to the memory control unit (14) based on the interruption of the power supply to the electronic device (10). The electronic device according to claim 3.

5. The memory control unit (14) is configured to detect the signal from the arithmetic unit (13) or the external terminal (16) by detecting the rising edge or falling edge. The electronic device according to claim 3.

6. The arithmetic unit (13) is configured to change the settings of the memory control unit (14) via the bus (15). The electronic device according to claim 1 or 2.

7. The memory control unit (14) is configured to transfer data from the first memory (11) to the second memory (12) without going through the bus (15). The electronic device according to claim 1 or 2.

8. The memory control unit (14) is configured to perform the erase sequence and write sequence for the second memory (12) itself, without having the arithmetic unit (13) perform them. The electronic device according to claim 7.

9. The arithmetic unit (13) is configured to read data written to the second memory (12) via the bus (15). The electronic device according to claim 1 or 2.

10. The arithmetic unit (13) is configured to check the data to be transferred from the first memory (11) to the second memory (12) by accessing the address of the first memory (11) that is scheduled to be transferred from the first memory (11) to the second memory (12). The electronic device according to claim 1 or 2.

11. A first memory (11) and A second memory (12) has a slower write speed than the first memory (11) and is non-volatile, The system includes an arithmetic unit (21) that can read and write data to the first memory (11) via a bus (15), The data writable capacity of the first memory (11) is greater than or equal to a predetermined capacity. The second memory (12) is configured to allow data to be written and erased in predetermined amounts. The aforementioned computing device (21) It has an address boundary to the first memory (11) corresponding to the set capacity, The system is configured to transfer data from the first memory (11) to the second memory (12) when the address of the first memory (11) to which data is to be written next exceeds the address boundary, and the amount of data written to the first memory (11) exceeds the set capacity which has an integer multiple of the predetermined capacity. The arithmetic unit (21) is configured to be able to set the address boundary. Electronic devices.

12. The predetermined capacity is the minimum erase data capacity of the second memory (12), The set capacity has a capacity equal to the predetermined capacity. The electronic device according to claim 11.

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