Method for forming conductive patterns
The conductive pattern formation method addresses non-uniform plating thickness by using dummy patterns with controlled exposure and etching techniques, ensuring consistent plating thickness and manufacturing efficiency for flexible printed circuit boards.
Patent Information
- Authority / Receiving Office
- JP · JP
- Patent Type
- Patents
- Current Assignee / Owner
- MEKTECH CO LTD
- Filing Date
- 2022-06-15
- Publication Date
- 2026-05-12
AI Technical Summary
The semi-additive method for forming conductive patterns on insulating substrates results in non-uniform plating thickness distribution due to varying aperture densities, which is exacerbated by areas requiring mechanical flexibility or high-speed signal transmission, making uniformity difficult to achieve.
A conductive pattern formation method that includes forming openings for dummy patterns with controlled exposure and etching techniques to maintain uniform aperture density, using tapered or undercut shapes to ensure consistent plating thickness across the substrate.
This method enables the formation of conductive patterns with suppressed plating thickness distribution while maintaining manufacturing efficiency, suitable for flexible printed circuit boards with varying densities and high-speed signal lines.
Smart Images
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Abstract
Description
Technical Field
[0001] The present invention relates to a method for forming a conductive pattern, and more particularly, to a method for forming a conductive pattern on an insulating substrate by a semi-additive method.
Background Art
[0002] Conventionally, as one method for forming a conductive pattern on an insulating substrate, a semi-additive method is known. The semi-additive method involves preparing a substrate provided with a thin conductive layer called a seed layer on an insulating substrate, and subjecting the opening of a plating resist formed thereon to an electrolytic plating process, thereby forming a conductive pattern such as wiring, pads, and grounds on the seed layer exposed at the opening. In the electrolytic plating process, plating is deposited from the opening of the plating resist by applying current from an arbitrary position of the substrate through the seed layer. In the semi-additive method, since the opening shape of the plating resist substantially becomes the shape of the conductive pattern, it is advantageous for forming fine wiring compared to the subtractive method.
[0003] In Patent Document 1, a pattern plating method is described for obtaining a wiring pattern with a uniform film thickness in the pattern plating of a pattern plating area where there is a single or a plurality of block wiring patterns with different pattern densities.
Prior Art Documents
Patent Documents
[0004]
Patent Document 1
Summary of the Invention
Problems to be Solved by the Invention
[0005] Incidentally, in the semi-additive method, the deposition behavior of the plating is not uniform with respect to the substrate surface and is greatly influenced by the aperture shape or aperture density of the plating resist. In areas with high aperture density, the applied electric field diffuses, resulting in thinner plating, while in areas with low aperture density, the electric field concentrates, resulting in thicker plating. As a result, if the non-uniformity of the aperture density is large, the thickness of the conductive pattern becomes non-uniform. Thus, the semi-additive method has the problem of large plating thickness distribution due to the influence of the density of the conductive pattern within the product (printed wiring board).
[0006] To address the above problem, the plating thickness distribution can be suppressed by making the aperture density of the plating resist uniform across the substrate. However, actual printed circuit boards typically have varying density of conductive patterns, making it difficult to uniformize the density of the conductive patterns.
[0007] Therefore, it is conceivable to create openings for dummy patterns in the plating resist to avoid conductive patterns such as wiring, thereby achieving uniformity in the opening density across the entire surface to be deposited.
[0008] However, it is not always possible to provide openings for dummy patterns. For example, it is undesirable to place a metallic dummy pattern in an area where mechanical properties such as bending are to be applied. For example, in the flexible printed circuit board 100A shown in Figure 8(a), conductive patterns 120 and 130 are formed on a flexible insulating substrate 110. That is, conductive pattern 120 is formed in conductive pattern formation area A, and conductive pattern 130 is formed in conductive pattern formation area B. Conductive pattern formation area A and conductive pattern formation area B are connected via a connecting area C. Mechanical properties such as bending may be applied to this connecting area C, and in such cases, it is undesirable to place a dummy pattern in the connecting area C.
[0009] Furthermore, it is undesirable to place dummy patterns in areas where signal lines carrying high-speed signals are located. In the flexible printed circuit board 100B shown in Figure 8(b), signal lines 140 are formed on the insulating substrate 110 in connection area C. The signal lines 140 are provided to propagate high-speed signals (for example, signals of several GHz or higher used in high-speed wireless communication) between conductive pattern formation area A and conductive pattern formation area B. In this case, placing dummy patterns in connection area C may prevent the desired transmission characteristics from being obtained.
[0010] This invention is based on the above technical understanding and aims to provide a conductive pattern formation method that can form a conductive pattern with suppressed plating thickness distribution by a semi-additive method while maintaining manufacturing efficiency. [Means for solving the problem]
[0011] The conductive pattern formation method according to the present invention is A method for forming a conductive pattern by a semi-additive method, A step of preparing an insulating substrate having a seed layer on its main surface, and forming a resist layer on the seed layer, The steps include forming an opening for a conductive pattern and an opening for a dummy pattern in the resist layer, A step of forming a plating layer on the seed layer exposed in the openings for the conductive pattern and the openings for the dummy pattern by electroplating, The step of removing the resist layer, A step of removing an exposed seed layer that is not covered by the plating layer from the seed layer by etching, wherein the plating layer formed in the dummy pattern opening is removed together with the exposed seed layer. It is equipped with.
[0012] Furthermore, in the conductive pattern formation method, In the process of forming the conductive pattern opening and the dummy pattern opening, the dummy pattern opening may be formed such that its opening width narrows at its bottom.
[0013] Furthermore, in the conductive pattern formation method, The steps of forming the conductive pattern opening and the dummy pattern opening are as follows: A step of exposing the resist layer such that the size of the dummy pattern opening is less than or equal to the lower limit of the achievable opening size based on the material of the resist layer and the performance of the exposure apparatus, The process may also include the step of developing the exposed resist layer to form the openings for the conductive pattern and the openings for the dummy pattern.
[0014] Furthermore, in the conductive pattern formation method, When the resist layer is negative type, the step of forming the opening for the conductive pattern and the opening for the dummy pattern is: A step of exposing the resist layer such that the amount of exposure around the area where the dummy pattern opening is to be formed is greater than the amount of exposure to other areas, The process may also include the step of developing the exposed resist layer to form the openings for the conductive pattern and the openings for the dummy pattern.
[0015] Furthermore, in the conductive pattern formation method, The exposure amount around the area where the dummy pattern opening is to be formed may be 1.5 times or more the exposure amount for the other areas.
[0016] Furthermore, in the conductive pattern formation method, When the resist layer is of the positive type, the steps of forming the opening for the conductive pattern and the opening for the dummy pattern are as follows: A step of exposing the resist layer such that the amount of exposure to the area where the dummy pattern opening is to be formed is less than the amount of exposure to other areas, A step of developing the exposed resist layer to form the opening for the conductive pattern and the opening for the dummy pattern may be provided.
[0017] Also, in the method for forming the conductive pattern, The width of the opening for the dummy pattern is smaller than the width of the opening for the conductive pattern, and in the step of removing the exposed seed layer by etching, an etchant that preferentially etches the interface between the seed layer and the plating layer may be used.
[0018] Also, in the method for forming the conductive pattern, The shape of the opening for the dummy pattern may be circular, regular polygonal, or star-shaped.
[0019] Also, in the method for forming the conductive pattern, The insulating substrate has flexibility, and the opening for the dummy pattern may be formed in a region where the insulating substrate is bent, a region where a high-speed signal line is formed, and / or a region where outer shape processing is performed. [[ID=*19]]
[0020] Also, in the method for forming the conductive pattern, At least one of the above steps may be performed in a roll-to-roll manner.
Advantages of the Invention
[0021] According to the present invention, it is possible to provide a method for forming a conductive pattern capable of forming a conductive pattern with a suppressed plating thickness distribution by a semi-additive method while maintaining the manufacturing efficiency.
Brief Description of the Drawings
[0022] [Figure 1] It is a flowchart for explaining a method for forming a conductive pattern according to the first embodiment. [Figure 2A] It is a cross-sectional view of a process for explaining a method for forming a conductive pattern according to the first embodiment. [Figure 2B] Figure 2A is followed by a cross-sectional view illustrating the conductive pattern formation method according to the first embodiment. [Figure 3] (a), (b), and (c) are all plan views showing examples of dummy pattern shapes. [Figure 4] This is an SEM image showing an example of a cross-section of a dummy pattern during etching according to the first embodiment. [Figure 5] This is a flowchart illustrating the conductive pattern formation method according to the second embodiment. [Figure 6A] This is a cross-sectional view illustrating a conductive pattern formation method according to a second embodiment. [Figure 6B] This is a cross-sectional view illustrating the conductive pattern formation method according to the second embodiment, following Figure 6A. [Figure 7] This is an SEM image showing an example of a cross-section of a dummy pattern during etching according to the second embodiment. [Figure 8] Both (a) and (b) are plan views of a flexible printed circuit board to illustrate an example where a dummy pattern cannot be left. [Modes for carrying out the invention]
[0023] Embodiments of the present invention will be described below with reference to the drawings. Note that the drawings are schematic and mainly show characteristic parts of each embodiment; the relationship between thickness and planar dimensions, the ratio of the thickness of each layer, etc., may differ from reality.
[0024] (First embodiment) The conductive pattern formation method according to the first embodiment will be described with reference to the flowchart in Figure 1 and the process cross-sectional views in Figures 2A and 2B. This embodiment is a method for forming a conductive pattern on an insulating substrate having a conductive layer formation region and a conductive layer formation prohibited region by a semi-additive method.
[0025] As shown in Figure 2A(1), an insulating substrate 11 is prepared with a seed layer 12 on its main surface (step S11). In this embodiment, the insulating substrate 11 is made of a flexible material such as polyimide. The seed layer 12 is, for example, a copper seed layer with a thickness of 2 μm.
[0026] Furthermore, the material of the insulating substrate 11 is not limited to polyimide-based materials; for example, it may be liquid crystal polymer (LCP), fluorine-based materials (PFA, PTFE, etc.).
[0027] Next, as shown in Figure 2A(2), a resist layer (plating resist) 13 is formed on the seed layer 12 (step S12). The resist layer 13 is made of a photosensitive material. In this embodiment, the resist layer 13 is negative type.
[0028] Next, as shown in Figure 2A(3), a conductive pattern opening 13p and a dummy pattern opening 13d are formed in the resist layer 13 (step S13). In this step, the dummy pattern opening 13d is formed in the region where the insulating substrate 11 is bent in the use state or mounting state, the region where high-speed signal lines are formed, and / or the region where the outer shape is processed. The region where the outer shape is processed is the region where punching or the like is performed, and is a region where no metal such as a plating layer is placed. The dummy pattern opening 13d is formed so that the density of openings in the resist layer 13 (conductive pattern opening 13p and dummy pattern opening 13d) is approximately uniform. For example, the width of the conductive pattern opening 13p is 20 μm, and the width of the dummy pattern opening 13d is 10 μm.
[0029] Step S13 is performed by a photolithography process. In this embodiment, a predetermined area of the resist layer 13 is exposed using a direct exposure apparatus, and then the exposed resist layer 13 is developed to form an aperture 13p for a conductive pattern and an aperture 13d for a dummy pattern. In the exposure process, the resist layer 13 is exposed so that the size of the dummy pattern aperture 13d is less than or equal to the lower limit of the achievable aperture size based on the material of the resist layer 13 and the performance of the exposure apparatus. For example, the upper surface of the resist layer 13 is exposed to an area other than the area where the dummy pattern aperture 13d is to be formed. The area where the dummy pattern aperture 13d is to be formed is set to a size less than or equal to the lower limit of the achievable aperture size.
[0030] When using Asahi Kasei Corporation's dry film resist UFG158 as the material for the resist layer 13 and Oak Manufacturing Co., Ltd.'s laser direct exposure system DIIMPACT Extra12 as the exposure system, the practical lower limit of the aperture of the plating resist is 11 μm at an exposure dose of 260 mJ. In this case, for example, the exposure system is set so that the size of the dummy pattern aperture 13d is a dot shape of φ10 μm, which is smaller than the aperture, and the resist layer 13 is exposed. When the dummy pattern aperture 13d was actually formed under these conditions, the aperture size at the upper end of the dummy pattern aperture 13d was 10 μm, but the aperture size at the lower end was 5 μm due to hem reduction.
[0031] If the resist layer 13 is positive type, the area where the dummy pattern aperture 13d is to be formed is exposed so that the area where the dummy pattern aperture 13d is to be formed is less than or equal to the lower limit of the achievable aperture size.
[0032] Alternatively, the photolithography process in step S13 may be performed using an exposure mask. In this case, first, an exposure mask (not shown) is placed over the resist layer 13. The exposure mask has a conductive pattern mask opening corresponding to the conductive pattern opening 13p and a dummy pattern mask opening corresponding to the dummy pattern opening 13d, and is placed on the resist layer 13 after alignment.
[0033] Subsequently, the resist layer 13 is exposed through an exposure mask (exposure step). After the exposure step, the exposure mask is removed and the exposed resist layer 13 is developed to form the conductive pattern opening 13p and the dummy pattern opening 13d.
[0034] The size of the mask aperture for the conductive pattern of the exposure mask (i.e., the size of the conductive pattern aperture 13p) shall be a dimension that is suitable for the resolution performance based on the material of the resist layer 13 and the exposure equipment (exposure amount) used in the exposure process.
[0035] On the other hand, the size of the mask opening for the dummy pattern in the exposure mask (i.e., the size of the dummy pattern opening 13d) is set to be less than or equal to the lower limit of the achievable opening size based on the material of the resist layer 13 and the exposure equipment used in the exposure process. As a result, the dummy pattern opening 13d is formed such that the opening width narrows at the bottom. That is, as shown in Figure 2A(3), the opening cross-section of the resist layer 13 takes on a tapered shape. The exposed area of the seed layer 12 becomes smaller than the design dimensions.
[0036] As described above, after developing the resist layer 13 to form the conductive pattern opening 13p and the dummy pattern opening 13d, a plating layer is formed on the seed layer 12 exposed to the conductive pattern opening 13p and the dummy pattern opening 13d by electroplating (step S14). That is, plating is deposited inside the conductive pattern opening 13p and the dummy pattern opening 13d. As a result, as shown in Figure 2B(1), a conductive pattern 14p is formed inside the conductive pattern opening 13p and a dummy pattern 14d is formed inside the dummy pattern opening 13d. Since the dummy pattern opening 13d is formed so that the opening density of the resist layer 13 is approximately uniform, the conductive pattern 14p (and the dummy pattern 14d) are formed to approximately the same thickness.
[0037] For example, copper plating is formed inside the conductive pattern opening 13p and the dummy pattern opening 13d by electrolytic copper plating. The thickness of the copper plating layer is, for example, 12 μm. The type of copper plating is not particularly limited.
[0038] The shape of the dummy pattern 14d is not particularly limited, but it is preferable that it has a symmetrical shape. For example, as shown in Figures 3(a) and (b), the shape of the dummy pattern opening is circular (dot-shaped) or star-shaped. Since etching proceeds isotropically in the subsequent process (step S16), if the dummy pattern is circular or star-shaped, it becomes easier to remove the dummy pattern, and as a result it can be removed with a small amount of etching, which is advantageous for forming fine wiring.
[0039] In addition, the shape of the opening for the dummy pattern may be a regular polygon, or it may be a wiring shape as shown in Figure 3(c).
[0040] When the shape of the dummy pattern opening is star-shaped or regular polygonal, hem blurring is likely to occur, allowing the dummy pattern 14d to be removed with less etching in the subsequent etching process (step S16). Therefore, it is suitable for forming fine wiring.
[0041] Next, as shown in Figure 2B(2), the resist layer 13 is removed (step S15). Since the dummy pattern opening 13d is formed so that the opening width narrows at the bottom, the dummy pattern 14d has an undercut shape. Figure 4 is an SEM image of the cross-section of the actually formed dummy pattern 14d during etching.
[0042] Next, as shown in Figures 2B(2) and (3), the exposed seed layer 12e of the seed layer 12 that is not covered by the plating layer (conductive pattern 14p and dummy pattern 14d) is removed by etching (step S16).
[0043] In step S16, for example, the copper seed layer is removed using a copper seed layer etching solution. The etching solution is not particularly limited, but for example, a sulfuric acid-hydrogen peroxide-based etching solution with FE-880 from JCU Corporation as an additive is used. Here, considering that the thickness of the seed layer 12 is 2 μm, the etching amount is set to 3 μm. Since the opening size at the lower end of the dummy pattern opening 13d is 5 μm, the dummy pattern 14d is removed from the insulating substrate 11 by etching by 3 μm.
[0044] In this embodiment, since the dummy pattern 14d has an undercut shape, the dummy pattern 14d is removed together with the exposed seed layer 12e during the etching process. This makes it possible to form a conductive pattern 14p with a suppressed plating thickness distribution.
[0045] Furthermore, at least one of the above processes may be carried out using a roll-to-roll method (continuous transport). Alternatively, all of the above processes may be carried out using a roll-to-roll method. This makes it possible to form a conductive pattern with suppressed plating thickness distribution while maintaining the manufacturing efficiency of flexible printed circuit boards.
[0046] Alternatively, a dummy pattern opening 13d with a tapered cross-section may be formed by exposing only the area around the region where the dummy pattern opening 13d is to be formed with a higher exposure amount than usual during the exposure process. That is, the resist layer 13 is exposed such that the amount of exposure around the area where the dummy pattern opening 13d is to be formed is greater than the amount of exposure to other exposure areas (hereinafter referred to as "other areas"). For example, the amount of exposure around the area where the dummy pattern opening 13d is to be formed is 1.5 times or more (preferably 2 times or more) the amount of exposure to other areas.
[0047] In practice, using a direct exposure apparatus, the area around the planned formation region for the dummy pattern aperture 13d was drawn with 500 mJ, and the other areas (including the area around the planned formation region for the conductive pattern aperture 13p) were drawn with 260 mJ. The width of the area around the planned formation region for the dummy pattern aperture 13d (for example, the width of the annular region) is not particularly limited, and is, for example, 1 to 5 μm. As a result, it was possible to form a dummy pattern aperture 13d with an aperture size of 10 μm at the upper end and an aperture size of 3 μm at the lower end. In this way, the drooping shape can be made more pronounced by adjusting the exposure amount.
[0048] The exposure amount can be increased by taking multiple exposures, or by taking a large exposure at once.
[0049] Furthermore, if the resist layer 13 is a positive type, the resist layer 13 is exposed such that the amount of exposure to the area where the dummy pattern opening 13d is to be formed is less than the amount of exposure to other areas. This makes it possible to form a dummy pattern opening 13d with a tapered cross-section.
[0050] Furthermore, the above exposure adjustment may be used in combination with a method that sets the size of the dummy pattern aperture 13d below the lower limit of the achievable aperture size.
[0051] As described above, in the conductive pattern formation according to the first embodiment, a dummy pattern 14d with an undercut shape is formed by forming the dummy pattern opening 13d such that the opening width narrows at its bottom. This makes it possible to remove the dummy pattern 14d in the process of etching off the exposed seed layer 12e. Therefore, a separate step for removing the dummy pattern 14d is unnecessary. Thus, according to this embodiment, a conductive pattern with a suppressed plating thickness distribution can be formed by the semi-additive method while maintaining manufacturing efficiency.
[0052] (Second embodiment) The conductive pattern formation method according to the second embodiment will be described with reference to the flowchart in Figure 5 and the process cross-sectional views in Figures 6A and 6B. One of the differences between this embodiment and the first embodiment is that, instead of forming an opening with a tapered cross-section as a dummy pattern opening, the dummy pattern is removed together with the exposed seed layer by using an etchant that preferentially etches the interface between the seed layer and the plating layer during the etching process of the exposed seed layer.
[0053] First, an insulating substrate 11 with a seed layer 12 on its main surface is prepared (step S21), and a resist layer 13 is formed on the seed layer 12 (step S22). Steps S21 and S22 are the same as steps S11 and S12 described in the first embodiment, so a detailed explanation is omitted.
[0054] Next, as shown in Figure 6A(1), a conductive pattern opening 13p and a dummy pattern opening 13d are formed in the resist layer 13 (step S23). The dummy pattern opening 13d is formed such that its width is smaller than the width of the conductive pattern opening 13p. In this step, the dummy pattern opening 13d is formed in the region where the insulating substrate 11 is bent, the region where high-speed signal lines are formed, and / or the region where the outer shape is processed. The dummy pattern opening 13d is formed so that the opening density of the resist layer 13 is substantially uniform, as in the first embodiment. However, unlike the first embodiment, the opening cross-section of the dummy pattern opening 13d is not a tapered shape, but a straight shape, similar to the conductive pattern opening 13p.
[0055] Next, as shown in Figure 6A(2), a plating layer is formed on the seed layer 12 exposed to the conductive pattern opening 13p and the dummy pattern opening 13d by electroplating (step S24). This forms a conductive pattern 14p in the conductive pattern opening 13p and a dummy pattern 14d in the dummy pattern opening 13d. After that, as shown in Figure 6A(3), the resist layer 13 is removed (step S25). Steps S24 and S25 are the same as steps S14 and S15 described in the first embodiment, so a detailed explanation is omitted.
[0056] Next, an etchant (seed layer etchant) that preferentially etches the interface between the seed layer 12 and the plating layer (conductive pattern 14p and dummy pattern 14d) is used to remove the dummy pattern 14d together with the exposed seed layer 12e (step S26). In this step, because an etchant for the seed layer is used, as shown in Figure 6B, the interface between the seed layer 12 and the plating layers 14p and 14d is preferentially etched, and as a result of the progression of undercuts, the dummy pattern 14d, which is smaller than the conductive pattern 14p, is removed together with the exposed seed layer 12e.
[0057] For example, Meltex's SE-300 can be used as an etchant for the seed layer. Figure 7 is an SEM image showing an example of a cross-section of the dummy pattern 14d during etching. By setting the etching amount to 3.5 μm, the dummy pattern 14d and the seed layer 12 beneath it are separated, resulting in the removal of the dummy pattern 14d from the insulating substrate 11.
[0058] As described above, in the case of the second embodiment as well, since the dummy pattern 14d is removed in the step of removing the exposed seed layer 12e, a conductive pattern 14p with a suppressed plating thickness distribution can be formed without increasing the number of steps.
[0059] Furthermore, at least one of the above processes may be carried out using a roll-to-roll method (continuous transport). Alternatively, all of the above processes may be carried out using a roll-to-roll method.
[0060] As described above, in the conductive pattern formation according to the second embodiment, the dummy pattern opening 13d is formed in the same way as the conductive pattern opening 13p, but in the process of etching off the exposed seed layer 12e, an etchant that preferentially etches the interface between the seed layer and the plating layer is used. As a result, the dummy pattern 14d can be removed together with the exposed seed layer 12e. Therefore, according to this embodiment, a conductive pattern with a suppressed plating thickness distribution can be formed by a semi-additive method while maintaining manufacturing efficiency.
[0061] Based on the above description, those skilled in the art may be able to conceive of additional effects and various modifications of the present invention, but the embodiments of the present invention are not limited to the individual embodiments described above. Components from different embodiments may be combined as appropriate. For example, in the etching step (step S16) of the first embodiment, an etchant that preferentially etches the interface between the seed layer 12 and the plating layer may be used.
[0062] Various additions, modifications, and partial deletions are permitted as long as they do not depart from the conceptual idea and spirit of the present invention derived from the claims and their equivalents. [Explanation of Symbols]
[0063] 11 Insulating substrate 12 Seed Layer 12e Exposed seed layer 13. Resist layer (plating resist) 13d Dummy pattern opening 13p Aperture for conductive pattern 14p conductive pattern 14d dummy pattern 100A, 100B Flexible Printed Circuit Board 110 Flexible insulating substrate 120,130 conductive patterns 140 signal line A, B Conductive pattern formation regions C connection area
Claims
1. A method for forming a conductive pattern by a semi-additive method, A step of preparing an insulating substrate having a seed layer on its main surface, and forming a resist layer on the seed layer, The steps include forming an opening for a conductive pattern and an opening for a dummy pattern in the resist layer, A step of forming a plating layer on the seed layer exposed in the openings for the conductive pattern and the openings for the dummy pattern by electroplating, The step of removing the resist layer, A step of removing an exposed seed layer that is not covered by the plating layer from the seed layer by etching, wherein the plating layer formed in the dummy pattern opening is removed together with the exposed seed layer. Equipped with, A method for forming the conductive pattern opening and the dummy pattern opening, wherein the dummy pattern opening is formed such that its opening width narrows at its bottom.
2. The steps of forming the conductive pattern opening and the dummy pattern opening are as follows: A step of exposing the resist layer such that the size of the dummy pattern opening is less than or equal to the lower limit of the achievable opening size based on the material of the resist layer and the performance of the exposure apparatus, The method according to claim 1, comprising the step of developing the exposed resist layer to form the opening for the conductive pattern and the opening for the dummy pattern.
3. When the resist layer is negative type, the step of forming the opening for the conductive pattern and the opening for the dummy pattern is: A step of exposing the resist layer such that the amount of exposure around the area where the dummy pattern opening is to be formed is greater than the amount of exposure to other areas, The method according to claim 1, comprising the step of developing the exposed resist layer to form the opening for the conductive pattern and the opening for the dummy pattern.
4. The method according to claim 3, wherein the exposure amount to the area surrounding the region where the dummy pattern opening is to be formed is 1.5 times or more the exposure amount to the other regions.
5. When the resist layer is of the positive type, the steps of forming the opening for the conductive pattern and the opening for the dummy pattern are as follows: A step of exposing the resist layer such that the amount of exposure to the area where the dummy pattern opening is to be formed is less than the amount of exposure to other areas, The method according to claim 1, comprising the step of developing the exposed resist layer to form the opening for the conductive pattern and the opening for the dummy pattern.
6. The method according to any one of claims 1 to 5, wherein the width of the dummy pattern opening is smaller than the width of the conductive pattern opening, and in the step of removing the exposed seed layer by etching, an etchant that preferentially etches the interface between the seed layer and the plating layer is used.
7. A method for forming a conductive pattern by a semi-additive method, A step of preparing an insulating substrate having a seed layer on its main surface, and forming a resist layer on the seed layer, The steps include forming an opening for a conductive pattern and an opening for a dummy pattern in the resist layer, A step of forming a plating layer on the seed layer exposed in the openings for the conductive pattern and the openings for the dummy pattern by electroplating, The step of removing the resist layer, A step of removing an exposed seed layer that is not covered by the plating layer from the seed layer by etching, wherein the plating layer formed in the dummy pattern opening is removed together with the exposed seed layer. Equipped with, The method wherein the shape of the opening for the dummy pattern is circular, a regular polygon, or a star shape.
8. The method according to claim 1, wherein the insulating substrate is flexible, and the dummy pattern opening is formed in a region where the insulating substrate is bent, a region where high-speed signal lines are formed, and / or a region where the outer shape is processed.
9. A method for performing at least one of the steps described in claim 1 in a roll-to-roll manner.