Indication device

Abstract

To provide a display device capable of improving overcurrent.SOLUTION: A display device comprises: a display panel including a plurality of data lines and pixels connected to the data lines; a first data driving portion including a plurality of pieces of first data IC connected to one ends of the plurality of data lines; a second data driving portion including a plurality of pieces of second data IC connected to the other ends of the plurality of data lines; a timing control portion that provides an input first lock signal and an input second lock signal to the first data driving portion and the second data driving portion, respectively; and a comparison circuit that receives an output first lock signal and an output second lock signal generated from the first data driving portion and the second data driving portion according to the input first lock signal and the input second lock signal, respectively, compares, and provides a synchronized synchronous lock signal to the timing control portion. The timing control portion transmits image data to the first data driving portion and the second data driving portion in a lock state of the synchronous lock signal. The first data driving portion and the second data driving portion output data voltage.SELECTED DRAWING: Figure 6

Description

Technical Field

[0006] , ,

[0007] , ,

[0001] The present invention relates to a display device.

Background Art

[0002] With the progress of the information society, various requirements for display devices for displaying images have increased. Recently, various flat display devices such as organic light-emitting display devices and liquid crystal display devices have been utilized.

[0003] In recent years, an organic light-emitting display device is driven in a double-bank structure in which data driving units are arranged at both ends of data wiring. In the double-bank structure, the same lock signal is simultaneously input to the front-stage data driving unit and the rear-stage data driving unit, and in response thereto, each of the front-stage data driving unit and the rear-stage data driving unit generates and outputs an output lock signal.

[0004] However, due to differences in electrical characteristics and the like between the front-stage data driving unit and the rear-stage data driving unit, the timings of the output lock signals may not match and become asynchronous.

[0005] In this case, since the output timings of the front-stage data driving unit and the rear-stage data driving unit do not match and become asynchronous, a potential difference in data voltage occurs at the upper and lower ends of the channel, and an overcurrent may occur. Further, there may be a problem that the data IC generates heat or burns due to this overcurrent.

Summary of the Invention

Problems to be Solved by the Invention

[0008] During the interval in which the lock states of the first output lock signal and the second output lock signal are asynchronous, the synchronous lock signal has an unlocked state, and in the unlocked state of the synchronous lock signal, the timing control unit turns off the transmission of the video data, and the outputs of the first data drive unit and the second data drive unit may be turned off.

[0009] During the interval in which at least one of the output first lock signal and the output second lock signal is in a lock failure state, the synchronization lock signal is in an unlock state, and in the unlock state of the synchronization lock signal, the timing control unit turns off the transmission of the video data, and the outputs of the first data drive unit and the second data drive unit may be turned off.

[0010] In the interval where the lock states of the first output lock signal and the second output lock signal are asynchronous, one of the first output lock signal and the other output lock signal may be in a locked state and the other in an unlocked state.

[0011] At least one of the output first lock signal and the output second lock signal may have an abnormal waveform when the lock fails.

[0012] When the input first lock signal is input, the plurality of first data ICs operate sequentially and output a lock signal, the lock signal output from the first data IC is input to the next first data IC, and the lock signal output from the last first data IC is the output first lock signal. When the input second lock signal is input, the plurality of second data ICs operate sequentially and output a lock signal, the lock signal output from the second data IC is input to the next second data IC, and the lock signal output from the last second data IC may be the output second lock signal.

[0013] The first data drive unit includes a first source board to which the plurality of first data ICs are connected, the second data drive unit includes a second source board to which the plurality of second data ICs are connected, the first source board includes a first lock signal wiring for transmitting input and output lock signals to the plurality of first data ICs, and the second source board may include a second lock signal wiring for transmitting input and output lock signals to the plurality of second data ICs.

[0014] The aforementioned pixel may include a light-emitting diode.

[0015] In other aspects, the present invention provides a display device comprising: a display panel including a plurality of data wirings and pixels connected to the data wirings; a first data drive unit including a plurality of first data ICs connected to one end of the plurality of data wirings; a second data drive unit including a plurality of second data ICs connected to the other end of the plurality of data wirings; a timing control unit that provides an input first lock signal and an input second lock signal to each of the first data drive unit and the second data drive unit; and a comparison circuit that receives, compares, and synchronizes output first lock signals and output second lock signals generated from the first data drive unit and the second data drive unit, respectively, based on the input first lock signal and the input second lock signal, and provides a synchronized synchronous lock signal to the timing control unit, wherein the output of the data voltages of the first data drive unit and the second data drive unit is adjusted by the synchronous lock signal.

[0016] In the locked state of the synchronization lock signal, the outputs of the data voltages of the first data drive unit and the second data drive unit can be synchronized.

[0017] During the interval in which the lock states of the first output lock signal and the second output lock signal are asynchronous, the synchronous lock signal has an unlocked state, and in the unlocked state of the synchronous lock signal, the outputs of the first data drive unit and the second data drive unit may be turned off.

[0018] During the interval in which at least one of the output first lock signal and the output second lock signal is in a lock failure state, the synchronization lock signal has an unlocked state, and in the unlocked state of the synchronization lock signal, the outputs of the first data drive unit and the second data drive unit may be turned off.

[0019] In the interval where the lock states of the first output lock signal and the second output lock signal are asynchronous, one of the first output lock signal and the other output lock signal may be in a locked state and the other in an unlocked state.

[0020] At least one of the output first lock signal and the output second lock signal may have an abnormal waveform when the lock fails.

[0021] The first data drive unit includes a first source board to which the plurality of first data ICs are connected, the second data drive unit includes a second source board to which the plurality of second data ICs are connected, the first source board includes a first lock signal wiring for transmitting input and output lock signals to the plurality of first data ICs, and the second source board may include a second lock signal wiring for transmitting input and output lock signals to the plurality of second data ICs.

[0022] The aforementioned pixel may include a light-emitting diode.

[0023] The data voltages output from the first data drive unit and the second data drive unit may be identical to each other. [Effects of the Invention]

[0024] In this invention, a first lock signal and a second lock signal are input to the preceding and succeeding data drive units of the double-bank structure. The first lock signal and the second lock signal output from the preceding and succeeding data drive units are compared by a comparison circuit to generate a synchronized synchronous lock signal. This synchronous lock signal is provided to a timing control unit, which uses the synchronous lock signal to adjust the transmission timing of the video data and synchronize the output of the data voltages of the preceding and succeeding data drive units.

[0025] This improves the phenomenon where a potential difference in output voltage occurs between the upper and lower ends of the channel during asynchronous sections or lock failure sections, resulting in overcurrent.

[0026] As a result, overheating and burning of data ICs in the preceding and succeeding data drive sections due to overcurrent can be improved. Furthermore, when the asynchronous section is long, image quality defects such as block dim can be improved.

Brief Description of the Drawings

[0027] [Figure 1] It is a diagram schematically showing a display device according to an embodiment of the present invention. [Figure 2] It is a circuit diagram schematically showing an example of a pixel according to an embodiment of the present invention. [Figure 3] It is a diagram schematically showing the configuration of a gate driving unit of a display device according to an embodiment of the present invention. [Figure 4] It is a timing diagram schematically showing an example of a driving signal output from a gate driving unit according to an embodiment of the present invention. [Figure 5] It is a cross-sectional view schematically showing an example of a cross-sectional structure of a display panel according to an embodiment of the present invention. [Figure 6] It is a diagram schematically showing a timing control unit, a data driving unit, and a comparison circuit of a display device according to an embodiment of the present invention. [Figure 7] It is a timing diagram schematically showing an example of an input lock signal, an output lock signal, a synchronization lock signal, and a data voltage output according to an embodiment of the present invention. [Figure 8] In an embodiment of the present invention, when asynchronization and lock failure of an output lock signal occur, it is a timing diagram schematically showing examples of an input lock signal, an output lock signal, a synchronization lock signal, and a data voltage output. [Figure 9] In a comparative example of the present invention, when asynchronization and lock failure of an output lock signal occur, it is a timing diagram schematically showing examples of an input lock signal, an output lock signal, and a data voltage output.

Modes for Carrying Out the Invention

[0028] The advantages and features of the present invention, and the methods for achieving them, will become clearer with reference to the embodiments described in detail with the drawings. However, the present invention is not limited to the embodiments disclosed below and can be embodied in a variety of different forms. These embodiments are provided so as to allow a person ordinary skill in the art to fully understand the scope of the invention, so as to make the disclosure of the present invention complete, and the present invention is defined by the scope of the claims.

[0029] The shapes, sizes, proportions, angles, and quantities disclosed in the drawings illustrating embodiments of the present invention are illustrative and the present invention is not limited thereto. Throughout the specification, the same reference numerals indicate the same components.

[0030] Furthermore, in describing the present invention, if it is determined that a specific explanation of related prior art would obscure the gist of the invention, such detailed explanation will be omitted. Wherever "equipped with," "includes," "possesses," "has," or "becomes" is used in this specification, other parts may be added unless "only / only" is also used. Also, where a component is described in the singular form, it may be interpreted as plural unless otherwise explicitly stated.

[0031] Furthermore, when interpreting the constituent elements, a margin of error shall be included even if not explicitly stated.

[0032] For example, when describing the positional relationship between two components using terms such as "adjacent" or "nearby," one or more other components may be located between those two components unless otherwise specified as "direct" or "directly."

[0033] Furthermore, when describing temporal relationships using phrases such as "after," "following," "next," or "before," discontinuous cases can be included unless "immediately" or "soon" is specified. Also, while terms such as "first" and "second" are used to distinguish components, the components are not limited to these terms. Therefore, the first component mentioned below may also be the second component within the technical concept of the present invention.

[0034] The features of each of the multiple embodiments of the present invention can be combined or integrated partially or entirely, enabling a wide range of technically diverse interconnections and drives. Furthermore, each embodiment can be implemented independently of or in conjunction with one another.

[0035] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. On the other hand, in the following embodiments, identical or similar components will be denoted by the same or similar reference numerals, and their specific descriptions may be omitted.

[0036] Figure 1 is a schematic diagram showing a display device according to an embodiment of the present invention, and Figure 2 is a schematic circuit diagram showing an example of a pixel according to an embodiment of the present invention. Figure 3 is a schematic diagram showing the configuration of the gate drive unit of the display device according to an embodiment of the present invention, and Figure 4 is a schematic timing diagram showing an example of a drive signal output from the gate drive unit according to an embodiment of the present invention.

[0037] Before going into specifics, the display device 10 according to this embodiment includes a light-emitting display device equipped with light-emitting diodes, and can include any display device to which a double-bank data drive structure is applied.

[0038] On the other hand, for the sake of explanation, in this embodiment, an organic light-emitting display device will be given as an example of the display device 10 and explained accordingly.

[0039] Referring to Figures 1 to 4, the display device 10 of this embodiment may include a display panel 100 and a drive circuit unit for driving the display panel 100.

[0040] Here, the drive circuit section may include, for example, a gate drive unit (or gate drive circuit) 210, a data drive unit (or data drive circuit) 220, and a timing control unit (or timing control circuit) 240. The drive circuit section may further include a power supply unit (or power supply circuit) 280 that supplies the power necessary to drive the display panel 100, the gate drive unit 210, the data drive unit 220, and the timing control unit 240.

[0041] Furthermore, the drive circuit section may include a comparison circuit 250 that compares the lock signals output by the double-bank data drive section 220, i.e., the output lock signals (LCK_out:LCK_out1, LCK_out2), synchronizes them to generate a synchronized lock signal LCKS, and provides it to the timing control section 240. Here, the potential of the lock signal may be, for example, lower than the gate high voltage (VGH, VEH) and lower than the source drive voltage (SVDD in Figure 6), but is not limited to this.

[0042] The display panel 100 may include a display area AA for displaying video, and a non-display area NA located outside (or surrounding) the display area AA.

[0043] In the display area AA, multiple pixels P can be arranged in a matrix along multiple horizontal lines (or row lines) and multiple vertical lines (or column lines).

[0044] Here, the multiple pixels P are of different colors and may include, but are not limited to, a red pixel, a green pixel, and a blue pixel that display red, green, and blue, respectively.

[0045] The display panel 100 can have all the signal wiring necessary to transmit drive signals for driving pixels P formed on the substrate.

[0046] For example, multiple data wirings DL that transmit data signals (or data voltages) of a video signal may extend vertically and be connected to pixels P on the corresponding vertical line.

[0047] Furthermore, a gate wiring GL that transmits a gate signal (or gate voltage) may extend horizontally and be connected to a pixel P on the corresponding horizontal line.

[0048] In this embodiment, multiple gate signals can be used to drive each pixel P, for example, a first scan signal SC1 to a fourth scan signal SC4 and a light emission control signal EM can be used. Therefore, multiple gate wirings GL can be used to transmit each of the multiple gate signals, for example, a first scan wiring SCL1 to a fourth scan wiring SCL4 and a light emission control wiring EML can be used.

[0049] In this way, multiple data lines DL and gate lines GL that intersect with each other can be used to partition a pixel P.

[0050] Each pixel P is a light-emitting element and may include a light-emitting diode OD, a plurality of transistors for driving it, and at least one capacitor.

[0051] On the other hand, in this embodiment, for the sake of explanation, we will take an 8T1C structure as an example, in which pixel P is equipped with eight transistors T1 to T7, DT and one capacitor Cst, as shown in Figure 2.

[0052] Referring to Figure 2, a pixel P may include a plurality of switching transistors, specifically a first transistor T1 through a seventh transistor T7, a drive transistor DT, a storage capacitor Cst, and a light-emitting diode OD.

[0053] Each of the first transistors T1 through T7 and the drive transistor DT may include a first electrode, a second electrode, and a gate electrode. Of the first and second electrodes, one may be the source electrode and the other the drain electrode.

[0054] Each of the first transistors T1 through T7 and the drive transistor DT may be a P-type transistor or an N-type transistor. On the other hand, Figure 2 shows an example where the second transistors T2 through T6 are P-type transistors, the first transistor T1 and the seventh transistor T7 are N-type transistors, and the drive transistor DT is a P-type transistor, but it is not limited to this. For example, the drive transistor DT may be an N-type transistor.

[0055] The first transistors T1 to T7 and the seventh transistor T7, and the drive transistor DT may comprise semiconductors of the same material or semiconductors of different materials. For example, some of the first transistors T1 to T7 and the seventh transistor T7, and the drive transistor DT may comprise one semiconductor layer from among a polycrystalline silicon layer, an oxide semiconductor layer, and an amorphous silicon layer, while other parts of the first transistors T1 to T7 and the seventh transistor T7, and the drive transistor DT may comprise other semiconductor layers from among a polycrystalline silicon layer, an oxide semiconductor layer, and an amorphous silicon layer.

[0056] On the other hand, oxide semiconductors have good off-current characteristics and can have characteristics suitable for switching transistors, so at least one of the first transistor T1 to the seventh transistor T7 can be equipped with an oxide semiconductor layer. Also, polycrystalline silicon has excellent mobility, so the driving transistor DT can be equipped with a polycrystalline silicon layer. Furthermore, the first transistor T1 to the seventh transistor T7 and the driving transistor DT can be configured in other forms. For example, the driving transistor DT may be equipped with an oxide semiconductor layer.

[0057] On the other hand, in this embodiment, we take the example of a case where the first transistor T1 and the seventh transistor T7 include an oxide semiconductor layer, and the other transistors T2 to T6 and DT include a polycrystalline silicon layer.

[0058] The gate signals provided to the nth horizontal line in Figure 2 (more specifically, the odd or even horizontal lines that make up the nth horizontal line) are provided from the corresponding nth stage in the gate drive unit 210, and for example, four scan signals, the first to fourth scan signals SC1 to SC4: SC1(n) to SC4(n), and two light emission control signals, the first and second light emission control signals EM: EM1(n) and EM2(n), may be provided. In this case, the display area AA can be configured to include the first to fourth scan wiring SCL1 to SCL4, which is connected to the nth stage and transmits the first to fourth scan signals SC1(n) to SC4(n) and the first and second light emission control signals EM1(n) and EM2(n) to the pixel P, as well as the first and second light emission control wiring EML1 and EML2. On the other hand, the gate drive unit 210 can also be configured to provide one light emission control signal instead of two light emission control signals EM1(n) and EM2(n).

[0059] The first transistor T1 can function as a sampling transistor, the second transistor T2 as a data supply transistor, the third and fourth transistors T3 and T4 as light emission control transistors, the fifth transistor T5 as a bias transistor, the sixth transistor T6 as a reset transistor (or first initialization transistor), and the seventh transistor as an initialization transistor (or second initialization transistor).

[0060] The light-emitting diode OD may include an anode and a cathode. The anode of the light-emitting diode OD is connected to the fifth node N5, and the cathode can receive a low-potential drive voltage EVSS.

[0061] The drive transistor DT may include a first electrode connected to the second node N2, a second electrode connected to the third node N3, and a gate electrode connected to the first node N1. The drive transistor DT can supply a drive current to the light-emitting diode OD based on the voltage at the first node N1 (i.e., the data voltage Vdata stored in the storage capacitor Cst).

[0062] The first transistor T1 may include a first electrode connected to a first node N1, a second electrode connected to a third node N3, and a gate electrode that receives a first scan signal SC1(n). The first transistor T1 may turn on in response to the first scan signal SC1, and a data voltage Vdata may be applied to (or written to, or sampled from) the gate electrode.

[0063] The storage capacitor Cst may be connected between the first node N1 and the fourth node N4. The storage capacitor Cst can store or hold the high potential drive voltage EVDD.

[0064] The second transistor T2 may include a first electrode connected to the data wiring DL (or receiving the data voltage Vdata), a second electrode connected to the second node N2, and a gate electrode that receives the second scan signal SC2(n). The second transistor T2 can turn on in response to the second scan signal SC2(n) and transmit the data voltage Vdata to the second node N2.

[0065] The third transistor T3 and the fourth transistor T4 (or the first and second light-emitting control transistors) are connected between the high-potential drive voltage EVDD and the light-emitting diode OD, forming a path through which the drive current generated by the drive transistor DT travels.

[0066] The third transistor T3 may include a first electrode connected to the fourth node N4 that receives a high-potential drive voltage EVDD, a second electrode connected to the second node N2, and a gate electrode that receives the first light emission control signal EM1(n).

[0067] The fourth transistor T4 may include a first electrode connected to the third node N3, a second electrode connected to the fifth node N5 (or the anode of the light-emitting diode OD), and a gate electrode that receives the second light-emitting control signal EM2(n).

[0068] The third and fourth transistors T3 and T4 are turned on in accordance with the corresponding first and second light emission control signals EM1(n) and EM2(n), providing a drive current to the light-emitting diode OD, which can then emit light at a brightness corresponding to the drive current.

[0069] The fifth transistor T5 may include a first electrode connected to a bias voltage wiring VobsL that transmits a bias voltage Vobs, a second electrode connected to a second node N2, and a gate electrode that receives a third scan signal SC3(n).

[0070] The sixth transistor T6 may include a first electrode connected to a reset voltage wiring (or first initialization voltage wiring) VarL that transmits the anode reset voltage (or first initialization voltage) Var, a second electrode connected to the fifth node N5, and a gate electrode that receives the third scan signal SC3(n).

[0071] The fifth and sixth transistors T5 and T6 are turned on in response to the third scan signal SC3(n), a bias voltage Vobs is applied to the second node N2, and an anode reset voltage Var may be applied to the fifth node N5 (i.e., the anode of the light-emitting diode OD).

[0072] The seventh transistor T7 may include a first electrode connected to the initialization voltage wiring ViniL that transmits the initialization voltage Vini, a second electrode connected to the first node N1, and a gate electrode that receives the fourth scan signal SC4(n).

[0073] The seventh transistor T7 can be turned on in response to the fourth scan signal SC4(n), apply the initialization voltage Vini, and initialize the gate electrode of the drive transistor DT. Unwanted charge may remain on the gate electrode of the drive transistor DT due to the high-potential drive voltage EVDD applied to the storage capacitor Cst. Therefore, by applying the initialization voltage Vini to the gate electrode of the drive transistor DT via the seventh transistor T7, the amount of residual charge can be initialized.

[0074] The 8T1C structure of pixel P described above is just one example, and pixel P in this embodiment may have other structures.

[0075] Referring again to Figure 1, the timing control unit 240 can process the video data Do input from the host system to suit the size and resolution of the display panel 100 and supply it to the data drive unit 220. The timing control unit 240 can use synchronization signals input from an external source, such as the dot clock signal CLK, the data enable signal DE, the horizontal synchronization signal HSY, and the vertical synchronization signal VSY, to generate a gate control signal GCS and a data control signal DCS. By supplying the gate control signal GCS and data control signal DCS thus generated to the gate drive unit 210 and the data drive unit 220, respectively, the gate drive unit 210 and the data drive unit 220 can be controlled.

[0076] The timing control unit 240 can also be configured in combination with various processors, such as microprocessors, mobile processors, and application processors, depending on the device in which it is implemented.

[0077] On the other hand, the host system may be, for example, a drive system that drives an electronic device in which the display device 10 is employed. Such an electronic device may be, for example, a TV navigation system, a monitor, a mobile device, or a wearable device.

[0078] The gate drive unit 210 receives a gate control signal GCS from the timing control unit 240, generates a gate signal, and can sequentially apply the gate signal to the gate wiring GL. For example, in the vertical direction, the gate signals can be output sequentially from the preceding stage to the succeeding stage.

[0079] The gate drive unit 210 can be located, for example, on at least one side of the display area AA. In this embodiment, we take as an example the case in which the gate drive unit 210 is configured to include a first gate drive unit 211 and a second gate drive unit 212 located on both sides of the display area AA, for example, on the left and right sides.

[0080] The gate drive unit 210 can, for example, have a GIP (gate-in-panel) structure and be directly formed in the non-display area NA on the substrate of the display panel 100. In this case, the gate drive unit 210 can be formed during the process of forming the elements of the display panel 100.

[0081] The gate drive unit 210 in the GIP structure may include, for example, a first scan drive circuit that sequentially outputs a first scan signal SC1, a second scan drive circuit that sequentially outputs a second scan signal SC2, a third scan drive circuit that sequentially outputs a third scan signal SC3, a fourth scan drive circuit that sequentially outputs a fourth scan signal SC4, a first light emission drive circuit that sequentially outputs a first light emission control signal EM1, and a second light emission drive circuit that sequentially outputs a second light emission control signal EM2.

[0082] Each of the first to fourth scan drive circuits, and the first and second light-emitting drive circuits, can be configured as a shift register including multiple stages that output the corresponding signals.

[0083] The gate drive unit 210 will be explained with reference to Figure 3. Figure 3 shows a part of the gate drive unit 210, and for the sake of explanation, it shows the configuration of the part of the gate drive unit 210 that drives the nth horizontal line, which is composed of the nth odd horizontal line (or the 2n-1th horizontal line) and the nth even horizontal line (or the 2nth horizontal line) in the display area AA.

[0084] The first gate drive unit 211 of the gate drive unit 210 can include, for example, a first scan stage SSC1(n), a third scan stage SSC3(n), and a fourth scan stage SSC4(n) which constitute a first scan drive circuit, a third scan drive circuit, and a fourth scan drive circuit, respectively; a first light-emitting stage SEM1(n) and a second light-emitting stage SEM2(n) which constitute a first light-emitting drive circuit and a second light-emitting drive circuit, respectively; and odd-numbered second scan stages SSC2_0(n) and even-numbered second scan stages SSC2_E(n) which constitute a second scan drive circuit.

[0085] Furthermore, the second gate drive unit 212 of the gate drive unit 210 can be configured with, for example, a first scan stage SSC1(n), a third scan stage SSC3(n), and a fourth scan stage SSC4(n) that constitute a first scan drive circuit, a third scan drive circuit, and a fourth scan drive circuit, respectively; a first light-emitting stage SEM1(n) and a second light-emitting stage SEM2(n) that constitute a first light-emitting drive circuit and a second light-emitting drive circuit, respectively; and odd-numbered second scan stages SSC2_0(n) and even-numbered second scan stages SSC2_E(n) that constitute a second scan drive circuit.

[0086] The arrangement of the first scan stage SSC1(n) to the fourth scan stage SSC4(n) and the first light emission stage SEM1(n) and the second light emission stage SEM2(n) shown in Figure 3 is just one example, and they can be arranged in various combinations in the first gate drive unit 211 and the second gate drive unit 212.

[0087] The first scan stage SSC1(n) can generate the first scan signal SC1(n) and output it to the corresponding first scan wiring SCL1. As a result, the pixels P_O(n) of the nth odd horizontal line and P_E(n) of the nth even horizontal line can both receive the applied first scan signal SC1(n).

[0088] An odd-numbered second scan stage SSC2_O(n) can generate an odd-numbered second scan signal SC2_O(n) and output it to the corresponding odd-numbered second scan line SCL2, and an even-numbered second scan stage SSC2_E(n) can generate an even-numbered second scan signal SC2_E(n) and output it to the corresponding even-numbered second scan line SCL2. As a result, the pixel P_O(n) of the nth odd-numbered horizontal line receives the odd-numbered second scan signal SC2_O(n), and the pixel P_E(n) of the nth even-numbered horizontal line receives the even-numbered second scan signal SC2_E(n). Here, the odd-numbered second scan signals SC2_O(n) and the even-numbered second scan signals SC2_E(n) have different timings. For example, each of the odd-numbered second scan signals SC2_O(n) and the even-numbered second scan signals SC2_E(n) can be applied to the data writing section of the nth odd-numbered horizontal line and the subsequent data writing section of the nth even-numbered horizontal line.

[0089] The third scan stage SSC3(n) generates the third scan signal SC3(n) and can output it to the corresponding third scan wiring SCL3. As a result, the pixels P_O(n) and P_E(n) of the nth odd and even horizontal lines can commonly receive the applied third scan signal SC3(n).

[0090] The fourth scan stage SSC4(n) generates the fourth scan signal SC4(n) and can output it to the corresponding fourth scan wiring SCL4. As a result, the pixels P_O(n) and P_E(n) of the nth odd and even horizontal lines can commonly receive the applied fourth scan signal SC4(n).

[0091] The first light-emitting stage SEM1(n) generates the first light-emitting control signal EM1(n) and can output it to the corresponding first light-emitting control signal EML1. As a result, the pixels P_O(n) and P_E(n) of the nth odd and even horizontal lines can commonly receive the application of the first light-emitting control signal EM1(n).

[0092] The second light emission stage SEM2(n) generates the second light emission control signal EM2(n) and can output it to the corresponding second light emission control signal EML2. As a result, the pixels P_O(n) and P_E(n) of the nth odd and even horizontal lines can commonly receive the application of the second light emission control signal EM2(n).

[0093] On the other hand, referring to Figure 3, a bias voltage wiring VobsL, a reset voltage wiring VarL, and an initialization voltage wiring ViniL can be placed between the gate drive unit 210 configured as described above and the display area AA.

[0094] The bias voltage wiring VobsL, reset voltage wiring VarL, and initialization voltage wiring ViniL can supply the bias voltage Vobs, anode reset voltage Var, and initialization voltage Vini, respectively, from the power supply unit 280 to the pixels P in the display area AA.

[0095] Figure 3 shows the bias voltage wiring VobsL, reset voltage wiring VarL, and initialization voltage wiring ViniL as being located on only one side of the display area AA, either the left or the right. However, this is not limited to this arrangement. They may be located on both sides, and even if they are located on one side, they are not limited to either the left or the right side.

[0096] Furthermore, referring to Figure 3, one or more optical regions OA1 and OA2 can be placed in the display region AA.

[0097] One or more optical regions OA1, OA2 can be arranged to overlap with one or more optical electronic devices, such as a camera (or image sensor) or sensing sensors such as a proximity sensor and an illuminance sensor. One or more optical regions OA1, OA2 can have a light-transmitting structure for the operation of the optical electronic devices and can have a transmittance of a predetermined level or higher. In other words, the number of pixels P per unit area in one or more optical regions OA1, OA2 may be smaller than the number of pixels P per unit area in the general area of ​​the display region AA excluding the optical regions OA1, OA2. That is, the resolution of one or more optical regions OA1, OA2 may be lower than the resolution of the general area within the display region AA.

[0098] Referring again to Figure 1, the data drive unit 220 receives video data Do and data control signal DSC from the timing control unit 240, converts the video data Do into analog video data data voltage Vdata according to the data control signal DCS, and outputs it to the corresponding data wiring DL.

[0099] The data drive unit 220 can have a double-bank structure that outputs a data voltage Vdata at both ends of the data wiring DL.

[0100] In this regard, the data drive unit 220 can consist of a first data drive unit 221, which is arranged (or connected) on one side of the display panel 100 (or display area AA), for example, on the upper side (or in front of it), and a second data drive unit 222, which is arranged (or connected) on the lower side (in the rear of it), for example, as an alternative to the display panel 100.

[0101] Each of the first data drive unit 221 and the second data drive unit 222 can be configured to include at least one data IC. In such a case, the data IC may be mounted on a flexible circuit film and connected to a non-display area NA on one side of the corresponding display panel 100, or it may be mounted directly on the non-display area NA.

[0102] The first data drive unit 221 and the second data drive unit 222 can form channels (or output channels) that correspond to and are connected to each of the multiple data wirings DL provided on the display panel 100. The first data drive unit 221 can have a channel that outputs the corresponding data voltage Vdata at the upper end of each data wiring DL. The second data drive unit 222 can have a channel that outputs the corresponding data voltage Vdata at the lower end of each data wiring DL.

[0103] Thus, the first data drive unit 221 and the second data drive unit 222, which are located above and below the display panel 100 respectively, may be supplied with the same (or identical) video data Do output from the timing control unit 240.

[0104] As a result, the same data voltage Vdata output from the first data drive unit 221 and the second data drive unit 222 can be applied to the upper and lower ends of each data wiring DL.

[0105] Thus, in a double-bank structure, the data wiring DL receives the same data voltage Vdata at both ends, allowing for a stable supply of the data voltage Vdata to the display area AA.

[0106] The power supply unit 280 generates the DC power necessary to drive the pixel array and drive circuit of the display panel 100, for example, using a DC-DC converter. The DC-DC converter may include a charge pump, regulator, buck converter, boost converter, etc.

[0107] The power supply unit 280 can, for example, receive a power voltage Vcc, which is a drive voltage for driving the display device 10, from a host system and generate DC voltages such as gate low voltages VGL and VEL, gate high voltages VGH and VEH, high potential drive voltage EVDD, low potential drive voltage EVSS, and source drive voltage (SVDD in Figure 6). The gate low voltages VGL and VEL and gate high voltages VGH and VEH can be supplied to the gate drive unit 210. The high potential drive voltage EVDD and low potential drive voltage EVSS can be supplied in common to the pixels P in the display panel 100. The source drive voltage SVDD can be supplied to the first data drive unit 221 and the second data drive unit 222, which constitute the data drive unit 220.

[0108] Here, the source drive voltage SVDD may, for example, be higher in potential than the high-potential drive voltage EVDD and lower in potential than the gate high voltages VGH and VEH, but is not limited to this. Also, the low-potential drive voltage EVSS may be lower, higher, or the same as the gate low voltages VGL and VEL.

[0109] The gate signal applied to the pixel P of the aforementioned display panel 100 will be explained with reference to Figure 4. For the sake of explanation, Figure 4 does not show the first and second light emission control signals EM(n) individually, but rather shows one representative light emission control signal EM(n) as an example.

[0110] A frame (or refresh frame) in which data is written and the video is refreshed can be divided into a non-emission section Tne and an emission section Te.

[0111] Such non-emission intervals Tne and emission intervals Te can be defined by emission control signals EM(n). High-level scan pulse intervals where the emission control signals EM(n) (e.g., first and second emission control signals EM1(n), EM2(n)) are at the turn-off level correspond to non-emission intervals Tne, and low-level intervals where the emission control signals EM(n) (e.g., first and second emission control signals EM1(n), EM2(n)) are at the turn-on level can correspond to emission intervals Te.

[0112] Within the non-emitting section Tne, a data voltage Vdata may be applied and written.

[0113] For example, during a data writing interval (or sampling interval) Ts in which odd and even second scan signals SC2_O(n) and SC2_E(n), more specifically low-level scan pulses that are their turn-on levels are applied, the respective data voltages Vdata of odd and even pixels P_O(n) and P_E(n) can be applied and written to the gate electrode of the drive transistor DT. Meanwhile, during such a data writing interval Ts, the threshold voltage of the drive transistor DT can be sampled and reflected in the gate electrode of the drive transistor DT.

[0114] In the data writing section Ts, the first scan signal SC1(n) has a high-level scan pulse that is at the turn-on level, and the corresponding first transistor T1 turns on.

[0115] On the other hand, within the non-emitting section Tne, there can be at least one bias section (or anode reset section) Tobs to which a bias voltage Vobs and an anode reset voltage Var are applied. In this embodiment, we take the case where the bias section Tobs is set before and after the data writing section Ts as an example. In this case, for the sake of explanation, the bias section Tobs set before data writing can be called the first bias section Tobs1, and the bias section Tobs set after data writing can be called the second bias section Tobs2.

[0116] In both the first bias section Tobs1 and the second bias section Tobs2, the third scan signal SC3(n) may have a low-level scan pulse that is the turn-on level.

[0117] In this case, the fifth transistor T5 is turned on, and the bias voltage Vobs can be applied to the second node N2 and the third node N3. As a result, on-bias stress operation can occur on the drive transistor DT.

[0118] Furthermore, the sixth transistor T6 is turned on, and an anode reset voltage Var can be applied to the fifth node N5. As a result, an anode reset operation can be performed on the anode electrode of the light-emitting diode OD.

[0119] On the other hand, an initialization voltage Vini may be applied between the data writing section Ts and the preceding first bias section Tobs1. In such an initialization section Ti, the fourth scan signal SC4(n) may have a high-level scan pulse that is the turn-on level. As a result, the corresponding seventh transistor T7 turns on, and the initialization voltage Vini may be applied to the first node N1, i.e., the gate electrode of the drive transistor DT. Furthermore, an initialization operation may be performed on the drive transistor DT.

[0120] Hereinafter, an example of the cross-sectional structure of the display panel 100 in this embodiment will be described with reference to Figure 5. Figure 5 is a schematic cross-sectional view showing an example of the cross-sectional structure of the display panel according to an embodiment of the present invention.

[0121] For the sake of explanation, two thin-film transistors TFT1 and TFT2 are shown in pixel P within display area AA in Figure 5. Here, the thin-film transistor TFT1, which is close to the substrate 101 and located relatively lower, is referred to as the first thin-film transistor TFT1, and this could be a polycrystalline silicon thin-film transistor. The thin-film transistor TFT2, which is farther from the substrate 101 and located relatively higher, is referred to as the second thin-film transistor TFT2, and this could be an oxide thin-film transistor.

[0122] On the other hand, the first thin-film transistor TFT1 may be a driving transistor (DT in Figure 2), but is not limited to this. For the sake of explanation, Figure 5 shows an example where the first thin-film transistor TFT1 is connected to a light-emitting diode OD. Furthermore, the second thin-film transistor TFT2 may be one of the first to seventh switching thin-film transistors (T1 to T7 in Figure 2), or more specifically, the first transistor T1 connected to the storage capacitor Cst, but is not limited to this.

[0123] The substrate 101 can be made of, for example, a thin glass substrate (or glass film) or a plastic substrate (or plastic film) to realize the flexible properties of the display panel 100.

[0124] In this case, if the substrate 101 is made of glass, for example, the substrate 101 can have a thickness of approximately 0.2 mm.

[0125] On the other hand, if the substrate 101 is made of a plastic substrate, for example, the substrate 101 may include at least one polyimide layer.

[0126] The first thin-film transistor TFT1 may comprise a first semiconductor layer 105 disposed on a substrate 101, a first gate electrode 115 superimposed on the semiconductor layer 105 with a first insulating layer 110 in between, and a first source electrode 151 and a first drain electrode 152 located above the first gate electrode 115 and on a fourth insulating layer 145. Here, the first semiconductor layer 105 can be formed from polycrystalline silicon, but is not limited to this.

[0127] The first semiconductor layer 105 may include a central channel region and source and drain regions on either side thereof. The first source electrode 151 and the first drain electrode 152 can be connected to the source and drain regions of the first semiconductor layer 105 via first contact holes 156 and second contact holes 157 formed in the insulating layers 110, 120, 125, 135, and 145 located beneath them.

[0128] A second insulating layer 120 can be formed on the first gate electrode 115 of the first thin-film transistor TFT1.

[0129] A first interlayer insulating layer 125 can be formed on the second insulating layer 120. A second thin-film transistor TFT2 can be formed on the first interlayer insulating layer 125.

[0130] The second thin-film transistor TFT2 may comprise a second semiconductor layer 130 on a first interlayer insulating layer 125, a second gate electrode 140 superimposed on the second semiconductor layer 130 with a third insulating layer 135 in between, and a second source electrode 153 and a second drain electrode 154 located above the second gate electrode 140 and on a fourth insulating layer 145. Here, the second semiconductor layer 130 may be formed from an oxide semiconductor, but is not limited thereto.

[0131] The second semiconductor layer 130 may include a central channel region and source and drain regions on either side thereof. The second source electrode 153 and the second drain electrode 154 can be connected to the source and drain regions of the second semiconductor layer 130 via third contact holes 158 and fourth contact holes 159 formed in the insulating layers 135 and 145 located beneath them.

[0132] A second interlayer insulating layer (or first planarization layer) 160 can be formed on the second thin-film transistor TFT2.

[0133] Here, the first insulating layer 110, the second insulating layer 120, the third insulating layer 135, and the fourth insulating layer 145 may, but are not limited to, inorganic insulating materials such as silicon nitride or silicon oxide.

[0134] Furthermore, the first interlayer insulating layer 125 and the second interlayer insulating layer 160 may, but are not limited to, organic insulating materials such as photoacrylic or benzocyclobutene.

[0135] A connecting electrode 162 can be formed on the second interlayer insulating layer 160. The connecting electrode 162 can be connected to the first drain electrode 152 via a contact hole 161 formed in the second interlayer insulating layer 160.

[0136] A third interlayer insulating layer (or second planarization layer) 163 can be formed on the connecting electrode 162. The third interlayer insulating layer 163 may, but is not limited to, an organic insulating material such as photoacrylic or benzocyclobutene.

[0137] A light-emitting diode (OD) and a bank (165) can be formed on the third interlayer insulating layer (163).

[0138] The light-emitting diode OD may include an anode electrode (or first electrode) 171, a light-emitting layer 172, and a cathode (or second electrode) 173.

[0139] The anode 171 can be connected to the connecting electrode 162 via a contact hole 164 formed in the third interlayer insulating layer 163.

[0140] The bank 165 can be positioned along the boundary of the pixel P and can be formed to cover the edge of the anode 171. The light-emitting layer 172 can be formed on the anode 171 exposed through the opening of the bank 165.

[0141] The cathode 173 is formed on the light-emitting layer 172 and can receive a low-potential driving voltage (EVSS in Figure 2).

[0142] A sealing layer 180 can be formed on the cathode 173. The sealing layer 180 may, but is not limited to, comprise at least one inorganic sealing layer and at least one organic sealing layer. In this invention, an example is given of a sealing layer 180 structure in which a first sealing layer 181, a second sealing layer 182, and a third sealing layer 183 are sequentially laminated.

[0143] The first sealing layer 181 is formed on the substrate 101 on which the cathode 173 is formed. The third sealing layer 183 is formed on the substrate 101 on which the second sealing layer 182 is formed, and together with the first sealing layer 181, it can be formed to surround the top, bottom, and sides of the second sealing layer 182. The first sealing layer 181 and the third sealing layer 183 can minimize or prevent external moisture and oxygen from penetrating the light-emitting diode OD. The first sealing layer 181 and the third sealing layer 183 can be formed from inorganic insulating materials that can be deposited at low temperatures, such as silicon nitride, silicon oxide, silicon oxynitride, or aluminum oxide.

[0144] The second sealing layer 182 acts as a buffer to alleviate stress between layers caused by warping of the display device 10, and can flatten the steps between layers. This second sealing layer 182 can be formed on the substrate 101 on which the first sealing layer 181 is formed from a non-photosensitive organic insulating material such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, polyethylene, or silicon oxycarbon (SiOC), or from a photosensitive organic insulating material such as photoacrylic, but is not limited to these. When the second sealing layer 182 is formed by an inkjet method, a dam DAM can be placed in the non-display area NA to prevent the liquid second sealing layer 182 from diffusing to the edges of the substrate 101. The dam DAM can be placed even closer to the edges of the substrate 101 than the second sealing layer 182. Such a dam DAM can prevent the second sealing layer 182 from diffusing to the pad area where the outermost conductive pads are placed on the substrate 101.

[0145] The dam (DAM) is designed to prevent the diffusion of the second sealing layer 182. However, if the second sealing layer 182 is formed to exceed the height of the dam during the manufacturing process, the organic layer of the second sealing layer 182 may be exposed to the outside, allowing moisture and other substances to easily penetrate into the interior of the light-emitting element. Therefore, at least 10 or more dams (DAMs) can be formed stacked on top of each other, but this is not the only way to do so.

[0146] The dam (DAM) can be formed simultaneously with the first interlayer insulating layer 125, the second interlayer insulating layer 160, and the third interlayer insulating layer 163. The lower layer of the dam can be formed at the same time as the first interlayer insulating layer 125, and the upper layer of the dam can be formed at the same time as the second interlayer insulating layer 160 and the third interlayer insulating layer 163, thereby laminating and forming a three-layer structure. As another example, the dam can also be formed using one or two of the first interlayer insulating layer 125, the second interlayer insulating layer 160, and the third interlayer insulating layer 163.

[0147] Therefore, the dam (DAM) can be made of the same material as the first interlayer insulating layer 125, the second interlayer insulating layer 160, and the third interlayer insulating layer 163, but is not limited to this.

[0148] Dams (DAMs) can be formed by superimposing them with low-potential drive voltage wiring (VSSLs). For example, in a non-display region (NA), low-potential drive voltage wiring (VSSLs) can be formed in the lower layer of the region where the dam (DAM) is located.

[0149] The gate drive unit 210, consisting of a low-potential drive voltage wiring VSSL and a GIP structure, is formed along the outside of the display panel 100, and the low-potential drive voltage wiring VSSL can be located outside the gate drive unit 210. The low-potential drive voltage wiring VSSL is also connected to the cathode 173, and a low-potential drive voltage EVSS can be applied to it. Although the gate drive unit 210 in the drawing is simply shown in plan and cross-section, it can have the same structure as the first and / or second thin-film transistors TFT1 and / or TFT2 in display area AA.

[0150] A touch layer (or touch element layer) 190 can be placed on the sealing layer 180. The touch buffer film 191 in the touch layer 190 can be positioned between the touch sensor metal, which includes touch electrode connection lines 192, 194 and touch electrodes 195, 196, and the cathode 173 of the light-emitting diode OD.

[0151] The touch buffer film 191 can block chemicals (such as developers and etching solutions) used in the manufacturing process of the touch sensor metal placed on the touch buffer film 191, or moisture from the outside, from penetrating into the light-emitting layer 172 which contains organic matter. As a result, the touch buffer film 191 can prevent damage to the light-emitting layer 172, which is sensitive to chemicals or moisture.

[0152] According to the structure of the mutual capacitive touch sensor, touch electrodes 195 and 196 are arranged on the touch buffer film 191, and the touch electrodes 195 and 196 can be arranged so as to intersect each other.

[0153] The touch electrode connecting wires 192 and 194 can electrically connect the touch electrodes 195 and 196. One of the touch electrode connecting wires 192 and 194 and the touch electrodes 195 and 196 can be located in different layers with the touch insulating film 193 in between. Alternatively, one of the touch electrode connecting wires 192 and 194 and the other can be located in different layers with the touch insulating layer 193 in between.

[0154] The touch electrode connection lines 192 and 194 are positioned to overlap with the bank 165, which can prevent a decrease in the aperture ratio, but are not limited to this arrangement.

[0155] On the other hand, some of the touch electrodes 195 and 196 and some of the touch electrode connecting wires 192 can be electrically connected to a touch drive circuit (not shown) via touch pads 198 and 199, passing through the top and sides of the sealing layer 180 and the top and sides of the dam DAM.

[0156] Parts of the touch electrodes 195 and 196, and parts of the touch electrode connecting lines 192, can receive touch drive signals from the touch drive circuit and transmit them to the touch electrodes 195 and 196, and can transmit touch sensing signals sensed by the touch electrodes 195 and 196 to the touch drive circuit.

[0157] For example, the drive IC (such as a data IC) of the data drive unit 220, which includes a touch drive circuit, is made of COF (Chip on Film) and can be connected to the non-display area NA on the substrate 101 of the display panel 100. In this case, the ends of the touch pads 198 and 199 are connected to the flexible circuit film on which the drive IC is mounted, and signals can be transmitted.

[0158] A touch protection film 197 can be placed on the touch electrodes 195 and 196. In Figure 5, the touch protection film 197 is shown to be placed only on the touch electrodes 195 and 196, but it is not limited to this. The touch protection film 197 can extend to the front or back of the dam (DAM) and can also be placed on the touch electrode connection line 192.

[0159] Furthermore, a color filter (not shown) can be placed on the sealing layer 180. The color filter may be located on the touch layer 190, or between the sealing layer 180 and the touch layer 190.

[0160] As described above, the display device 10 of this embodiment uses a double-bank data drive unit 220. Therefore, the same lock signal (i.e., input lock signal or lock voltage) LCK_in:LCK_in1, LCK_in2 is input to the first data drive unit 221 and the second data drive unit 222 of the data drive unit 220, and clock training, i.e., clock recognition, is performed. When clock training is completed (or successful), the first data drive unit 221 and the second data drive unit 222 can generate an output lock signal LCK_out as a feedback signal to the input lock signal LCK_in.

[0161] Here, clock training refers to the process in which, for example, the timing control unit 240 provides a training clock to the first data drive unit 221 and the second data drive unit 222, and the first data drive unit 221 and the second data drive unit 222 correctly recognize the training clock. Such clock training may be performed, for example, between the initial drive period after the display device 10 is powered on and the blank period between frames.

[0162] For example, when a power voltage Vcc is input to the power supply unit 500 to drive the display device 10, the power supply unit 500 generates any drive voltage necessary to drive the display device 10, and the timing control unit 240 can synchronize with the input timing of the power voltage Vcc and generate and output a lock signal (i.e., an input lock signal) LCK_in.

[0163] Thus, the lock signal (i.e., the lock signal) LCK_in output from the timing control unit 240 can be input simultaneously to the first data drive unit 221 and the second data drive unit 222. For the sake of explanation, the lock signal (i.e., the input lock signal) LCK_in input to the preceding first data drive unit 221 can be referred to as the input first lock signal LCK_in1, and the lock signal (i.e., the input lock signal) LCK_in input to the subsequent second data drive unit 222 can be referred to as the input second lock signal LCK_in2.

[0164] When the first input lock signal LCK_in1 and the second input lock signal LCK_in2 are transmitted at the same timing, the first data drive unit 221 and the second data drive unit 222 can perform clock training individually.

[0165] Once the clock training is complete, the first data drive unit 221 and the second data drive unit 222 can individually generate and output an output lock signal LCK_out.

[0166] For example, the first data drive unit 221 and the second data drive unit 222 can be connected in a cascaded manner and consist of multiple data ICs that operate sequentially. Each of the multiple data ICs can sequentially perform clock training when a lock signal (i.e., an input lock signal) LCK_in is input, generate a lock signal, and output it.

[0167] In this case, the first data drive unit 221 performs clock training on the first data IC using the input first lock signal LCK_in1, generates the corresponding output lock signal, and provides it to the second data IC. In this manner, the last data IC performs clock training, generates the corresponding output lock signal LCK_out, and transmits this output lock signal, the output first lock signal LCK_out1, to the comparator circuit 250. In this way, the first data drive unit 221 allows multiple data ICs to sequentially receive the lock signal input, perform clock training, and output the output first lock signal LCK_out1.

[0168] Similarly, in the second data drive unit 222, the first data IC performs clock training based on the input second lock signal LCK_in2, generates the corresponding output lock signal, and provides it to the second data IC. In this manner, the last data IC performs clock training, generates the corresponding output lock signal LCK_out, and transmits this output lock signal, the output second lock signal LCK_out2, to the comparator circuit 250. In this way, the second data drive unit 222 allows multiple data ICs to sequentially receive the lock signal input, perform clock training, and output the output second lock signal LCK_out2.

[0169] In this way, the first output lock signal LCK_out1 output by the last data IC of the first data drive unit 221 and the second output lock signal LCK_out2 output by the last data IC of the second data drive unit 222 are provided to the comparator circuit 250, which can compare the first output lock signal LCK_out1 and the second output lock signal LCK_out2.

[0170] For example, by comparing the first output lock signal LCK_out1 and the second output lock signal LCK_out2, it is possible to confirm whether the output timings of the first output lock signal LCK_out1 and the second output lock signal LCK_out2 between the first data drive unit 221 and the second data drive unit 222 are matched or synchronized. Also, for example, by checking whether either the first output lock signal LCK_out1 or the second output lock signal LCK_out2 is in a lock failure state (for example, by checking whether it has a very unusual waveform), it is possible to confirm whether at least one of the first data drive unit 221 or the second data drive unit 222 has failed clock training and whether a lock failure has occurred.

[0171] The comparison circuit 250 compares the output first lock signal LCK_out1 and the output second lock signal LCK_out2, synchronizes the lock states of the output first lock signal LCK_out1 and the output second lock signal LCK_out2, generates a synchronized lock signal (i.e., a synchronous lock signal) LCKS, and transmits it to the timing control unit 240.

[0172] The timing control unit 240 adjusts the transmission of video data Do to the first data drive unit 221 and the second data drive unit 222 in accordance with the synchronized synchronous lock signal LCKS, which indicates that the lock state is synchronized, thereby synchronizing the output timing of the first data drive unit 221 and the second data drive unit 222.

[0173] For example, if one of the output first lock signal LCK_out1 and the output second lock signal LCK_out2 is delayed compared to the other and is not synchronized with each other, i.e., asynchronous, the transmission timing of the video data Do can be adjusted in accordance with the synchronization lock signal LCKS generated based on the delayed output lock signal LCK_out, and provided to the first data drive unit 221 and the second data drive unit 222.

[0174] Furthermore, if a lock failure occurs in either the first data drive unit 221 or the second data drive unit 222, the lock failure is reflected, and the resulting synchronous lock signal LCKS turns off (or cancels) the transmission of video data Do, thereby turning off the output operation of the data voltage Vdata of both the first data drive unit 221 and the second data drive unit 222.

[0175] In this way, the output lock signals of the first data drive unit 221 and the second data drive unit 222 can be monitored in real time through the comparison circuit 250, the lock state can be synchronized, and the transmission of video data Do to the first data drive unit 221 and the second data drive unit 222 can be adjusted.

[0176] This makes it possible to mitigate or prevent the occurrence of a potential difference in the data voltage Vdata between the preceding and succeeding stages during the asynchronous intervals and lock failure intervals of the preceding and succeeding stage output lock signals, i.e., the first lock signal LCK_out1 and the second lock signal LCK_out2. As a result, it is possible to mitigate or prevent overcurrent caused by the potential difference in the data voltage Vdata between the upper and lower ends of the channel, thereby mitigating or preventing the data IC from overheating or burning due to overcurrent. Furthermore, it is possible to mitigate or prevent image quality defects such as block dim that occur due to a longer delay in the output lock signal LCK_out.

[0177] In this manner, the configuration and method of this embodiment, which compares and synchronizes the output first lock signal LCK_out1 and the output second lock signal LCK_out2 between the preceding first data drive unit 221 and the subsequent second data drive unit 222 to adjust the transmission of video data Do to the first data drive unit 221 and the second data drive unit 222, and adjusts the output timing of the first data drive unit 221 and the second data drive unit 222, will be described in more detail below.

[0178] Figure 6 is a schematic diagram showing the timing control unit, data drive unit, and comparison circuit of a display device according to an embodiment of the present invention. Figure 7 is a schematic timing diagram showing the input lock signal, output lock signal, synchronous lock signal, and data voltage output according to an embodiment of the present invention. Figure 8 is a schematic timing diagram showing an example of the input lock signal, output lock signal, synchronous lock signal, and data voltage output when asynchronous operation and lock failure of the output lock signal occur in an embodiment of the present invention. Figure 9 is a schematic timing diagram showing an example of the input lock signal, output lock signal, and data voltage output when asynchronous operation and lock failure of the output lock signal occur in a comparative example of the present invention.

[0179] Referring to Figure 6 in conjunction with Figures 1 to 5, the display device 10 of this embodiment can use a double-bank data drive unit 220. The double-bank data drive unit 220 may include a first data drive unit 221 and a second data drive unit 222 connected to the front and rear of the display panel 100, respectively.

[0180] On the other hand, the display device 10 of this embodiment is driven with a variable refresh rate (VRR) that adjusts the drive frequency, i.e., the refresh rate, in order to reduce power consumption, thereby achieving low power operation.

[0181] Referring to Figures 7 and 8, for example, the frequency, i.e., the refresh rate, while the display device 10 is driven by the application of a power voltage Vcc can be varied, but as an example, it can be varied between 60Hz and 120Hz. Here, when driving at a high speed of 120Hz, the display panel 100 is driven by refresh frames FRr, in which the image (or data voltage Vdata: Vdata1, Vdata2) is refreshed, and by skip frames FRs, in which the image is not refreshed and the previous image is kept as is. When driving at a low speed of 60Hz, VRR driving, driven by refresh frames FRr, is given as an example. On the other hand, SC in Figures 7, 8, and 9 indicates the scan signals (SC1 to SC4 in Figures 2 and 3) output from the gate drive unit 210.

[0182] The first data drive unit 221 and the second data drive unit 222 in the double-bank structure can each include, for example, multiple data ICs (DICs). In this embodiment, we take the example where the first data drive unit 221 includes three first data ICs (DIC1) which are the first to third first data ICs (DIC1(1) to DIC1(3)), and the second data drive unit 222 includes three second data ICs (DIC2) which are the first to third second data ICs (DIC2(1) to DIC2(3)).

[0183] The first data drive unit 221 and the second data drive unit 222 in this double-bank structure can output the same data voltage Vdata for each channel to the upper and lower ends of the data wiring DL.

[0184] For the sake of explanation, the data voltage Vdata output from the preceding first data drive unit 221 can be referred to as the first data voltage (or preceding data voltage) Vdata1, and the data voltage Vdata output from the subsequent second data drive unit 222 can be referred to as the second data voltage (or subsequent data voltage) Vdata2.

[0185] Furthermore, in this embodiment, we will give an example of the case in which the data ICs (DICs) of the first data drive unit 221 and the second data drive unit 222 are mounted on a flexible circuit film (FCF) using the COF method.

[0186] On the other hand, the first data drive unit 221 may include a first source board SPCB1, which is a source board SPCB to which a plurality of first data ICs (DIC1) are connected. Similarly, the second data drive unit 222 may include a second source board SPCB2, which is a source board SPCB to which a plurality of second data ICs (DIC2) are connected.

[0187] In this regard, the signal output from the timing control unit 240 can be transmitted to the first data IC (DIC1) via the first source board SPCB1, and can also be transmitted to the second data IC (DIC2) via the second source board SPCB2.

[0188] Here, the first source board SPCB1 can have a first lock signal wiring LCKL1 formed on it, which is a lock signal wiring LCKL that transmits a lock signal. The second source board SPCB2 can also have a second lock signal wiring LCKL2 formed on it, which is a lock signal wiring LCKL that transmits a lock signal.

[0189] For example, the input first lock signal LCK_in1 output from the timing control unit 240 is input to the first first data IC (DIC1(1)), where it undergoes clock training and can output a lock signal. Next, the lock signal (or first output lock signal) output from the first first data IC (DIC1(1)) is input to the second first data IC (DIC1(2)), where it undergoes clock training and can output a lock signal. Next, the lock signal (or second output lock signal) output from the second first data IC (DIC1(2)) is input to the third first data IC (DIC1(3)), where it undergoes clock training and can output the output first lock signal LCK_out1. In this way, the output first lock signal LCK_out1, which is the lock signal output from the last third first data IC (DIC1(3)), can be transmitted to the comparator circuit 250.

[0190] Thus, in order to transmit the input first lock signal LCK_in1 provided by the timing control unit 240, the output lock signals generated by the first first data IC (DIC1(1)) and the second first data IC (DIC1(2)), and the output first lock signal LCK_out1 generated by the third first data IC (DICI(3)), a first lock signal wiring LCKL1 can be formed on the first source board SPCB1.

[0191] Furthermore, lock signal wiring for input and output of the lock signal can also be formed on the flexible circuit film (FCF) on which the first data IC (DIC1) is mounted.

[0192] Furthermore, the input second lock signal LCK_in2 output from the timing control unit 240 is input to the first second data IC (DIC2(1)), where it undergoes clock training and can output a lock signal. Next, the lock signal (or first output lock signal) output from the first second data IC (DIC2(1)) is input to the second second data IC (DIC2(2)), where it undergoes clock training and can output a lock signal. Next, the lock signal (or second output lock signal) output from the second second data IC (DIC2(2)) is input to the third second data IC (DIC2(3)), where it undergoes clock training and can output a second output lock signal LCK_out2. In this way, the output second lock signal LCK_out2, which is the lock signal output from the last third second data IC (DIC2(3)), can be transmitted to the comparator circuit 250.

[0193] Thus, in order to transmit the input second lock signal LCK_in2 provided from the timing control unit 240, the output lock signals generated by the first second data IC (DIC2(1)) and the second second data IC (DIC2(2)), and the output second lock signal LCK_out2 generated by the third second data IC (DIC2(3)), a second lock signal wiring LCKL2 can be formed on the second source board SPCB2.

[0194] Furthermore, lock signal wiring for input and output of the lock signal can also be formed on the flexible circuit film (FCF) on which the second data IC (DIC2) is mounted.

[0195] On the other hand, the timing control unit 240 and the comparison circuit 250 can be implemented on a control board CPCB, for example, but are not limited to this.

[0196] The timing control unit 240 can provide the corresponding first data drive unit 221 and second data drive unit 222 with a first input lock signal LCK_in1 and a second input lock signal LCK_in2, which are the same input lock signal LCK_in.

[0197] Referring to Figure 7, for example, the input first lock signal LCK_in1 and the input second lock signal LCK_in2 can be synchronized with each other and input to the corresponding first data drive unit 221 and second data drive unit 222 at the same timing.

[0198] The input first lock signal LCK_in1 and the input second lock signal LCK_in2 can be at a high level, synchronized with the time when the display device 10 is powered on and the power voltage Vcc is applied to the power supply unit 280. Such high-level input first lock signal LCK_in1 and input second lock signal LCK_in2 can be held substantially for the duration of the operation of the display device 10 and input to the first data drive unit 221 and the second data drive unit 222.

[0199] Referring to Figures 7 and 8, the input first lock signal LCK_in1 and the input second lock signal LCK_in2 can be continuously output from the time of power-on until the last output time (or last frame) in the first data drive unit 221 and the second data drive unit 222 before power-off.

[0200] Thus, the input first lock signal LCK_in1 and input second lock signal LCK_in2 output from the timing control unit 240 from the time of power-on are input to the corresponding first data drive unit 221 and second data drive unit 222, and the first data drive unit 221 and second data drive unit 222 perform clock training and can output the output first lock signal LCK_out1 and output second lock signal LCK_out2.

[0201] For example, immediately after the display device 10 is powered on, during a power-on sequence that takes place for a predetermined time, the first data drive unit 221 and the second data drive unit 222 can perform clock training and output a first lock signal LCK_out1 and a second lock signal LCK_out2. Furthermore, during blank intervals between adjacent frames FR, for example, during the output interval of the vertical synchronization signal VSY, clock training can be performed and output a first lock signal LCK_out1 and a second lock signal LCK_out2.

[0202] The output first lock signal LCK_out1 and the output second lock signal LCK_out2 can be output after a predetermined time has elapsed from the start of the input first lock signal LCK_in1 and the input second lock signal LCK_in2. Furthermore, the output first lock signal LCK_out1 and the output second lock signal LCK_out2 can be continuously held for substantially the entire operating time of the display device 10.

[0203] Referring to Figure 7, in the normal operating state of the display device 10, the first output lock signal LCK_out1 and the second output lock signal LCK_out2 are started after a predetermined time has elapsed from the power-on point and can be continuously output until the last output point (or last frame) of the first data drive unit 221 and the second data drive unit 222 before power-off.

[0204] The comparison circuit 250 receives the output first lock signal LCK_out1 and the output second lock signal LCK_out2 output from the first data drive unit 221 and the second data drive unit 222, compares the states of the output first lock signal LCK_out1 and the output second lock signal LCK_out2, synchronizes their lock states, and generates a synchronous lock signal LCKS.

[0205] For example, the comparison circuit 250 compares the first output lock signal LCK_out1 and the second output lock signal LCK_out2 to check whether the output timings are synchronously matched or asynchronously matched. If they are asynchronous, the lock state can be matched and synchronized.

[0206] In this regard, referring to Figures 7 and 8, for example, the first output lock signal LCK_out1 may be output first from the power-on sequence, followed by the second output lock signal LCK_out2 with a delay. Conversely, the second output lock signal LCK_out2 may be output first from the power-on sequence, followed by the first output lock signal LCK_out1 with a delay.

[0207] Thus, the output delay of either the first output lock signal LCK_out1 or the second output lock signal LCK_out2 can be caused by the RC component of the wiring that transmits the lock signal and external factors. For example, if the RC resistance differs between the signal transmission wiring between the input of the first input lock signal LCK_in1 and the output of the first output lock signal LCK_out1, and between the signal transmission wiring between the input of the second input lock signal LCK_in2 and the output of the second output lock signal LCK_out2, or due to external factors, the output timing between the first output lock signal LCK_out1 and the second output lock signal LCK_out2 may differ.

[0208] Furthermore, referring to Figure 7, the first output lock signal LCK_out1 may terminate normally from the power-off sequence of the display device 10, and then the second output lock signal LCK_out2 may terminate with a delay. Conversely, referring to Figure 8, the first output lock signal LCK_out1 may terminate normally from the power-off sequence, and prior to that, the second output lock signal LCK_out2 may terminate.

[0209] Thus, if one of the output first lock signal LCK_out1 and the output second lock signal LCK_out2 is in a high-level locked state and the other is in a low-level unlocked state, and their lock states do not match, resulting in asynchronous operation, the comparator circuit 250 can output a synchronous lock signal LCKS, which has a low level of the unlocked state, during the asynchronous period.

[0210] Conversely, if both the first output lock signal LCK_out1 and the second output lock signal LCK_out2 have a high-level locked state, the comparator circuit 250 can output a synchronous lock signal LCKS with a high level of the locked state during the same lock interval. Referring to Figures 7 and 8, for example, the comparator circuit 250 can generate a high-level synchronous lock signal LCKS after the second output lock signal LCK_out2, which is delayed from the power-on sequence, has switched to the locked state.

[0211] Furthermore, the comparison circuit 250 compares the output first lock signal LCK_out1 and the output second lock signal LCK_out2 to check whether at least one of the first data drive unit 221 and the second data drive unit 222 is operating abnormally and whether a lock failure has occurred. If a lock failure has occurred, it can synchronize the signals by matching them to the unlocked state.

[0212] In this regard, referring to Figure 8, for example, the second data drive unit 222 is abnormally driven with a 120Hz refresh frame FRr, resulting in a lock failure. As a result, the output second lock signal LCK_out2 cannot maintain a normal high level, and the waveform may become abnormal. When a lock failure occurs in this way, the second data drive unit 222 fails to recognize the clock and performs abnormal output operation, which can cause noise to be generated in the second data voltage Vdata2 output from the second data drive unit 222.

[0213] Thus, if a lock failure occurs in the second data drive unit 222 and the output second lock signal LCK_out2 is in an abnormal lock failure state, the comparator circuit 250 can output a low-level synchronous lock signal LCKS in an unlocked state during the period of such lock failure.

[0214] Thus, by comparing the first output lock signal LCK_out1 and the second output lock signal LCK_out2, if their lock states are asynchronous or at least one of them is in a lock failure state, the comparator circuit 250 can set the synchronous lock signal LCKS to a low level indicating an unlocked state. Conversely, if both the first output lock signal LCK_out1 and the second output lock signal LCK_out2 are in a locked state, the comparator circuit 250 can set the synchronous lock signal LCKS to a high level indicating a locked state.

[0215] In this way, the synchronous lock signal LCKS, whose lock state is synchronized by the comparison circuit 250, is provided to the timing control unit 240, and the timing control unit 240 can adjust the transmission timing of video data Do to the first data drive unit 221 and the second data drive unit 222 based on the synchronous lock signal LCKS.

[0216] In this regard, referring to Figure 8, for example, if the lock states of the first output lock signal LCK_out1 and the second output lock signal LCK_out2 are asynchronous, or if at least one of them is in a lock failure state, the synchronous lock signal LCKS will be at a low level in the unlock state, and in accordance with the unlock state of such synchronous lock signal LCKS, the timing control unit 240 can turn off the transmission of video data Do to the first data drive unit 221 and the second data drive unit 222.

[0217] In this regard, if the output first lock signal LCK_out1 and the output second lock signal LCK_out2 are asynchronous, the timing control unit 240 can turn off the transmission of video data Do during such asynchronous intervals. As a result, during these asynchronous intervals, the outputs of the data voltages Vdata1 and Vdata2 of the first data drive unit 221 and the second data drive unit 222 may be turned off.

[0218] For example, as shown in Figure 8, if the output of the second output lock signal LCK_out2 is delayed from the first output lock signal LCK_out1 in the power-on sequence until the initial section within the 60Hz driven refresh frame FRr where the outputs of the first data drive unit 221 and the second data drive unit 222 start, the synchronization lock signal LCKS may maintain a low level until the initial section of the refresh frame FRr where the delay occurred, and then switch to a high level.

[0219] Furthermore, as shown in Figure 8, if the output of the second lock signal LCK_out2 terminates before the final section of the 60Hz driven refresh frame FRr where the outputs of the first data drive unit 221 and the second data drive unit 222 terminate, the synchronization lock signal LCKS may maintain a high level until just before the final section of the refresh frame FRr where it terminated first, and then switch to a low level.

[0220] Thus, if the second output lock signal LCK_out2 is output with a delay or finishes earlier than the first output lock signal LCK_out1, and the first output lock signal LCK_out1 and the second output lock signal LCK_out2 become asynchronous with each other, the timing control unit 240 can turn off the transmission of video data Do during the asynchronous period. Also, in a period in which the second output lock signal LCK_out2 has a high-level lock state and the synchronous lock signal LCKS has a high-level lock state, the timing control unit 240 can transmit video data Do according to the lock state of the synchronous lock signal LCKS.

[0221] In this way, during the interval when the first output lock signal LCK_out1 and the second output lock signal LCK_out2 are asynchronous, the transmission of video data Do is turned off, and the outputs of the first data voltage Vdata1 and the second data voltage Vdata2 of the preceding and succeeding stages are turned off. During the interval when both are locked, the transmission of video data Do is resumed, and the same first data voltage Vdata1 and second data voltage Vdata2 can be synchronized and output.

[0222] As a result, in the asynchronous interval between the first output lock signal LCK_out1 and the second output lock signal LCK_out2, the output timing of the preceding first data drive unit 221 and the succeeding second data drive unit 222 becomes asynchronous, which can mitigate or prevent the occurrence of an overcurrent due to a potential difference in the output voltage between the upper and lower ends of the channel. Consequently, it is possible to mitigate or prevent overheating and burning of the data IC (DIC) due to overcurrent that occurs when the outputs of the preceding and succeeding stages become asynchronous. Furthermore, if the asynchronous interval of the output is long, it is possible to mitigate or prevent image quality defects such as block dim.

[0223] Referring to the comparative example in Figure 9, in the comparative example's display device, the power supply unit 280 provides a single input lock signal LCK_in to the first data drive unit 221 and the second data drive unit 222. The timing control unit 240 receives the output first lock signal LCK_out1 and the output second lock signal LCK_out2 from the first data drive unit 221 and the second data drive unit 222. If either the output first lock signal LCK_out1 or the output second lock signal LCK_out2 is in a locked state, regardless of whether synchronization is enabled or disabled, it transmits video data Do to the first data drive unit 221 and the second data drive unit 222, and the first data drive unit 221 and the second data drive unit 222 can output the corresponding data voltages Vdata1 and Vdata2.

[0224] In the driving of this comparative example, video data Do is transmitted even in the asynchronous section between the first output lock signal LCK_out1 and the second output lock signal LCK_out2. In the asynchronous section, for example, the asynchronous section of the power-on sequence or power-off sequence, the first data drive unit 221 outputs the first data voltage Vdata1, and the second data drive unit 222 is unable to output the second data voltage Vdata2 which is the same as the first data voltage Vdata1. As a result, a voltage potential difference is generated between the upper and lower ends of the channel, which can cause overcurrent.

[0225] In contrast, in this embodiment, as described above, the first output lock signal LCK_out1 and the second output lock signal LCK_out2 are synchronized to generate a synchronous lock signal LCKS. As a result, the outputs of the first data drive unit 221 and the second data drive unit 222 are turned off during the asynchronous interval between the first output lock signal LCK_out1 and the second output lock signal LCK_out2, and the outputs of the first data drive unit 221 and the second data drive unit 222 are performed during the interval when both are locked. Consequently, the potential difference of the output voltage between the upper and lower ends of the channel is mitigated or reduced during the asynchronous interval, thereby limiting overcurrent due to the potential difference.

[0226] Furthermore, if at least one of the output first lock signal LCK_out1 and the output second lock signal LCK_out2 is in a lock failure state, the timing control unit 240 can turn off the transmission of video data Do during the lock failure period, and as a result, the outputs of the data voltages Vdata1 and Vdata2 of the first data drive unit 221 and the second data drive unit 222 may be turned off during that period.

[0227] For example, as shown in Figure 8, if the output second lock signal LCK_out2 is in a lock failure state during a 120Hz driven refresh frame FRr (i.e., the second data drive unit 222 fails to lock), the synchronous lock signal LCKS may be at a low level during the refresh frame FRr in which the lock failure occurred.

[0228] Thus, when the second output lock signal LCK_out2 is in a lock failure state, the timing control unit 240 can turn off the transmission of video data Do during the lock failure period. Also, when the second output lock signal LCK_out2 switches to a high-level lock state and the synchronization lock signal LCKS is in a high-level lock state, the timing control unit 240 can transmit video data Do according to the lock state of the synchronization lock signal LCKS.

[0229] In this way, during the period when the output second lock signal LCK_out2 is in an abnormal lock failure state, the transmission of video data Do is turned off, and the outputs of the preceding and succeeding first data voltage Vdata1 and second data voltage Vdata2 are turned off. During the period when the lock state is normal, video data Do is transmitted, and the same first data voltage Vdata1 and second data voltage Vdata2 can be synchronized and output.

[0230] As a result, in the lock failure section, the preceding first data drive unit 221 outputs a normal output, while the subsequent second data drive unit 222 outputs an abnormal output. This creates a potential difference in the output voltage between the upper and lower ends of the channel, which can mitigate or prevent the phenomenon of overcurrent. Consequently, overheating and combustion of the data IC (DIC) due to overcurrent during lock failure can be mitigated or prevented.

[0231] Referring to the comparative example in Figure 9, the comparative example display device transmits video data Do to the first data drive unit 221 and the second data drive unit 222 regardless of whether the lock fails, as long as either the first output lock signal LCK_out1 or the second output lock signal LCK_out2 is in a locked state. The first data drive unit 221 and the second data drive unit 222 can then output the corresponding data voltages Vdata1 and Vdata2.

[0232] In the driving of this comparative example, video data Do is transmitted even during the lock failure section, and the first data drive unit 221 outputs the first data voltage Vdata1 normally, but the second data drive unit 222 is unable to output the second data voltage Vdata2, which is the same as the first data voltage Vdata1, normally and outputs an abnormal value. For example, the second data drive unit 222 will generate noise in its output voltage due to the lock failure.

[0233] As a result, a potential difference in the output voltage occurs between the upper and lower ends of the channel, which can cause overcurrent. For example, if the output voltage of the second data drive unit 222 is fixed to the source drive voltage SVDD, an overcurrent may occur to the first data drive unit 221.

[0234] In contrast, in this embodiment, as described above, the first output lock signal LCK_out1 and the second output lock signal LCK_out2 are synchronized to generate a synchronous lock signal LCKS. As a result, during the lock failure interval of the second output lock signal LCK_out2, the outputs of the first data drive unit 221 and the second data drive unit 222 are turned off. Consequently, during the lock failure interval, the potential difference of the output voltage between the upper and lower ends of the channel is mitigated or reduced, thereby limiting overcurrent due to the potential difference.

[0235] As described above, in the embodiment of the present invention, an input first lock signal and an input second lock signal are input to the preceding and succeeding data drive units of the double-bank structure, and the output first lock signal and output second lock signal output from the preceding and succeeding data drive units are compared by a comparison circuit to generate a synchronized synchronous lock signal, which is provided to the timing control unit. The timing control unit can adjust the transmission timing of the video data using the synchronous lock signal and synchronize the output of the data voltages of the preceding and succeeding data drive units.

[0236] This improves the phenomenon where a potential difference in the output voltage occurs between the upper and lower ends of the channel during asynchronous sections or lock failure sections, resulting in overcurrent.

[0237] As a result, overheating and burning of data ICs in the preceding and succeeding data drive sections due to overcurrent can be improved. Furthermore, when the asynchronous section is long, image quality defects such as block dim can be improved.

[0238] The embodiments of the present invention described above are examples, and the present invention can be freely modified without departing from the technical spirit of the invention. Therefore, the present invention includes the claims and modifications of the present invention within an equivalent scope. [Explanation of Symbols]

[0239] 10…Display device 100... Display panel 210...Gate drive unit 220...Data drive unit 221...First data drive unit 222...Second data drive unit 240... Timing Control Unit 250…Comparison circuit 280...Power supply section AA…display area NA…Hidden area GL...Gate wiring DL...Data wiring P...Pixel DIC...Data IC DIC1...First data IC DIC2...Second data IC LCK_in…Input lock signal LCK_in1…Input 1st lock signal LCK_in2… Input second lock signal LCK_out…Output lock signal LCK_out1…Output 1 lock signal LCK_out2…Output second lock signal LCKS… Synchronization lock signal

Claims

1. A display panel including multiple data lines and pixels connected to the data lines, A first data drive unit including a plurality of first data ICs connected to one end of the plurality of data wirings, A second data drive unit including a plurality of second data ICs connected to the other ends of the plurality of data wirings, A timing control unit that provides an input first lock signal to the first data drive unit and an input second lock signal to the second data drive unit, A comparison circuit that directly receives an output first lock signal generated based on the input first lock signal from the first data drive unit, directly receives an output second lock signal generated based on the input second lock signal from the second data drive unit, compares the output first lock signal and the output second lock signal, and provides a synchronous lock signal generated by synchronizing the lock state based on the output first lock signal and the output second lock signal to the timing control unit. Includes, The timing control unit transmits video data to the first data drive unit and the second data drive unit while the synchronization lock signal is locked, and the first data drive unit and the second data drive unit output data voltages. During the interval in which the lock states of the first output lock signal and the second output lock signal are asynchronous, or during the interval in which at least one of the first output lock signal and the second output lock signal is in a lock failure state, the power supply unit supplies the source drive voltage to the first data drive unit and the second data drive unit. Display device.

2. During the interval in which the lock states of the first output lock signal and the second output lock signal are asynchronous, the synchronous lock signal has an unlocked state. In the unlocked state of the synchronization lock signal, the timing control unit turns off the transmission of the video data, and the outputs of the first data drive unit and the second data drive unit are turned off. The display device according to claim 1.

3. During the interval in which at least one of the output first lock signal and the output second lock signal is in the lock failure state, the synchronization lock signal is in the unlock state. In the unlocked state of the synchronization lock signal, the timing control unit turns off the transmission of the video data, and the outputs of the first data drive unit and the second data drive unit are turned off. The display device according to claim 1.

4. The display device according to claim 2, wherein, in the interval in which the lock states of the first output lock signal and the second output lock signal become asynchronous, one of the first output lock signal and the other of the second output lock signal is in a locked state and the other is in an unlocked state.

5. The display device according to claim 3, wherein at least one of the output first lock signal and the output second lock signal has an abnormal waveform in the state of lock failure.

6. When the input first lock signal is received, the plurality of first data ICs operate sequentially and output lock signals. The lock signal output from the first data IC is input to the next first data IC, and the lock signal output from the last first data IC is the output first lock signal. When the input second lock signal is received, the plurality of second data ICs operate sequentially and output lock signals. The lock signal output from one second data IC is input to the next second data IC, and the lock signal output from the last second data IC is the output second lock signal. The display device according to claim 1.

7. The first data drive unit includes a first source board to which the plurality of first data ICs are connected. The second data drive unit includes a second source board to which the plurality of second data ICs are connected. The first source board includes a first lock signal wiring that transmits input and output lock signals to the plurality of first data ICs, The second source board includes a second lock signal wiring that transmits input and output lock signals to the plurality of second data ICs. The display device according to claim 6.

8. The display device according to claim 1, wherein the pixel includes a light-emitting diode.

9. The display device according to claim 1, wherein, in the locked state of the synchronization lock signal, the outputs of the data voltages of the first data drive unit and the second data drive unit are synchronized.

10. A display panel including multiple data lines and pixels connected to the data lines, A first data drive unit including a plurality of first data ICs connected to one end of the plurality of data wirings, A second data drive unit including a plurality of second data ICs connected to the other ends of the plurality of data wirings, A timing control unit that provides an input first lock signal to the first data drive unit and an input second lock signal to the second data drive unit, A comparison circuit that directly receives an output first lock signal generated based on the input first lock signal from the first data drive unit, directly receives an output second lock signal generated based on the input second lock signal from the second data drive unit, compares the output first lock signal and the output second lock signal, and provides a synchronous lock signal generated by synchronizing the lock state based on the output first lock signal and the output second lock signal to the timing control unit. Includes, In the locked state of the synchronization lock signal, the outputs of the data voltages of the first data drive unit and the second data drive unit are synchronized. During the interval in which the lock states of the first output lock signal and the second output lock signal are asynchronous, or during the interval in which at least one of the first output lock signal and the second output lock signal is in a lock failure state, the power supply unit supplies the source drive voltage to the first data drive unit and the second data drive unit. Display device.

11. During the interval in which the lock states of the first output lock signal and the second output lock signal become asynchronous with respect to each other, the synchronous lock signal has an unlocked state. When the synchronization lock signal is unlocked, the outputs of the first data drive unit and the second data drive unit are turned off. The display device according to claim 10.

12. During the interval in which at least one of the output first lock signal and the output second lock signal is in the lock failure state, the synchronization lock signal has an unlock state. When the synchronization lock signal is unlocked, the outputs of the first data drive unit and the second data drive unit are turned off. The display device according to claim 10.

13. The display device according to claim 11, wherein, in the interval in which the lock states of the first output lock signal and the second output lock signal are asynchronous, one of the first output lock signal and the other of the second output lock signal is in a locked state and the other is in an unlocked state.

14. The display device according to claim 12, wherein at least one of the output first lock signal and the output second lock signal has an abnormal waveform in the state of lock failure.

15. The first data drive unit includes a first source board to which the plurality of first data ICs are connected. The second data drive unit includes a second source board to which the plurality of second data ICs are connected. The first source board includes a first lock signal wiring that transmits input and output lock signals to the plurality of first data ICs, The second source board includes a second lock signal wiring that transmits input and output lock signals to the plurality of second data ICs. The display device according to claim 10.

16. The display device according to claim 10, wherein the pixel includes a light-emitting diode.

17. The display device according to claim 10, wherein the data voltages output from the first data drive unit and the second data drive unit are the same as those output from each other.

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