Semiconductor equipment

Abstract

To provide a semiconductor device with a novel structure.SOLUTION: A semiconductor device includes a digital calculator, an analog calculator, a first memory circuit, and a second memory circuit. Each of the analog calculator, the first memory circuit, and the second memory circuit includes a transistor including an oxide semiconductor in a channel formation region. The first memory circuit has a function of supplying first weight data as digital data to the digital calculator. The digital calculator has a function of performing product-sum operation using the first weight data. The second memory circuit has a function of supplying second weight data as analog data to the analog calculator. The analog calculator has a function of performing product-sum operation using the second weight data. In at least one transistor including the oxide semiconductor in the channel formation region included in the analog calculator and the second memory circuit, the amount of current flowing between a source and a drain is the amount of current flowing when the transistor operates in a subthreshold region.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] This specification describes semiconductor devices and the like.

[0002] It should be noted that one aspect of the present invention is not limited to the above-mentioned technical field. Examples of technical fields of one aspect of the present invention disclosed herein include semiconductor devices, imaging devices, display devices, light-emitting devices, energy storage devices, memory devices, display systems, electronic devices, lighting devices, input devices, input / output devices, methods for driving them, or methods for manufacturing them. [Background technology]

[0003] Electronic devices containing semiconductor devices, including CPUs (Central Processing Units), are becoming widespread. To process large amounts of data at high speed in such devices, technological development to improve the performance of semiconductor devices is active. One technology that achieves high performance is the so-called SoC (System on Chip), which tightly couples an accelerator such as a GPU (Graphics Processing Unit) with the CPU. However, with SoC-based high-performance semiconductor devices, increased heat generation and power consumption become problematic.

[0004] In AI (Artificial Intelligence) technology, the computational load increases due to the enormous amount of computation and the large number of parameters. This increase in computational load leads to increased heat generation and power consumption, so architectures to reduce computational load are being actively proposed. Representative architectures include Binary Neural Networks (BNNs) and Ternary Neural Networks (TNNs), which are particularly effective in reducing circuit size and power consumption (see, for example, Patent Document 1). [Prior art documents] [Patent Documents]

[0005] [Patent Document 1] International Publication No. 2019 / 078924 [Overview of the project] [Problems that the invention aims to solve]

[0006] AI computations require high-speed processing because they involve a vast number of repetitions of sum-of-products operations using weight data and input data. Memory cell arrays need to hold large amounts of weight data and intermediate data. In memory cell arrays that hold large amounts of weight data and intermediate data, the weight data and intermediate data are read to the arithmetic circuit via bit lines. Because the frequency of reading weight data and intermediate data is high, the bandwidth between the memory cell array and the arithmetic circuit can become the limiting factor in the operating speed.

[0007] Increasing the number of parallel connections between the memory cell array and the arithmetic circuit allows for a higher bandwidth connection between the two, which is advantageous for accelerating arithmetic processing. However, this increases the number of connections between the arithmetic circuit and the memory cell array, which may significantly increase the area of ​​the peripheral circuitry.

[0008] Furthermore, in AI computation, reducing the charging and discharging energy of the bit lines is crucial for achieving low power consumption.

[0009] To reduce the charging and discharging energy of bit lines, shortening the bit lines is effective. However, this would require arranging arithmetic circuits and memory cell arrays alternately, which could significantly increase the area of ​​peripheral circuits. Another technique to shorten bit lines involves integrating transistors vertically using bonding technology. However, with bonding technology, the spacing between the connection points for electrical connection is large, which could actually increase parasitic capacitance and prevent a reduction in charging and discharging energy.

[0010] One aspect of the present invention aims to provide a semiconductor device with reduced power consumption. Alternatively, one aspect of the present invention aims to provide a semiconductor device with improved computational processing speed. Another aspect of the present invention aims to provide a semiconductor device with improved computational accuracy. Alternatively, one aspect of the present invention aims to provide a miniaturized semiconductor device. Alternatively, one aspect of the present invention aims to provide a semiconductor device with a novel configuration.

[0011] Furthermore, one aspect of the present invention does not necessarily need to solve all of the above-mentioned problems; it is sufficient if it can solve at least one of them. Also, the description of the above-mentioned problems does not preclude the existence of other problems. Other problems will naturally become clear from the description in the specification, claims, drawings, etc., and it is possible to extract other problems from the description in the specification, claims, drawings, etc. [Means for solving the problem]

[0012] One aspect of the present invention is a semiconductor device comprising a digital arithmetic unit, an analog arithmetic unit, a first memory circuit, and a second memory circuit, wherein the analog arithmetic unit, the first memory circuit, and the second memory circuit each include a transistor having an oxide semiconductor in its channel formation region, the first memory circuit has the function of supplying first weight data as digital data to the digital arithmetic unit, the digital arithmetic unit has the function of performing a multiply-accumulate operation using the first weight data, the second memory circuit has the function of supplying second weight data as analog data to the analog arithmetic unit, the analog arithmetic unit has the function of performing a multiply-accumulate operation using the second weight data, and in at least one of the transistors having an oxide semiconductor in its channel formation region included in the analog arithmetic unit and the second memory circuit, the amount of current flowing between the source and drain is the amount of current flowing when the transistor operates in the subthreshold region.

[0013] In the above configuration, the digital arithmetic unit may be in a non-operating state while the analog arithmetic unit is operating, and the analog arithmetic unit may be in a non-operating state while the digital arithmetic unit is operating.

[0014] In the above, it is preferable that the digital arithmetic unit performs convolution operations. Furthermore, in the above, it is preferable that the analog arithmetic unit performs fully connected operations.

[0015] In the above, it is preferable that the digital arithmetic unit includes a transistor having silicon in the channel formation region. Furthermore, in the above, it is preferable that the digital arithmetic unit is provided on the first layer, and the analog arithmetic unit, first memory circuit, and second memory circuit are provided on the second layer, with the second layer being provided on top of the first layer. Furthermore, in the above, it is preferable that the first memory circuit is superimposed on the digital arithmetic unit.

[0016] Further embodiments of the present invention are described in the following descriptions of embodiments and in the drawings. [Effects of the Invention]

[0017] One aspect of the present invention can provide a semiconductor device with reduced power consumption. Alternatively, one aspect of the present invention can provide a semiconductor device with improved computational processing speed. Alternatively, one aspect of the present invention can provide a semiconductor device with improved computational accuracy. Alternatively, one aspect of the present invention can provide a miniaturized semiconductor device. Alternatively, one aspect of the present invention can provide a semiconductor device with a novel configuration.

[0018] The description of multiple effects does not preclude the existence of other effects. Furthermore, one embodiment of the present invention does not necessarily have to possess all of the exemplified effects. In addition, any problems, effects, and novel features of one embodiment of the present invention other than those described above will become clear from the description and drawings of this specification. [Brief explanation of the drawing]

[0019] [Figure 1] Figures 1A and 1B illustrate an example of the configuration of a semiconductor device. [Figure 2] Figures 2A and 2B illustrate an example of a semiconductor device configuration. [Figure 3] Figures 3A and 3B illustrate an example of a semiconductor device configuration. [Figure 4] Figure 4 illustrates an example of a semiconductor device configuration. [Figure 5] Figures 5A and 5B illustrate an example of the configuration of a semiconductor device. [Figure 6] Figures 6A and 6B illustrate an example of a semiconductor device configuration. [Figure 7] Figures 7A and 7B illustrate an example of the configuration of a semiconductor device. [Figure 8] Figure 8 illustrates an example of a semiconductor device configuration. [Figure 9] Figures 9A and 9B illustrate an example of the configuration of a semiconductor device. [Figure 10] Figures 10A and 10B illustrate an example of the configuration of a semiconductor device. [Figure 11] Figures 11A, 11B, and 11C illustrate an example configuration of a semiconductor device. [Figure 12] Figure 12 illustrates an example of a semiconductor device configuration. [Figure 13] Figure 13 is a diagram illustrating an example of a semiconductor device configuration. [Figure 14] Figures 14A and 14B illustrate an example of the configuration of a semiconductor device. [Figure 15] Figures 15A and 15B illustrate an example of the configuration of a semiconductor device. [Figure 16] Figures 16A and 16B illustrate an example of a semiconductor device configuration. [Figure 17] Figures 17A and 17B illustrate an example of the configuration of a semiconductor device. [Figure 18] Figure 18 illustrates an example of the configuration of a computing system. [Figure 19] Figure 19 is a diagram illustrating an example of a CPU configuration. [Figure 20] Figures 20A and 20B illustrate an example of a CPU configuration. [Figure 21] Figure 21 is a schematic cross-sectional view showing an example of the configuration of a semiconductor device. [Figure 22] Figures 22A to 22C are schematic cross-sectional diagrams showing examples of transistor configurations. [Figure 23] Figure 23 is a schematic cross-sectional view showing an example of the configuration of a semiconductor device. [Figure 24] Figures 24A and 24B are schematic cross-sectional diagrams showing examples of transistor configurations. [Figure 25] Figure 25 is a schematic cross-sectional diagram showing an example of a transistor configuration. [Figure 26] Figure 26A illustrates the classification of IGZO crystal structures, Figure 26B illustrates the XRD spectrum of crystalline IGZO, and Figure 26C illustrates the micro-electron diffraction pattern of crystalline IGZO. [Figure 27] Figure 27A is a perspective view showing an example of a semiconductor wafer, Figure 27B is a perspective view showing an example of a chip, and Figures 27C and 27D are perspective views showing examples of electronic components. [Figure 28] Figure 28 is a perspective view showing an example of an electronic device. [Figure 29] Figures 29A to 29C are perspective views showing an example of an electronic device. [Modes for carrying out the invention]

[0020] Embodiments of the present invention are described below. However, it will be readily apparent to those skilled in the art that an embodiment of the present invention is not limited to the following description, and that its form and details can be modified in various ways without departing from the spirit and scope of the present invention. Therefore, an embodiment of the present invention is not to be interpreted as being limited to the contents of the embodiments shown below.

[0021] In this specification, the ordinal numbers "1st," "2nd," and "3rd" are used to avoid confusion of constituent elements. Therefore, they do not limit the number of constituent elements, nor do they limit the order of the constituent elements. For example, a constituent element referred to as "1st" in one embodiment of this specification may be referred to as "2nd" in another embodiment or in the claims. For example, a constituent element referred to as "1st" in one embodiment of this specification may be omitted in another embodiment or in the claims.

[0022] In drawings, identical elements, elements with similar functions, elements of the same material, or elements formed simultaneously may be denoted by the same reference numeral, and repeated explanations may be omitted.

[0023] In this specification, for example, the power supply potential VDD may be abbreviated as potential VDD, VDD, etc. This also applies to other components (e.g., signals, voltages, circuits, elements, electrodes, wiring, etc.).

[0024] Furthermore, when the same designation is used for multiple elements, especially when it is necessary to distinguish them, identification designations such as "_1", "_2", "[n]", and "[m,n]" may be added to the designation. For example, the second wiring GL is written as wiring GL[2].

[0025] (Embodiment 1) The configuration and operation of a semiconductor device according to one aspect of the present invention will be described.

[0026] In this specification, the term "semiconductor device" refers to any device that can function by utilizing semiconductor properties. Semiconductor elements such as transistors, as well as semiconductor circuits, computing devices, and memory devices, are all forms of semiconductor devices. Display devices (such as liquid crystal displays and light-emitting displays), projection devices, lighting devices, electro-optical devices, energy storage devices, memory devices, semiconductor circuits, imaging devices, and electronic devices may also be considered to have semiconductor devices.

[0027] Figures 1A and 1B are diagrams illustrating a semiconductor device 100 according to one aspect of the present invention.

[0028] The semiconductor device 100 includes a digital calculator 101, an analog calculator 102, an oxide semiconductor memory (OS Memory) 103, and an oxide semiconductor memory (OS Memory) 104. The digital calculator 101 preferably has a transistor with silicon in its channel formation region (Si transistor). The analog calculator 102 preferably has a transistor with oxide semiconductor in its channel formation region (OS transistor). The oxide semiconductor memories 103 and 104 also have OS transistors.

[0029] The semiconductor device 100 functions as an accelerator capable of performing multiply-accumulate operations, and can switch between a digital arithmetic unit 101 and an analog arithmetic unit 102 depending on the type of operation. Figure 1A shows the state in which the digital arithmetic unit 101 is operating, and Figure 1B shows the state in which the analog arithmetic unit 102 is operating. As shown in Figure 1A, the analog arithmetic unit 102 is inactive while the digital arithmetic unit 101 is inactive. Also, as shown in Figure 1B, the digital arithmetic unit 101 is inactive while the analog arithmetic unit 102 is operating.

[0030] As shown in Figure 1A, the digital arithmetic unit 101 performs a sum-of-accumulate operation using the weight data W1 input from the oxide semiconductor memory 103 and the input data A1, and outputs the result as output data MAC1. The weight data W1 output by the oxide semiconductor memory 103 is output as digital data.

[0031] In this case, the OS transistor provided in the oxide semiconductor memory 103 has an extremely small current flowing between its source and drain when it is off, i.e., a leakage current. The oxide semiconductor memory 103 can be used as a non-volatile memory by using its characteristic of having an extremely small leakage current to hold a charge corresponding to the data within the memory circuit.

[0032] Furthermore, it is preferable to provide the oxide semiconductor memory 103 with a memory circuit that allows for non-destructive reading of the stored data without damaging it. This enables repeated processing using the same weight data at a high computation speed. Therefore, it is possible to speed up the parallel processing of multiply-accumulate operations in neural networks, which involve repeating data reading operations many times.

[0033] Furthermore, in the digital arithmetic unit 101, it is preferable that the input data A1 and weight data W1 be digital data that is resistant to noise. This enables the digital arithmetic unit 101 to perform calculations with high precision.

[0034] By using the oxide semiconductor memory 103 and digital arithmetic unit 101 as described above, the semiconductor device 100 can perform highly accurate and high-performance arithmetic processing. Therefore, the semiconductor device 100 can efficiently perform processing using the same weight data, such as in a convolutional neural network. The detailed configuration and specific examples of the oxide semiconductor memory 103 and digital arithmetic unit 101 will be described in the embodiments below.

[0035] As shown in Figure 1B, the analog arithmetic unit 102 performs a sum-of-accumulate operation using the weight data W2 input from the oxide semiconductor memory 104 and the input data A2, and outputs the result as output data MAC2. Here, the weight data W2 output by the oxide semiconductor memory 104 is output as analog data.

[0036] The analog arithmetic unit 102 can perform multiplication using the translinear principle utilizing the subthreshold region. Here, the OS transistors used in the analog arithmetic unit 102 and the oxide semiconductor memory 104 have lower off-currents than Si transistors, and the gate voltage range in which they operate in the subthreshold region can be widened. Therefore, in the analog arithmetic unit 102 and the oxide semiconductor memory 104, the OS transistors can be driven relatively easily in the subthreshold region with low current values.

[0037] By driving the OS transistor in the subthreshold region with low current values, the power consumption of the analog arithmetic unit 102 and the oxide semiconductor memory 104 can be reduced. In AI technology calculations, sum-of-accumulate operations using weight data and input data are repeated an enormous number of times, resulting in enormous power consumption. In particular, power consumption becomes significantly higher in fully connected operations where weight data is frequently rewritten. In contrast, by driving the analog arithmetic unit 102 and the oxide semiconductor memory 104 in the subthreshold region, power consumption can be effectively reduced.

[0038] By using the oxide semiconductor memory 104 and analog arithmetic unit 102 as described above, the semiconductor device 100 can perform arithmetic processing with low power consumption. Therefore, the semiconductor device 100 can perform power-efficient arithmetic processing that involves frequently rewriting weight data, such as fully connected arithmetic. The detailed configuration and specific examples of the oxide semiconductor memory 104 and analog arithmetic unit 102 will be described in the embodiments below.

[0039] As described above, the semiconductor device 100 shown in this embodiment can operate the digital arithmetic unit 101 when performing repetitive calculations using the same weight data, and the analog arithmetic unit 102 when frequently rewriting the weight data. By using the digital arithmetic unit 101 and the analog arithmetic unit 102 in this way, it is possible to perform calculations with high accuracy, high performance, and low power consumption overall.

[0040] Furthermore, the semiconductor device 100 shown in this embodiment can also process multiple operations in parallel. If the multiple operations include repetitive operations using the same weight data and operations that frequently rewrite the weight data, the digital arithmetic unit 101 and the analog arithmetic unit 102 may be operated in parallel. In other words, while the digital arithmetic unit 101 processes repetitive operations using the same weight data, the analog arithmetic unit 102 can process operations that frequently rewrite the weight data in parallel. For example, when performing operations with a CNN (Convolutional Neural Network) model, the analog arithmetic unit 102 can process fully connected operations while the digital arithmetic unit 101 can perform the next convolution operation in parallel.

[0041] Next, the arrangement of the digital arithmetic unit 101, analog arithmetic unit 102, oxide semiconductor memory 103, and oxide semiconductor memory 104 in the semiconductor device 100 will be explained using Figures 2A and 2B.

[0042] Figure 2A shows an example in which a digital arithmetic unit 101 is formed on a silicon substrate, and an analog arithmetic unit 102, an oxide semiconductor memory 103, and an oxide semiconductor memory 104 are arranged on top of the digital arithmetic unit 101. In Figure 2A, an xy plane is set approximately parallel to the upper surface of the silicon substrate, and element layers for forming the analog arithmetic unit 102, the oxide semiconductor memory 103, and the oxide semiconductor memory 104 are provided above in the z-axis direction. This configuration allows for high integration of the semiconductor device 100, which functions as an accelerator, and improves the processing speed per unit area. This also allows for miniaturization of the semiconductor device 100.

[0043] Furthermore, as shown in Figure 2A, it is preferable to provide the oxide semiconductor memory 103 superimposed on the digital arithmetic unit 101. This configuration allows for a shorter wiring distance between the oxide semiconductor memory 103 and the digital arithmetic unit 101. As a result, the processing speed when rewriting the weight data of the digital arithmetic unit 101 can be improved, and power consumption during this process can be reduced.

[0044] The arrangement of the components of the semiconductor device 100 shown in this embodiment is not limited to the arrangement shown in Figure 2A. For example, as shown in Figure 2B, the analog arithmetic unit 102 and the element layers forming the oxide semiconductor memory 104 may be stacked on top of the element layer forming the oxide semiconductor memory 103. Such a configuration can further miniaturize the semiconductor device 100.

[0045] Furthermore, although the above describes a configuration in which a Si transistor is used for the digital arithmetic unit 101, this embodiment is not limited to this, and a configuration in which a Si transistor is used for the analog arithmetic unit 102 is also possible.

[0046] Furthermore, although the above describes a configuration in which a Si transistor is used for the digital arithmetic unit 101 and an OS transistor is used for the analog arithmetic unit 102, this embodiment is not limited to this. For example, a configuration in which OS transistors are used for both the digital arithmetic unit 101 and the analog arithmetic unit 102 is also possible.

[0047] In this case, as shown in Figure 3A, an oxide semiconductor arithmetic unit (OS Calculator) 105 and an oxide semiconductor memory (OS Memory) 106 can be arranged on the silicon circuit (Si Circuit) 107. Here, the oxide semiconductor arithmetic unit 105 is an arithmetic unit formed of OS transistors, and combines digital and analog arithmetic units. The oxide semiconductor memory 106 has the function of supplying weight data to the oxide semiconductor arithmetic unit 105. The silicon circuit 107 may have any function, for example, it may function as a drive circuit, read circuit, memory circuit, arithmetic circuit, etc.

[0048] As shown in Figure 3A, the device is configured such that an element layer for forming an oxide semiconductor arithmetic unit 105 and an oxide semiconductor memory 106 is provided on a silicon substrate.

[0049] Furthermore, the arrangement of the parts of the semiconductor device 100 shown in this embodiment is not limited to the arrangement shown in Figure 3A. For example, as shown in Figure 3B, an element layer for forming an oxide semiconductor memory 106 may be stacked on an element layer for forming an oxide semiconductor arithmetic unit 105. By adopting such a configuration, the semiconductor device 100, which functions as an accelerator, can be highly integrated, and the arithmetic processing speed per unit area can be improved. This also makes it possible to miniaturize the semiconductor device 100.

[0050] Furthermore, the semiconductor device 100 described above can be configured as a semiconductor device having a CPU 110 and a bus 120, as shown in Figure 4. With this configuration, a portion of the calculations of the program executed by the CPU 110 can be performed by the semiconductor device 100, which functions as an accelerator.

[0051] The CPU 110 has the function of performing at least one general-purpose processing, such as executing an operating system, controlling data, performing various calculations, or executing a program. Here, the CPU 110 has a CPU core 200 and a backup circuit 222. The CPU core 200 corresponds to one or more CPU cores.

[0052] The CPU 110 can retain data within the CPU core 200 even if the power supply voltage is interrupted, thanks to the backup circuit 222. The power supply voltage can be controlled by electrical disconnection from the power domain using a power switch or the like. As the backup circuit 222, for example, an OS memory having an OS transistor is preferred.

[0053] Furthermore, the bus 120 electrically connects the CPU 110 and the semiconductor device 100, which functions as an accelerator. In other words, data can be transmitted between the CPU 110 and the semiconductor device 100 via the bus 120.

[0054] The detailed configurations of the CPU 110, CPU core 200, backup circuit 222, and bus 120 will be described in the embodiments described later.

[0055] As described above, one aspect of the present invention can provide a semiconductor device with reduced power consumption. Alternatively, one aspect of the present invention can provide a semiconductor device with improved processing speed. Alternatively, one aspect of the present invention can provide a semiconductor device with improved calculation accuracy. Alternatively, one aspect of the present invention can provide a miniaturized semiconductor device.

[0056] This embodiment can be appropriately combined with other embodiments shown in this specification.

[0057] (Embodiment 2) In this embodiment, some of the configurations and operations of the semiconductor device 100 shown in the previous embodiment will be described.

[0058] Figure 5A is a diagram illustrating a semiconductor device 10 according to one embodiment of the present invention. Here, the semiconductor device 10 is part of the semiconductor device 100 and has a digital arithmetic unit 101 and an oxide semiconductor memory 103 as shown in the previous embodiment.

[0059] The semiconductor device 10 functions as an accelerator, executing a program (also called a kernel or kernel program) called from a host program. The semiconductor device 10 can perform, for example, parallel processing of matrix operations in graphics processing, parallel processing of multiply-accumulate operations in neural networks, and parallel processing of floating-point operations in scientific and technical calculations.

[0060] The semiconductor device 10 includes a memory circuit section 20 (also called a memory cell array), an arithmetic circuit 30, and a switching circuit 40. Here, the arithmetic circuit 30 corresponds to the digital arithmetic unit 101 shown in the previous embodiment, and the memory circuit section 20 corresponds to the oxide semiconductor memory 103 shown in the previous embodiment. The arithmetic circuit 30 and the switching circuit 40 are provided on a layer 11 having transistors in the xy plane in the figure. The memory circuit section 20 is provided on a layer 12 having transistors in the xy plane in the figure.

[0061] Layer 11 has a transistor (Si transistor) with silicon in the channel formation region. Layer 12 has a transistor (OS transistor) with oxide semiconductor in the channel formation region. Layers 11 and 12 are provided on different layers in a direction approximately perpendicular to the xy plane (z direction in Figure 5A). Therefore, the semiconductor device 10 shown in Figure 5B has a stacked structure similar to the digital arithmetic unit 101 and oxide semiconductor memory 103 shown in Figure 2A or Figure 2B.

[0062] The memory circuit section 20, which is composed of OS transistors, can be stacked with the arithmetic circuit 30 and the switching circuit 40, which can be composed of Si transistors. In other words, the memory circuit section 20 is provided on the same substrate as the arithmetic circuit 30 and the switching circuit 40. Therefore, the memory circuit section 20 can be arranged without increasing the circuit area. By placing the area on which the memory circuit section 20 is provided on the same substrate as the arithmetic circuit 30 and the switching circuit 40, the memory capacity required for arithmetic processing in the semiconductor device 10, which functions as an accelerator, can be increased compared to the case where the memory circuit section 20, the arithmetic circuit 30, and the switching circuit 40 are provided on the same layer. By increasing the memory capacity, the number of data transfers required for arithmetic processing from the external storage device to the semiconductor device can be reduced, thereby lowering power consumption.

[0063] The memory circuit section 20 is illustrated as an example of a plurality of memory circuit sections 20_1 to 20_4. Each memory circuit section has a plurality of memory circuits 21. In each of the memory circuit sections 20_1 to 20_4, the plurality of memory circuits 21 are connected to the switching circuit 40 via wiring LBL_1 to LBL_4 (also called local bit lines or read bit lines), as shown in Figure 5A.

[0064] The memory circuit 21 can have a NOSRAM circuit configuration. "NOSRAM (registered trademark)" is an abbreviation for "Nonvolatile Oxide Semiconductor RAM". NOSRAM refers to a memory in which the memory cell is a 2-transistor type (2T) or 3-transistor type (3T) gain cell and the access transistor is an OS transistor. The memory circuit 21 is a memory composed of OS transistors. The layer 12 having the memory circuit 21 can be stacked on the layer 11 having the arithmetic circuit 30 and the switching circuit 40. Since the memory circuit section 20 having the memory circuit 21 is provided on the layer 11 having the arithmetic circuit 30 and the switching circuit 40, it is possible to reduce the area overhead caused by having the memory circuit section 20.

[0065] Furthermore, OS transistors have extremely low leakage current, meaning that the current flowing between the source and drain in the off state is very small. NOSRAM can be used as non-volatile memory by utilizing this extremely low leakage current characteristic to hold a charge corresponding to the data within the memory circuit. In particular, NOSRAM can be read without destroying the stored data (non-destructive read), making it suitable for parallel processing of multiply-accumulate operations in neural networks, which involve repeating data read operations many times.

[0066] The memory circuit 21 is preferably a memory having an OS transistor, such as NOSRAM or DOSRAM (hereinafter also referred to as OS memory). Since the band gap of the metal oxide that functions as an oxide semiconductor is 2.5 eV or more, the OS transistor has an extremely small off current. As an example, with a source-drain voltage of 3.5 V and at room temperature (25°C), the off current per 1 μm of channel width is 1 × 10⁻¹⁶. -20 Less than A, 1 x 10 -22 Less than A, or 1 × 10 -24 It can be less than A. Therefore, the amount of charge leaking from the holding node via the OS transistor in the OS memory is extremely small. Consequently, the OS memory can function as a non-volatile memory circuit, enabling power gating of the semiconductor device 10.

[0067] Semiconductor devices with high-density transistor integration can generate heat due to circuit operation. This heat can raise the temperature of the transistors, altering their characteristics and potentially causing changes in field-effect mobility or a decrease in operating frequency. OS transistors have higher thermal tolerance than Si transistors, making them less susceptible to changes in field-effect mobility due to temperature fluctuations, and also less prone to a decrease in operating frequency. Furthermore, OS transistors tend to maintain the characteristic of exponentially increasing drain current with respect to gate-source voltage even at high temperatures. Therefore, using OS transistors enables stable operation in high-temperature environments.

[0068] Metal oxides applicable to OS transistors include Zn oxide, Zn-Sn oxide, Ga-Sn oxide, In-Ga oxide, In-Zn oxide, and In-M-Zn oxide (where M is Ti, Ga, Y, Zr, La, Ce, Nd, Sn, or Hf). In particular, metal oxides using Ga as M are preferred for OS transistors because adjusting the elemental ratios can result in transistors with excellent electrical properties such as field-effect mobility. Furthermore, oxides containing indium and zinc may also contain one or more elements selected from aluminum, gallium, yttrium, copper, vanadium, beryllium, boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, and others.

[0069] To improve the reliability and electrical characteristics of OS transistors, the metal oxide applied to the semiconductor layer is preferably a metal oxide having a crystalline portion, such as CAAC-OS, CAC-OS, or nc-OS. CAAC-OS is an abbreviation for c-axis-aligned crystalline oxide semiconductor. CAC-OS is an abbreviation for Cloud-Aligned Composite oxide semiconductor. nc-OS is an abbreviation for nanocrystalline oxide semiconductor.

[0070] CAAC-OS has a c-axis orientation and a crystal structure in which multiple nanocrystals are linked in the ab-plane direction, resulting in a strained structure. Strain refers to the area where the orientation of the lattice arrangement changes between regions with aligned lattice arrangements and other regions with aligned lattice arrangements, within the region where multiple nanocrystals are linked.

[0071] CAC-OS has the function of allowing electrons (or holes) to flow as carriers and the function of not allowing electrons to flow as carriers. By separating the function of allowing electrons to flow from the function of not allowing electrons to flow, both functions can be maximized. In other words, by using CAC-OS in the channel formation region of an OS transistor, both high on-current and extremely low off-current can be achieved.

[0072] Because metal oxides have a large band gap, electrons are not easily excited, and the effective mass of holes is large, OS transistors are less prone to avalanche decay compared to general Si transistors. Therefore, for example, hot carrier degradation caused by avalanche decay can be suppressed. By suppressing hot carrier degradation, OS transistors can be driven at high drain voltages.

[0073] OS transistors are storage-type transistors that use electrons as majority carriers. Therefore, compared to inverting transistors with pn junctions (typically Si transistors), they are less affected by DIBL (Drain-Induced Barrier Lowering), one of the short-channel effects. In other words, OS transistors have higher resistance to short-channel effects than Si transistors.

[0074] OS transistors have high resistance to short-channel effects, allowing for a reduction in channel length without degrading the reliability of the OS transistor. Therefore, using OS transistors can increase the integration density of circuits. As the channel length is reduced, the drain field strength increases, but as mentioned above, OS transistors are less prone to avalanche decay than Si transistors.

[0075] Furthermore, because OS transistors have high resistance to short-channel effects, it is possible to use thicker gate insulators than Si transistors. For example, even in fine transistors with channel length and channel width of 50 nm or less, it may be possible to provide a gate insulator about 10 nm thick. By increasing the thickness of the gate insulator, parasitic capacitance can be reduced, thereby improving the operating speed of the circuit. In addition, by increasing the thickness of the gate insulator, leakage current through the gate insulator is reduced, leading to a reduction in static current consumption.

[0076] As described above, the semiconductor device 10, having a memory circuit 21 which is an OS memory, can retain data even when the power supply voltage is interrupted. Therefore, power gating of the semiconductor device 10 becomes possible, and power consumption can be significantly reduced.

[0077] The data stored in the memory circuit 21 is data corresponding to the weight parameters used in the sum-of-accumulate operation of the neural network (weight data). By using digital data for the weight data, a semiconductor device that is resistant to noise and capable of high-speed calculations can be created. Alternatively, the weight data may be analog data. Since NOSRAM can hold the potential of analog values, it can be configured to convert the data to digital data as needed. A memory circuit 21 capable of holding analog data can hold weight data with a high number of bits without increasing the number of memory circuits.

[0078] The switching circuits 40_1 to 40_4, shown as an example of the switching circuit 40, have the function of selecting the potential of the wirings LBL_1 to LBL_4 extending from each of the multiple memory circuit sections 20_1 to 20_4 and transmitting it to the wiring GBL (also called the global bit line). The output terminals of the switching circuits 40_1 to 40_4 are connected to the wiring GBL. The switching circuit 40 needs to prevent the simultaneous supply of output potentials of the selected switching circuit 40 and the unselected switching circuit 40, which would cause a shoot-through current. The switching circuit 40 can use, for example, a three-state buffer whose output potential state is controlled by a control signal. In this configuration example, the wiring GBL can avoid simultaneous supply of output potentials because the selected switching circuit buffers the input potential and the output of the unselected switching circuit becomes high impedance. It is preferable that the switching circuit 40 is composed of Si transistors. This configuration allows for high-speed switching of the connection state.

[0079] The arithmetic circuits 30_1 to 30_4, shown as examples of the arithmetic circuit 30, have the function of repeatedly performing the same operation, such as multiply-accumulate operations. The input data and weight data input for multiply-accumulate operations in the arithmetic circuit 30 are preferably digital data. Digital data is less susceptible to noise. Therefore, the arithmetic circuit 30 is suitable for performing arithmetic operations that require highly accurate calculation results. The arithmetic circuit 30 is preferably composed of Si transistors. This configuration allows it to be stacked with OS transistors.

[0080] The arithmetic circuits 30_1 to 30_4 are supplied with weight data held in the memory circuit 21 via wiring LBL_1 to LBL_4 and wiring GBL. In addition, the arithmetic circuits 30_1 to 30_4 are supplied with input data (A1, A2, A3, A4) from an external source. The arithmetic circuits 30_1 to 30_4 perform multiply-accumulate operations using the weight data held in the memory circuit 21 and the input data from an external source.

[0081] The weight data provided to the arithmetic circuits 30_1 to 30_4 is weight data selected by multiple memory circuit sections 20_1 to 20_4, switched by switching circuits 40_1 to 40_4, and provided via wiring GBL. In other words, the arithmetic circuits 30_1 to 30_4 can perform arithmetic processing using the same weight data, such as multiply-accumulate operations. Therefore, the semiconductor device 10 in one aspect of the present invention can efficiently perform processing using the same weight data, similar to a convolutional neural network.

[0082] Furthermore, the weight data provided to the arithmetic circuits 30_1 to 30_4 can be provided to the wiring GBL by switching the data previously provided to wiring LBL_1 to LBL_4 using the switching circuits 40_1 to 40_4. Therefore, the weight data provided to wiring GBL can be switched at a speed consistent with the electrical characteristics of the Si transistors. As a result, even if the time required to read the weight data from the memory circuits 20_1 to 20_4 to wiring LBL_1 to LBL_4 is long, the weight data can be switched and processed at high speed by reading the weight data to wiring LBL_1 to LBL_4 in advance.

[0083] The wiring LBL extending from the memory circuit section 20 to the switching circuit 40 is used to obtain weight data W, as shown in Figure 5B. data This is the wiring for transmitting data from layer 12 to layer 11. Weight data W is transmitted from memory circuit 21 to wiring LBL. data To enable high-speed reading, it is preferable to shorten the wiring LBL. It is also preferable to shorten the wiring LBL to reduce the energy consumption associated with charging and discharging. In other words, it is preferable to configure the switching circuit 40 to be distributed in the xy plane of layer 11 so as to be close to the wiring LBL (arrows extending in the z direction in the figure) which are provided extending in the z direction.

[0084] Furthermore, the arithmetic circuits 30_1 to 30_4 are configured to be provided for each bit line LBL_1 to LBL_4, which is the bit line for reading from the memory circuit 21, i.e., for each column (Column-Parallel Calculation). With this configuration, data equal to the number of columns of wiring LBL can be processed in parallel. Compared to multiply-accumulate operations using a CPU or GPU, Column-Parallel Calculation is not limited by the data bus size (32 bits, etc.), so the degree of parallelism of operations can be greatly increased, thereby improving the computational efficiency for massive computational processing such as training of deep neural networks (deep learning), a type of AI technology, and scientific and technical calculations that perform floating-point operations. In addition, since the calculation of data output from the arithmetic circuit 30 can be completed and read, the power generated by memory access (data transfer between the arithmetic circuit and memory, etc.) can be reduced, and the increase in heat generation and power consumption can be suppressed. Furthermore, by reducing the physical distance between the arithmetic circuit 30 and the memory circuit section 20, for example by stacking the components to shorten the wiring distance, parasitic capacitance in the signal lines can be reduced, thus enabling lower power consumption.

[0085] Next, Figure 6A describes a block diagram including a semiconductor device 10, a CPU 110, and a bus 120 that function as an AI accelerator. Note that the CPU 110 and bus 120 correspond to those shown in the previous embodiment.

[0086] Figure 6A shows the semiconductor device 10 described in Figures 5A and 5B, as well as the CPU 110 and bus 120. The CPU 110 has a CPU core 200 and a backup circuit 222. The semiconductor device 10, which functions as an accelerator, shows a drive circuit 50, memory circuit sections 20_1 to 20_N (where N is a natural number greater than or equal to 2), a memory circuit 21, a switching circuit 40, and arithmetic circuits 30_1 to 30_N.

[0087] The CPU 110 has functions for general-purpose processing, such as executing the operating system, controlling data, performing various calculations, and executing programs. The CPU 110 has a CPU core 200. The CPU core 200 corresponds to one or more CPU cores. The CPU 110 also has a backup circuit 222 that can retain data in the CPU core 200 even if the power supply voltage is interrupted. The power supply voltage can be controlled by electrical disconnection from the power domain using a power switch or the like. Note that the power supply voltage is sometimes called the drive voltage. As the backup circuit 222, for example, an OS memory having an OS transistor is preferred.

[0088] The backup circuit 222, which is composed of OS transistors, can be stacked with the CPU core 200, which can be composed of Si transistors. Since the area of ​​the backup circuit 222 is smaller than the area of ​​the CPU core 200, the backup circuit 222 can be placed on the CPU core 200 without increasing the circuit area. The backup circuit 222 has the function of holding the data of the registers of the CPU core 200. The backup circuit 222 is also called a data holding circuit. Further details of the configuration of the CPU core 200 equipped with the backup circuit 222 having OS transistors will be explained in Embodiment 5.

[0089] Memory circuit sections 20_1 to 20_N each contain weight data W1 to W held in memory circuit 21. N The selected weight data is output to the switching circuit 40 via wiring LBL (not shown). The switching circuit 40 outputs the selected weight data W via wiring GBL (not shown). SEL The output is sent to each arithmetic circuit 30_1 to 30_N. The drive circuit 50 sends input data A1 to A to the arithmetic circuits 30_1 to 30_N via the input data line. N Outputs.

[0090] The drive circuit 50 has the function of outputting signals to control the writing and reading of weight data in the memory circuit sections 20_1 to 20_N. The drive circuit 50 also has the function of providing input data to the arithmetic circuits 30_1 to 30_N to perform multiply-accumulate operations of the neural network, and holding the output data obtained from the multiply-accumulate operations of the neural network.

[0091] Bus 120 electrically connects the CPU 110 and the semiconductor device 10. In other words, data can be transmitted between the CPU 110 and the semiconductor device 10 via bus 120.

[0092] Figure 6B is a diagram illustrating the positional relationships of each component in the semiconductor device 10 shown in Figure 6A, when N is set to 6.

[0093] The memory circuit sections 20_1 to 20_6, which are composed of OS transistors, and the arithmetic circuits 30_1 to 30_6 are electrically connected via wiring LBL_1 to LBL_6, which are provided in a direction approximately perpendicular to the substrate surface on which the drive circuit 50, switching circuit 40, and arithmetic circuits 30_1 to 30_6 are located. "Approximately perpendicular" refers to a state in which the components are arranged at an angle of 85 degrees or more and 95 degrees or less. In this specification, the X, Y, and Z directions shown in Figure 6B, etc., are directions that are orthogonal to or intersect with each other. Furthermore, the X and Y directions are parallel or approximately parallel to the substrate surface, and the Z direction is perpendicular or approximately perpendicular to the substrate surface.

[0094] Each of the memory circuit sections 20_1 to 20_6 has a memory circuit 21. The memory circuit sections 20_1 to 20_6 may be referred to as device memory or shared memory. The memory circuit 21 has a transistor 22. By making the semiconductor layer 23 of the transistor 22 an oxide semiconductor (metal oxide), the memory circuit 21 can be composed of the OS transistors described above.

[0095] Each of the plurality of memory circuits 21 included in the memory circuit units 20_1 to 20_6 is connected to wiring LBL_1 to LBL_6. The wiring LBL_1 to LBL_6 is connected to the switching circuit 40 via wiring extending in the z direction. The switching circuit 40 is configured to amplify the potential of any one of the wiring LBL_1 to LBL_6 and transmit it to the wiring GBL. By adopting such a configuration, the weight data applied to the wiring GBL can be switched at high speed by controlling the switching circuit 40.

[0096] The arithmetic circuits 30_1 to 30_6 perform arithmetic operations based on the weight data input via the wiring GBL and the input data A given from the drive circuit 50 via the input data line. IN Since the memory circuit units 20_1 to 20_6 that hold the weight data can be arranged on the upper layer, the arithmetic circuits 30_1 to 30_6 can be arranged efficiently. Therefore, the input data lines extending from the drive circuit 50 can be shortened, and the semiconductor device 10 can be made to consume less power and operate at higher speed.

[0097] Next, the advantages of adopting the configuration of FIG. 6B will be described. In FIG. 7A, for the sake of explanation, each configuration of FIG. 6B is shown in a block diagram. It is assumed that weight data W1 to W6 are read from the memory circuits 21 in the six memory circuit units 20_1 to 20_6 to the wiring LBL_1 to LBL_6. The switching circuit 40 will be described as switching circuits 40_1 to 40_6 connected to the wiring LBL_1 to LBL_6. The weight data selected from the weight data W1 to W6 by the switching circuit 40 and applied to the wiring GBL will be described as weight data W. SEL It is assumed that input data A1 to A6 are given to the arithmetic circuits 30_1 to 30_6, and output data MAC1 to MAC6 are obtained.

[0098] Wiring LBL extending in the vertical direction connecting the upper and lower layers in the wiring LBL_1 to LBL_6 PThese wires are shorter than horizontally extending wires. Therefore, the parasitic capacitance of wires LBL_1 to LBL_6 can be reduced, the charge required for charging and discharging the wires can be reduced, and power consumption can be lowered and computational efficiency can be improved. In addition, reading from the memory circuit 21 to wires LBL_1 to LBL_6 can be done at high speed.

[0099] Through the GBL wiring, the arithmetic circuits 30_1 to 30_6 can perform calculations using the same weight data. This configuration is suitable for the calculations of a convolutional neural network that performs calculations using the same weight data.

[0100] Figure 7B shows an example of a circuit configuration applicable to the switching circuit 40 shown in Figure 7A. The three-state buffer shown in Figure 7B has the function of amplifying and transmitting the potential of wiring LBL to wiring GBL according to the control signal EN. The switching circuit 40 can be considered a multiplexer. It has the function of selecting one from multiple input signals.

[0101] Figure 8 shows a timing chart illustrating the operation of the configuration described in Figure 7A. The semiconductor device 10 performs calculation processing in accordance with the toggle operation of the clock signal CLK (for example, from time T1 to T7). By increasing the frequency of the clock signal CLK, the calculation processing speed can be increased.

[0102] When input data A1 to A6 are rapidly switched according to the clock signal CLK as shown in the diagram, A1a to A111, A2a to A211, A3a to A311, A4a to A411, A5a to A511, and A6a to A611, it is necessary to rapidly switch the data of the wiring GBL that provides the weight data.

[0103] In one embodiment of the present invention, the weight data to be selected from wiring LBL to wiring GBL by the switching circuit 40 is pre-read into wiring LBL_1 to LBL_6, thereby enabling high-speed switching of the data of the wiring GBL that provides the weight data. For example, weight data W1 can be read into wiring LBL_1 at time T1, and the switching circuit 40 can be switched at time T6 to output weight data W1 from wiring LBL_1 to wiring GBL. At times T2 to T7, and after time T7, the timing of reading the weight data to wiring LBL and selecting the weight data in wiring GBL can be made different, thereby enabling switching of weight data in accordance with the clock signal CLK.

[0104] Figure 9A shows a specific example of the arithmetic circuit configuration. Figure 9A illustrates an example of the configuration of an arithmetic circuit 30 that can perform a multiply-accumulate operation on input data of 8-bit weight data. In Figure 9A, a multiplier circuit 24, an adder circuit 25, and a register 26 are shown. The 16-bit data multiplied by the multiplier circuit 24 is input to the adder circuit 25. The output of the adder circuit 25 is held in the register 26, and the data multiplied by the multiplier circuit 24 and the adder circuit 25 are added together to perform the multiply-accumulate operation. The register is controlled by the clock signal CLK and the reset signal reset_B. In the figure, "α" in "17+α" indicates the carry-over that occurs when the multiplied data is added. With this configuration, the weight data W SEL and input data A IN This allows you to obtain MAC, which is an output data equivalent to a sum-of-products operation.

[0105] Furthermore, although Figure 9A describes a configuration that performs arithmetic processing using 8 bits of data, one aspect of the present invention is also applicable to a configuration that uses 1 bit of data. This configuration is illustrated in Figure 9B, similar to Figure 9A. In the case of 1 bit of data, arithmetic processing should be performed according to the number of bits, as shown in Figure 9B.

[0106] Figure 10A illustrates an example of a circuit configuration applicable to the memory circuit section 20 of the semiconductor device 10 of the present invention. Figure 10A shows write word lines WWL_1 to WWL_M, read word lines RWL_1 to RWL_M, write bit lines WBL_1 to WBL_N, and wiring LBL_1 to LBL_N arranged in a matrix of M rows and N columns (M and N are natural numbers of 2 or more). The memory circuit 21 connected to each word line and bit line is also shown.

[0107] Figure 10B illustrates an example of a circuit configuration applicable to the memory circuit 21. The memory circuit 21 includes transistors 61, 62, 63, and a capacitive element 64 (also called a capacitor).

[0108] One of the sources or drains of transistor 61 is connected to the write bit line WBL. The gate of transistor 61 is connected to the write word line WWL. The other of the sources or drains of transistor 61 is connected to one electrode of the capacitive element 64 and the gate of transistor 62. One of the sources or drains of transistor 62 and the other electrode of the capacitive element 64 are connected to a wire that provides a fixed potential, such as ground potential. The other of the sources or drains of transistor 62 is connected to one of the sources or drains of transistor 63. The gate of transistor 63 is connected to the read word line RWL. The other of the sources or drains of transistor 63 is connected to the wire LBL. The wire LBL is connected to the wire GBL via the switching circuit 40. The wire LBL is connected to the switching circuit 40 via a wire that extends in a direction approximately perpendicular to the substrate surface on which the arithmetic circuit 30 is provided, as described above.

[0109] The circuit configuration of the memory circuit 21 shown in Figure 10B corresponds to a 3-transistor (3T) gain cell NOSRAM. Transistors 61 to 63 are OS transistors. OS transistors have an extremely small current flowing between their source and drain when off, i.e., a leakage current. NOSRAM can be used as a non-volatile memory by using this extremely low leakage current characteristic to hold a charge corresponding to the data within the memory circuit.

[0110] The circuit configuration applicable to the memory circuit 21 in Figure 10A is not limited to the 3T type NOSRAM in Figure 10B. For example, a circuit equivalent to the DOSRAM shown in Figure 11A may also be used. Figure 11A illustrates a memory circuit 21A having a transistor 61A and a capacitive element 64A. Transistor 61A is an OS transistor. The memory circuit 21A is illustrated in an example where it is connected to the bit line BL, word line WL, and back gate line BGL.

[0111] The circuit configuration applicable to the memory circuit 21 in Figure 10A may also be a circuit corresponding to the 2T type NOSRAM shown in Figure 11B. Figure 11B illustrates the memory circuit 21B having transistors 61B, 62B and capacitive element 64B. Transistors 61B and 62B are OS transistors. Transistors 61B and 62B may be OS transistors with semiconductor layers arranged on different layers, or they may be OS transistors with semiconductor layers arranged on the same layer. The memory circuit 21B illustrates an example where it is connected to a write bit line WBL, a read bit line RBL, a write word line WWL, a read word line RWL, a source line SL and a back gate line BGL.

[0112] A circuit configuration applicable to the memory circuit 21 in Figure 10A may also be a circuit combining the 3T type NOSRAM shown in Figure 11C. Figure 11C illustrates a memory circuit 21C having a memory circuit 21_P and a memory circuit 21_N that can hold data of different logics. Figure 11C also illustrates a memory circuit 21_P having transistors 61_P, 62_P, 63_P and a capacitive element 64_P, and a memory circuit 21_N having transistors 61_N, 62_N, 63_N and a capacitive element 64_N. Each transistor in memory circuits 21_P and 21_N is an OS transistor. Each transistor in memory circuits 21_P and 21_N may be an OS transistor with semiconductor layers arranged on different layers, or it may be an OS transistor with semiconductor layers arranged on the same layer. The memory circuit 21C is shown in an example where it is connected to the write bit line WBL_P, wiring LBL_P, write bit line WBL_N, wiring LBL_N, write word line WWL, and read word line RWL. The memory circuit 21C can hold data with different logic, read data with different logic to wiring LBL_P and wiring LBL_N, and output it to wiring GBL_P and wiring GBL_N via the switching circuit 40, as in Figure 7.

[0113] In the configuration shown in Figure 11C, an exclusive OR (XOR) circuit may be provided so that data equivalent to the multiplication of the data held in memory circuit 21_P and memory circuit 21_N is output to wiring LBL. By adopting this configuration, the operation equivalent to multiplication in the arithmetic circuit 30 can be omitted, thereby reducing power consumption.

[0114] Figure 12 illustrates the computational flow of a convolutional neural network. Figure 12 shows the input layer 90A, the hidden layer 90B (also called the hidden layer), and the output layer 90C. The input layer 90A shows the input processing of the input data 91 (shown as "Input" in the figure). The hidden layer 90B shows the convolutional operations 92, 93, and 95 (shown as "Conv." in the figure), and multiple pooling operations 94 and 96 (shown as "Pool." in the figure). The output layer 90C shows the fully connected operation 97 (shown as "Full" in the figure). The computational flow in the input layer 90A, hidden layer 90B, and output layer 90C is just one example, and in actual convolutional neural network computations, other operations such as softmax operations may be performed.

[0115] In the convolutional neural network shown in Figure 12, multiple convolution operations 92, 93, and 95 are performed, as shown in Figure 12. In the convolution operations, the same weight data is used for the calculations. Therefore, by applying the configuration of one embodiment of this implementation, which performs calculations using the same weight data, it is possible to achieve both high operating speed and low power consumption.

[0116] Furthermore, as shown in the previous embodiment, it is preferable to perform the fully connected arithmetic processing 97 using the analog arithmetic unit 102 and the oxide semiconductor memory 104. Since the analog arithmetic unit 102 and the oxide semiconductor memory 104 can be driven in the subthreshold region, power consumption can be reduced.

[0117] Next, a detailed block diagram of the semiconductor device 10 is shown in Figure 13.

[0118] Figure 13 shows the configurations corresponding to the memory circuit section 20, memory circuit 21, arithmetic circuit 30, switching circuit 40, layer 11, and layer 12, as described in Figures 5A and 5B, and Figures 6A and 6B, as well as an example of the configuration of the drive circuit 50 shown in Figures 6A and 6B.

[0119] Figure 13 shows the controller 71, row decoder 72, word line driver 73, column decoder 74, write driver 75, precharge circuit 76, input / output buffer 81, and arithmetic control circuit 82, corresponding to the drive circuit 50 described in Figures 6A and 6B.

[0120] Figure 14A is a diagram showing the blocks that control the memory circuit section 20 for each configuration shown in Figure 13. In Figure 14A, the controller 71, row decoder 72, word line driver 73, column decoder 74, write driver 75, and precharge circuit 76 are shown separately.

[0121] The controller 71 processes external input signals to generate control signals for the row decoder 72 and column decoder 74. The external input signals are control signals for controlling the memory circuit section 20, such as write enable signals and read enable signals. The controller 71 also handles data input and output between the CPU 110 and the semiconductor device 10 via the bus 120.

[0122] The row decoder 72 generates a signal to drive the word line driver 73. The word line driver 73 generates signals to be supplied to the write word line WWL and the read word line RWL. The column decoder 74 generates a signal to drive the write driver 75. The write driver 75 generates weight data to be supplied to the memory circuit 21. The precharge circuit 76 has the function of precharging the wiring LBL, etc. The signals corresponding to the weight data read from the memory circuit 21 of the memory circuit section 20 are input to the switching circuit 40 via the wiring LBL, as explained in Figures 6A and 6B, etc.

[0123] Figure 14B is a diagram showing the blocks that control the arithmetic circuit 30 and the switching circuit 40 for each configuration shown in Figure 13.

[0124] The controller 71 processes external input signals and generates control signals for the arithmetic control circuit 82. The controller 71 also generates various signals such as address signals and clock signals for controlling the arithmetic circuit 30. The arithmetic control circuit 82 receives input data A1 to A1 on the data input line in accordance with the control of the controller 71 and the output of the input / output buffer 81. N The arithmetic control circuit 82 outputs a control signal to control the switching circuit 40. As explained in Figures 6A and 6B, the switching circuit 40 provides one of the weight data given by multiple wiring LBLs to multiple arithmetic circuits 30 via wiring GBL. The arithmetic circuits 30 generate output data MAC corresponding to the sum-of-accumulate operation by switching the given weight data and input data. The generated output data MAC is temporarily held as intermediate data in memory such as SRAM or registers in the arithmetic control circuit 82 via the input / output buffer 81. The held intermediate data is re-input to the arithmetic circuits 30.

[0125] In one aspect of the present invention, the semiconductor device 10 is preferably configured to be used in combination with multiple devices in order to enable parallel computing with a higher number of parallel connections. An example of this configuration will be explained with reference to Figures 15A and 15B.

[0126] Figure 15A illustrates a configuration corresponding to the semiconductor device 10 described above, showing a controller 71G that performs data input / output and control between semiconductor devices 10_1 to 10_n (where n is a number of 2 or more) and semiconductor devices 10_1 to 10_n. The controller 71G has a memory circuit 60 such as SRAM internally. The controller 71G stores the output data MAC obtained from the multiple semiconductor devices 10_1 to 10_n in the memory circuit 60. The controller 71G then uses the output data MAC stored in the memory circuit 60 to input data A from the multiple semiconductor devices 10_1 to 10_n. IN The configuration will output in this way. This configuration will enable parallel computing with a high degree of parallelism using multiple semiconductor devices.

[0127] Furthermore, in Figure 15B, which is a different configuration example from Figure 15A, the controller 71G applies another calculation process to the output data held in the memory circuit 60, and the resulting input data is used as input data A in multiple semiconductor devices 10_1 to 10_n. IN _1 to A IN The configuration is such that _n is output. In this configuration, for example, the controller 71G performs arithmetic processing based on the activation function, pooling processing, and normalization processing on the output data held in the memory circuit 60. This configuration allows for parallel computing with a high degree of parallelism using multiple semiconductor devices, as well as efficient processing of arithmetic operations other than convolution.

[0128] In the semiconductor device 10, the buffer memory in the input / output buffer 81 is used to input output data MAC, corresponding to the calculation result of the arithmetic circuit 30, as intermediate data to the arithmetic control circuit 82. The arithmetic control circuit 82 can output this intermediate data again as input data to the arithmetic circuit 30. Therefore, calculation processing can be performed without reading the data during the calculation to a main memory or other external location outside the semiconductor device 10. In addition, in the semiconductor device 10, the electrical connection between the memory circuit and the arithmetic circuit can be made via wiring through openings provided in an insulating film, etc., so the number of parallel connections can be increased by increasing the number of wires. Therefore, the semiconductor device 10 can perform parallel calculations with a number of bits exceeding the data bus width of the CPU 110. Furthermore, since the number of times a huge amount of weight data is transferred between the CPU 110 and the semiconductor device can be reduced, power consumption can be reduced.

[0129] As described above, one aspect of the present invention can provide a semiconductor device that functions as an accelerator and is miniaturized. Alternatively, one aspect of the present invention can provide a semiconductor device that functions as an accelerator and has improved arithmetic processing speed. Alternatively, one aspect of the present invention can provide a semiconductor device that functions as an accelerator and has improved arithmetic accuracy. Alternatively, one aspect of the present invention can provide a semiconductor device that functions as an accelerator and has reduced power consumption. Alternatively, a semiconductor device that functions as an accelerator with a novel configuration can be provided.

[0130] This embodiment can be appropriately combined with other embodiments shown in this specification.

[0131] (Embodiment 3) This embodiment describes some of the configurations and operations of the semiconductor device 100 shown in the previous embodiment. The semiconductor device shown in this embodiment is a part of the semiconductor device 100 and has an analog arithmetic unit 102 and an oxide semiconductor memory 104 as shown in the previous embodiment.

[0132] <Example Configuration> Figures 16A and 16B show an example configuration of a multiplication cell, which is a semiconductor device according to one aspect of the present invention. This multiplication cell, for example, is configured to perform multiplication using the translinear principle. Furthermore, this multiplication cell, for example, has the function of holding first data, and also has the function of outputting the product of the first data and the second data when second data is input to it. Here, the first data corresponds to the weight data W2 shown in Figure 1B, and the second data corresponds to the input data A2 shown in Figure 1B.

[0133] The circuit MC shown in Figure 16A has transistors M1 to M10, capacitor C1, and capacitor CG. The circuit MC can be functionally divided into circuit MC1, which has transistors M5 to M10, and circuit MC2, which has transistors M1 to M4 and capacitor C1. Here, circuit MC1 corresponds to the analog arithmetic unit 102 shown in the previous embodiment, and circuit MC2 corresponds to the oxide semiconductor memory 104 shown in the previous embodiment.

[0134] Circuits MC1 and MC2 can be provided on the same layer, similar to the analog arithmetic unit 102 and oxide semiconductor memory 104 shown in Figures 2A and 2B. Although Figures 2A and 2B show the regions of the analog arithmetic unit 102 and the oxide semiconductor memory 104 separately, the system is not limited to this, and a single circuit MC, which combines circuits MC1 and MC2, may be provided in an array.

[0135] When the circuit MC is arranged in an array, as shown in Figure 16B, circuit MC1 may be provided on layer MCL1 which has transistors in the xy plane in the figure, and circuit MC2 may be provided on layer MCL2 which also has transistors in the xy plane in the figure. Layers MCL1 and MCL2 have transistors (OS transistors) with oxide semiconductors in the channel formation region. Layers MCL1 and MCL2 are provided on different layers in a direction approximately perpendicular to the xy plane (z direction in Figure 16B). With this configuration, as shown in Figure 16B, the wiring that transmits weight data W2 from circuit MC2 to circuit MC1 can be shortened. This makes it possible to speed up the reading of weight data W2 and reduce the power consumption associated with reading.

[0136] Transistors M1 to M10 can be, for example, OS transistors. In particular, the metal oxide included in the channel formation region of the OS transistor is preferably, for example, In-M-Zn oxide having indium, element M, and zinc (element M is one or more selected from aluminum, gallium, yttrium, tin, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, or magnesium). Alternatively, transistors M1 to M10 may be, for example, transistors having silicon in the channel formation region (Si transistors). As for silicon, for example, single-crystal silicon, amorphous silicon (sometimes called hydrogenated amorphous silicon), microcrystalline silicon, or polycrystalline silicon can be used. In addition to OS transistors and Si transistors, other types of transistors that can be used include those in which Ge is included in the channel formation region, those in which compound semiconductors such as ZnSe, CdS, GaAs, InP, GaN, and SiGe are included in the channel formation region, those in which carbon nanotubes are included in the channel formation region, and those in which organic semiconductors are included in the channel formation region.

[0137] Unless otherwise specified, each of transistors M1, M3, and M4 may function as a switching element, for example. That is, the gate, source, and drain of each of these transistors may be appropriately supplied with voltages within the range in which they operate as switching elements. However, one aspect of the present invention is not limited thereto. For example, at least one of these transistors may operate in the saturation region or the linear region when turned on. Or, at least one of transistors M1, M3, and M4 may operate in the subthreshold region to reduce the amount of current flowing through these transistors. Or, at least one of transistors M1, M3, and M4 may operate in a combination of the linear region, the saturation region, and the subthreshold region. Alternatively, at least one of transistors M1, M3, and M4 may operate in a combination of linear and saturated regions, or in a combination of saturated and subthreshold regions, or in a combination of linear and subthreshold regions.

[0138] In this specification, the saturation region refers to the region where the gate-source voltage is greater than the threshold voltage, and the difference between the gate-source voltage and the threshold voltage is greater than the source-drain voltage. Alternatively, the saturation region refers to the region where the drain current of the transistor remains almost unchanged even when the source-drain voltage is changed. Alternatively, the saturation region refers to the region where the drain current is proportional to the square of the gate-source voltage. Alternatively, the saturation region includes regions that can be considered as each of the regions described above.

[0139] Furthermore, in this specification, the linear region refers to the region where the gate-source voltage is greater than the threshold voltage, and the difference between the gate-source voltage and the threshold voltage is less than the source-drain voltage. Alternatively, the linear region refers to the region where the channel formation region acts as a resistor, and the drain current of the transistor changes linearly with respect to the change in the source-drain voltage. Alternatively, the linear region includes regions that can be considered as each of the regions described above.

[0140] Furthermore, in this specification, the subthreshold region refers to the region in a graph showing the gate voltage (Vg)-drain current (Id) characteristics of a transistor where the gate voltage is lower than the threshold voltage. Alternatively, the subthreshold region refers to the region where current flows due to carrier diffusion, deviating from the gradient dual-channel approximation (a model that only considers drift current). Alternatively, the subthreshold region refers to the region where the drain current increases exponentially with increasing gate voltage. Alternatively, the subthreshold region includes regions that can be considered as the regions described in each of the above explanations.

[0141] Furthermore, the drain current when a transistor operates in the subthreshold region is called the subthreshold current. The subthreshold current increases exponentially with respect to the gate voltage, regardless of the drain voltage. Circuit operation using the subthreshold current can reduce the effects of variations in drain voltage.

[0142] OS transistor is 1 × 10 -20 Less than A, 1 x 10 -22 Less than A, or 1 × 10 -24 It has a drain current per 1 μm of channel width of less than A. Furthermore, the OS transistor has a threshold voltage of 1.0 × 10⁻¹⁰ -8 A or less, 1.0×10 -12 A or less, or 1.0 × 10 -15A drain current of less than A per 1 μm channel width flows. In other words, OS transistors can have a wide range of gate voltages in which they operate in the subthreshold region. Specifically, the threshold voltage of the OS transistor is V th In that case, in the subthreshold region, V th -1.0V or more V th The following, or V th -0.5V or more V th The circuit can be operated using gate voltages within the following voltage range.

[0143] On the other hand, Si transistors have a large off-current and a narrow gate voltage range in which they operate in the subthreshold region. When utilizing the subthreshold current, OS transistors can operate in a wider gate voltage range than Si transistors. By driving OS transistors in the subthreshold region with low current values, the power consumption of the circuit motor can be reduced.

[0144] In this specification, the off-region of a transistor refers to the region where the gate-source voltage is lower than the subthreshold voltage. When the gate-source voltage of a transistor is in the off-region, the transistor is considered to be in the off state. In this specification, the current that flows when a transistor is in the off state is referred to as the off-current or leakage current.

[0145] Furthermore, unless otherwise specified, each of transistors M2, M5 through M10 shall include operating in the subthreshold region.

[0146] The first terminal of transistor M1 is electrically connected to wiring VDE, the second terminal of transistor M1 is electrically connected to the first terminal of transistor M2, and the gate of transistor M1 is electrically connected to wiring WWLB and the first terminal of capacitor CG. The first terminal of transistor M3 is electrically connected to wiring WDL, and the second terminal of transistor M3 is electrically connected to the gate of transistor M2, the second terminal of capacitor CG, and the first terminal of capacitor C1. The second terminal of transistor M2 is electrically connected to the first terminal of transistor M4, the second terminal of capacitor C1, the gate of transistor M5, the first terminal of transistor M7, and the gate of transistor M8. The second terminal of transistor M4 is electrically connected to wiring VGE, and the gate of transistor M4 is electrically connected to wiring WWL. The first terminal of transistor M5 is electrically connected to wiring VDE, and the second terminal of transistor M5 is electrically connected to the first terminal of transistor M6 and the gate of transistor M7. The gate of transistor M6 is electrically connected to wiring XDL, and the second terminal of transistor M6 is electrically connected to wiring VGE. The second terminal of transistor M7 is also electrically connected to wiring VGE. The first terminal of transistor M8 is electrically connected to wiring VDE, and the second terminal of transistor M8 is electrically connected to the first terminal of transistor M9 and the gate of transistor M10. The gate of transistor M9 is electrically connected to wiring BDL, and the second terminal of transistor M9 is electrically connected to wiring VGE. The first terminal of transistor M10 is electrically connected to wiring OL, and the second terminal of transistor M10 is electrically connected to wiring VGE.

[0147] Wiring VDE functions, for example, as wiring that provides a constant voltage. This constant voltage can be, for example, a high power supply voltage.

[0148] The VGE wiring, for example, functions as wiring that provides a constant voltage. This constant voltage can be, for example, a low power supply voltage or ground potential.

[0149] Wiring WWL, for example, functions as a write signal line for writing the first data to circuit MC.

[0150] Wiring WWLB functions, for example, as wiring that transmits an inverted signal to the write signal sent to wiring WWL. Alternatively, wiring WWLB may supply a variable potential (e.g., high-level potential, low-level potential, etc.) instead of the inverted signal.

[0151] Wiring WDL functions, for example, as a write data line for writing a voltage corresponding to the first data to the circuit MC.

[0152] Wiring XDL, for example, functions as a signal line for inputting a voltage corresponding to the second data to the circuit MC.

[0153] Therefore, transistor M6, which has a gate electrically connected to wiring XDL, functions as a current source. Also, as mentioned above, transistor M6 operates in the subthreshold region, so a current in the subthreshold region flows between the first and second terminals of transistor M6.

[0154] Wiring BDL functions, for example, as a signal line that inputs a voltage to the circuit MC to adjust the amount of current according to the calculation result between the first data and the second data.

[0155] Therefore, transistor M9, which has a gate electrically connected to wiring BDL, functions as a current source. Also, as mentioned above, transistor M9 operates in the subthreshold region, so a current in the subthreshold region flows between the first and second terminals of transistor M9.

[0156] The amount of current flowing through transistor M9 can be, for example, a variable or constant applied to a circuit that performs calculations according to the function system included in the ACTV circuit described later.

[0157] For example, the wiring OL functions as a wire for outputting a current corresponding to the product of the first data and the second data.

[0158] <Example of operation> Next, an example of the operation of the circuit MC in Figure 16A will be described. In this example, the potential supplied by wiring VDE is defined as the high power supply potential, and the potential supplied by wiring VGE is defined as the ground potential (V GND )

[0159] <<Writing operation>> First, let's describe an example of the operation of writing the first data to the circuit MC.

[0160] A high-level potential is input to the wiring WWL. As a result, this high-level potential is input to the gates of transistors M3 and M4, causing both transistors M3 and M4 to turn on.

[0161] At this time, a conduction occurs between the wiring VGE and the second terminal of capacitor C1 (the second terminal of transistor M2) via transistor M4, so the potential of the second terminal of capacitor C1 (the second terminal of transistor M2) is V GND This is the result.

[0162] At this time, conduction occurs between the wiring WDL and the first terminal of capacitor C1 (the second terminal of capacitor CG, the gate of transistor M2, etc.) via transistor M3. Here, a signal corresponding to the first data (hereinafter referred to as voltage V) is sent to the wiring WDL. W By sending this, a voltage V corresponding to the first data is transmitted to the first terminal of capacitor C1 (the second terminal of capacitor CG, the gate of transistor M2, etc.). W This will be written.

[0163] Furthermore, the inverted signal of the signal transmitted to the wiring WWL is input to the WWLB wiring. Specifically, a low-level potential is input to the WWLB wiring. As a result, this low-level potential is applied to the gate of transistor M1 (the first terminal of the capacitor CG). This causes transistor M1 to turn off.

[0164] A voltage V is applied to the first terminal of capacitor C1 (the second terminal of capacitor CG, the gate of transistor M2, etc.). W After the code is written, a low-level potential is input to the WWL wiring. As a result, the gates of transistors M3 and M4 are each input this low-level potential, causing transistors M3 and M4 to turn off. Also, as a result, the first terminal of capacitor C1 becomes floating, and the voltage between the first and second terminals of capacitor C1 V W -V GND It is retained.

[0165] More precisely, when the potential applied to the gate of transistor M3 changes from a high-level potential to a low-level potential, the voltage V written to the first terminal of capacitor C1 is affected by the parasitic capacitance between the gate and the second terminal of transistor M3. W The voltage may drop. For convenience, in this specification, the voltage V is determined by the parasitic capacitance between the gate and the second terminal of transistor M3. W The voltage stepped down from can also be considered a voltage corresponding to the first data. In the circuit MC of Figure 16A, the voltage V WTo prevent voltage drop, a capacitance CG is provided. When the potential supplied to the gate of transistor M3 changes from a high-level potential to a low-level potential, that is, when the potential supplied by wiring WWL changes from a high-level potential to a low-level potential, the inverted signal of the signal transmitted to wiring WWL is input to wiring WWLB, so the potential of wiring WWLB changes from a low-level potential to a high-level potential. At this time, the potential of the first terminal of capacitance CG increases from a low-level potential to a high-level potential, so the potential of the second terminal of capacitance CG (the first terminal of capacitance C1, the gate of transistor M2, etc.) is ideally boosted by the potential difference between the high-level potential and the low-level potential due to the capacitive coupling of capacitance CG. Here, the potential difference to be boosted is the voltage V due to the parasitic capacitance between the gate and the second terminal of transistor M3. W By making it equal to the stepped-down potential difference, the voltage V when transistor M3 is turned off is obtained. W This prevents voltage drop. The configuration of the capacitor CG to make the potential difference boosted by the capacitive coupling of the capacitor CG equal to the potential difference stepped down by the parasitic capacitance between the gate and the second terminal of transistor M3 will be described later.

[0166] Alternatively, at this time, instead of supplying an inverted signal of the signal transmitted to wiring WWL to wiring WWLB, a low-level potential may be supplied to turn off transistor M1. This allows for the simultaneous retention of the first data to circuit MC and the cessation of the supply of a high power potential to the first terminal of transistor M2.

[0167] <<Multiplication operation>> Next, we will explain an example of the multiplication operation between the first data and the second data in the MC circuit.

[0168] When a high-level potential is input to the wiring WWLB, transistor M1 turns on, and a high power supply potential is input to the first terminal of transistor M2. A current flows between the first and second terminals of transistor M2, corresponding to the voltage between the gate and second terminal of transistor M2. Here, the amount of current flowing between the first and second terminals of transistor M2 is I WLet's assume that transistor M2 operates in the subthreshold region, W This represents the amount of current in the current range within the subthreshold region.

[0169] Furthermore, the current flowing between the first and second terminals of transistor M2 flows through transistor M7 to wiring VGE. Here, assuming that transistor M7 also operates in the subthreshold region, the current I flows between the first and second terminals of transistor M7. W Assume that a current of I flows. In this case, the current I W This can be expressed by the following formula.

[0170]

number

[0171] Note V M7gs This is the voltage between the gate and the second terminal of transistor M7. Also, I0 is V M7gs This is the current value that flows when is 0, and is determined by the threshold voltage of transistor M7, temperature, device structure, etc. J is a correction coefficient determined by temperature, device structure, etc.

[0172] Additionally, V is set as the voltage corresponding to the second data in the wiring XDL. X Assume that the following is input. At this time, the voltage between the gate and the second terminal of transistor M6 is V X -V GND Therefore, between the first and second terminals of transistor M6, V X -V GND A current flows accordingly. Also, here, the amount of current flowing between the first and second terminals of transistor M6 is I X Let's assume that transistor M6 operates in the subthreshold region, X This represents the amount of current in the current range within the subthreshold region.

[0173] Furthermore, the current flowing between the first and second terminals of transistor M6 is the current flowing from the wiring VDE through transistor M5 to the first terminal of transistor M6. Here, assuming that transistor M5 also operates in the subthreshold region, the current I flows between the first and second terminals of transistor M5. X Assume that a current of I flows. In this case, the current I X This can be expressed by the following formula.

[0174]

number

[0175] Note V M5gs This is the voltage between the gate and the second terminal of transistor M5. Also, I0 is V M5gs This is the current value that flows when is 0, and is determined by the threshold voltage of transistor M5, temperature, device structure, etc. J is a correction coefficient determined by temperature, device structure, etc. Note that I0 and J used in equation (1.2) are the same as I0 and J used in equation (1.1).

[0176] Additionally, V is used as the voltage to adjust the output current in the wiring BDL. B Assume that the input is V. At this time, the voltage between the gate and the second terminal of transistor M9 is V B -V GND Therefore, between the first and second terminals of transistor M9, V B -V GND A current flows accordingly. Also, here, the amount of current flowing between the first and second terminals of transistor M9 is I B This is the case. Furthermore, if transistor M9 operates in the subthreshold region, I B This represents the amount of current in the current range within the subthreshold region.

[0177] Furthermore, the current flowing between the first and second terminals of transistor M9 is the current flowing from the wiring VDE through transistor M8 to the first terminal of transistor M9. Here, assuming that transistor M8 also operates in the subthreshold region, the current I flows between the first and second terminals of transistor M8. B Assume that a current of I flows. In this case, the current I B This can be expressed by the following formula.

[0178]

number

[0179] Note V M8gs This is the voltage between the gate and the second terminal of transistor M8. Also, I0 is V M8gs This is the current value that flows when is 0, and is determined by the threshold voltage of transistor M8, temperature, device structure, etc. J is a correction coefficient determined by temperature, device structure, etc. Note that I0 and J used in equation (1.3) are the same as I0 and J used in equations (1.1) and (1.2).

[0180] Furthermore, the current flowing between the first and second terminals of transistor M10 is determined according to the voltage between the gate and the second terminal of transistor M10. Y In this case, the current I Y This can be expressed by the following formula.

[0181]

number

[0182] Note V M10gs This is the voltage between the gate and the second terminal of transistor M10. Also, I0 is V M10gsThis is the current value that flows when is 0, and is determined by the threshold voltage of transistor M10, temperature, device structure, etc. J is a correction coefficient determined by temperature, device structure, etc. Note that I0 and J used in equation (1.4) are the same as I0 and J used in equations (1.1) through (1.3).

[0183] Here, consider a closed circuit in the following order: wiring VGE, second terminal of transistor M7, gate of transistor M7, second terminal of transistor M5, gate of transistor M5, gate of transistor M8, second terminal of transistor M8, gate of transistor M10, second terminal of transistor M10, wiring VGE. In this closed circuit, according to Kirchhoff's second law (voltage law), the following equation holds:

[0184]

number

[0185] Furthermore, by rewriting each voltage term in equation (1.5) using equations (1.1) to (1.4), the following equation is obtained.

[0186]

number

[0187] In other words, the current I flowing between the first and second terminals of transistor M10 Y is, I W and I X It can be expressed as the product of . Therefore, the current I flowing from wiring OL Y By measuring I W and I X A value corresponding to the product of can be calculated.

[0188] The configuration of the multiplication cell included in one embodiment of the present invention is not limited to the circuit MC shown in Figure 16A. Depending on the circumstances, the multiplication cell included in one embodiment of the present invention can have a configuration that modifies the circuit MC shown in Figure 16A.

[0189] Furthermore, the transistors M1 to M10 shown in Figure 16A are, for example, n-channel transistors with gates above and below the channel, and each of the transistors M1 to M10 has a first gate and a second gate. However, in this specification, for convenience, the first gate is sometimes referred to as the gate (or front gate) and the second gate as the back gate, but the first gate and the second gate can be interchanged. Therefore, in this specification, the term "gate" can be replaced with the term "back gate." Similarly, the term "back gate" can be replaced with the term "gate." For example, the connection configuration "the gate is electrically connected to the first wiring and the back gate is electrically connected to the second wiring" can be replaced with the connection configuration "the back gate is electrically connected to the first wiring and the gate is electrically connected to the second wiring."

[0190] Furthermore, a semiconductor device according to one aspect of the present invention does not depend on the connection configuration of the transistor's back gate. Transistors M1 to M10 shown in Figure 16A have back gates, and although the connection configuration of the back gate is not shown, the electrical connection destination of the back gate can be determined at the design stage. For example, in a transistor having a back gate, the gate and the back gate may be electrically connected in order to increase the on-current of the transistor. Also, for example, in a transistor having a back gate, wiring electrically connected to an external circuit may be provided to vary the threshold voltage of the transistor or to reduce the off-current of the transistor, and a fixed or variable potential may be applied to the back gate of the transistor by the external circuit.

[0191] <Example of semiconductor device configuration> This section describes an example of a semiconductor device configuration to which the circuit MC shown in Figure 16A can be applied.

[0192] Figure 17A is a circuit diagram showing an example configuration of a semiconductor device to which the circuit MC of Figure 16A can be applied. The semiconductor device SDV1 shown in Figure 17A includes, as an example, circuit WDC, circuit XDC, circuit BDC, circuit WWC, cell array CA, and circuit ACTV. Circuit ACTV also includes, as an example, circuits ADR[1] to ADR[n].

[0193] A cell array CA has, for example, multiple circuits MC as shown in Figure 16A. Specifically, in a cell array CA, multiple circuits MC are arranged in an m x n matrix (where m is an integer greater than or equal to 1, and n is an integer greater than or equal to 1). In Figure 17A, as an example, circuits MC[1,1], MC[m,1], MC[1,n], and MC[m,n] are illustrated as circuits MC within a cell array CA.

[0194] Circuit MC[1,1] is electrically connected to wiring WDL[1], wiring WWL[1], wiring WWLB[1], wiring XDL[1], wiring BDL[1], and wiring OL[1]. Also, circuit MC[m,1] is electrically connected to wiring WDL[1], wiring WWL[m], wiring WWLB[m], wiring XDL[m], wiring BDL[m], and wiring OL[1]. Also, circuit MC[1,n] is electrically connected to wiring WDL[n], wiring WWL[1], wiring WWLB[1], wiring XDL[1], wiring BDL[1], and wiring OL[n]. Furthermore, circuit MC[m,n] is electrically connected to wiring WDL[n], wiring WWL[m], wiring WWLB[m], wiring XDL[m], wiring BDL[m], and wiring OL[n].

[0195] In other words, when i is an integer between 1 and m and j is an integer between 1 and n, the circuit MC[i,j] (not shown in Figure 17A) is electrically connected to the wiring WDL[j], the wiring WWL[i], the wiring WWLB[i], the wiring XDL[i], the wiring BDL[i], and the wiring OL[j].

[0196] Note that wiring WDL[j] corresponds to wiring WDL shown in Figure 16A. Also, wiring WWL[i] corresponds to wiring WWL shown in Figure 16A, and wiring WWLB[i] corresponds to wiring WWLB shown in Figure 16A. Furthermore, wiring XDL[i] corresponds to wiring XDL shown in Figure 16A, and wiring BDL[i] corresponds to wiring BDL shown in Figure 16A. Also, wiring OL[j] corresponds to wiring OL shown in Figure 16A.

[0197] Circuit WDC is electrically connected to wiring WDL[1] through WDL[n]. Circuit XDC is electrically connected to wiring XDL[1] through XDL[m]. Circuit BDC is electrically connected to wiring BDL[1] through BDL[m]. Circuit WWC is electrically connected to wiring WWL[1] through WWL[m] and wiring WWLB[1] through WWLB[m]. Each of circuits ADR[1] through ADR[n] is electrically connected to wiring OL[1] through OL[n] and wiring ZL[1] through ZL[n].

[0198] Circuit WDC functions, for example, as a drive circuit that provides each of the wirings WDL[1] to WDL[n] with a voltage corresponding to the first data to be written to the circuit MC contained in the cell array CA.

[0199] Circuit XDC functions, for example, as a drive circuit that provides each of the wirings XDL[1] through XDL[m] with a voltage corresponding to a second data to be input to circuit MC contained in cell array CA.

[0200] Circuit BDC functions, for example, as a drive circuit that provides a voltage to each of the wirings BDL[1] to BDL[m] to adjust the amount of current flowing through the wiring OL according to the calculation result, for input to the circuit MC included in the cell array CA.

[0201] For example, the circuit WWC has a function to select the circuit MC to which the first data will be written when writing the first data to each of the wirings WWL[1] to WWL[m] in the cell array CA. Specifically, for example, when writing the first data to the circuit MC[i,1] to circuit MC[i,n] located in the i-th row of the cell array CA, the circuit WWC can select the circuit MC[i,1] to circuit MC[i,n] as the destination for writing the first data by applying a high-level potential to the wiring WWL[i] and a low-level potential to the wirings WWL[1] to WWL[m] other than the wiring WWL[i].

[0202] Also, as an example, circuit WWC has a function of transmitting an inverted signal of the selection signal transmitted to wiring WWL[i] to wiring WWLB[i]. Also, circuit WWC may transmit a different signal to wiring WWLB[i] instead of the inverted signal. For example, circuit WWC may have a function of inputting a low-level potential to wiring WWLB[i] when a low-level potential is input to wiring WWL[i]. Thereby, the circuit MC in FIG. 16A can simultaneously hold the first data and stop supplying the high-power supply potential to the first terminal of transistor M2.

[0203] By paying attention to the j-th column of the cell array CA, the sum of I output by each of circuits MC[1,j] to MC[m,j] flows through wiring OL as a current amount. Here, let the current flowing through transistor M2 of circuit MC[i,j] be I Y [i,j], the current flowing through transistor M6 of circuit MC[i,j] be I W [i], and the current amount flowing from wiring OL to circuit MC[i,j] be I X [i,j]. Further, when the current amounts flowing through transistors M9 of each of circuits MC[1,j] to MC[m,j] are I Y , the current amount I B [j] flowing through wiring OL can be expressed by the following equation. S Circuit ADR[j], as an example, has a function of outputting a voltage corresponding to the current amount flowing from wiring OL[j] to circuit ADR[j], a function of performing an operation according to a predefined function system using the voltage, and a function of outputting the result of the operation of the function to wiring ZL[j].

[0204]

Equation

[0205]

[0206] ​Note that, as in the semiconductor device SDV2 shown in FIG. 17B, a configuration in which the circuit BGC is provided may be adopted. The circuit BGC is electrically connected to the wirings BGL[1] to BGL[m]. As an example, the circuit BGC has a function of inputting a desired constant voltage to each of the wirings BGL[1] to BGL[m]. That is, the circuit BGC functions as a circuit that supplies a constant voltage to the back gates of the transistors included in the circuits MC[1,1] to MC[m,n].

[0207] As described above, by using the circuit MC shown in FIG. 16A, a voltage corresponding to the first data can be written into the circuit MC. Further, the circuit MC can output a current I Y corresponding to the product of the first data and the second data to the wiring OL. Further, by using the semiconductor device SDV1 in FIG. 17A or the semiconductor device SDV2 in FIG. 17B, the sum of products of a plurality of first data and a plurality of second data can be calculated.

[0208] Note that the present embodiment can be appropriately combined with other embodiments shown in this specification.

[0209] (Embodiment 4) In the present embodiment, an example of the operation when a part of the operations of the program executed by the CPU110 described in the above embodiment is executed by the accelerator described as the semiconductor device 100 will be described.

[0210] FIG. 18 is a diagram for explaining an example of the operation when a part of the operations of the program executed by the CPU is executed by the accelerator. The accelerator can select a digital arithmetic unit 101 or an analog arithmetic unit 102 according to the type of operation.

[0211] A host program is executed by the CPU (host program execution; step S1).

[0212] <00When the CPU confirms an instruction to allocate a data area in the memory circuit section that is required when performing calculations using the accelerator (memory allocation instruction; step S2), it allocates the data area in the memory circuit section (memory allocation; step S3).

[0213] Next, the CPU transmits weight data, which is input data, from the main memory or external storage device to the memory circuit unit (data transmission; step S4). The memory circuit unit receives the weight data and stores it in the area reserved in step S3 (data reception; step S5).

[0214] When the CPU confirms the instruction to start the kernel program (starting the kernel program; step S6), the accelerator starts executing the kernel program (starting the calculation; step S7).

[0215] Immediately after the accelerator starts executing the kernel program, the CPU may be switched from the computation state to the PG (power gating) state (PG state transition; step S8). In that case, just before the accelerator finishes executing the kernel program, the CPU is switched from the PG state back to the computation state (PG state termination; step S9). By keeping the CPU in the PG state from step S8 to step S9, power consumption and heat generation can be suppressed for the entire computing system.

[0216] When the accelerator finishes executing the kernel program, the output data is stored in the memory unit within the accelerator that holds the calculation results (completion complete; step S10).

[0217] After the kernel program has finished executing, if the CPU confirms an instruction to send the output data stored in the memory unit to main memory or an external storage device (data transmission request; step S11), the output data is sent to main memory or an external storage device and stored in main memory or an external storage device (data transmission; step S12).

[0218] By repeating the operations from step S1 to step S12 described above, it is possible to suppress the power consumption and heat generation of the CPU and accelerator while performing a portion of the calculations performed by the CPU on the accelerator. One embodiment of the present invention is a semiconductor device having a non-von Neumann architecture, which can perform calculations with extremely low power consumption compared to a von Neumann architecture, where power consumption increases with increasing processing speed.

[0219] This embodiment can be appropriately combined with descriptions of other embodiments.

[0220] (Embodiment 5) This embodiment describes an example of a CPU having CPU cores capable of power gating.

[0221] Figure 19 shows an example configuration of the CPU 110. The CPU 110 includes a CPU core 200, an L1 (level 1) cache memory device 202, an L2 cache memory device 203, a bus interface unit 205, power switches 210-212, and a level shifter (LS) 214. The CPU core 200 includes a flip-flop 220.

[0222] The bus interface unit 205 interconnects the CPU core 200, the L1 cache memory device 202, and the L2 cache memory device 203.

[0223] In response to externally input interrupt signals and signals such as SLEEP1 issued by the CPU 110, the PMU 193 generates the clock signal GCLK1 and various PG (power gating) control signals. The clock signal GCLK1 and PG control signals are input to the CPU 110. The PG control signals control the power switches 210-212 and the flip-flop 220.

[0224] Power switches 210 and 211 respectively control the supply of voltages VDDD and VDD1 to the virtual power line V_VDD (hereinafter referred to as the V_VDD line). Power switch 212 controls the supply of voltage VDDH to level shifter (LS) 214. Voltages VSSS are input to CPU 110 and PMU 193 without passing through a power switch. Voltage VDDD is input to PMU 193 without passing through a power switch.

[0225] Voltages VDDD and VDD1 are drive voltages for CMOS circuits. Voltage VDD1 is lower than voltage VDDD and is the drive voltage in the sleep state. Voltage VDDH is the drive voltage for OS transistors and is higher than voltage VDDD.

[0226] Each of the L1 cache memory device 202, L2 cache memory device 203, and bus interface unit 205 has at least one power domain that can be power-gated. One or more power switches are provided in the power domain that can be power-gated. These power switches are controlled by a PG control signal.

[0227] Flip-flop 220 is used for a register. A backup circuit is provided in flip-flop 220. Flip-flop 220 will be described below.

[0228] Fig. 20A shows a circuit configuration example of flip-flop 220 (Flip-flop). Flip-flop 220 has a scan flip-flop (Scan Flip-flop) 221 and a backup circuit (Buckup Circuit) 222.

[0229] Scan flip-flop 221 has nodes D1, Q1, SD, SE, RT, CK, and clock buffer circuit 221A.

[0230] Node D1 is a data input node, node Q1 is a data output node, and node SD is an input node for scan test data. Node SE is an input node for signal SCE. Node CK is an input node for clock signal GCLK1. Clock signal GCLK1 is input to clock buffer circuit 221A. The analog switch of scan flip-flop 221 is connected to nodes CK1 and CKB1 of clock buffer circuit 221A. Node RT is an input node for the reset signal.

[0231] The signal SCE is a scan enable signal and is generated by the PMU193. The PMU193 generates signals BK and RC. The level shifter 214 level-shifts signals BK and RC to generate signals BKH and RCH. Signal BK is a backup signal, and signal RC is a recovery signal.

[0232] The circuit configuration of scan flip-flop 221 is not limited to Figure 20. Flip-flops available in standard circuit libraries can be used.

[0233] The backup circuit 222 includes nodes SD_IN, SN11, transistors M11 to M13, and a capacitive element C11.

[0234] Node SD_IN is the input node for scan test data and is connected to node Q1 of scan flip-flop 221. Node SN11 is the holding node of backup circuit 222. Capacitor element C11 is a holding capacitance for holding the voltage of node SN11.

[0235] Transistor M11 controls the conduction state between node Q1 and node SN11. Transistor M12 controls the conduction state between node SN11 and node SD. Transistor M13 controls the conduction state between node SD_IN and node SD. The on / off states of transistors M11 and M13 are controlled by signal BKH, and the on / off state of transistor M12 is controlled by signal RCH.

[0236] Transistors M11 to M13 are OS transistors, similar to transistors 61 to 63 in the memory circuit 21 described above. Transistors M11 to M13 are shown with back gates. The back gates of transistors M11 to M13 are connected to a power line that supplies voltage VBG1.

[0237] It is preferable that at least transistors M11 and M12 are OS transistors. Due to the characteristics of OS transistors, which have an extremely low off-current, the voltage drop at node SN11 can be suppressed, and since data retention consumes almost no power, the backup circuit 222 has non-volatile properties. Since data is rewritten by charging and discharging the capacitive element C11, the backup circuit 222 is, in principle, not limited in the number of rewrites, and data can be written and read with low energy.

[0238] It is highly preferable that all transistors in the backup circuit 222 are OS transistors. As shown in Figure 20B, the backup circuit 222 can be stacked on top of the scan flip-flop 221, which is composed of a silicon CMOS circuit.

[0239] The backup circuit 222 has significantly fewer elements than the scan flip-flop 221, so there is no need to change the circuit configuration or layout of the scan flip-flop 221 in order to stack the backup circuit 222. In other words, the backup circuit 222 is a highly versatile backup circuit. Furthermore, since the backup circuit 222 can be placed within the area where the scan flip-flop 221 is formed, the area overhead of the flip-flop 220 can be reduced to zero even when the backup circuit 222 is incorporated. Therefore, by providing the backup circuit 222 on the flip-flop 220, power gating of the CPU core 200 becomes possible. Because less energy is required for power gating, it is possible to power gate the CPU core 200 with high efficiency.

[0240] By providing the backup circuit 222, a parasitic capacitance from transistor M11 is added to node Q1. However, this is small compared to the parasitic capacitance from the logic circuit connected to node Q1, so it does not affect the operation of scan flip-flop 221. In other words, even with the backup circuit 222, the performance of flip-flop 220 is not substantially reduced.

[0241] For example, the CPU core 200 can be configured in low-power states such as clock gating, power gating, and hibernation. The PMU 193 selects the low-power mode for the CPU core 200 based on interrupt signals, the SLEEP1 signal, etc. For example, when transitioning from the normal operating state to the clock gating state, the PMU 193 stops generating the clock signal GCLK1.

[0242] For example, when transitioning from normal operation to hibernation, the PMU193 performs voltage and / or frequency scaling. For example, when performing voltage scaling, the PMU193 turns off power switch 210 and turns on power switch 211 to input voltage VDD1 to the CPU core 200. Voltage VDD1 is a voltage that does not cause data loss in scan flip-flop 221. When performing frequency scaling, the PMU193 reduces the frequency of the clock signal GCLK1.

[0243] When the CPU core 200 transitions from normal operation to power gating, the data on scan flip-flop 221 is backed up to backup circuit 222. When the CPU core 200 returns from power gating to normal operation, the data on backup circuit 222 is recovered to scan flip-flop 221.

[0244] The backup circuit 222 using OS transistors is highly suitable for normally-off computing because it has low dynamic and static power consumption. The CPU 110, including the CPU core 200 with the OS transistor backup circuit 222, can be referred to as NoffCPU (registered trademark). NoffCPU has non-volatile memory and can stop power supply when operation is not required. Even with the addition of a flip-flop 220, it is possible to minimize performance degradation and dynamic power consumption increases of the CPU core 200.

[0245] The CPU core 200 may have multiple power domains capable of power gating. Each power domain is provided with one or more power switches for controlling voltage input. The CPU core 200 may also have one or more power domains that are not power gated. For example, a power gating control circuit for controlling the flip-flop 220 and power switches 210-212 may be provided in a power domain that is not power gated.

[0246] Note that the application of flip-flop 220 is not limited to CPU 110. In CPU 110, flip-flop 220 can be applied to registers located in power domains that are power-gated.

[0247] This embodiment can be appropriately combined with descriptions of other embodiments.

[0248] (Embodiment 6) This embodiment describes an example of the configuration of a semiconductor device as described in the above embodiment, and an example of the configuration of a transistor that can be applied to the semiconductor device as described in the above embodiment.

[0249] <Example of semiconductor device configuration> Figure 21 shows an example of a semiconductor device described in the above embodiment, which includes a transistor 300, a transistor 500, and a capacitive element 600. Figure 22A shows a cross-sectional view of transistor 500 in the channel length direction, Figure 22B shows a cross-sectional view of transistor 500 in the channel width direction, and Figure 22C shows a cross-sectional view of transistor 300 in the channel width direction.

[0250] Transistor 500 is an OS transistor (OS transistor) having a metal oxide in its channel formation region. Transistor 500 has a low off-current and characteristics in which its field-effect mobility does not change easily even at high temperatures. By applying transistor 500 to the transistors included in the analog arithmetic unit 102, oxide semiconductor memory 103, and oxide semiconductor memory 104 shown in the above embodiment, a semiconductor device can be realized in which the operating capability does not degrade easily even at high temperatures. In particular, by utilizing the characteristic of low off-current and applying transistor 500 to the transistors included in the oxide semiconductor memory 103 and oxide semiconductor memory 104, the written potential can be maintained for a long time.

[0251] Transistor 500 is provided, for example, above transistor 300, and capacitive element 600 is provided, for example, above transistors 300 and 500. Capacitive element 600 can be a capacitor included in the oxide semiconductor memory 103 and oxide semiconductor memory 104 described in the above embodiment. Depending on the circuit configuration, capacitive element 600 shown in Figure 21 does not necessarily have to be provided.

[0252] The transistor 300 is provided on a substrate 310 and has an element isolation layer 312, a conductor 316, an insulator 315, a semiconductor region 313 consisting of a part of the substrate 310, a low-resistance region 314a that functions as a source region or drain region, and a low-resistance region 314b. The transistor 300 can be applied to, for example, a transistor included in the digital arithmetic unit 101 described in the above embodiment. In Figure 21, the gate of transistor 300 is shown to be electrically connected to either the source or drain of transistor 500 via a pair of electrodes of the capacitive element 600. However, depending on the configuration of the digital arithmetic unit 101, either the source or drain of transistor 300 may be electrically connected to either the source or drain of transistor 500 via a pair of electrodes of the capacitive element 600. Alternatively, either the source or drain of transistor 300 may be electrically connected to the gate of transistor 500 via a pair of electrodes of the capacitive element 600. Furthermore, each terminal of transistor 300 may not be electrically connected to any of the terminals of transistor 500 or any of the terminals of the capacitive element 600.

[0253] By using the above configuration, it is possible to form an OS-containing device layer on top of a Si-containing device layer, as shown in Figures 2A, 2B, 3A, and 3B.

[0254] Furthermore, it is preferable to use a semiconductor substrate (for example, a single crystal substrate or a silicon substrate) as the substrate 310.

[0255] As shown in Figure 22C, the transistor 300 has its semiconductor region 313's top surface and side surface in the channel width direction covered by a conductor 316 via an insulator 315. By making the transistor 300 a Fin type in this way, the effective channel width can be increased, thereby improving the on-characteristics of the transistor 300. In addition, the contribution of the gate electrode's electric field can be increased, thus improving the off-characteristics of the transistor 300.

[0256] Note that transistor 300 can be either a p-channel or n-channel type.

[0257] In the low-resistance region 314a and low-resistance region 314b, which are the channel-forming region of the semiconductor region 313, the region near it, the source region, or the drain region, it is preferable that a semiconductor such as a silicon-based semiconductor is included, and it is preferable that single-crystal silicon is included. Alternatively, it may be formed from a material having Ge (germanium), SiGe (silicon germanium), GaAs (gallium arsenide), GaAlAs (gallium aluminum arsenide), GaN (gallium nitride), etc. A configuration using silicon in which the effective mass is controlled by applying stress to the crystal lattice and changing the lattice spacing is also possible. Alternatively, the transistor 300 may be made into a HEMT (High Electron Mobility Transistor) by using GaAs and GaAlAs, etc.

[0258] The low-resistance region 314a and the low-resistance region 314b include, in addition to the semiconductor material applied to the semiconductor region 313, elements that impart n-type conductivity, such as arsenic and phosphorus, or elements that impart p-type conductivity, such as boron.

[0259] The conductor 316, which functions as the gate electrode, can be made of a conductive material such as silicon, a semiconductor material, a metallic material, an alloy material, or a metal oxide material, which contains an element that imparts n-type conductivity such as arsenic or phosphorus, or an element that imparts p-type conductivity such as boron.

[0260] Furthermore, since the work function is determined by the material of the conductor, the threshold voltage of the transistor can be adjusted by selecting the material of the conductor. Specifically, it is preferable to use a material containing at least one of titanium nitride and tantalum nitride as the conductor. In addition, in order to achieve both conductivity and embedding properties, it is preferable to use a laminate of metallic materials containing at least one of tungsten and aluminum as the conductor, and using tungsten is particularly preferable in terms of heat resistance.

[0261] The element isolation layer 312 is provided to separate multiple transistors formed on the substrate 310. The element isolation layer can be formed using methods such as LOCOS (LOCal Oxidation of Silicon), STI (Shallow Trench Isolation), or mesa isolation.

[0262] Note that the transistor 300 shown in Figure 21 is just one example, and its structure is not limited to that; any appropriate transistor may be used depending on the circuit configuration or driving method. For example, the transistor 300 may have a planar structure instead of the FIN type shown in Figure 22C. Also, for example, if the semiconductor device is a unipolar circuit consisting only of OS transistors, the configuration of transistor 300 may be the same as that of transistor 500 which uses an oxide semiconductor, as shown in Figure 23. Details of transistor 500 will be described later. In this specification, a unipolar circuit refers to a circuit that includes a transistor with only one polarity, such as an n-channel transistor or a p-channel transistor.

[0263] In Figure 23, the transistor 300 is provided on the substrate 310A. In this case, the substrate 310A may be a semiconductor substrate, similar to the substrate 310 of the semiconductor device in Figure 21. Also, in Figure 23, if the substrate 310A is a semiconductor substrate, similar to the substrate 310 of the semiconductor device in Figure 21, the transistor 300 shown in Figure 21 may be formed on the semiconductor substrate. Furthermore, as the substrate 310A, for example, an SOI substrate, a glass substrate, a quartz substrate, a plastic substrate, a sapphire glass substrate, a metal substrate, a stainless steel substrate, a substrate with stainless steel foil, a tungsten substrate, a substrate with tungsten foil, a flexible substrate, a laminated film, paper containing fibrous material, or a base film can be used. Examples of glass substrates include barium borosilicate glass, aluminoborsilicate glass, or soda-lime glass. Examples of flexible substrates, laminated films, and base films are listed below. Examples of plastics include polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyethersulfone (PES), and polytetrafluoroethylene (PTFE). Alternatively, examples include synthetic resins such as acrylic. Alternatively, examples include polypropylene, polyester, polyvinyl fluoride, or polyvinyl chloride. Alternatively, examples include polyamide, polyimide, aramid, epoxy resin, inorganic vapor-deposited film, or paper.

[0264] By using the above configuration, a second OS-containing element layer can be formed on top of a first OS-containing element layer, as shown in Figures 2B, 3B, 5B, and 16B.

[0265] In the transistor 300 shown in Figure 21, insulators 320, 322, 324, and 326 are stacked in order from the substrate 310 side.

[0266] For insulators 320, 322, 324, and 326, for example, silicon oxide, silicon oxide nitride, silicon oxide nitride, silicon nitride, aluminum oxide, aluminum oxide nitride, aluminum oxide nitride, aluminum nitride, etc. may be used.

[0267] In this specification, silicon oxidizide refers to a material in which the oxygen content is greater than the nitrogen content, and silicon nitride refers to a material in which the nitrogen content is greater than the oxygen content. Furthermore, in this specification, aluminum oxidizide refers to a material in which the oxygen content is greater than the nitrogen content, and aluminum nitride refers to a material in which the nitrogen content is greater than the oxygen content.

[0268] The insulator 322 may also function as a planarizing film that flattens steps caused by the insulator 320 and the transistor 300 covered by the insulator 322. For example, the upper surface of the insulator 322 may be planarized by a planarizing treatment using a chemical mechanical polishing (CMP) method or the like to improve its flatness.

[0269] Furthermore, it is preferable to use a film for the insulator 324 that has barrier properties to prevent impurities such as hydrogen from diffusing from the substrate 310 or the transistor 300 to the region where the transistor 500 is provided.

[0270] As an example of a film having barrier properties against hydrogen, silicon nitride formed by the CVD method can be used. However, when hydrogen diffuses into a semiconductor element having an oxide semiconductor, such as transistor 500, the properties of the semiconductor element may deteriorate. Therefore, it is preferable to use a film that suppresses hydrogen diffusion between transistor 500 and transistor 300. Specifically, a film that suppresses hydrogen diffusion is a film that has a low hydrogen desorption rate.

[0271] The amount of hydrogen desorption can be analyzed, for example, using a thermal desorption gas analysis (TDS) method. For example, in TDS analysis, the amount of hydrogen desorption from insulator 324, when the film surface temperature is in the range of 50°C to 500°C, is calculated as 10 × 10¹⁶ hydrogen atoms per unit area of ​​insulator 324. 15 atoms / cm 2 The following is preferably 5 × 10 15 atoms / cm 2 The following is acceptable.

[0272] Furthermore, it is preferable that the dielectric constant of the insulator 326 is lower than that of the insulator 324. For example, the relative permittivity of the insulator 326 is preferably less than 4, and more preferably less than 3. Also, for example, the relative permittivity of the insulator 326 is preferably 0.7 times or less, and more preferably 0.6 times or less, than that of the relative permittivity of the insulator 324. By using a material with a low dielectric constant as the interlayer film, parasitic capacitance occurring between wiring can be reduced.

[0273] Furthermore, insulators 320, 322, 324, and 326 have embedded conductors 328 and 330, which connect to the capacitive element 600 or the transistor 500. Conductors 328 and 330 function as plugs or wires. Conductors that function as plugs or wires may be grouped together and assigned the same reference numeral. In this specification, the wire and the plug connected to the wire may be an integrated unit. That is, a part of the conductor may function as a wire, and a part of the conductor may function as a plug.

[0274] The plugs and wiring (conductor 328, conductor 330, etc.) can be made of conductive materials such as metal materials, alloy materials, metal nitride materials, or metal oxide materials, which can be used in a single layer or in a laminated form. It is preferable to use a high-melting-point material containing at least one of the following, such as tungsten and molybdenum, which provides both heat resistance and conductivity, and tungsten is preferred. Alternatively, it is preferable to form them with a low-resistance conductive material containing at least one of the following, such as aluminum and copper. Using a low-resistance conductive material can reduce the wiring resistance.

[0275] A wiring layer may be provided on the insulator 326 and the conductor 330. For example, in Figure 21, insulators 350, 352, and 354 are sequentially stacked on top of insulators 326 and conductor 330. Conductors 356 are formed on insulators 350, 352, and 354. Conductors 356 function as plugs or wiring for connecting to transistor 300. Conductors 356 can be provided using the same material as conductors 328 and 330.

[0276] For example, it is preferable that insulator 350, like insulator 324, be an insulator that has barrier properties against impurities, including at least one, such as water and hydrogen. Also, as insulators 352 and 354, it is preferable to use insulators with relatively low dielectric constants, like insulator 326, in order to reduce parasitic capacitance that occurs between the wiring. Furthermore, it is preferable that conductor 356 contains a conductor that has barrier properties against impurities, including at least one, such as water and hydrogen. In particular, a conductor that has barrier properties against hydrogen is formed in the openings of insulator 350 that has barrier properties against hydrogen. With this configuration, transistor 300 and transistor 500 can be separated by the barrier layer, and the diffusion of hydrogen from transistor 300 to transistor 500 can be suppressed.

[0277] For example, tantalum nitride may be used as the conductor that has barrier properties against hydrogen. Furthermore, by laminating tantalum nitride with highly conductive tungsten, it is possible to suppress the diffusion of hydrogen from the transistor 300 while maintaining conductivity as wiring. In this case, it is preferable that the tantalum nitride layer, which has barrier properties against hydrogen, is in contact with the insulator 350, which also has barrier properties against hydrogen.

[0278] Furthermore, insulator 360, insulator 362, and insulator 364 are stacked in order on insulator 354 and conductor 356.

[0279] It is preferable that the insulator 360, like the insulator 324, is an insulator that has barrier properties against impurities, including at least one such impurity, such as water and hydrogen. Therefore, as the insulator 360, for example, a material that can be used for the insulator 324 can be used.

[0280] Insulators 362 and 364 function as interlayer insulating films and planarizing films, respectively. Furthermore, it is preferable that insulators 362 and 364, like insulator 324, be insulators that have barrier properties against impurities, including at least one such impurity, such as water and hydrogen. Therefore, materials applicable to insulator 324 can be used as insulators 362 and / or insulator 364.

[0281] Furthermore, openings are formed in the regions of insulators 360, 362, and 364 that overlap with a portion of the conductor 356, and the conductor 366 is provided to fill these openings. The conductor 366 is also formed on insulator 362. The conductor 366 functions, for example, as a plug or wiring for connecting to transistor 300. The conductor 366 can be provided using the same material as conductors 328 and 330.

[0282] Insulators 510, 512, 514, and 516 are sequentially layered on the insulator 364 and the conductor 366. Preferably, one of the insulators 510, 512, 514, and 516 is made of a material that has barrier properties against oxygen or hydrogen.

[0283] For example, it is preferable to use a film for insulators 510 and 514 that has barrier properties to prevent impurities such as hydrogen from diffusing from the substrate 310 or the region where the transistor 300 is provided to the region where the transistor 500 is provided. Therefore, the same material as that used for insulator 324 can be used.

[0284] As an example of a film having hydrogen barrier properties, silicon nitride formed by the CVD method can be used. However, when hydrogen diffuses into a semiconductor element having an oxide semiconductor, such as transistor 500, the characteristics of the semiconductor element may deteriorate. Therefore, it is preferable to use a film that suppresses hydrogen diffusion between transistor 500 and transistor 300. Specifically, a film that suppresses hydrogen diffusion is a film that has a low hydrogen desorption rate.

[0285] Furthermore, as a film having barrier properties against hydrogen, it is preferable to use metal oxides such as aluminum oxide, hafnium oxide, and tantalum oxide for insulators 510 and 514.

[0286] In particular, aluminum oxide exhibits a high barrier effect, preventing the permeation of both oxygen and impurities such as hydrogen and moisture, which can cause fluctuations in the electrical properties of transistors. Therefore, aluminum oxide can prevent the ingress of impurities such as hydrogen and moisture into the transistor 500 during and after the transistor manufacturing process. It can also suppress the release of oxygen from the oxides constituting the transistor 500. For this reason, it is suitable for use as a protective film for transistor 500.

[0287] Furthermore, for example, the same materials as those used for insulator 320 can be used for insulator 512 and insulator 516. Additionally, by applying materials with relatively low dielectric constants to these insulators, parasitic capacitance between wiring can be reduced. For example, silicon oxide films or silicon oxynitride films can be used as insulators 512 and insulator 516.

[0288] Furthermore, insulators 510, 512, 514, and 516 have a conductor 518 and a conductor constituting the transistor 500 (for example, the conductor 503 shown in Figures 22A and 22B) embedded in them. The conductor 518 functions as a plug or wiring for connecting to the capacitive element 600 or the transistor 300. The conductor 518 can be provided using the same material as the conductors 328 and 330.

[0289] In particular, the conductor 518 in the region in contact with the insulator 510 and the insulator 514 is preferably a conductor having barrier properties against oxygen, hydrogen, and water. With this configuration, transistor 300 and transistor 500 can be separated by a layer having barrier properties against oxygen, hydrogen, and water, and the diffusion of hydrogen from transistor 300 to transistor 500 can be suppressed.

[0290] A transistor 500 is provided above the insulator 516.

[0291] As shown in Figures 22A and 22B, the transistor 500 comprises an insulator 516 on an insulator 514, a conductor 503 (conductor 503a and conductor 503b) arranged to be embedded in the insulator 514 or insulator 516, an insulator 522 on the insulator 516 and on the conductor 503, an insulator 524 on the insulator 522, an oxide 530a on the insulator 524, an oxide 530b on the oxide 530a, a conductor 542a on the oxide 530b, an insulator 571a on the conductor 542a, and an oxide The structure includes a conductor 542b on 530b, an insulator 571b on the conductor 542b, an insulator 552 on the oxide 530b, an insulator 550 on the insulator 552, an insulator 554 on the insulator 550, a conductor 560 (conductor 560a and conductor 560b) located on the insulator 554 and overlapping with a portion of the oxide 530b, and an insulator 544 arranged on the insulator 522, insulator 524, oxide 530a, oxide 530b, conductor 542a, conductor 542b, insulator 571a, and insulator 544 on the insulator 571b. Here, as shown in Figures 22A and 22B, insulator 552 is in contact with the top surface of insulator 522, the side surface of insulator 524, the side surface of oxide 530a, the side surface and top surface of oxide 530b, the side surface of conductor 542, the side surface of insulator 571, the side surface of insulator 544, the side surface of insulator 580, and the bottom surface of insulator 550. The top surface of conductor 560 is positioned so as to be roughly the same height as the top of insulator 554, the top of insulator 550, the top of insulator 552, and the top surface of insulator 580. Insulator 574 is in contact with at least a portion of the top surface of conductor 560, the top of insulator 552, the top of insulator 550, the top of insulator 554, and the top surface of insulator 580.

[0292] Insulators 580 and 544 are provided with openings that reach oxide 530b. Insulators 552, 550, 554, and 560 are arranged within these openings. In addition, in the channel length direction of transistor 500, conductors 560, 552, 550, and 554 are provided between insulators 571a and conductor 542a, and between insulators 571b and conductor 542b. Insulator 554 has a region in contact with the side surface of conductor 560 and a region in contact with the bottom surface of conductor 560.

[0293] Preferably, the oxide 530 has an oxide 530a disposed on the insulator 524 and an oxide 530b disposed on top of the oxide 530a. By having the oxide 530a below the oxide 530b, the diffusion of impurities from structures formed below the oxide 530a to the oxide 530b can be suppressed.

[0294] Although the transistor 500 is shown as having a configuration in which oxide 530 consists of two layers, oxide 530a and oxide 530b, the present invention is not limited to this. For example, the transistor 500 can have a single layer of oxide 530b or a stacked structure of three or more layers. Alternatively, the oxide 530a and oxide 530b can each have a stacked structure.

[0295] Conductor 560 functions as the first gate (also called the top gate) electrode, and conductor 503 functions as the second gate (also called the back gate) electrode. Insulators 552, 550, and 554 function as the first gate insulators, and insulators 522 and 524 function as the second gate insulators. Note that gate insulators are sometimes called gate insulating layers or gate insulating films. Conductor 542a functions as either the source or the drain, and conductor 542b functions as either the source or the drain. At least a portion of the region of oxide 530 that overlaps with conductor 560 functions as a channel-forming region.

[0296] Here, an enlarged view of the vicinity of the channel formation region in FIG. 22A is shown in FIG. 24A. By supplying oxygen to the oxide 530b, a channel formation region is formed in the region between the conductor 542a and the conductor 542b. Therefore, as shown in FIG. 24A, the oxide 530b has a region 530bc that functions as the channel formation region of the transistor 500, and regions 530ba and 530bb that are provided so as to sandwich the region 530bc and function as a source region or a drain region. At least a part of the region 530bc overlaps with the conductor 560. In other words, the region 530bc is provided in the region between the conductor 542a and the conductor 542b. The region 530ba is provided so as to overlap with the conductor 542a, and the region 530bb is provided so as to overlap with the conductor 542b.

[0297] The region 530bc that functions as the channel formation region has less oxygen deficiency (in this specification, the oxygen deficiency in the metal oxide may be referred to as V O (oxygen vacancy).) or a lower impurity concentration than the regions 530ba and 530bb, and thus is a high-resistance region with a low carrier concentration. Therefore, the region 530bc can be said to be of i-type (intrinsic) or substantially i-type.

[0298] In a transistor using a metal oxide, if impurities or oxygen deficiency (V O ) are present in the region where the channel in the metal oxide is formed, the electrical characteristics are likely to vary and the reliability may deteriorate. Also, hydrogen near the oxygen deficiency (V O ) may form a defect in which hydrogen enters the oxygen deficiency (V O ) (hereinafter, may be referred to as V O H.) and generate electrons serving as carriers. For this reason, if the region where the channel in the oxide semiconductor is formed contains oxygen deficiency, the transistor tends to have normally-on characteristics (characteristics in which a channel exists even without applying a voltage to the gate electrode and current flows through the transistor). Therefore, in the region where the channel in the oxide semiconductor is formed, impurities, oxygen deficiency, and V OIt is preferable that H is reduced as much as possible.

[0299] Also, regions 530ba and 530bb that function as a source region or a drain region have a high oxygen deficiency (V O ), or a high concentration of at least one impurity such as hydrogen, nitrogen, and a metal element, which increases the carrier concentration and results in a low-resistance region. That is, regions 530ba and 530bb are n-type regions with a high carrier concentration and low resistance compared to region 530bc.

[0300] Here, the carrier concentration of region 530bc that functions as a channel formation region is preferably 1×10 18 cm -3 or less, more preferably less than 1×10 17 cm -3 less, even more preferably less than 1×10 16 cm -3 less, even more preferably less than 1×10 13 cm -3 less, even more preferably less than 1×10 12 cm -3 less, and even more preferably less than 1×10 -9 cm -3 For the lower limit value of the carrier concentration of region 530bc that functions as a channel formation region, there is no particular limitation, but for example, it can be 1×10

[0301] Furthermore, a region may be formed between region 530bc and region 530ba or region 530bb, where the carrier concentration is equal to or lower than that of region 530ba and region 530bb, and equal to or higher than that of region 530bc. In other words, this region functions as a junction region between region 530bc and region 530ba or region 530bb. The hydrogen concentration in this junction region may be equal to or lower than that of region 530ba and region 530bb, and equal to or higher than that of region 530bc. Also, the oxygen deficiency in this junction region may be equal to or less than that of region 530ba and region 530bb, and equal to or greater than that of region 530bc.

[0302] Although Figure 24A shows an example in which regions 530ba, 530bb, and 530bc are formed in oxide 530b, the present invention is not limited to this. For example, each of the above regions may be formed not only in oxide 530b but also in oxide 530a.

[0303] Furthermore, in oxide 530, it can be difficult to clearly detect the boundaries between each region. The concentrations of metal elements, as well as impurity elements such as hydrogen and nitrogen, detected within each region may not be limited to stepwise changes between regions, but may also change continuously within each region. In other words, the closer a region is to the channel-forming region, the lower the concentrations of metal elements, as well as impurity elements such as hydrogen and nitrogen should be.

[0304] In transistor 500, it is preferable to use a metal oxide (hereinafter also referred to as an oxide semiconductor) that functions as a semiconductor for the oxide 530 (oxide 530a and oxide 530b) which includes the channel formation region.

[0305] Furthermore, it is preferable to use a metal oxide that functions as a semiconductor and has a band gap of 2 eV or more, preferably 2.5 eV or more. By using a metal oxide with a large band gap in this way, the off-current of the transistor can be reduced.

[0306] As oxide 530, for example, a metal oxide such as In-M-Zn oxide having indium, element M, and zinc (element M is one or more selected from aluminum, gallium, yttrium, tin, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, or magnesium) may be used. Alternatively, In-Ga oxide, In-Zn oxide, or indium oxide may be used as oxide 530.

[0307] Here, it is preferable that the atomic ratio of In to element M in the metal oxide used for oxide 530b is greater than the atomic ratio of In to element M in the metal oxide used for oxide 530a.

[0308] In this way, by placing oxide 530a below oxide 530b, the diffusion of impurities and oxygen from structures formed below oxide 530a to oxide 530b can be suppressed.

[0309] Furthermore, because oxides 530a and 530b share a common element other than oxygen (as a main component), the defect level density at the interface between oxide 530a and oxide 530b can be reduced. Because the defect level density at the interface between oxide 530a and oxide 530b can be reduced, the influence of interfacial scattering on carrier conduction is small, resulting in a high on-current.

[0310] The oxide 530b is preferably crystalline. In particular, it is preferable to use CAAC-OS (c-axis aligned crystalline oxide semiconductor) as the oxide 530b.

[0311] CAAC-OS has a highly crystalline, dense structure, and is free from impurities and defects (e.g., oxygen deficiencies (V)). O It is a metal oxide with few impurities (such as). In particular, by heat-treating the metal oxide after its formation at a temperature that does not cause polycrystallization of the metal oxide (for example, between 400°C and 600°C), the CAAC-OS can be made to have a more crystalline and dense structure. By increasing the density of the CAAC-OS in this way, the diffusion of impurities or oxygen in the CAAC-OS can be further reduced.

[0312] On the other hand, because it is difficult to identify clear grain boundaries in CAAC-OS, the decrease in electron mobility caused by grain boundaries is less likely to occur. Therefore, metal oxides containing CAAC-OS have stable physical properties. As a result, metal oxides containing CAAC-OS are heat resistant and highly reliable.

[0313] In transistors using oxide semiconductors, the electrical properties tend to fluctuate and reliability may be poor if impurities and oxygen vacancies are present in the region where the channel is formed in the oxide semiconductor. Furthermore, hydrogen near the oxygen vacancy can fill the oxygen vacancy, creating a defect (hereinafter referred to as V). O Sometimes called H, it forms a channel and generates electrons that become carriers. For this reason, if the region where the channel is formed in the oxide semiconductor contains oxygen vacancies, the transistor is likely to exhibit normally-on characteristics (a characteristic in which the channel exists and current flows through the transistor even without applying voltage to the gate electrode). Therefore, in the region where the channel is formed in the oxide semiconductor, impurities, oxygen vacancies, and V are likely to be present. O It is preferable that H is reduced as much as possible. In other words, it is preferable that the region in the oxide semiconductor where the channel is formed has a reduced carrier concentration and is type i (intrinsed) or substantially type i.

[0314] In contrast, by placing an insulator containing oxygen that is released by heating (hereinafter sometimes referred to as excess oxygen) near the oxide semiconductor and performing heat treatment, oxygen is supplied from the insulator to the oxide semiconductor, eliminating oxygen deficiencies and V O H can be reduced. However, if an excessive amount of oxygen is supplied to the source or drain region, it may cause a decrease in the on-current of transistor 500 or a decrease in the field-effect mobility. Furthermore, variations in the oxygen supplied to the source or drain region within the substrate surface will result in variations in the characteristics of the semiconductor device containing the transistor.

[0315] Therefore, in an oxide semiconductor, the region 530bc, which functions as a channel-forming region, preferably has a reduced carrier concentration and is i-type or substantially i-type, while the regions 530ba and 530bb, which function as a source region or drain region, preferably have a high carrier concentration and are n-type. In other words, oxygen vacancies in region 530bc of the oxide semiconductor, and V O It is preferable to reduce H so that an excessive amount of oxygen is not supplied to regions 530ba and 530bb.

[0316] Therefore, in this embodiment, with the conductor 542a and conductor 542b placed on the oxide 530b, microwave treatment is performed in an oxygen-containing atmosphere to eliminate oxygen deficiencies in region 530bc, and V O The aim is to reduce H. Here, microwave processing refers to processing using a device that has a power supply that generates high-density plasma using microwaves, for example.

[0317] By performing microwave treatment in an oxygen-containing atmosphere, the oxygen gas can be plasmaized using microwaves or high-frequency waves such as RF, and this oxygen plasma can be applied. At this time, microwaves or high-frequency waves such as RF can also be irradiated into region 530bc. Due to the action of plasma, microwaves, etc., the V of region 530bc O By cleaving H, hydrogen H is removed from region 530bc, and oxygen is lost V. OIt can be supplemented with oxygen. In other words, in region 530bc, "V O H → H + V O The following reaction occurs, which reduces the hydrogen concentration in region 530bc. Therefore, the oxygen deficiency in region 530bc, and V O This can reduce H and lower the carrier concentration.

[0318] Furthermore, when performing microwave processing in an oxygen-containing atmosphere, the effects of microwaves, or high frequencies such as RF, and oxygen plasma are shielded by conductors 542a and 542b and do not reach regions 530ba and 530bb. In addition, the effects of oxygen plasma can be reduced by insulators 571 and 580, which are provided covering oxide 530b and conductor 542. As a result, during microwave processing, V O This prevents a decrease in H and avoids the supply of excessive oxygen, thus preventing a drop in carrier concentration.

[0319] Furthermore, it is preferable to perform microwave treatment in an oxygen-containing atmosphere after the deposition of the insulating film that will become the insulator 552, or after the deposition of the insulating film that will become the insulator 550. By performing microwave treatment in an oxygen-containing atmosphere via the insulator 552 or insulator 550 in this way, oxygen can be efficiently injected into region 530bc. In addition, by arranging the insulator 552 in contact with the side surface of the conductor 542 and the surface of region 530bc, the injection of more oxygen than necessary into region 530bc can be suppressed, thereby suppressing oxidation of the side surface of the conductor 542. Furthermore, oxidation of the side surface of the conductor 542 can be suppressed when the insulating film that will become the insulator 550 is deposited.

[0320] Furthermore, the oxygen injected into region 530bc can take various forms, such as oxygen atoms, oxygen molecules, and oxygen radicals (also called O radicals, which are atoms or molecules with unpaired electrons, or ions). It is preferable that the oxygen injected into region 530bc be one or more of the above forms, and particularly preferable that it be oxygen radicals. Additionally, the film quality of insulators 552 and 550 can be improved, thereby increasing the reliability of transistor 500.

[0321] In this way, oxygen vacancies are selectively created in the oxide semiconductor region 530bc, and V O By removing H, region 530bc can be made i-type or substantially i-type. Furthermore, the supply of excess oxygen to regions 530ba and 530bb, which function as source or drain regions, can be suppressed, thereby maintaining the n-type configuration. This suppresses variations in the electrical characteristics of transistor 500 and reduces variations in the electrical characteristics of transistor 500 within the substrate plane.

[0322] By adopting the above configuration, it is possible to provide a semiconductor device with minimal variation in transistor characteristics. Furthermore, it is possible to provide a semiconductor device with good reliability and excellent electrical characteristics.

[0323] Furthermore, as shown in Figure 22B, in a cross-sectional view of the transistor 500 in the channel width direction, there may be a curved surface between the side surface and the top surface of the oxide 530b. In other words, the ends of the side surface and the ends of the top surface may be curved (hereinafter also referred to as rounded).

[0324] The radius of curvature of the curved surface is preferably greater than 0 nm and less than the film thickness of the oxide 530b in the region overlapping with the conductor 542, or less than half the length of the region without the curved surface. Specifically, the radius of curvature of the curved surface is greater than 0 nm and 20 nm or less, preferably 1 nm to 15 nm, and more preferably 2 nm to 10 nm. By adopting such a shape, the coverage of the oxide 530b by the insulator 552, insulator 550, insulator 554, and conductor 560 can be improved.

[0325] The oxide 530 preferably has a laminated structure of multiple oxide layers with different chemical compositions. Specifically, in the metal oxide used for oxide 530a, it is preferable that the atomic ratio of element M to the main metal element is greater than the atomic ratio of element M to the main metal element in the metal oxide used for oxide 530b. Furthermore, in the metal oxide used for oxide 530a, it is preferable that the atomic ratio of element M to In is greater than the atomic ratio of element M to In in the metal oxide used for oxide 530b. Furthermore, in the metal oxide used for oxide 530b, it is preferable that the atomic ratio of In to element M is greater than the atomic ratio of In to element M in the metal oxide used for oxide 530a.

[0326] Furthermore, it is preferable that the oxide 530b is a crystalline oxide such as CAAC-OS. Crystalline oxides such as CAAC-OS have few impurities and defects (such as oxygen deficiencies), and possess a dense structure with high crystallinity. Therefore, the extraction of oxygen from the oxide 530b by the source electrode or drain electrode can be suppressed. As a result, even when heat treatment is performed, the extraction of oxygen from the oxide 530b can be reduced, and the transistor 500 is stable against high temperatures (so-called thermal budget) in the manufacturing process.

[0327] Here, at the junction of oxide 530a and oxide 530b, the lower end of the conduction band changes smoothly. In other words, the lower end of the conduction band at the junction of oxide 530a and oxide 530b can be said to change continuously or to be a continuous junction. To achieve this, it is desirable to lower the defect level density of the mixed layer formed at the interface between oxide 530a and oxide 530b.

[0328] Specifically, by having oxides 530a and 530b share a common element other than oxygen as a main component, a mixed layer with a low defect level density can be formed. For example, if oxide 530b is In-M-Zn oxide, oxide 530a may be In-M-Zn oxide, M-Zn oxide, an oxide of element M, In-Zn oxide, indium oxide, etc.

[0329] Specifically, for oxide 530a, a metal oxide with an atomic ratio of In:M:Zn = 1:3:4 or a similar composition, or an atomic ratio of In:M:Zn = 1:1:0.5 or a similar composition, may be used. Similarly, for oxide 530b, a metal oxide with an atomic ratio of In:M:Zn = 1:1:1 or a similar composition, or an atomic ratio of In:M:Zn = 4:2:3 or a similar composition, may be used. Note that "similar composition" includes a range of ±30% of the desired atomic ratio. Furthermore, it is preferable to use gallium as element M.

[0330] Furthermore, when depositing metal oxide films by sputtering, the above atomic ratio is not limited to the atomic ratio of the deposited metal oxide film, but may also be the atomic ratio of the sputtering target used for depositing the metal oxide film.

[0331] Furthermore, as shown in Figure 22A and other figures, by providing an insulator 552 made of aluminum oxide or the like in contact with the top and side surfaces of the oxide 530, the indium contained in the oxide 530 may be unevenly distributed at and near the interface between the oxide 530 and the insulator 552. As a result, the atomic ratio near the surface of the oxide 530 becomes similar to that of indium oxide, or similar to that of In-Zn oxide. By increasing the atomic ratio of indium near the surface of the oxide 530, particularly oxide 530b, the field-effect mobility of the transistor 500 can be improved.

[0332] By configuring oxides 530a and 530b as described above, the defect level density at the interface between oxide 530a and oxide 530b can be reduced. As a result, the influence of interface scattering on carrier conduction is reduced, and transistor 500 can obtain a large on-current and high frequency characteristics.

[0333] It is preferable that at least one of the insulators 512, 514, 544, 571, 574, 576, and 581 function as a barrier insulating film that suppresses the diffusion of impurities such as water and hydrogen from the substrate side or from above the transistor 500 into the transistor 500. Therefore, it is preferable that at least one of the insulators 512, 514, 544, 571, 574, 576, and 581 be an insulating material that has the function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (N2O, NO, NO2, etc.), and copper atoms (i.e., the above impurities do not easily permeate through it). Alternatively, it is preferable to use an insulating material that has the function of suppressing the diffusion of oxygen (e.g., at least one of oxygen atoms, oxygen molecules, etc.) (i.e., the above oxygen does not easily permeate through it).

[0334] In this specification, a barrier insulating film refers to an insulating film that has barrier properties. In this specification, barrier properties refer to the function of suppressing the diffusion of the corresponding substance (also called low permeability), or the function of capturing and fixing the corresponding substance (also called gettering).

[0335] It is preferable to use insulators 512, 514, 544, 571, 574, 576, and 581 that have the function of suppressing the diffusion of impurities such as water and hydrogen, and oxygen. For example, aluminum oxide, magnesium oxide, hafnium oxide, gallium oxide, indium gallium zinc oxide, silicon nitride, or silicon nitride oxide can be used. For example, it is preferable to use silicon nitride, which has higher hydrogen barrier properties, as insulators 512, 544, and 576. Also, for example, it is preferable to use aluminum oxide or magnesium oxide, which have high hydrogen capture and hydrogen fixation functions, as insulators 514, 571, 574, and 581. This makes it possible to suppress the diffusion of impurities such as water and hydrogen from the substrate side to the transistor 500 side via insulators 512 and 514. Alternatively, it is possible to suppress the diffusion of impurities such as water and hydrogen from the interlayer insulating film located outside the insulator 581 towards the transistor 500. Alternatively, it is possible to suppress the diffusion of oxygen contained in the insulator 524, etc., towards the substrate side via the insulators 512 and 514. Alternatively, it is possible to suppress the diffusion of oxygen contained in the insulator 580, etc., upward from the transistor 500 via the insulator 574, etc. Thus, it is preferable to have a structure in which the transistor 500 is surrounded by insulators 512, 514, 571, 544, 574, 576, and 581, which have the function of suppressing the diffusion of impurities such as water and hydrogen, and oxygen.

[0336] Here, it is preferable to use oxides having an amorphous structure as insulators 512, 514, 544, 571, 574, 576, and 581. For example, AlO x (x is any number greater than 0), or MgO y It is preferable to use a metal oxide such as (y is any number greater than 0). In such an amorphous metal oxide, oxygen atoms have dangling bonds, and these dangling bonds may have the property of capturing or fixing hydrogen. By using such an amorphous metal oxide as a component of the transistor 500, or by providing it around the transistor 500, hydrogen contained in the transistor 500, or hydrogen present around the transistor 500, can be captured or fixed. It is particularly preferable to capture or fix hydrogen contained in the channel formation region of the transistor 500. By using an amorphous metal oxide as a component of the transistor 500, or by providing it around the transistor 500, it is possible to manufacture a transistor 500 and a semiconductor device that have good characteristics and are highly reliable.

[0337] Furthermore, while insulators 512, 514, 544, 571, 574, 576, and 581 are preferably amorphous, they may also have regions of polycrystalline structure. In addition, insulators 512, 514, 544, 571, 574, 576, and 581 may have a multilayer structure in which an amorphous layer and a polycrystalline layer are stacked. For example, a stacked structure in which a polycrystalline layer is formed on top of an amorphous layer may also be possible.

[0338] The insulators 512, 514, 544, 571, 574, 576, and 581 can be deposited using, for example, a sputtering method. Since the sputtering method does not require the use of hydrogen-containing molecules in the deposition gas, the hydrogen concentration of insulators 512, 514, 544, 571, 574, 576, and 581 can be reduced. The deposition method is not limited to sputtering, and chemical vapor deposition (CVD), molecular beam epitaxy (MBE), pulsed laser deposition (PLD), atomic layer deposition (ALD), etc., may be used as appropriate.

[0339] Furthermore, it may be preferable to lower the resistivity of insulators 512, 544, and 576. For example, the resistivity of insulators 512, 544, and 576 may be approximately 1 × 10⁻⁶. 13 By setting the resistivity to Ωcm, insulators 512, 544, and 576 can mitigate charge-up of conductors 503, 542, and 560 in processes using plasma in semiconductor device manufacturing. The resistivity of insulators 512, 544, and 576 is preferably 1 × 10⁻⁶. 10 Ωcm or more, 1 × 10 15 The density should be less than or equal to Ωcm.

[0340] Furthermore, it is preferable that insulators 516, 574, 580, and 581 have a lower dielectric constant than insulator 514. By using a material with a low dielectric constant as the interlayer film, parasitic capacitance between wirings can be reduced. For example, silicon oxide, silicon oxynitride, silicon oxide with added fluorine, silicon oxide with added carbon, silicon oxide with added carbon and nitrogen, and porous silicon oxide may be used as insulators 516, 580, and 581 as appropriate.

[0341] Furthermore, it is preferable that the insulator 581 functions as an insulator, for example, an interlayer film, a planarization film, or the like.

[0342] The conductor 503 is arranged to overlap with the oxide 530 and the conductor 560. Here, it is preferable that the conductor 503 is embedded in an opening formed in the insulator 516. In some cases, a portion of the conductor 503 may be embedded in the insulator 514.

[0343] The conductor 503 comprises a conductor 503a and a conductor 503b. Conductor 503a is provided in contact with the bottom surface and side wall of the opening. Conductor 503b is provided so as to be embedded in a recess formed in conductor 503a. Here, the upper height of conductor 503b is approximately equal to the upper height of conductor 503a and the upper height of insulator 516.

[0344] Here, it is preferable to use a conductive material for the conductor 503a that has the function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (N2O, NO, NO2, etc.), and copper atoms. Alternatively, it is preferable to use a conductive material that has the function of suppressing the diffusion of oxygen (for example, at least one such as oxygen atoms or oxygen molecules).

[0345] By using a conductive material that has the function of reducing hydrogen diffusion for the conductor 503a, it is possible to prevent impurities such as hydrogen contained in the conductor 503b from diffusing into the oxide 530 via the insulator 524, etc. Furthermore, by using a conductive material that has the function of suppressing oxygen diffusion for the conductor 503a, it is possible to suppress the oxidation of the conductor 503b and the resulting decrease in conductivity. As a conductive material that has the function of suppressing oxygen diffusion, it is preferable to use, for example, titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, ruthenium oxide, etc. Therefore, the conductive material can be used as a single layer or in a laminate for the conductor 503a. For example, titanium nitride can be used for the conductor 503a.

[0346] Furthermore, it is preferable that the conductor 503b be a conductive material mainly composed of tungsten, copper, or aluminum. For example, tungsten may be used for the conductor 503b.

[0347] The conductor 503 may function as a second gate electrode. In this case, the threshold voltage (Vth) of transistor 500 can be controlled by changing the potential applied to conductor 503 independently of the potential applied to conductor 560, rather than in conjunction with it. In particular, by applying a negative potential to conductor 503, it is possible to increase the Vth of transistor 500 and reduce the off-current. Therefore, applying a negative potential to conductor 503 reduces the drain current when the potential applied to conductor 560 is 0V compared to not applying a negative potential.

[0348] Furthermore, the electrical resistivity of the conductor 503 is designed considering the potential applied to the conductor 503, and the film thickness of the conductor 503 is set to match this electrical resistivity. The film thickness of the insulator 516 is approximately the same as that of the conductor 503. Here, it is preferable to make the film thicknesses of the conductor 503 and the insulator 516 as thin as possible within the limits permitted by the design of the conductor 503. By making the film thickness of the insulator 516 thin, the absolute amount of impurities such as hydrogen contained in the insulator 516 can be reduced, thereby reducing the diffusion of these impurities into the oxide 530.

[0349] Furthermore, the conductor 503 should be larger than the area of ​​the oxide 530 that does not overlap with the conductors 542a and 542b when viewed from above. In particular, as shown in Figure 22B, it is preferable that the conductor 503 extends to the area outside the edges of the oxide 530a and oxide 530b in the channel width direction. That is, it is preferable that the conductor 503 and the conductor 560 are superimposed on the outside of the side surface of the oxide 530 in the channel width direction, with an insulator in between. With this configuration, the channel formation region of the oxide 530 can be electrically surrounded by the electric field of the conductor 560 which functions as the first gate electrode and the electric field of the conductor 503 which functions as the second gate electrode. In this specification, a transistor structure in which the channel formation region is electrically surrounded by the electric fields of the first gate and the second gate is called a surrounded channel (S-channel) structure.

[0350] In this specification, an S-channel transistor refers to a transistor structure in which the channel formation region is electrically surrounded by the electric fields of one and the other of a pair of gate electrodes. Furthermore, the S-channel structure disclosed in this specification is different from the Fin-type structure and the Planar-type structure. By adopting an S-channel structure, it is possible to create a transistor that has improved resistance to short-channel effects, or in other words, a transistor in which short-channel effects are less likely to occur.

[0351] Furthermore, as shown in Figure 22B, the conductor 503 is extended to function as wiring. However, the configuration is not limited to this, and a conductor that functions as wiring may be provided beneath the conductor 503. Also, it is not necessary to provide one conductor 503 for each transistor. For example, the conductor 503 may be shared by multiple transistors.

[0352] In the transistor 500, the conductor 503 is shown as a stacked structure of conductor 503a and conductor 503b, but the present invention is not limited to this. For example, the conductor 503 may be provided as a single layer or as a stacked structure of three or more layers.

[0353] Insulators 522 and 524 function as gate insulators.

[0354] Preferably, the insulator 522 has the function of suppressing the diffusion of hydrogen (for example, at least one such as a hydrogen atom or a hydrogen molecule). Furthermore, preferably, the insulator 522 has the function of suppressing the diffusion of oxygen (for example, at least one such as an oxygen atom or an oxygen molecule). For example, it is preferable that the insulator 522 has the function of suppressing the diffusion of one or both hydrogen and oxygen more effectively than the insulator 524.

[0355] The insulator 522 may be an insulator containing an oxide of either or both of the insulating materials aluminum and hafnium. Preferably, the insulator is an oxide containing aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium (hafnium aluminate). When the insulator 522 is formed using such a material, the insulator 522 functions as a layer that suppresses the release of oxygen from the oxide 530 to the substrate side and the diffusion of impurities such as hydrogen from the periphery of the transistor 500 to the oxide 530. Therefore, by providing the insulator 522, it is possible to suppress the diffusion of impurities such as hydrogen into the inside of the transistor 500 and to suppress the generation of oxygen vacancies in the oxide 530. In addition, it is possible to suppress the reaction of the conductor 503 with the oxygen contained in the insulator 524 and the oxide 530.

[0356] Alternatively, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide may be added to the above-mentioned insulator. Alternatively, these insulators may be subjected to nitriding treatment. Furthermore, insulator 522 may be used by laminating silicon oxide, silicon oxide nitride, or silicon nitride onto these insulators.

[0357] Furthermore, the insulator 522 may be a single-layer or multi-layer insulator containing so-called high-k materials, such as aluminum oxide, hafnium oxide, tantalum oxide, or zirconium oxide. As transistors become smaller and more integrated, thinning of the gate insulator can lead to problems such as leakage current. By using a high-k material as the insulator that functions as the gate insulator, it is possible to reduce the gate potential during transistor operation while maintaining the physical film thickness. In addition, materials with high dielectric constants, such as lead zirconate titanate (PZT), strontium titanate (SrTiO3), and (Ba,Sr)TiO3 (BST), may also be used as the insulator 522.

[0358] The insulator 524 in contact with the oxide 530 can be, for example, silicon oxide, silicon oxide nitride, or the like, as appropriate.

[0359] Furthermore, during the manufacturing process of the transistor 500, it is preferable to perform a heat treatment while the surface of the oxide 530 is exposed. This heat treatment may be performed at, for example, 100°C to 600°C, more preferably 350°C to 550°C. The heat treatment should be performed in an atmosphere of nitrogen gas or an inert gas, or in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas. For example, it is preferable to perform the heat treatment in an oxygen atmosphere. This supplies oxygen to the oxide 530, thereby preventing oxygen deficiency (V OThis can reduce the amount of oxygen released. The heat treatment may also be performed under reduced pressure. Alternatively, the heat treatment may be performed in an atmosphere of nitrogen gas or an inert gas, and then in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas to replenish the oxygen that has been removed. Alternatively, the heat treatment may be performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas, and then continuously in an atmosphere of nitrogen gas or an inert gas.

[0360] Furthermore, by performing an oxygenation treatment on oxide 530, oxygen deficiencies in oxide 530 are repaired by the supplied oxygen, or in other words, "V O This can accelerate the reaction "+O→null". Furthermore, the oxygen supplied reacts with the hydrogen remaining in oxide 530, removing the hydrogen as H2O (dehydration). As a result, the hydrogen remaining in oxide 530 recombines with the oxygen vacancy and V O This can suppress the formation of H.

[0361] Furthermore, the insulators 522 and 524 may have a laminated structure of two or more layers. In this case, the laminated structure is not limited to being made of the same material, but may be made of different materials. Also, the insulator 524 may be superimposed with the oxide 530a to form an island-like structure. In this case, the insulator 544 will be in contact with the side surface of the insulator 524 and the upper surface of the insulator 522.

[0362] Conductors 542a and 542b are provided in contact with the upper surface of oxide 530b. Conductors 542a and 542b function as the source electrode or drain electrode of transistor 500, respectively.

[0363] As the conductor 542 (conductor 542a and conductor 542b), it is preferable to use, for example, a nitride containing tantalum, a nitride containing titanium, a nitride containing molybdenum, a nitride containing tungsten, a nitride containing tantalum and aluminum, or a nitride containing titanium and aluminum. In one embodiment of the present invention, a nitride containing tantalum is particularly preferred. Alternatively, for example, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, or an oxide containing lanthanum and nickel may be used. These materials are preferred because they are conductive materials that are resistant to oxidation or maintain conductivity even when absorbing oxygen.

[0364] Furthermore, hydrogen contained in oxide 530b, etc., may diffuse into conductor 542a or conductor 542b. In particular, by using tantalum-containing nitrides for conductor 542a and conductor 542b, hydrogen contained in oxide 530b, etc., is more likely to diffuse into conductor 542a or conductor 542b, and the diffused hydrogen may combine with nitrogen present in conductor 542a or conductor 542b. In other words, hydrogen contained in oxide 530b, etc., may be absorbed by conductor 542a or conductor 542b.

[0365] Furthermore, it is preferable that no curved surface is formed between the side surface of the conductor 542 and the top surface of the conductor 542. By using a conductor 542 without such a curved surface, the cross-sectional area of ​​the conductor 542 in the channel width direction can be increased. This increases the conductivity of the conductor 542 and increases the on-current of the transistor 500.

[0366] The insulator 571a is provided in contact with the upper surface of the conductor 542a, and the insulator 571b is provided in contact with the upper surface of the conductor 542b. Preferably, the insulator 571 functions as a barrier insulating film against oxygen. Therefore, it is preferable that the insulator 571 has a function to suppress the diffusion of oxygen. For example, it is preferable that the insulator 571 has a function to suppress the diffusion of oxygen more effectively than the insulator 580. As the insulator 571, for example, a silicon-containing nitride such as silicon nitride may be used. Furthermore, it is preferable that the insulator 571 has a function to capture impurities such as hydrogen. In that case, as the insulator 571, an amorphous metal oxide, such as aluminum oxide or magnesium oxide, may be used. In particular, it is preferable to use amorphous aluminum oxide or amorphous aluminum oxide as the insulator 571 because it may be possible to capture or fix hydrogen more effectively. This makes it possible to manufacture a transistor 500 and semiconductor device with good characteristics and high reliability.

[0367] The insulator 544 is provided so as to cover the insulator 524, oxide 530a, oxide 530b, conductor 542, and insulator 571. Preferably, the insulator 544 has the function of capturing and fixing hydrogen. In that case, it is preferable that the insulator 544 includes silicon nitride or an insulator such as an amorphous metal oxide, for example, aluminum oxide or magnesium oxide. Alternatively, for example, a laminated film of aluminum oxide and silicon nitride on the aluminum oxide may be used as the insulator 544.

[0368] By providing the insulators 571 and 544 as described above, the conductor 542 can be surrounded by an insulator that has barrier properties against oxygen. In other words, the oxygen contained in insulators 524 and 580 can be prevented from diffusing into the conductor 542. This prevents the conductor 542 from being directly oxidized by the oxygen contained in insulators 524 and 580, which would increase its resistivity and reduce the on-current.

[0369] The insulator 552 functions as part of the gate insulator. Preferably, the insulator 552 is a barrier insulating film against oxygen. The insulator 552 can be any insulator that can be used for the insulator 574 described above. The insulator 552 may be an insulator containing an oxide of either or both aluminum and hafnium. Examples of such insulators include aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), and an oxide containing hafnium and silicon (hafnium silicate). In this embodiment, aluminum oxide is used as the insulator 552. In this case, the insulator 552 is an insulator containing at least oxygen and aluminum.

[0370] As shown in Figure 22B, the insulator 552 is provided in contact with the top and side surfaces of oxide 530b, the side surface of oxide 530a, the side surface of insulator 524, and the top surface of insulator 522. In other words, the regions of oxide 530a, oxide 530b, and insulator 524 that overlap with the conductor 560 are covered by the insulator 552 in the cross-section in the channel width direction. This allows the insulator 552, which has an oxygen barrier property, to block the desorption of oxygen from oxide 530a and oxide 530b during heat treatment, etc. Thus, the formation of oxygen vacancies (Vo) in oxide 530a and oxide 530b can be reduced. O H can be reduced. Therefore, the electrical characteristics of transistor 500 can be improved, and its reliability can be enhanced.

[0371] Conversely, even if an excess amount of oxygen is present in the insulator 580 and insulator 550, it is possible to suppress the excessive supply of such oxygen to oxides 530a and 530b. Therefore, it is possible to suppress the excessive oxidation of regions 530ba and 530bb via region 530bc, which would otherwise cause a decrease in the on-current of transistor 500 or a decrease in field-effect mobility.

[0372] Furthermore, as shown in Figure 22A, the insulator 552 is provided in contact with the sides of the conductor 542, insulator 571, insulator 544, and insulator 580. Therefore, oxidation of the side surface of the conductor 542 and the formation of an oxide film on that side surface can be reduced. This makes it possible to suppress a decrease in the on-current of the transistor 500 or a decrease in the field-effect mobility.

[0373] Furthermore, the insulator 552, along with the insulator 554, the insulator 550, and the conductor 560, must be provided in the opening formed in the insulator 580 or the like. When miniaturizing the transistor 500, it is preferable that the film thickness of the insulator 552 be thin. The film thickness of the insulator 552 is preferably 0.1 nm or more, 0.5 nm or more, or 1.0 nm or more, and preferably 1.0 nm or less, 3.0 nm or less, or 5.0 nm or less. The above-mentioned lower and upper limits can be combined. In this case, it is sufficient that the insulator 552 has a region with the above-mentioned film thickness in at least a part of it. Furthermore, it is preferable that the film thickness of the insulator 552 is thinner than the film thickness of the insulator 550. In this case, it is sufficient that the insulator 552 has a region with a thinner film thickness than the insulator 550 in at least a part of it.

[0374] To deposit the insulator 552 with a thin film thickness as described above, it is preferable to use the ALD method. ALD methods include thermal ALD, which uses only thermal energy for the reaction between the precursor and reactant, and plasma-enhanced ALD (PEALD), which uses plasma-excited reactants. The PEALD method is preferable in some cases because the use of plasma allows for film deposition at lower temperatures.

[0375] The ALD method utilizes the self-regulating properties of atoms to deposit atoms layer by layer, resulting in several advantages: ultra-thin film deposition is possible, deposition on structures with high aspect ratios is possible, film deposition with fewer defects such as pinholes is possible, film deposition with excellent coverage is possible, and film deposition is possible at low temperatures. Therefore, the insulator 552 can be deposited with good coverage on the sides of openings formed in the insulator 580, etc., with the thin film thickness described above.

[0376] Note that precursors used in the ALD method may contain carbon and other impurities. Therefore, films formed by the ALD method may contain more carbon and other impurities compared to films formed by other film deposition methods. The quantity of impurities can be quantified using secondary ion mass spectrometry (SIMS) or X-ray photoelectron spectroscopy (XPS).

[0377] The insulator 550 functions as part of the gate insulator. It is preferable that the insulator 550 is placed in contact with the upper surface of the insulator 552. The insulator 550 can be silicon oxide, silicon oxynitride, silicon nitride, silicon nitride, silicon oxide with added fluorine, silicon oxide with added carbon, silicon oxide with added carbon and nitrogen, or silicon oxide with vacancies. In particular, silicon oxide and silicon oxynitride are preferred because they are stable with respect to heat. In this case, the insulator 550 will be an insulator having at least oxygen and silicon.

[0378] Similar to the insulator 524, it is preferable that the insulator 550 has a reduced concentration of impurities such as water and hydrogen. The film thickness of the insulator 550 is preferably 1 nm or more, or 0.5 nm or more, and preferably 15.0 nm or less, or 20 nm or less. The above-mentioned lower and upper limits can be combined. In this case, the insulator 550 only needs to have a region with the above-mentioned film thickness in at least a part of it.

[0379] Figures 22A and 22B show a configuration in which the insulator 550 is a single layer, but the present invention is not limited to this, and a laminated structure of two or more layers is also possible. For example, as shown in Figure 24B, the insulator 550 may be a laminated structure of two layers: an insulator 550a and an insulator 550b on top of the insulator 550a.

[0380] As shown in Figure 24B, when the insulator 550 has a two-layer laminated structure, it is preferable that the lower insulator 550a is formed using an insulator that is permeable to oxygen, and the upper insulator 550b is formed using an insulator that has the function of suppressing the diffusion of oxygen. With this configuration, it is possible to suppress the diffusion of oxygen contained in the insulator 550a to the conductor 560. In other words, it is possible to suppress the decrease in the amount of oxygen supplied to the oxide 530. In addition, it is possible to suppress the oxidation of the conductor 560 by the oxygen contained in the insulator 550a. For example, the insulator 550a may be made using a material that can be used for the insulator 550 as described above, and the insulator 550b may be an insulator containing an oxide of aluminum and / or hafnium. As such an insulator, aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), an oxide containing hafnium and silicon (hafnium silicate), etc., can be used. In this embodiment, hafnium oxide is used as the insulator 550b. In this case, the insulator 550b is an insulator having at least oxygen and hafnium. Furthermore, the film thickness of the insulator 550b is preferably 0.5 nm or more, or 1.0 nm or more, and preferably 3.0 nm or less, or 5.0 nm or less. The above-mentioned lower and upper limits can be combined. In this case, the insulator 550b only needs to have a region with the above-mentioned film thickness in at least a portion of it.

[0381] Furthermore, when silicon oxide or silicon oxynitride is used for insulator 550a, an insulating material with a high dielectric constant, such as a high-k material, may be used for insulator 550b. By making the gate insulator a laminated structure of insulator 550a and insulator 550b, a laminated structure that is stable against heat and has a high dielectric constant can be made. Therefore, it becomes possible to reduce the gate potential applied during transistor operation while maintaining the physical film thickness of the gate insulator. In addition, it becomes possible to thin the equivalent oxide film thickness (EOT) of the insulator that functions as a gate insulator. Thus, the dielectric breakdown voltage of insulator 550 can be increased.

[0382] The insulator 554 functions as part of the gate insulator. Preferably, a barrier insulating film against hydrogen is used as the insulator 554. This prevents impurities such as hydrogen contained in the conductor 560 from diffusing into the insulator 550 and oxide 530b. The insulator 554 can be any insulator that can be used for the insulator 576 described above. For example, silicon nitride deposited by the PEALD method can be used as the insulator 554. In this case, the insulator 554 will be an insulator containing at least nitrogen and silicon.

[0383] Furthermore, the insulator 554 may also have barrier properties against oxygen. This can suppress the diffusion of oxygen contained in the insulator 550 into the conductor 560.

[0384] Furthermore, the insulator 554, along with the insulator 552, the insulator 550, and the conductor 560, must be provided in an opening formed in the insulator 580 or the like. In order to miniaturize the transistor 500, it is preferable that the film thickness of the insulator 554 be thin. The film thickness of the insulator 554 is preferably 0.1 nm or more, 0.5 nm or more, or 1.0 nm or more, and preferably 3.0 nm or less, or 5.0 nm or less. The above-mentioned lower and upper limits can be combined. In this case, it is sufficient that the insulator 554 has a region with the above-mentioned film thickness in at least a part of it. Furthermore, it is preferable that the film thickness of the insulator 554 is thinner than the film thickness of the insulator 550. In this case, it is sufficient that the insulator 554 has a region with a thinner film thickness than the insulator 550 in at least a part of it.

[0385] The conductor 560 functions as the first gate electrode of the transistor 500. Preferably, the conductor 560 has a conductor 560a and a conductor 560b placed on top of the conductor 560a. For example, it is preferable that the conductor 560a is arranged to enclose the bottom and sides of the conductor 560b. Also, as shown in Figures 22A and 22B, the height of the top of the conductor 560 roughly coincides with the height of the top of the insulator 550. In Figures 22A and 22B, the conductor 560 is shown as a two-layer structure of conductor 560a and conductor 560b, but it can also be a single-layer structure or a stacked structure of three or more layers.

[0386] It is preferable to use a conductive material for the conductor 560a that has the function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules, and copper atoms. Alternatively, it is preferable to use a conductive material that has the function of suppressing the diffusion of oxygen (for example, at least one such as oxygen atoms or oxygen molecules).

[0387] Furthermore, because the conductor 560a has the function of suppressing oxygen diffusion, it is possible to suppress the oxidation of the conductor 560b by the oxygen contained in the insulator 550, which would otherwise reduce its conductivity. As a conductive material that has the function of suppressing oxygen diffusion, it is preferable to use, for example, titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, ruthenium oxide, etc.

[0388] Furthermore, since the conductor 560 also functions as wiring, it is preferable to use a conductor with high conductivity. For example, the conductor 560b can be a conductive material mainly composed of tungsten, copper, or aluminum. Also, the conductor 560b can have a laminated structure. Specifically, for example, the conductor 560b can be titanium, or titanium nitride and the above-mentioned conductive material.

[0389] Furthermore, in transistor 500, the conductor 560 is formed self-aligningly to fill the openings formed in the insulator 580 and the like. By forming the conductor 560 in this way, the conductor 560 can be reliably positioned in the region between the conductors 542a and 542b without the need for alignment.

[0390] Furthermore, as shown in Figure 22B, in the channel width direction of transistor 500, it is preferable that the height of the bottom surface of the region of conductor 560 where conductor 560 and oxide 530b do not overlap, with reference to the bottom surface of insulator 522, is lower than the height of the bottom surface of oxide 530b. By configuring conductor 560, which functions as a gate electrode, to cover the side and top surfaces of the channel formation region of oxide 530b via insulator 550 or the like, it becomes easier to apply the electric field of conductor 560 to the entire channel formation region of oxide 530b. Therefore, the on-current of transistor 500 can be increased and the frequency characteristics can be improved. With respect to the bottom surface of the insulator 522, the difference between the height of the bottom surface of the conductor 560 and the height of the bottom surface of oxide 530b in the region where the oxides 530a and 530b and the conductor 560 do not overlap is preferably 0 nm or more, 3 nm or more, or 5 nm or more, and preferably 20 nm or less, 50 nm or less, or 100 nm or less. The above-mentioned lower and upper limits can be combined.

[0391] The insulator 580 is provided on the insulator 544, and openings are formed in the regions where the insulator 550 and the conductor 560 are provided. The upper surface of the insulator 580 may also be flattened.

[0392] The insulator 580, which functions as an interlayer film, preferably has a low dielectric constant. By using a material with a low dielectric constant as the interlayer film, parasitic capacitance occurring between wiring can be reduced. The insulator 580 is preferably made of the same material as the insulator 516, for example. Silicon oxide and silicon oxynitride are particularly preferred because they are thermally stable. Materials such as silicon oxide, silicon oxynitride, and silicon oxide with vacancies are particularly preferred because they can easily form regions containing oxygen that is desorbed by heating.

[0393] Preferably, the insulator 580 has a reduced concentration of impurities such as water and hydrogen. For example, the insulator 580 may be made of silicon oxide such as silicon oxide or silicon oxynitride.

[0394] The insulator 574 preferably functions as a barrier insulating film that suppresses the diffusion of impurities such as water and hydrogen into the insulator 580 from above, and preferably has the function of capturing impurities such as hydrogen. Furthermore, the insulator 574 preferably functions as a barrier insulating film that suppresses the permeation of oxygen. As the insulator 574, an amorphous metal oxide, such as aluminum oxide, may be used. In this case, the insulator 574 will be an insulator having at least oxygen and aluminum. By providing an insulator 574 in the region sandwiched between the insulator 512 and the insulator 580, in contact with the insulator 580, and having the function of capturing impurities such as hydrogen, impurities such as hydrogen contained in the insulator 580 can be captured, and the amount of hydrogen in that region can be kept constant. In particular, using aluminum oxide with an amorphous structure as the insulator 574 is preferable because it may be possible to capture or fix hydrogen more effectively. This makes it possible to manufacture a transistor 500 and a semiconductor device with good characteristics and high reliability.

[0395] The insulator 576 functions as a barrier insulating film that suppresses the diffusion of impurities such as water and hydrogen from above into the insulator 580. The insulator 576 is placed on top of the insulator 574. Preferably, the insulator 576 is a silicon-containing nitride such as silicon nitride or silicon nitride oxide. For example, silicon nitride deposited by sputtering may be used as the insulator 576. By depositing the insulator 576 by sputtering, a high-density silicon nitride film can be formed. Alternatively, as the insulator 576, silicon nitride deposited by PEALD or CVD may be further laminated on top of the silicon nitride deposited by sputtering.

[0396] Furthermore, one of the first or second terminals of transistor 500 is electrically connected to conductor 540a, which functions as a plug, and the other of the first or second terminal of transistor 500 is electrically connected to conductor 540b. In this specification, conductors 540a and conductor 540b are collectively referred to as conductor 540.

[0397] As an example, the conductor 540a is provided in a region that overlaps with the conductor 542a. Specifically, in the region that overlaps with the conductor 542a, openings are formed in the insulators 571, 544, 580, 574, 576, and 581 shown in Figure 22A, as well as insulators 582 and 586 shown in Figure 21, and the conductor 540a is provided inside these openings. Furthermore, as an example, the conductor 540b is provided in a region that overlaps with the conductor 542b. Specifically, in the region overlapping with the conductor 542b, openings are formed in the insulators 571, 544, 580, 574, 576, and 581 shown in Figure 22A, as well as insulators 582 and 586 shown in Figure 21, and the conductor 540b is provided inside these openings. Insulators 582 and 586 will be described later.

[0398] Furthermore, as shown in Figure 22A, an insulator 541a may be provided between the side surface of the opening in the region overlapping with the conductor 542a and the conductor 540a, as an insulator that provides a barrier against impurities. Similarly, an insulator 541b may be provided between the side surface of the opening in the region overlapping with the conductor 542b and the conductor 540b, as an insulator that provides a barrier against impurities. In this specification, insulators 541a and 541b will be collectively referred to as insulator 541.

[0399] It is preferable that the conductors 540a and 540b are made of conductive materials mainly composed of tungsten, copper, or aluminum. Furthermore, the conductors 540a and 540b may be arranged in a laminated structure.

[0400] Furthermore, when the conductor 540 has a laminated structure, it is preferable to use a conductive material that has the function of suppressing the permeation of impurities such as water and hydrogen for the first conductor arranged near the insulators 574, 576, 581, 580, 544, and 571. For example, it is preferable to use tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, ruthenium oxide, etc. The conductive material that has the function of suppressing the permeation of impurities such as water and hydrogen may be used in a single layer or a laminate. In addition, it is possible to suppress the mixing of impurities such as water and hydrogen contained in the layer above insulator 576 into the oxide 530 through conductors 540a and 540b.

[0401] As insulators 541a and 541b, any barrier insulating film that can be used for insulator 544 and the like may be used. For example, as insulators 541a and 541b, insulators such as silicon nitride, aluminum oxide, and silicon oxide nitride may be used. Since insulators 541a and 541b are provided in contact with insulators 574, 576, and 571, it is possible to suppress the mixing of impurities such as water and hydrogen contained in insulator 580 and the like into the oxide 530 through conductors 540a and 540b. Silicon nitride is particularly suitable because it has high blocking properties for hydrogen. In addition, it is possible to prevent oxygen contained in insulator 580 from being absorbed by conductors 540a and 540b.

[0402] When the insulators 541a and 541b are arranged in a laminated structure as shown in Figure 22A, it is preferable that the first insulator in contact with the inner wall of the opening, such as the insulator 580, and the second insulator inside it, use a combination of an oxygen barrier insulating film and a hydrogen barrier insulating film.

[0403] For example, aluminum oxide deposited by the ALD method can be used as the first insulator, and silicon nitride deposited by the PEALD method can be used as the second insulator. This configuration suppresses oxidation of the conductor 540 and further reduces the incorporation of hydrogen into the conductor 540.

[0404] While the transistor 500 shows a configuration in which the first insulator and the second conductor of the insulator 541 are stacked, the present invention is not limited thereto. For example, the insulator 541 may be provided as a single layer or as a stacked structure of three or more layers. Similarly, while the transistor 500 shows a configuration in which the first conductor and the second conductor of the conductor 540 are stacked, the present invention is not limited thereto. For example, the conductor 540 may be provided as a single layer or as a stacked structure of three or more layers.

[0405] Furthermore, as shown in Figure 21, conductors 610 and 612, which function as wiring, may be placed in contact with the upper part of conductor 540a and the upper part of conductor 540b. It is preferable that conductors 610 and 612 be made of conductive materials mainly composed of tungsten, copper, or aluminum. The conductors can also be made of laminated material. Specifically, for example, the conductor may be made of titanium, or titanium nitride, laminated with the conductive material. The conductors may also be formed to be embedded in openings provided in the insulator.

[0406] The structure of the transistors included in the semiconductor device of the present invention is not limited to the transistor 500 shown in Figures 21, 22A, 22B, and 23. The structure of the transistors included in the semiconductor device of the present invention may be changed depending on the circumstances.

[0407] For example, the transistor 500 shown in Figures 21, 22A, 22B, and 23 may have the configuration shown in Figure 25. The transistor in Figure 25 differs from the transistor 500 shown in Figures 21, 22A, 22B, and 23 in that it has oxide 543a and oxide 543b. In this specification, oxide 543a and oxide 543b will be collectively referred to as oxide 543. Furthermore, the cross-sectional configuration in the channel width direction of the transistor in Figure 25 can be the same as the cross-sectional configuration of the transistor 500 shown in Figure 22B.

[0408] The oxide 543a is provided between the oxide 530b and the conductor 542a, and the oxide 543b is provided between the oxide 530b and the conductor 542b. Here, it is preferable that the oxide 543a is in contact with the upper surface of the oxide 530b and the lower surface of the conductor 542a. It is also preferable that the oxide 543b is in contact with the upper surface of the oxide 530b and the lower surface of the conductor 542b.

[0409] It is preferable that the oxide 543 has the function of suppressing oxygen permeation. Placing the oxide 543, which has the function of suppressing oxygen permeation, between the conductor 542, which functions as a source electrode or drain electrode, and the oxide 530b is preferable because it reduces the electrical resistance between the conductor 542 and the oxide 530b. With such a configuration, it may be possible to improve the electrical characteristics, field effect mobility, and reliability of the transistor 500.

[0410] Furthermore, a metal oxide containing element M may be used as oxide 543. In particular, element M may be aluminum, gallium, yttrium, or tin. It is also preferable that oxide 543 has a higher concentration of element M than oxide 530b. Gallium oxide may also be used as oxide 543. Furthermore, a metal oxide such as In-M-Zn oxide may be used as oxide 543. Specifically, in the metal oxide used for the oxide, it is preferable that the atomic ratio of element M to In is greater than the atomic ratio of element M to In in the metal oxide used for oxide 530b. Furthermore, the film thickness of oxide 543 is preferably 0.5 nm or more, or 1 nm or more, and preferably 2 nm or less, 3 nm or less, or 5 nm or less. The above-mentioned lower and upper limits can be combined. Furthermore, it is preferable that oxide 543 is crystalline. When oxide 543 is crystalline, the release of oxygen in oxide 530 can be suitably suppressed. For example, if oxide 543 has a hexagonal crystal structure, it may be possible to suppress the release of oxygen from oxide 530.

[0411] An insulator 582 is provided on the insulator 581, and an insulator 586 is provided on the insulator 582.

[0412] It is preferable that the insulator 582 is made of a material that provides a barrier to at least one of oxygen and hydrogen. Therefore, the same material as that used for the insulator 514 can be used for the insulator 582. For example, it is preferable that the insulator 582 be made of a metal oxide such as aluminum oxide, hafnium oxide, or tantalum oxide.

[0413] Furthermore, the insulator 586 can be made of the same material as the insulator 320. Additionally, by applying materials with relatively low dielectric constants to these insulators, parasitic capacitance between wiring can be reduced. For example, a silicon oxide film or a silicon oxynitride film can be used as the insulator 586.

[0414] Next, we will describe the capacitive element 600 and its surrounding wiring or plug, which are included in the semiconductor device shown in Figures 21 and 23. Note that the capacitive element 600, wiring, and / or plug are provided above the transistor 500 shown in Figures 21 and 23.

[0415] The capacitive element 600, for example, includes a conductor 610, a conductor 620, and an insulator 630.

[0416] A conductor 610 is provided on either the conductor 540a or the conductor 540b, the conductor 546, and the insulator 586. The conductor 610 functions as one of the pair of electrodes of the capacitive element 600.

[0417] Furthermore, a conductor 612 is provided on the other of the conductor 540a or conductor 540b, and on the insulator 586. The conductor 612 functions as a plug, wiring, terminal, etc., for electrically connecting the transistor 500 with the wiring or circuit elements above it. Specifically, for example, the conductor 612 can be the wiring WDL in the semiconductor device SDV1 described in Embodiment 3.

[0418] Note that the conductor 612 and the conductor 610 may be formed at the same time.

[0419] The conductors 612 and 610 can be a metal film containing an element selected from molybdenum, titanium, tantalum, tungsten, aluminum, copper, chromium, neodymium, or scandium, or a metal nitride film (tantalum nitride film, titanium nitride film, molybdenum nitride film, tungsten nitride film) composed of the above elements. Alternatively, conductive materials such as indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, or indium tin oxide with silicon oxide added can also be used.

[0420] In Figure 21, the conductors 612 and 610 are shown as single-layer structures, but the configuration is not limited to this, and a laminated structure of two or more layers is also possible. For example, a conductor with high adhesion to both the barrier conductor and the highly conductive conductor may be formed between the barrier conductor and the highly conductive conductor.

[0421] An insulator 630 is provided on the insulator 586 and the conductor 610. The insulator 630 functions as a dielectric sandwiched between the pair of electrodes of the capacitive element 600.

[0422] Examples of insulators 630 include silicon oxide, silicon oxide nitride, silicon oxide nitride, silicon nitride, aluminum oxide, aluminum oxide nitride, aluminum oxide nitride, aluminum nitride, hafnium oxide, hafnium oxide nitride, hafnium oxide nitride, hafnium nitride, zirconium oxide, and others. The insulator 630 can also be provided as a laminate or a single layer using the materials described above.

[0423] Furthermore, for example, the insulator 630 may be a laminated structure of a material with high dielectric strength, such as silicon oxidnitride, and a high dielectric constant (high-k) material. With this configuration, the capacitive element 600 can secure sufficient capacitance by having a high dielectric constant (high-k) insulator, and the dielectric strength is improved by having an insulator with high dielectric strength, thereby suppressing electrostatic discharge breakdown of the capacitive element 600.

[0424] Examples of high-dielectric constant (high-k) materials (materials with a high relative permittivity) that serve as insulators include gallium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium, oxidized nitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxidized nitrides containing silicon and hafnium, or nitrides containing silicon and hafnium.

[0425] Alternatively, the insulator 630 may be a single-layer or multi-layer insulator containing a high-k material such as aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO3), or (Ba,Sr)TiO3 (BST). Furthermore, as the insulator 630, a compound containing hafnium and zirconium, such as an oxide containing zirconium and hafnium, may be used. As semiconductor devices become more miniaturized and integrated, thinning of the dielectric material used in gate insulators and capacitive elements can lead to problems such as leakage current in transistors and capacitive elements. By using a high-k material as the insulator functioning as the dielectric material for gate insulators and capacitive elements, it becomes possible to reduce the gate potential during transistor operation and ensure the capacitance of capacitive elements while maintaining the physical film thickness.

[0426] Furthermore, a ferroelectric material may be used as the insulator 630. Examples include a mixed crystal of hafnium oxide and zirconium oxide (also called "HZO"), or a material obtained by adding element X (element X being silicon (Si), aluminum (Al), gadolinium (Gd), yttrium (Y), lanthanum (La), strontium (Sr), etc.) to hafnium oxide. Alternatively, a piezoelectric ceramic having a perovskite structure may be used as the insulator 630. Examples include lead zirconate titanate (PZT), strontium bismuth tantalate (SBT), bismuth ferrite (BFO), or barium titanate.

[0427] A conductor 620 is provided so as to be superimposed on the conductor 610 via an insulator 630. The conductor 610 functions as one of a pair of electrodes of the capacitive element 600. Alternatively, the conductor 620 can be, for example, a wiring WWLB in the semiconductor device SDV1 described in Embodiment 3.

[0428] The conductor 620 can be made of conductive materials such as metal materials, alloy materials, or metal oxide materials. It is preferable to use a high-melting-point material containing at least one of the following, such as tungsten and molybdenum, which provides both heat resistance and conductivity, and it is particularly preferable to use tungsten. When forming it simultaneously with other structures such as conductors, at least one of the following, which are low-resistance metallic materials, such as Cu (copper) and Al (aluminum), may be used. For example, the conductor 620 can be made of a material that is applicable to the conductor 610. Furthermore, the conductor 620 may be a laminated structure of two or more layers, rather than a single-layer structure.

[0429] An insulator 640 is provided on the conductor 620 and the insulator 630. For the insulator 640, it is preferable to use a film with barrier properties that prevents the diffusion of impurities such as hydrogen into the region where the transistor 500 is provided. Therefore, the same material as that used for the insulator 324 can be used.

[0430] An insulator 650 is provided on the insulator 640. The insulator 650 can be provided using the same material as the insulator 320. The insulator 650 may also function as a planarizing film that covers the uneven shape below it. Therefore, the insulator 650 can be made of a material that can be applied to, for example, the insulator 324.

[0431] Incidentally, although the capacitive element 600 shown in Figures 21 and 23 is of the planar type, the shape of the capacitive element is not limited to this. The capacitive element 600 may be of a cylindrical type, for example, instead of a planar type.

[0432] Furthermore, a wiring layer may be provided above the capacitive element 600. For example, in Figure 21, insulators 411, 412, 413, and 414 are provided in order above the insulator 650. The figure also shows a configuration in which a conductor 416, which functions as a plug or wiring, is provided on insulators 411, 412, and 413. In addition, the conductor 416 can be provided in a region that overlaps with the conductor 660, which will be described later, as an example.

[0433] Furthermore, the insulators 630, 640, and 650 are provided with openings in the regions that overlap with the conductor 612, and the conductor 660 is provided to fill these openings. The conductor 660 functions as a plug and wiring that electrically connects to the conductor 416 included in the wiring layer described above.

[0434] It is preferable that insulators 411 and 414 be insulators that have barrier properties against impurities, such as water and hydrogen, similar to insulator 324. Therefore, materials applicable to insulator 324, for example, can be used as insulators 411 and 414.

[0435] For insulators 412 and 413, it is preferable to use insulators with a relatively low dielectric constant, similar to insulator 326, in order to reduce parasitic capacitance between the wires.

[0436] Furthermore, the conductor 612 and the conductor 416 can be provided using, for example, the same materials as the conductor 328 and the conductor 330.

[0437] By applying the structure described in this embodiment to a semiconductor device using a transistor having an oxide semiconductor, it is possible to suppress fluctuations in the electrical characteristics of the transistor and improve its reliability. Alternatively, miniaturization or high integration can be achieved in a semiconductor device using a transistor having an oxide semiconductor.

[0438] This embodiment can be appropriately combined with other embodiments shown in this specification.

[0439] (Embodiment 7) This embodiment describes metal oxides (hereinafter also referred to as oxide semiconductors) that can be used in the OS transistor described in the above embodiment.

[0440] The metal oxide preferably contains at least indium or zinc. It is particularly preferable that it contains indium and zinc. In addition, it is preferable that it contains aluminum, gallium, yttrium, tin, etc. It may also contain one or more selected from boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, cobalt, etc.

[0441] <Classification of crystal structures> First, we will explain the classification of crystal structures in oxide semiconductors using Figure 26A. Figure 26A is a diagram illustrating the classification of crystal structures in oxide semiconductors, specifically IGZO (a metal oxide containing In, Ga, and Zn).

[0442] As shown in Figure 26A, oxide semiconductors are broadly classified into "Amorphous," "Crystalline," and "Crystal." "Amorphous" includes completely amorphous semiconductors. "Crystalline" includes CAAC (c-axis-aligned crystalline), nc (nanocrystalline), and CAC (Cloud-Aligned Composite). Note that single crystal, polycrystal, and completely amorphous semiconductors are excluded from the "Crystalline" classification. "Crystal" includes single crystal and polycrystal semiconductors.

[0443] The structure within the thick frame shown in Figure 26A represents an intermediate state between "Amorphous" and "Crystal," and belongs to a new boundary region (New crystalline phase). In other words, this structure can be described as being completely different from the energetically unstable "Amorphous" and "Crystal" states.

[0444] The crystal structure of a film or substrate can be evaluated using X-ray diffraction (XRD) spectroscopy. Figure 26B shows the XRD spectrum obtained by GIXD (Grazing-Incidence XRD) measurement of a CAAC-IGZO film classified as "Crystalline." The GIXD method is also known as the thin-film method or Seemann-Bohlin method. Hereafter, the XRD spectrum obtained by the GIXD measurement shown in Figure 26B will simply be referred to as the XRD spectrum. The composition of the CAAC-IGZO film shown in Figure 26B is approximately In:Ga:Zn = 4:2:3 [atomic ratio]. The thickness of the CAAC-IGZO film shown in Figure 26B is 500 nm.

[0445] As shown in Figure 26B, the XRD spectrum of the CAAC-IGZO film shows a peak indicating clear crystallinity. Specifically, the XRD spectrum of the CAAC-IGZO film shows a peak indicating c-axis orientation near 2θ=31°. As shown in Figure 26B, the peak near 2θ=31° is asymmetrical with respect to the angle at which the peak intensity was detected.

[0446] Furthermore, the crystal structure of a film or substrate can be evaluated by the diffraction pattern (also called the nano-beam electron diffraction pattern) observed by nano-beam electron diffraction (NBED). The diffraction pattern of a CAAC-IGZO film is shown in Figure 26C. Figure 26C shows the diffraction pattern observed by NBED with the electron beam incident parallel to the substrate. The composition of the CAAC-IGZO film shown in Figure 26C is approximately In:Ga:Zn=4:2:3 [atomic ratio]. In nano-beam electron diffraction, electron diffraction is performed with a probe diameter of 1 nm.

[0447] As shown in Figure 26C, the diffraction pattern of the CAAC-IGZO film shows multiple spots indicating c-axis orientation.

[0448] <<Oxide semiconductor structure>> Note that when focusing on the crystal structure, oxide semiconductors may be classified differently from those shown in Figure 26A. For example, oxide semiconductors can be divided into single-crystal oxide semiconductors and other non-single-crystal oxide semiconductors. Examples of non-single-crystal oxide semiconductors include the aforementioned CAAC-OS and nc-OS. Non-single-crystal oxide semiconductors also include polycrystalline oxide semiconductors, pseudo-amorphous oxide semiconductors (a-like OS), and amorphous oxide semiconductors.

[0449] Here, we will explain the details of the CAAC-OS, nc-OS, and a-like OS mentioned above.

[0450] [CAAC-OS] CAAC-OS is an oxide semiconductor having multiple crystalline regions, the c-axis of which is oriented in a specific direction. This specific direction is the thickness direction of the CAAC-OS film, the normal direction to the surface on which the CAAC-OS film is formed, or the normal direction to the surface of the CAAC-OS film. A crystalline region is a region with periodic atomic arrangement. If we consider the atomic arrangement as a lattice arrangement, then a crystalline region is also a region with a aligned lattice arrangement. Furthermore, CAAC-OS has regions where multiple crystalline regions are connected in the ab-plane direction, and these regions may exhibit distortion. Distortion refers to a point in the connected region where the orientation of the lattice arrangement changes between a region with a aligned lattice arrangement and another region with a aligned lattice arrangement. In short, CAAC-OS is an oxide semiconductor that is c-axis oriented and does not exhibit clear orientation in the ab-plane direction.

[0451] Each of the multiple crystalline regions described above is composed of one or more minute crystals (crystals with a maximum diameter of less than 10 nm). When a crystalline region is composed of a single minute crystal, the maximum diameter of that crystalline region is less than 10 nm. When a crystalline region is composed of many minute crystals, the size of that crystalline region may be around several tens of nanometers.

[0452] Furthermore, in In-M-Zn oxides (where element M is one or more elements selected from aluminum, gallium, yttrium, tin, titanium, etc.), CAAC-OS tends to have a layered crystalline structure (also called a layered structure) consisting of layers containing indium (In) and oxygen (hereinafter referred to as the In layer) and layers containing element M, zinc (Zn), and oxygen (hereinafter referred to as the (M,Zn) layer). Note that indium and element M are mutually substitutable. Therefore, the (M,Zn) layer may contain indium. Also, the In layer may contain element M. Also, the In layer may contain Zn. This layered structure can be observed, for example, as a lattice image in high-resolution TEM images.

[0453] When structural analysis of a CAAC-OS film is performed using an XRD instrument, for example, out-of-plane XRD measurements using θ / 2θ scanning show a peak indicating c-axis orientation at 2θ = 31° or nearby. Note that the position of the c-axis orientation peak (value of 2θ) may vary depending on the type and composition of the metal elements constituting the CAAC-OS.

[0454] Furthermore, for example, multiple bright spots are observed in the electron diffraction pattern of a CAAC-OS film. These spots are observed at point-symmetric positions with respect to the incident electron beam spot (also called the direct spot) that passed through the sample.

[0455] When the crystal region is observed from the specific direction described above, the lattice arrangement within that crystal region is based on a hexagonal lattice, but the unit cell is not necessarily a regular hexagon and may be non-regular hexagonal. Furthermore, the strain may have lattice arrangements such as pentagons or heptagons. Moreover, in CAAC-OS, clear grain boundaries cannot be observed even near the strain. In other words, it can be seen that the formation of grain boundaries is suppressed by the strain in the lattice arrangement. This is thought to be because CAAC-OS can tolerate strain due to the fact that the arrangement of oxygen atoms is not dense in the ab-plane direction, and the bond distance between atoms changes due to the substitution of metal atoms.

[0456] A crystal structure in which clear grain boundaries are observed is called a polycrystal. Grain boundaries act as recombination centers, trapping carriers and potentially causing a decrease in transistor on-current and field-effect mobility. Therefore, CAAC-OS, in which clear grain boundaries are not observed, is one of the crystalline oxides with a suitable crystal structure for the semiconductor layer of a transistor. In addition, a structure containing Zn is preferred for the composition of CAAC-OS. For example, In-Zn oxide and In-Ga-Zn oxide are preferred because they suppress the generation of grain boundaries more than In oxide.

[0457] CAAC-OS is an oxide semiconductor with high crystallinity and no clearly defined grain boundaries. Therefore, CAAC-OS is less susceptible to the decrease in electron mobility caused by grain boundaries. Furthermore, since the crystallinity of oxide semiconductors can decrease due to the inclusion of impurities or the generation of defects, CAAC-OS can be said to be an oxide semiconductor with few impurities and defects (such as oxygen vacancies). Consequently, oxide semiconductors containing CAAC-OS have stable physical properties. Therefore, oxide semiconductors containing CAAC-OS are heat-resistant and highly reliable. In addition, CAAC-OS is stable even at high temperatures (so-called thermal budget) during the manufacturing process. Therefore, using CAAC-OS in OS transistors allows for greater flexibility in the manufacturing process.

[0458] [nc-OS] nc-OS exhibits periodicity in atomic arrangement in minute regions (e.g., regions between 1 nm and 10 nm, particularly between 1 nm and 3 nm). In other words, nc-OS contains minute crystals. These minute crystals are also called nanocrystals because their size is, for example, between 1 nm and 10 nm, particularly between 1 nm and 3 nm. Furthermore, nc-OS shows no regularity in crystal orientation between different nanocrystals. Therefore, no orientation is observed throughout the film. Consequently, depending on the analytical method, nc-OS may be indistinguishable from a-like OS and amorphous oxide semiconductors. For example, when structural analysis of an nc-OS film is performed using an XRD instrument, no peaks indicating crystallinity are detected in out-of-plane XRD measurements using θ / 2θ scanning. Also, when electron diffraction (also called limited-field electron diffraction) is performed on an nc-OS film using an electron beam with a probe diameter larger than that of the nanocrystals (e.g., 50 nm or larger), a diffraction pattern resembling a halo pattern is observed. On the other hand, when electron diffraction (also called nanobeam electron diffraction) is performed on an nc-OS film using an electron beam with a probe diameter close to or smaller than the size of the nanocrystal (for example, 1 nm to 30 nm), an electron diffraction pattern may be obtained in which multiple spots are observed within a ring-shaped region centered on a direct spot.

[0459] [a-like OS] a-like OS is an oxide semiconductor having a structure between nc-OS and amorphous oxide semiconductors. a-like OS has porous or low-density regions. That is, a-like OS has lower crystallinity compared to nc-OS and CAAC-OS. Also, a-like OS has a higher hydrogen concentration in the film compared to nc-OS and CAAC-OS.

[0460] <<Oxide Semiconductor Composition>> Next, we will explain the details of CAC-OS mentioned above. Note that CAC-OS refers to the material composition.

[0461] [CAC-OS] CAC-OS is a material composition in which, for example, the elements constituting the metal oxide are unevenly distributed in sizes of 0.5 nm to 10 nm, preferably 1 nm to 3 nm, or close to that size. In the following, a state in which one or more metal elements are unevenly distributed in a metal oxide, and the regions containing these metal elements are mixed in sizes of 0.5 nm to 10 nm, preferably 1 nm to 3 nm, or close to that size, is also referred to as a mosaic or patchy state.

[0462] Furthermore, CAC-OS is a composite metal oxide having a mosaic-like structure formed by the separation of the material into a first region and a second region, with the first region distributed within the film (hereinafter also referred to as a cloud-like structure). In other words, CAC-OS is a composite metal oxide having a structure in which the first region and the second region are mixed.

[0463] Here, the atomic ratios of In, Ga, and Zn to the metal elements constituting the CAC-OS in In-Ga-Zn oxide are denoted as [In], [Ga], and [Zn], respectively. For example, in the CAC-OS of In-Ga-Zn oxide, the first region is the region where [In] is greater than the [In] in the composition of the CAC-OS film. The second region is the region where [Ga] is greater than the [Ga] in the composition of the CAC-OS film. Alternatively, for example, the first region is the region where [In] is greater than the [In] in the second region, and [Ga] is smaller than the [Ga] in the second region. The second region is the region where [Ga] is greater than the [Ga] in the first region, and [In] is smaller than the [In] in the first region.

[0464] Specifically, the first region described above is a region whose main components are indium oxide, indium zinc oxide, etc. The second region described above is a region whose main components are gallium oxide, gallium zinc oxide, etc. In other words, the first region can be rephrased as a region whose main component is In. Similarly, the second region can be rephrased as a region whose main component is Ga.

[0465] Furthermore, a clear boundary may not be observed between the first region and the second region described above.

[0466] For example, in the case of CAC-OS in In-Ga-Zn oxide, EDX mapping obtained using energy dispersive X-ray spectroscopy (EDX) confirms that it has a structure in which regions mainly composed of In (first region) and regions mainly composed of Ga (second region) are unevenly distributed and mixed.

[0467] When CAC-OS is used in a transistor, the conductivity due to the first region and the insulation due to the second region work complementaryly to give CAC-OS a switching function (on / off function). In other words, CAC-OS has conductive function in part of the material, insulating function in part of the material, and semiconductor function as a whole. By separating the conductive function and the insulating function, both functions can be maximized. Therefore, by using CAC-OS in a transistor, a high on-current (I) can be achieved. on This enables high field-effect mobility (μ) and good switching operation.

[0468] Oxide semiconductors can take on diverse structures, each possessing different properties. One embodiment of the present invention may include two or more of the following: amorphous oxide semiconductors, polycrystalline oxide semiconductors, a-like OS, CAC-OS, nc-OS, and CAAC-OS.

[0469] <Transistors containing oxide semiconductors> Next, we will explain the case where the above oxide semiconductor is used in a transistor.

[0470] By using the above-mentioned oxide semiconductor in transistors, it is possible to realize transistors with high field-effect mobility. Furthermore, it is possible to realize highly reliable transistors.

[0471] It is preferable to use an oxide semiconductor with a low carrier concentration for the transistor. For example, the carrier concentration of an oxide semiconductor is 1 × 10⁻⁶. 17 cm -3 The following is preferably 1 × 10 15 cm -3 More preferably 1 × 10 13 cm -3 More preferably 1 × 10 11 cm -3 More preferably 1 × 10 10 cm -3 It is less than 1 × 10 -9 cm-3 This concludes the explanation. Furthermore, when lowering the carrier concentration of an oxide semiconductor film, the impurity concentration in the oxide semiconductor film should be lowered to reduce the defect level density. In this specification, a low impurity concentration and low defect level density are referred to as high-purity intrinsic or substantially high-purity intrinsic. Note that oxide semiconductors with low carrier concentrations may also be referred to as high-purity intrinsic or substantially high-purity intrinsic oxide semiconductors.

[0472] Furthermore, oxide semiconductor films that are highly pure or substantially highly pure have a low defect level density, which may result in a low trap level density.

[0473] Furthermore, charges trapped in the trap levels of oxide semiconductors can take a long time to disappear, sometimes behaving like fixed charges. Therefore, transistors in which channel formation regions are formed in oxide semiconductors with a high trap level density may exhibit unstable electrical properties.

[0474] Therefore, reducing the impurity concentration in the oxide semiconductor is effective in stabilizing the electrical characteristics of the transistor. Furthermore, in order to reduce the impurity concentration in the oxide semiconductor, it is preferable to also reduce the impurity concentration in adjacent films. Examples of impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, and silicon.

[0475] <Impurities> Here, we will explain the effects of various impurities in oxide semiconductors.

[0476] In oxide semiconductors, if at least one of the Group 14 elements, silicon and carbon, is present, defect levels are formed in the oxide semiconductor. Therefore, the concentration of at least one of silicon and carbon in the oxide semiconductor and the concentration of at least one of silicon and carbon near the interface with the oxide semiconductor (concentrations obtained by secondary ion mass spectrometry (SIMS)) are calculated as 2 × 10⁻¹⁰. 18 atoms / cm 3The following is preferably 2 × 10 17 atoms / cm 3 The following applies:

[0477] Furthermore, if an oxide semiconductor contains alkali metals or alkaline earth metals, it may form defect levels and generate carriers. Therefore, transistors using oxide semiconductors containing alkali metals or alkaline earth metals tend to exhibit normally-on characteristics. For this reason, the concentration of alkali metals or alkaline earth metals in the oxide semiconductor obtained by SIMS should be set to 1 × 10⁻⁶. 18 atoms / cm 3 The following is preferably 2 × 10 16 atoms / cm 3 Do the following:

[0478] Furthermore, in oxide semiconductors, the presence of nitrogen generates electrons, which act as carriers, increasing the carrier concentration and making it easier for the semiconductor to become n-type. As a result, transistors using oxide semiconductors containing nitrogen tend to exhibit normally-on characteristics. Alternatively, the presence of nitrogen in oxide semiconductors can lead to the formation of trap levels. As a result, the electrical properties of the transistor may become unstable. For this reason, the nitrogen concentration in oxide semiconductors obtained by SIMS should be set to 5 × 10⁻⁶. 19 atoms / cm 3 Less than 5 × 10 18 atoms / cm 3 More preferably 1 × 10 18 atoms / cm 3 More preferably 5 × 10 17 atoms / cm 3 Do the following:

[0479] Furthermore, hydrogen contained in oxide semiconductors can react with oxygen bonded to metal atoms to form water, potentially creating oxygen vacancies. Hydrogen can then fill these vacancies, generating electrons, which act as carriers. Additionally, some of the hydrogen can combine with oxygen bonded to metal atoms to generate electrons. Therefore, transistors using oxide semiconductors containing hydrogen tend to exhibit normally-on characteristics. For this reason, it is preferable to reduce the hydrogen content in oxide semiconductors as much as possible. Specifically, in oxide semiconductors, the hydrogen concentration obtained by SIMS should be 1 × 10⁻⁶. 20 atoms / cm 3 Less than 1 × 10 19 atoms / cm 3 Less than 5x10 18 atoms / cm 3 Less than 1 × 10 18 atoms / cm 3 Make it less than.

[0480] By using an oxide semiconductor with sufficiently reduced impurities in the channel formation region of a transistor, stable electrical characteristics can be provided.

[0481] This embodiment can be appropriately combined with other embodiments shown in this specification.

[0482] (Embodiment 8) This embodiment shows an example of a semiconductor wafer on which the semiconductor device shown in the above embodiment is formed, and an example of an electronic component into which the semiconductor device is incorporated.

[0483] <Semiconductor wafers> First, an example of a semiconductor wafer on which semiconductor devices are formed will be explained using Figure 27A.

[0484] The semiconductor wafer 4800 shown in Figure 27A comprises a wafer 4801 and a plurality of circuit sections 4802 provided on the upper surface of the wafer 4801. The portion of the upper surface of the wafer 4801 without circuit sections 4802 is the spacing 4803, which is the region for dicing.

[0485] The semiconductor wafer 4800 can be manufactured by forming multiple circuit sections 4802 on the surface of wafer 4801 in a previous process. Alternatively, the opposite side of wafer 4801 from where the circuit sections 4802 are formed may be ground to thin the wafer 4801. This process reduces warping of the wafer 4801, enabling miniaturization of the component.

[0486] The next step is the dicing process. Dicing is performed along the scribe lines SCL1 and SCL2 (sometimes referred to as dicing lines or cutting lines) indicated by the dashed lines. In order to facilitate the dicing process, it is preferable that the spacing 4803 be arranged so that multiple scribe lines SCL1 are parallel, multiple scribe lines SCL2 are parallel, and scribe lines SCL1 and SCL2 are perpendicular.

[0487] By performing the dicing process, a chip 4800a, as shown in Figure 27B, can be cut from the semiconductor wafer 4800. The chip 4800a has a wafer 4801a, a circuit section 4802, and spacing 4803a. It is preferable to make the spacing 4803a as small as possible. In this case, the width of the spacing 4803 between adjacent circuit sections 4802 should be approximately the same length as the cutting allowance of the scribe line SCL1 or the cutting allowance of the scribe line SCL2.

[0488] The shape of the element substrate in one embodiment of the present invention is not limited to the shape of the semiconductor wafer 4800 shown in Figure 27A. For example, it may be a rectangular semiconductor wafer. The shape of the element substrate can be appropriately changed depending on the manufacturing process of the element and the apparatus for manufacturing the element.

[0489] <Electronic Components> Figure 27C shows a perspective view of the electronic component 4700 and the circuit board (mounted board 4704) on which the electronic component 4700 is mounted. The electronic component 4700 shown in Figure 27C has a chip 4800a within a mold 4711. As shown in Figure 27C, the chip 4800a may have a configuration in which circuit sections 4802 are stacked. Figure 27C omits some parts to show the inside of the electronic component 4700. The electronic component 4700 has a land 4712 on the outside of the mold 4711. The land 4712 is electrically connected to an electrode pad 4713, and the electrode pad 4713 is electrically connected to the chip 4800a by a wire 4714. The electronic component 4700 is mounted, for example, on a printed circuit board 4702. Multiple such electronic components are combined and electrically connected on the printed circuit board 4702 to complete the mounted board 4704.

[0490] Figure 27D shows a perspective view of electronic component 4730. Electronic component 4730 is an example of a SiP (System in package) or MCM (Multi Chip Module). Electronic component 4730 has an interposer 4731 on a package substrate 4732 (printed circuit board), and a semiconductor device 4735 and multiple semiconductor devices 4710 are provided on the interposer 4731.

[0491] Electronic component 4730 includes a semiconductor device 4710. The semiconductor device 4710 can be, for example, the semiconductor device described in the above embodiment, or a high-bandwidth memory (HBM). Furthermore, the semiconductor device 4735 can be an integrated circuit (semiconductor device) such as a CPU, GPU, FPGA, or memory device.

[0492] The package substrate 4732 can be a ceramic substrate, a plastic substrate, or a glass epoxy substrate, etc. The interposer 4731 can be a silicon interposer, a resin interposer, etc.

[0493] The interposer 4731 has multiple wirings and functions to electrically connect multiple integrated circuits with different terminal pitches. The multiple wirings are provided in a single layer or multiple layers. The interposer 4731 also functions to electrically connect integrated circuits provided on the interposer 4731 to electrodes provided on the package substrate 4732. For these reasons, the interposer is sometimes referred to as a "redistribution substrate" or "intermediate substrate." In addition, through electrodes may be provided on the interposer 4731, and these through electrodes may be used to electrically connect the integrated circuits and the package substrate 4732. Furthermore, in silicon interposers, TSVs (Through Silicon Vias) can be used as through electrodes.

[0494] It is preferable to use a silicon interposer as the interposer 4731. Since silicon interposers do not require active elements, they can be manufactured at a lower cost than integrated circuits. On the other hand, since the wiring of a silicon interposer can be formed using a semiconductor process, it is easy to form fine wiring, which is difficult with resin interposers.

[0495] In HBMs, many connections are necessary to achieve a wide memory bandwidth. Therefore, the interposer on which the HBM is mounted requires fine and high-density wiring. For this reason, it is preferable to use a silicon interposer for mounting the HBM.

[0496] Furthermore, in SiP or MCM using silicon interposers, reliability degradation due to differences in expansion coefficients between the integrated circuit and the interposer is less likely to occur. In addition, because silicon interposers have high surface flatness, connection failures between the integrated circuit and the silicon interposer are less likely to occur. In particular, in 2.5D packages (2.5-dimensional packaging) where multiple integrated circuits are arranged side by side on the interposer, it is preferable to use a silicon interposer.

[0497] Alternatively, a heat sink (heat dissipation plate) may be provided on top of the electronic component 4730. If a heat sink is provided, it is preferable to align the heights of the integrated circuits provided on the interposer 4731. For example, in the electronic component 4730 shown in this embodiment, it is preferable to align the heights of the semiconductor device 4710 and the semiconductor device 4735.

[0498] To mount the electronic component 4730 onto another substrate, electrodes 4733 may be provided at the bottom of the package substrate 4732. Figure 27D shows an example where electrodes 4733 are formed with solder balls. By providing solder balls in a matrix at the bottom of the package substrate 4732, BGA (Ball Grid Array) mounting can be achieved. Alternatively, electrodes 4733 may be formed with conductive pins. By providing conductive pins in a matrix at the bottom of the package substrate 4732, PGA (Pin Grid Array) mounting can be achieved.

[0499] The electronic component 4730 can be mounted on other boards using various mounting methods, not limited to BGA and PGA. For example, mounting methods such as SPGA (Staggered Pin Grid Array), LGA (Land Grid Array), QFP (Quad Flat Package), QFJ (Quad Flat J-leaded package), or QFN (Quad Flat Non-leaded package) can be used.

[0500] This embodiment can be appropriately combined with other embodiments shown in this specification.

[0501] (Embodiment 9) This embodiment describes an example of an electronic device having the semiconductor device described in the above embodiment. Figure 28 illustrates how the electronic component 4700 having the semiconductor device is included in each electronic device.

[0502] [mobile phone] The information terminal 5500 shown in Figure 28 is a type of information terminal, specifically a mobile phone (smartphone). The information terminal 5500 has a housing 5510 and a display unit 5511. For input interfaces, a touch panel is provided on the display unit 5511, and buttons are provided on the housing 5510.

[0503] The information terminal 5500 can execute applications utilizing artificial intelligence by applying the semiconductor device described in the above embodiment. Examples of applications utilizing artificial intelligence include applications that recognize conversations and display the content of those conversations on the display unit 5511, applications that recognize characters, figures, etc., entered by the user on the touch panel provided on the display unit 5511 and display them on the display unit 5511, and applications that perform at least one biometric authentication such as fingerprints and voiceprints.

[0504] [Wearable devices] Figure 28 also shows a wristwatch-type information terminal 5900 as an example of a wearable device. The information terminal 5900 includes a housing 5901, a display unit 5902, operation buttons 5903, a control element 5904, a band 5905, and the like.

[0505] Similar to the information terminal 5500 mentioned above, wearable devices can run applications utilizing artificial intelligence by applying the semiconductor device described in the above embodiment. Examples of applications utilizing artificial intelligence include applications that manage the health status of a person wearing the wearable device, and navigation systems that select and guide the user along the optimal route based on the destination input.

[0506] [Information terminal] Figure 28 also illustrates a desktop information terminal 5300. The desktop information terminal 5300 comprises a main unit 5301, a display 5302, and a keyboard 5303.

[0507] The desktop information terminal 5300, like the information terminal 5500 mentioned above, can run applications utilizing artificial intelligence by applying the semiconductor device described in the above embodiment. Examples of applications utilizing artificial intelligence include design support software, document editing software, and automatic menu generation software. Furthermore, the desktop information terminal 5300 can be used to develop new artificial intelligence.

[0508] In the above, smartphones, desktop information terminals, and wearable devices were used as examples of electronic devices and illustrated in Figure 28, but other information devices can also be applied. Examples of information devices other than smartphones, desktop information terminals, and wearable devices include PDAs (Personal Digital Assistants), notebook computers, and workstations.

[0509] [electric appliances] Figure 28 also shows an electric refrigerator-freezer 5800 as an example of an electrical appliance. The electric refrigerator-freezer 5800 has a casing 5801, a refrigerator door 5802, a freezer door 5803, etc.

[0510] By applying the semiconductor device described in the above embodiment to the electric refrigerator 5800, an electric refrigerator 5800 with artificial intelligence can be realized. By utilizing artificial intelligence, the electric refrigerator 5800 can have at least one of the following functions: a function to automatically generate menus based on the ingredients stored in the electric refrigerator 5800 and their expiration dates, and a function to automatically adjust the temperature to suit the ingredients stored in the electric refrigerator 5800.

[0511] In this example, an electric refrigerator was described as an electrical appliance, but other electrical appliances include, for example, vacuum cleaners, microwave ovens, electric ovens, rice cookers, water heaters, induction heating (IH) cookers, water dispensers, heating and cooling appliances including air conditioners, washing machines, dryers, and audio-visual equipment.

[0512] [Game console] Figure 28 also shows a portable game console 5200, which is an example of a game console. The portable game console 5200 has a casing 5201, a display unit 5202, buttons 5203, etc.

[0513] Furthermore, Figure 28 illustrates a home console 7500, which is an example of a game console. The home console 7500 has a main unit 7520 and a controller 7522. The controller 7522 can be connected to the main unit 7520 wirelessly or via a wired connection. Although not shown in Figure 28, the controller 7522 may include at least one of the following: a display unit for displaying game images, a touch panel as an input interface other than buttons, a joystick, a rotary knob, and a sliding knob. Moreover, the controller 7522 is not limited to the shape shown in Figure 28, and its shape may be changed in various ways depending on the genre of game. For example, in shooting games such as FPS (First Person Shooter), a controller with triggers as buttons and shaped like a gun can be used. Also, for example, in music games, a controller shaped like a musical instrument or musical equipment can be used. Furthermore, home game consoles may not use controllers, but instead be equipped with cameras, depth sensors, microphones, etc., and operated by the game player's gestures and / or voice.

[0514] Furthermore, the video from the aforementioned game console can be output by display devices such as television sets, personal computer displays, game displays, and head-mounted displays.

[0515] By applying the semiconductor device described in the above embodiment to the portable game console 5200, a low-power portable game console 5200 can be realized. Furthermore, because the low power consumption reduces heat generation from the circuit, the impact of heat on the circuit itself, peripheral circuits, and modules can be minimized.

[0516] Furthermore, by applying the semiconductor device described in the above embodiment to the portable game console 5200, a portable game console 5200 with artificial intelligence can be realized.

[0517] Normally, the progression of a game, the behavior of creatures appearing in the game, and the phenomena that occur in the game are determined by the game's program. However, by applying artificial intelligence to the 5200 handheld game console, it becomes possible to express things that are not limited to the game's program. For example, it becomes possible to express changes in the content of questions asked by the player, the game's progress, the time, and the behavior of characters appearing in the game.

[0518] Furthermore, when playing games that require multiple players on the 5200 handheld game console, artificial intelligence can be used to create anthropomorphic game players. By using AI-generated game players as opponents, it becomes possible to play the game even by a single player.

[0519] Figure 28 illustrates a portable game console as an example of a game console, but the electronic devices of one aspect of the present invention are not limited to this. Examples of electronic devices of one aspect of the present invention include home game consoles, arcade game machines installed in entertainment facilities (game centers, amusement parks, etc.), and pitching machines for batting practice installed in sports facilities.

[0520] [Mobile] The semiconductor device described in the above embodiment can be applied to a mobile vehicle and the area around the driver's seat of the vehicle.

[0521] Figure 28 shows an example of a mobile device, the automobile 5700.

[0522] The driver's seat area of ​​the automobile 5700 is equipped with an instrument panel capable of displaying at least one of the following: a speedometer, tachometer, odometer, fuel gauge, gear status, and air conditioning settings. A display device for showing this information may also be provided around the driver's seat.

[0523] In particular, by displaying images from an imaging device (not shown) installed in the automobile 5700, the display device can compensate for obstructed views from pillars and other obstructions, as well as blind spots in the driver's seat, thereby enhancing safety. In other words, by displaying images from an imaging device installed on the outside of the automobile 5700, blind spots can be compensated for, and safety can be enhanced.

[0524] Since the semiconductor device described in the above embodiment can be applied as a component of artificial intelligence, for example, it can be used in an autonomous driving system for automobile 5700. Furthermore, it can be used in systems that perform road guidance, hazard prediction, and the like. The display device may be configured to display information such as road guidance and hazard prediction.

[0525] Although automobiles are described above as an example of a mobile device, mobile devices are not limited to automobiles. For example, mobile devices can also include trains, monorails, ships, and flying objects (helicopters, unmanned aerial vehicles (drones), airplanes, rockets), and a semiconductor device according to one aspect of the present invention can be applied to these mobile devices to provide them with a system utilizing artificial intelligence.

[0526] [camera] The semiconductor device described in the above embodiment can be applied to a camera.

[0527] Figure 28 shows a digital camera 6240, which is an example of an imaging device. The digital camera 6240 has a housing 6241, a display unit 6242, operation buttons 6243, a shutter button 6244, etc., and a detachable lens 6246 is attached to the digital camera 6240. In this example, the digital camera 6240 is configured so that the lens 6246 can be removed from the housing 6241 and replaced, but the lens 6246 and housing 6241 may be integrated. Furthermore, the digital camera 6240 may be configured to allow for the attachment of at least one additional device, such as a strobe device and a viewfinder.

[0528] By applying the semiconductor device described in the above embodiment to the digital camera 6240, a low-power digital camera 6240 can be realized. Furthermore, because the low power consumption reduces heat generation from the circuit, the impact of heat on the circuit itself, peripheral circuits, and modules can be minimized.

[0529] Furthermore, by applying the semiconductor device described in the above embodiment to the digital camera 6240, a digital camera 6240 with artificial intelligence can be realized. By utilizing artificial intelligence, the digital camera 6240 can have functions such as automatically recognizing subjects such as faces and objects, adjusting the focus according to the subject, automatically firing the flash according to the environment, and toning the color of captured images.

[0530] [Video camera] The semiconductor device described in the above embodiment can be applied to a video camera.

[0531] Figure 28 shows a video camera 6300, which is an example of an imaging device. The video camera 6300 includes a first housing 6301, a second housing 6302, a display unit 6303, operation keys 6304, a lens 6305, a connection unit 6306, etc. The operation keys 6304 and the lens 6305 are provided in the first housing 6301, and the display unit 6303 is provided in the second housing 6302. The first housing 6301 and the second housing 6302 are connected by the connection unit 6306, and the angle between the first housing 6301 and the second housing 6302 can be changed by the connection unit 6306. The image on the display unit 6303 may be switched according to the angle between the first housing 6301 and the second housing 6302 at the connection unit 6306.

[0532] When recording video captured with the 6300 video camera, encoding is required according to the data recording format. By utilizing artificial intelligence, the 6300 video camera can perform AI-based pattern recognition during encoding. This pattern recognition allows the camera to calculate differential data for people, animals, objects, etc., contained in consecutive captured image data, and compress the data.

[0533] [Extension devices for PCs] The semiconductor device described in the above embodiment can be applied to computers such as PCs (Personal Computers) and expansion devices for information terminals.

[0534] Figure 29A shows an example of such an expansion device, an external expansion device 6100 for a PC, equipped with a portable, arithmetic-processing chip. The expansion device 6100 can perform arithmetic processing by connecting to a PC, for example, via USB (Universal Serial Bus). Although Figure 29A illustrates a portable form of the expansion device 6100, the expansion device according to one aspect of the present invention is not limited to this, and may be a relatively large form of expansion device equipped with, for example, a cooling fan.

[0535] The expansion device 6100 comprises a housing 6101, a cap 6102, a USB connector 6103, and a circuit board 6104. The circuit board 6104 is housed in the housing 6101. The circuit board 6104 is provided with circuits for driving semiconductor devices and the like described in the above embodiment. For example, the circuit board 6104 is fitted with a chip 6105 (for example, a semiconductor device, electronic component 4700, memory chip, etc., as described in the above embodiment) and a controller chip 6106. The USB connector 6103 functions as an interface for connecting to external devices.

[0536] By using the expansion device 6100 with a PC, the processing power of that PC can be increased. This allows even PCs with insufficient processing power to perform calculations such as artificial intelligence and video processing.

[0537] [Broadcasting System] The semiconductor device described in the above embodiment can be applied to a broadcasting system.

[0538] Figure 29B schematically illustrates data transmission in a broadcasting system. Specifically, Figure 29B shows the path from radio waves (broadcast signals) transmitted from broadcasting station 5680 to television receiving devices (TVs) 5600 in each household. TV 5600 is equipped with a receiving device (not shown), and the broadcast signal received by antenna 5650 is transmitted to TV 5600 via this receiving device.

[0539] In Figure 29B, antenna 5650 is shown as a UHF (Ultra High Frequency) antenna, but antennas such as BS / 110°CS antennas and CS antennas can also be used as antenna 5650.

[0540] Radio waves 5675A and 5675B are broadcast signals for terrestrial broadcasting. Radio tower 5670 amplifies the received radio wave 5675A and transmits radio wave 5675B. Each household can receive radio wave 5675B with antenna 5650 and watch terrestrial broadcasts on TV 5600. Note that the broadcasting system is not limited to terrestrial broadcasting as shown in Figure 29B, but may also include satellite broadcasting using artificial satellites, data broadcasting via fiber optic lines, etc.

[0541] The broadcasting system described above may also be an artificial intelligence-based broadcasting system by applying the semiconductor device described in the above embodiment. When broadcasting data is transmitted from the broadcasting station 5680 to the TVs 5600 in each home, the broadcasting data is compressed by an encoder, and when the antenna 5650 receives the broadcasting data, the decoder of the receiving device included in the TV 5600 restores the broadcasting data. By using artificial intelligence, for example, in motion compensation prediction, which is one of the compression methods of the encoder, it is possible to recognize display patterns included in the display image. It is also possible to perform in-frame prediction using artificial intelligence. Furthermore, for example, when low-resolution broadcasting data is received and the broadcasting data is displayed on a high-resolution TV 5600, image interpolation processing such as upconversion can be performed when the decoder restores the broadcasting data.

[0542] The broadcasting system utilizing artificial intelligence described above is suitable for ultra-high-definition television (UHDTV: 4K, 8K) broadcasting, where the amount of broadcast data increases.

[0543] Furthermore, as an application of artificial intelligence on the TV5600 side, for example, a recording device equipped with artificial intelligence may be provided in the TV5600. By configuring it in this way, the recording device can be programmed to learn the user's preferences, enabling it to automatically record programs that match the user's preferences.

[0544] [Authentication System] The semiconductor device described in the above embodiment can be applied to an authentication system.

[0545] Figure 29C shows a palm print authentication device, which has a housing 6431, a display unit 6432, a palm print reading unit 6433, and wiring 6434.

[0546] Figure 29C shows how the palm print authentication device acquires the palm print of hand 6435. The acquired palm print is processed using artificial intelligence pattern recognition to determine whether the palm print belongs to the person concerned. This makes it possible to construct a highly secure authentication system. Furthermore, the authentication system according to one aspect of the present invention is not limited to a palm print authentication device, but may also be a device that acquires biometric information such as fingerprints, veins, face, iris, voiceprint, genes, or body size to perform biometric authentication.

[0547] This embodiment can be appropriately combined with other embodiments shown in this specification.

[0548] (Notes regarding the descriptions in this specification, etc.) The above embodiments and a description of each component in those embodiments are provided below.

[0549] The configurations shown in each embodiment can be appropriately combined with the configurations shown in other embodiments or examples to form one aspect of the present invention. Furthermore, if multiple configuration examples are shown within one embodiment, these configuration examples can be appropriately combined.

[0550] Furthermore, the content described in one embodiment (even if only a part of it) can be applied to, combined with, or substituted for other content described in the same embodiment (even if only a part of it), and / or content described in one or more other embodiments (even if only a part of it).

[0551] The content described in the embodiments refers to the content described using various figures or the content described using text in the specification in each embodiment.

[0552] Furthermore, a diagram (even a part of it) described in one embodiment can be combined with another part of that diagram, another diagram (even a part of it) described in that embodiment, and / or a diagram (even a part of it) described in one or more other embodiments to form even more diagrams.

[0553] Furthermore, in this specification, block diagrams classify components by function and show them as independent blocks. However, in actual circuits, it is difficult to separate components by function, and there may be cases where multiple functions are involved in a single circuit, or where a single function is involved across multiple circuits. Therefore, the blocks in the block diagrams are not limited to the components described in the specification, and can be appropriately rephrased depending on the situation.

[0554] Furthermore, in the drawings, the size, layer thickness, or area are shown at arbitrary sizes for the sake of explanation. Therefore, they are not necessarily limited to that scale. Also, the drawings are schematic for clarity and are not limited to the shapes or values ​​shown in the drawings. For example, they may include variations in signals, voltages, or currents due to noise, or variations in signals, voltages, or currents due to timing differences.

[0555] Furthermore, the positional relationships of the components illustrated in drawings are relative. Therefore, when explaining components with reference to drawings, terms such as "above" and "below" may be used for convenience. The positional relationships of the components are not limited to those described herein and can be appropriately rephrased depending on the situation.

[0556] In this specification and other documents, when describing the connections of a transistor, the terms "one of the source or drain" (or first electrode or first terminal) and "the other of the source or drain" (or second electrode or second terminal) are used to refer to the other of the source and drain. This is because the source and drain of a transistor vary depending on the transistor's structure or operating conditions. The terms source and drain of a transistor can be appropriately rephrased as source (drain) terminal or source (drain) electrode, depending on the context.

[0557] Furthermore, the terms "electrode" and "wiring" in this specification do not functionally limit these components. For example, "electrode" may be used as part of "wiring," and vice versa. Moreover, the terms "electrode" and "wiring" also include cases where multiple "electrodes" and "wiring" are formed as a single unit.

[0558] Furthermore, in this specification, voltage and potential may be used interchangeably as appropriate. Voltage is the potential difference from a reference potential; for example, if the reference potential is the ground voltage (earth voltage), then voltage can be replaced with potential. Ground potential does not necessarily mean 0V. Note that potential is relative, and depending on the reference potential, it may change the potential applied to wiring, etc.

[0559] Furthermore, in this specification, the term "node" can be replaced with terms such as terminal, wiring, electrode, conductive layer, conductor, impurity region, etc., depending on the circuit configuration or device structure. Also, terminals, wiring, etc., can be replaced with "node."

[0560] In this specification, when A and B are said to be connected, it means that A and B are electrically connected. Here, when A and B are electrically connected, it means that when an object (such as a switch, transistor, or diode, or a circuit including such an object and wiring) is present between A and B, the transmission of electrical signals between A and B is possible. Note that when A and B are electrically connected, this includes cases where A and B are directly connected. Here, when A and B are directly connected, it means that the transmission of electrical signals between A and B is possible via wiring (or electrodes, etc.) without the need for the aforementioned object. In other words, a direct connection means a connection that can be considered as the same circuit diagram when represented by an equivalent circuit.

[0561] In this specification, a switch refers to a device that has the function of controlling whether or not to allow current to flow by being in a conductive state (on state) or a non-conductive state (off state). Alternatively, a switch refers to a device that has the function of selecting and switching the path through which current flows.

[0562] In this specification, channel length refers, for example, to the distance between the source and drain in the region where the semiconductor (or the part of the semiconductor through which current flows when the transistor is ON) and the gate overlap in a top view of a transistor, or in the region where the channel is formed.

[0563] In this specification, channel width refers, for example, to the length of the region where the semiconductor (or the part of the semiconductor through which current flows when the transistor is ON) and the gate electrode overlap, or the region in which the channel is formed, where the source and drain face each other.

[0564] In this specification, terms such as "film" and "layer" may be interchanged depending on the context or situation. For example, the term "conductive layer" may be changed to "conductive film." Or, for example, the term "insulating film" may be changed to "insulating layer." [Explanation of Symbols]

[0565] A1: Input data, A2: Input data, C1: Capacitance, C11: Capacitance element, CK1: Node, D1: Node, GCLK1: Clock signal, LBL_N: Wiring, LBL_1: Wiring, LBL_4: Wiring, LBL_6: Wiring, M1: Transistor, M2: Transistor, M3: Transistor, M4: Transistor, M5: Transistor, M6: Transistor, M7: Transistor, M8: Transistor, M9: Transistor, M10: Transistor, M11: Transistor, M12: Transistor, M13: Transistor, MAC1: Output data, MAC2: Output Data, MC1: Circuit, MC2: Circuit, MCL1: Layer, MCL2: Layer, Q1: Node, RWL_M: Read word line, RWL_1: Read word line, SCL1: Scribe line, SCL2: Scribe line, SDV1: Semiconductor device, SDV2: Semiconductor device, SLEEP1: Signal, SN11: Node, T1: Time, T2: Time, T6: Time, T7: Time, W1: Data, W2: Data, WBL_1: Write bit line, WBL_N: Write bit line, WWL_M: Write word line, WWL_1: Write word line, 10: Semiconductor device, 10_n: Semiconductor device ,10_1: Semiconductor device, 11: Layer, 12: Layer, 20: Memory circuit section, 20_N: Memory circuit section, 20_1: Memory circuit section, 20_4: Memory circuit section, 20_6: Memory circuit section, 21: Memory circuit, 21_N: Memory circuit, 21_P: Memory circuit, 21A: Memory circuit, 21B: Memory circuit, 21C: Memory circuit, 22: Transistor, 23: Semiconductor layer, 24: Multiplication circuit, 25: Addition circuit, 26: Register, 30: Arithmetic circuit, 30_N: Arithmetic circuit, 30_1: Arithmetic circuit, 30_4: Arithmetic circuit, 30_6: Arithmetic circuit, 40: Switching circuit, 40_1: Switching circuit, 40_4: Switching circuit, 40_6: Switching circuit, 50: Drive circuit, 60: Memory circuit, 61: Transistor, 61_N: Transistor, 61_P: Transistor, 61A: Transistor, 61B: Transistor, 62: Transistor, 62_N: Transistor, 62_P: Transistor, 62B: Transistor, 63: Transistor, 63_N: Transistor, 63_P: Transistor, 64: Capacitive element, 64_N: Capacitive element, 64_P: Capacitive element, 64A: Capacitive element, 64B: Capacitive element, 71: Controller, 71G: Controller, 72: Low decoder,73: Word line driver, 74: Column decoder, 75: Driver, 76: Precharge circuit, 81: Input / output buffer, 82: Arithmetic control circuit, 90A: Input layer, 90B: Intermediate layer, 90C: Output layer, 91: Input processing, 92: Arithmetic processing, 93: Arithmetic processing, 94: Pooling arithmetic processing, 95: Arithmetic processing, 96: Pooling arithmetic processing, 97: Fully connected arithmetic processing, 100: Semiconductor device, 101: Digital arithmetic unit, 102: Analog arithmetic unit, 103: Oxide semiconductor memory, 104: Oxide semiconductor memory, 105: Oxide semiconductor arithmetic unit, 106: Oxide semiconductor memory, 1 07: Silicon circuit, 110: CPU, 120: Bus, 193: PMU, 200: CPU core, 202: Cache memory device, 203: Cache memory device, 205: Bus interface section, 210: Power switch, 211: Power switch, 212: Power switch, 214: Level shifter, 220: Flip-flop, 221: Scan flip-flop, 221A: Clock buffer circuit, 222: Backup circuit, 300: Transistor, 310: Substrate, 310A: Substrate, 312: Element isolation layer, 313: Semiconductor region, 314a: Low resistance Region, 314b: Low resistance region, 315: Insulator, 316: Conductor, 320: Insulator, 322: Insulator, 324: Insulator, 326: Insulator, 328: Conductor, 330: Conductor, 350: Insulator, 352: Insulator, 354: Insulator, 356: Conductor, 360: Insulator, 362: Insulator, 364: Insulator, 366: Conductor, 411: Insulator, 412: Insulator, 413: Insulator, 414: Insulator, 416: Conductor, 500: Transistor, 503: Conductor, 503a: Conductor, 503b: Conductor, 510: Insulator, 512: Insulator, 514: Insulator, 516: Insulator Body, 518: Conductor, 522: Insulator, 524: Insulator, 530: Oxide, 530a: Oxide, 530b: Oxide, 530ba: Region, 530bb: Region, 530bc: Region, 540: Conductor, 540a: Conductor, 540b: Conductor, 541: Insulator, 541a: Insulator, 541b: Insulator, 542: Conductor, 542a: Conductor, 542b: Conductor, 543: Oxide, 543a: Oxide, 543b: Oxide, 544: Insulator, 546: Conductor, 550: Insulator, 550a: Insulator, 550b: Insulator, 552: Insulator, 554: Insulator, 560: Conductor,560a: Conductor, 560b: Conductor, 571: Insulator, 571a: Insulator, 571b: Insulator, 574: Insulator, 576: Insulator, 580: Insulator, 581: Insulator, 582: Insulator, 586: Insulator, 600: Capacitive element, 610: Conductor, 612: Conductor, 620: Conductor, 630: Insulator, 640: Insulator, 650: Insulator, 660: Conductor, 4700: Electronic component, 4702: Printed circuit board, 4704: Mounted circuit board, 4710: Semiconductor device, 4711: Mold, 4712: Land, 4713: Electrode pad, 47 14: Wire, 4730: Electronic component, 4731: Interposer, 4732: Package substrate, 4733: Electrode, 4735: Semiconductor device, 4800: Semiconductor wafer, 4800a: Chip, 4801: Wafer, 4801a: Wafer, 4802: Circuit section, 4803: Spacing, 4803a: Spacing, 5200: Portable game console, 5201: Enclosure, 5202: Display section, 5203: Button, 5300: Desktop information terminal, 5301: Main unit, 5302: Display, 5303: Keyboard, 5500: Information terminal 5510: Enclosure, 5511: Display unit, 5600: TV, 5650: Antenna, 5670: Radio tower, 5675A: Radio waves, 5675B: Radio waves, 5680: Broadcasting station, 5700: Automobile, 5800: Electric refrigerator / freezer, 5801: Enclosure, 5802: Door for refrigerator compartment, 5803: Door for freezer compartment, 5900: Information terminal, 5901: Enclosure, 5902: Display unit, 5903: Operation buttons, 5904: Control unit, 5905: Band, 6100: Expansion device, 6101: Enclosure, 6102: Cap, 6103: USB connector, 6104: Circuit board, 6 105: Chip, 6106: Controller chip, 6240: Digital camera, 6241: Casing, 6242: Display unit, 6243: Operation buttons, 6244: Shutter button, 6246: Lens, 6300: Video camera, 6301: Casing, 6302: Casing, 6303: Display unit, 6304: Operation keys, 6305: Lens, 6306: Connection unit, 6431: Casing, 6432: Display unit, 6433: Palm print reader, 6434: Wiring, 6435: Hand, 7500: Home game console, 7520: Main unit, 7522: Controller,

Claims

[Claim 1] A semiconductor device having an analog arithmetic unit and a memory circuit, The memory circuit has a transistor having an oxide semiconductor in the channel formation region. The memory circuit has the function of supplying weight data as analog data to the analog arithmetic unit. The analog arithmetic unit has a function to perform sum-of-accumulate operations using the weight data, The analog arithmetic unit has a first transistor having an oxide semiconductor in the channel formation region, The analog arithmetic unit has the function of flowing a current between the source and drain of the first transistor that corresponds to the product of the weight data and the input data, A semiconductor device having the function of operating the first transistor in a subthreshold region and passing a current corresponding to the product between the source and drain of the first transistor.

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