Frequency delta-sigma modulation signal output circuit and sensor module

Abstract

To provide a frequency delta-sigma modulation signal output circuit capable of generating a frequency delta-sigma modulation signal with reduced noise components.SOLUTION: A frequency delta-sigma modulation signal output circuit includes: a phase modulation circuit that generates a phase modulation signal by generating n delay signals by delaying a signal under measurement, where n is any integer greater than or equal to 2, and randomly selecting one of the n delay signals in synchronization with the signal under measurement; and a frequency ratio digital conversion circuit that generates a frequency delta-sigma modulated signal using a reference signal and the phase modulation signal.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to a frequency delta-sigma modulation signal output circuit and a sensor module.

Background Art

[0002] A frequency delta-sigma modulation signal output circuit that generates a frequency delta-sigma modulation signal indicating the ratio of the frequency of a reference signal to the frequency of a measured signal is known. The frequency delta-sigma modulation signal output circuit has a frequency delta-sigma modulation section, and the frequency delta-sigma modulation section frequency delta-sigma modulates the measured signal using the reference signal to generate a frequency delta-sigma modulation signal. Generally, it is known that when the measured signal is sampled with the reference signal, periodic quantization noise called an idle tone occurs. When a large idle tone occurs, the accuracy of the frequency delta-sigma modulation signal deteriorates significantly.

[0003] In response to this problem, Patent Document 1 discloses a phase modulation circuit that generates a plurality of delayed signals obtained by delaying a measured signal and outputs a phase modulation signal by periodically selecting any one of the plurality of delayed signals, and a frequency ratio digital conversion circuit that generates a frequency delta-sigma modulation signal using the reference signal and the phase modulation signal. A frequency delta-sigma modulation signal output circuit including the above is described.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] According to the frequency delta-sigma modulation signal output circuit described in Patent Document 1, idle tone is reduced by using a phase-modulated signal in which the phase of the signal under test is modulated, thus reducing the noise component contained in the frequency delta-sigma modulation signal. However, further reduction of the noise component is desired. [Means for solving the problem]

[0006] One embodiment of the frequency delta-sigma modulation signal output circuit according to the present invention is: A phase modulation circuit generates n delayed signals by delaying the signal under test, where n is any integer greater than or equal to 2, and generates a phase-modulated signal by randomly selecting one of the n delayed signals in synchronization with the rising edge at which the high-level period of the signal under test begins and the falling edge at which the low-level period of the signal under test begins. Includes a frequency ratio digital conversion circuit that generates a frequency delta-sigma modulated signal using a reference signal and the phase-modulated signal. fruit , The aforementioned frequency ratio digital conversion circuit is The unit includes a time digital value generation unit that generates a time digital value corresponding to the phase difference between the reference signal and the phase modulated signal, The time digital value generation unit has an oscillator that starts oscillating when it detects the rising edge or falling edge of the phase modulation signal, and stops oscillating when the number of oscillations reaches a predetermined number. The reciprocal count integration value synthesis unit includes a multiplier that multiplies a first count value obtained by counting the reference signal by an integer k, and a subtractor that outputs a second count value which is the difference between the first count value multiplied by an integer k and the time digital value. The frequency delta-sigma modulated signal is generated based on the difference between the second count value and a third count value obtained by holding the second count value in synchronization with a clock signal generated based on the phase-modulated signal and the reference signal. The predetermined number of times is set to 2 to the power of m (where m is a positive integer), which is equal to the integer k.

[0007] One embodiment of the frequency delta-sigma modulation signal output circuit according to the present invention is: A phase modulation circuit generates n delayed signals by delaying the signal under test, where n is any integer greater than or equal to 1, and generates a phase-modulated signal by randomly selecting either the signal under test or the n delayed signals in synchronization with the rising edge at which the high-level period of the signal under test begins and the falling edge at which the low-level period of the signal under test begins. Includes a frequency ratio digital conversion circuit that generates a frequency delta-sigma modulated signal using a reference signal and the phase-modulated signal. fruit , The aforementioned frequency ratio digital conversion circuit is The unit includes a time digital value generation unit that generates a time digital value corresponding to the phase difference between the reference signal and the phase modulated signal, The time digital value generation unit has an oscillator that starts oscillating when it detects the rising edge or falling edge of the phase modulation signal, and stops oscillating when the number of oscillations reaches a predetermined number. The reciprocal count integration value synthesis unit includes a multiplier that multiplies a first count value obtained by counting the reference signal by an integer k, and a subtractor that outputs a second count value which is the difference between the first count value multiplied by an integer k and the time digital value. The frequency delta-sigma modulated signal is generated based on the difference between the second count value and a third count value obtained by holding the second count value in synchronization with a clock signal generated based on the phase-modulated signal and the reference signal. The predetermined number of times is set to 2 to the power of m (where m is a positive integer), which is equal to the integer k.

[0008] One aspect of the sensor module according to the present invention is one aspect of the frequency delta-sigma modulation signal output circuit and a physical quantity sensor, and includes The measurement signal is a signal based on the output signal of the physical quantity sensor.

Brief Description of the Drawings

[0009] [Figure 1] Block diagram showing the configuration of the frequency delta-sigma modulation signal output circuit of the first embodiment. [Figure 2] Diagram showing a configuration example of the frequency ratio digital conversion circuit in the first embodiment. [Figure 3] Diagram showing a configuration example of the phase modulation circuit in the first embodiment. [Figure 4] Timing chart for explaining the operation of the phase modulation circuit in the first embodiment. [Figure 5] Timing chart for explaining the operation of the phase modulation circuit of Comparative Example A. [Figure 6] Timing chart for explaining the operation of the phase modulation circuit of Comparative Example B. [Figure 7] Timing chart for explaining the operation of the phase modulation circuit of Comparative Example C. [Figure 8] Diagram showing an example of the frequency spectrum of a signal obtained by sampling a measurement signal with a reference signal. [Figure 9] Diagram showing an example of the frequency spectrum of a signal obtained by sampling the phase modulation signal in Comparative Example A with a reference signal. [Figure 10] Diagram showing an example of the frequency spectrum of a signal obtained by sampling the phase modulation signal in the first embodiment with a reference signal. [Figure 11] This figure shows an example of output signal variation when the signal under measurement is not modulated. [Figure 12] A diagram showing an example of output signal variation in Comparative Example A. [Figure 13] A diagram showing an example of output signal variation in Comparative Example B. [Figure 14] A diagram showing an example of output signal variation in Comparative Example C. [Figure 15] A figure showing an example of output signal variation in the first embodiment. [Figure 16] A diagram showing an example of the configuration of a phase modulation circuit in the second embodiment. [Figure 17] A timing chart diagram illustrating the operation of the phase modulation circuit in the second embodiment. [Figure 18] A diagram showing an example configuration of a frequency ratio digital conversion circuit in the third embodiment. [Figure 19] A block diagram showing an example configuration of the frequency delta-sigma modulation signal output circuit of the fourth embodiment. [Figure 20] A diagram showing an example configuration of a frequency ratio digital conversion circuit in the fourth embodiment. [Figure 21] A diagram showing an example configuration of the time digital value generation unit. [Figure 22] A diagram showing an example of the oscillator configuration. [Figure 23] A timing chart illustrating an example of the operation of a frequency ratio digital conversion circuit. [Figure 24] A timing chart illustrating an example of the operation of a frequency ratio digital conversion circuit. [Figure 25] A perspective view showing the configuration of the sensor module. [Figure 26] Disassembled perspective view of the sensor module. [Figure 27] A perspective view illustrating the schematic configuration of a sensor element for detecting acceleration. [Figure 28] A cross-sectional diagram illustrating the schematic configuration of an acceleration detector using a sensor element that detects acceleration. [Modes for carrying out the invention]

[0010] Preferred embodiments of the present invention will be described in detail below with reference to the drawings. The embodiments described below are not intended to unduly limit the scope of the present invention as described in the claims. Furthermore, not all of the configurations described below are necessarily essential components of the present invention.

[0011] 1. Frequency delta-sigma modulation signal output circuit 1-1. First Embodiment Figure 1 is a block diagram showing the configuration of the frequency delta-sigma modulated signal output circuit of the first embodiment. As shown in Figure 1, the frequency delta-sigma modulated signal output circuit 1 of the first embodiment includes a phase modulation circuit 2, a frequency ratio digital conversion circuit 3, and a low-pass filter circuit 4.

[0012] The frequency delta-sigma modulation signal output circuit 1 receives the reference signal CLK and the signal to be measured, X, which includes the frequency signal of the object being measured, as input. The frequency delta-sigma modulation signal output circuit 1 then generates and outputs an output signal OUT that represents the frequency ratio between the signal to be measured X and the reference signal CLK. Since the reciprocal of frequency is the period, the output signal OUT can also be said to be a signal that represents the period ratio between the signal to be measured X and the reference signal CLK.

[0013] The signal under test X is input to the phase modulation circuit 2. The phase modulation circuit 2 generates n delayed signals by delaying the signal under test X, and generates a phase-modulated signal Xpm by randomly selecting one of the n delayed signals in synchronization with the signal under test X. n is an integer greater than or equal to 2, and the delay times of the n delayed signals relative to the signal under test X are different from each other.

[0014] The frequency ratio digital conversion circuit 3 generates a frequency delta-sigma modulated signal Sfdsm using the reference signal CLK and the phase modulation signal Xpm. The frequency delta-sigma modulated signal Sfdsm is a signal that indicates the frequency ratio between the signal under test X and the reference signal CLK. Since the reciprocal of frequency is the period, the frequency delta-sigma modulated signal Sfdsm can also be said to be a signal that indicates the period ratio between the signal under test X and the reference signal CLK.

[0015] A filter circuit is provided after the frequency ratio digital conversion circuit 3. As shown in Figure 1, in this embodiment, a low-pass filter circuit 4 is provided as a filter circuit after the frequency ratio digital conversion circuit 3. The low-pass filter circuit 4 extracts the low-frequency components contained in the frequency delta-sigma modulated signal Sfdsm and outputs it as the output signal OUT. A general low-pass filter, lag-reed filter, lag filter, etc., can be used for the low-pass filter circuit 4.

[0016] The details of the frequency ratio digital conversion circuit 3 and the phase modulation circuit 2 will be explained using Figures 2 and 3.

[0017] Figure 2 shows an example configuration of the frequency ratio digital conversion circuit 3. As shown in Figure 2, the frequency ratio digital conversion circuit 3 includes a D flip-flop circuit 31, a D flip-flop circuit 32, and an exclusive OR circuit 33.

[0018] The D flip-flop circuit 31 holds the phase-modulated signal Xpm in synchronization with the rising edge of the reference signal CLK. The D flip-flop circuit 32 holds the phase-modulated signal Xpm held by the D flip-flop circuit 31 in synchronization with the rising edge of the reference signal CLK. The exclusive OR circuit 33 calculates the exclusive OR of the signal held by the D flip-flop circuit 31 and the signal held by the D flip-flop circuit 32 and outputs it as a frequency delta-sigma modulated signal Sfdsm.

[0019] In the frequency ratio digital conversion circuit 3 configured as described above, a signal indicating the rising or falling edge timing of the phase modulation signal Xpm is output as a frequency delta-sigma modulation signal Sfdsm. With the frequency ratio digital conversion circuit 3 configured as described above, it becomes possible to count both the rising and falling edges of the phase modulation signal Xpm. In other words, the frequency ratio digital conversion circuit 3 shown in Figure 2 can count at twice the frequency, thereby increasing the SNR. SNR stands for Signal-Noise Ratio.

[0020] Figure 3 shows an example of the configuration of the phase modulation circuit 2. As shown in Figure 3, the phase modulation circuit 2 includes a control circuit 21, a multiplexer 22, and a plurality of delay circuits 23.

[0021] The control circuit 21 receives the signal X to be measured as input. The control circuit 21 generates a control signal Ctrl that is synchronized with the rising and falling edges of the signal X to be measured.

[0022] The multiplexer 22 receives n delay signals Xd1 to Xdn and a control signal Ctrl. In the example in Figure 3, delay signal Xd1 is the signal obtained when the signal under test X has passed through one delay circuit 23, delay signal Xd2 is the signal obtained when the signal under test X has passed through two delay circuits 23, and delay signal Xdn is the signal obtained when the signal under test X has passed through n delay circuits 23. That is, for each integer i between 1 and n, delay signal Xd is the signal obtained when the signal under test X has passed through i delay circuits 23. For example, if the delay times of the n delay circuits 23 are approximately equal, the delay times of the n delay signals Xd1 to Xdn for the signal under test X will be different from each other.

[0023] The multiplexer 22 generates a phase-modulated signal Xpm by randomly selecting one of the delay signals Xd1 to Xdn according to the control signal Ctrl. Here, "randomly selecting" does not mean truly random selection, but may also mean pseudo-random selection. For example, the control circuit 21 may generate a control signal Ctrl for pseudo-random selection of one of the delay signals Xd1 to Xdn based on pseudo-random numbers generated by various known pseudo-random number generation algorithms. Alternatively, for example, the control circuit 21 may generate a control signal Ctrl for pseudo-random selection of one of the delay signals Xd1 to Xdn based on random numbers generated by a hardware random number generator.

[0024] In the following explanation, we will assume that the delay time of all n delay circuits 23 is Δt. That is, the delay time of delay signal Xd1 is time Δt, the delay time of delay signal Xd2 is 2×Δt, and the delay time of delay signal Xdn is n×Δt. In other words, for each integer i between 1 and n, the delay time of delay signal Xdi is i×Δt. However, the delay circuits 23 may each have a different configuration, and the delay times of delay signals Xd1 to Xdn must be different from each other.

[0025] Figure 4 is a timing chart illustrating an example of the operation of the phase modulation circuit 2. In the example in Figure 4, the integer n is 3, and the phase modulation signal Xpm is generated based on three delayed signals Xd1, Xd2, and Xd3.

[0026] Figure 4 shows an arbitrary reference time T0 within the rising edge of the signal under test X. The control circuit 21 outputs a control signal Ctrl to select the delay signal Xd3 during the period Tc1 from the reference time T0 when the signal under test X rises until the next rising edge of the signal under test X, when the signal under test X is at a high level, and when the signal under test X is at a low level. Therefore, the phase-modulated signal Xpm in period Tc1 rises with a time delay of 3 × Δt relative to the rising edge of the signal under test X, and falls with a time delay of 3 × Δt relative to the falling edge of the signal under test X.

[0027] Furthermore, during the period Tc2 following period Tc1 until the next rising edge of the signal X under test, the control circuit 21 outputs a control signal Ctrl to select the delay signal Xd1 when the signal X under test is at a high level, and outputs a control signal Ctrl to select the delay signal Xd3 when the signal X under test is at a low level. Therefore, the phase-modulated signal Xpm in period Tc2 rises with a time delay Δt relative to the rising edge of the signal X under test, and falls with a time delay of 3 × Δt relative to the falling edge of the signal X under test.

[0028] Furthermore, during the period Tc3 following the period Tc2 until the next rising edge of the signal under test X, the control circuit 21 outputs a control signal Ctrl to select the delay signal Xd2 when the signal under test X is at a high level, and outputs a control signal Ctrl to select the delay signal Xd1 when the signal under test X is at a low level. Therefore, the phase-modulated signal Xpm in period Tc3 rises with a time delay of 2 × Δt relative to the rising edge of the signal under test X, and falls with a time delay of Δt relative to the falling edge of the signal under test X.

[0029] Furthermore, the control circuit 21 outputs a control signal Ctrl to select the delay signal Xd1 during the period Tc4 after period Tc3 until the next rising edge of the signal X under test. This control signal Ctrl is output during periods when the signal X under test is at a high level, and during periods when the signal X under test is at a low level. Therefore, the phase-modulated signal Xpm in period Tc4 rises with a time delay Δt relative to the rising edge of the signal X under test, and falls with a time delay Δt relative to the falling edge of the signal X under test.

[0030] Thus, in the example shown in Figure 4, during periods Tc1 to Tc4, the multiplexer 22 generates the phase-modulated signal Xpm by randomly selecting one of the three delay signals Xd1, Xd2, and Xd3 according to the control signal Ctrl. Although not explained in detail, as shown in Figure 4, after period Tc4, during each period Tc5 to Tc12 until the measured signal X rises sequentially, the multiplexer 22 also generates the phase-modulated signal Xpm by randomly selecting one of the three delay signals Xd1, Xd2, and Xd3 according to the control signal Ctrl.

[0031] In contrast, Figure 5 is a timing chart illustrating an example of the operation of Comparative Example A, where the multiplexer 22 generates the phase-modulated signal Xpm by regularly selecting one of the two delay signals Xd1 and Xd2.

[0032] In the example shown in Figure 5, the control circuit 21 outputs a control signal Ctrl to select the delay signal Xd1 during the period Tc1a from the reference time T0 when the signal X to be measured rises until the next rise of the signal X to be measured, and during the period Tc2a after period Tc1a until the next rise of the signal X to be measured. During the period when the signal X to be measured is at a high level, the control circuit 21 outputs a control signal Ctrl to select the delay signal Xd1 during the period when the signal X to be measured is at a low level. Therefore, the phase-modulated signal Xpm in periods Tc1a and Tc2a rises with a time delay Δt relative to the rising edge of the signal X to be measured, and falls with a time delay Δt relative to the falling edge of the signal X to be measured.

[0033] Furthermore, the control circuit 21 outputs a control signal Ctrl to select the delay signal Xd2 during the period Tc3a after period Tc2a until the next rising edge of the signal X under test, and during the period Tc4a after period Tc3a until the next rising edge of the signal X under test, when the signal X under test is at a high level, and when the signal X under test is at a low level. Therefore, the phase-modulated signal Xpm in periods Tc3a and Tc4a rises with a time delay of 2 × Δt relative to the rising edge of the signal X under test, and falls with a time delay of 2 × Δt relative to the falling edge of the signal X under test.

[0034] Furthermore, the control circuit 21 outputs a control signal Ctrl to select the delay signal Xd2 during the period Tc1b after period Tc4a until the next rising edge of the signal X under test, and during the period Tc2b after period Tc1b until the next rising edge of the signal X under test, when the signal X under test is at a high level, and outputs a control signal Ctrl to select the delay signal Xd2 during the period when the signal X under test is at a low level. Therefore, the phase-modulated signal Xpm in periods Tc1b and Tc2b rises with a time delay of 2 × Δt relative to the rising edge of the signal X under test, and falls with a time delay of 2 × Δt relative to the falling edge of the signal X under test.

[0035] Furthermore, the control circuit 21 outputs a control signal Ctrl to select the delay signal Xd1 during the period Tc3b after period Tc2b until the next rising edge of the signal X under test, and during the period Tc4b after period Tc3b until the next rising edge of the signal X under test. During the period when the signal X under test is at a high level, the control circuit 21 outputs a control signal Ctrl to select the delay signal Xd1 during the period when the signal X under test is at a low level. Therefore, the phase-modulated signal Xpm in periods Tc3b and Tc4b rises with a time delay Δt relative to the rising edge of the signal X under test, and falls with a time delay Δt relative to the falling edge of the signal X under test.

[0036] Then, a period Tma consisting of periods Tc1a, Tc2a, Tc3a, and Tc4a, and a period Tmb consisting of periods Tc1b, Tc2b, Tc3b, and Tc4b are repeated alternately. In this way, in comparative example A, the multiplexer 22 generates the phase-modulated signal Xpm by regularly selecting one of the two delay signals Xd1 and Xd2 according to the control signal Ctrl, with the period consisting of periods Tma and Tmb being one period.

[0037] Figure 6 is a timing chart illustrating an example of the operation of Comparative Example B, where the multiplexer 22 generates the phase-modulated signal Xpm by regularly selecting one of the two delay signals Xd1 and Xd2.

[0038] In the example shown in Figure 6, the control circuit 21 outputs a control signal Ctrl to select the delay signal Xd1 during the period Tc1c from the reference time T0 when the signal X to be measured rises until the next rise of the signal X to be measured, and during the period Tc2c after Tc1c until the next rise of the signal X to be measured. During the period when the signal X to be measured is at a high level, the control circuit 21 outputs a control signal Ctrl to select the delay signal Xd2 during the period when the signal X to be measured is at a low level. Therefore, the phase-modulated signal Xpm in periods Tc1c and Tc2c rises with a time delay of Δt relative to the rising edge of the signal X to be measured, and falls with a time delay of 2×Δt relative to the falling edge of the signal X to be measured.

[0039] Furthermore, the control circuit 21 outputs a control signal Ctrl to select the delay signal Xd2 during the period Tc3c (after period Tc2c) until the next rising edge of the signal X under test) and the period Tc4c (after period Tc3c) until the next rising edge of the signal X under test), and outputs a control signal Ctrl to select the delay signal Xd1 during the period when the signal X under test is at a high level. Therefore, the phase-modulated signal Xpm in periods Tc3c and Tc4c rises with a time delay of 2 × Δt relative to the rising edge of the signal X under test, and falls with a time delay of Δt relative to the falling edge of the signal X under test.

[0040] Then, the period Tmc, consisting of periods Tc1c, Tc2c, Tc3c, and Tc4c, is repeated. In this way, in comparative example B, the multiplexer 22 generates the phase-modulated signal Xpm by regularly selecting one of the two delay signals Xd1 and Xd2 according to the control signal Ctrl, with the period Tmc being one period.

[0041] Figure 7 is a timing chart illustrating an example of the operation of Comparative Example C, assuming that the multiplexer 22 generates the phase-modulated signal Xpm by regularly selecting one of the three delay signals Xd1, Xd2, and Xd3.

[0042] In the example shown in Figure 7, the control circuit 21 outputs a control signal Ctrl to select the delay signal Xd1 during the period Tc1d from the reference time T0 when the signal X to be measured rises until the next rise of the signal X to be measured, and during the period Tc2d after Tc1d until the next rise of the signal X to be measured. During the period when the signal X to be measured is at a high level, the control circuit 21 outputs a control signal Ctrl to select the delay signal Xd2 during the period when the signal X to be measured is at a low level. Therefore, the phase-modulated signal Xpm during periods Tc1d and Tc2d rises with a time delay of Δt relative to the rising edge of the signal X to be measured, and falls with a time delay of 2×Δt relative to the falling edge of the signal X to be measured.

[0043] Furthermore, the control circuit 21 outputs a control signal Ctrl to select the delay signal Xd3 during the period Tc3d after period Tc2d until the next rising edge of the signal X under test, and during the period Tc4d after period Tc3d until the next rising edge of the signal X under test, when the signal X under test is at a high level, and outputs a control signal Ctrl to select the delay signal Xd2 during the period when the signal X under test is at a low level. Therefore, the phase-modulated signal Xpm in periods Tc3d and Tc4d rises with a time delay of 3 × Δt relative to the rising edge of the signal X under test, and falls with a time delay of 2 × Δt relative to the falling edge of the signal X under test.

[0044] Furthermore, the control circuit 21 outputs a control signal Ctrl to select the delay signal Xd2 during the period Tc1e, from the period Tc4d until the next rising edge of the signal X under test, and during the period Tc2e, from the period Tc1e until the next rising edge of the signal X under test, when the signal X under test is at a high level, and outputs a control signal Ctrl to select the delay signal Xd3, when the signal X under test is at a low level. Therefore, the phase-modulated signal Xpm in periods Tc1e and Tc2e rises with a time delay of 2 × Δt relative to the rising edge of the signal X under test, and falls with a time delay of 3 × Δt relative to the falling edge of the signal X under test.

[0045] Furthermore, the control circuit 21 outputs a control signal Ctrl to select the delay signal Xd2 during the period Tc3e after period Tc2e until the next rising edge of the signal X under test, and during the period Tc4e after period Tc3e until the next rising edge of the signal X under test, when the signal X under test is at a high level, and outputs a control signal Ctrl to select the delay signal Xd1 during the period when the signal X under test is at a low level. Therefore, the phase-modulated signal Xpm in periods Tc3e and Tc4e rises with a time delay of 2 × Δt relative to the rising edge of the signal X under test, and falls with a time delay of Δt relative to the falling edge of the signal X under test.

[0046] Then, a period Tmd consisting of periods Tc1d, Tc2d, Tc3d, and Tc4d, and a period Tme consisting of periods Tc1e, Tc2e, Tc3e, and Tc4e, are repeated alternately. In this way, in comparative example C, the multiplexer 22 generates the phase-modulated signal Xpm by regularly selecting one of the three delay signals Xd1, Xd2, and Xd3 according to the control signal Ctrl, with the period consisting of periods Tmd and Tme being one period.

[0047] Here, the signal obtained by sampling the signal under test X with the reference signal CLK generates periodic quantization noise called idle tone. However, when the fractional part of the frequency ratio between the signal under test X and the reference signal CLK is close to 0, a large idle tone is generated. Figure 8 shows an example of a frequency spectrum obtained by fast Fourier transforming the signal obtained by sampling the signal under test X with the reference signal CLK when the fractional part of the frequency ratio between the signal under test X and the reference signal CLK is close to 0. In the example in Figure 8, peaks caused by idle tone occur around 300Hz and 700Hz-800Hz. In Figure 8, the peak around 40Hz is caused by the signal being measured, but if the upper limit of the measurement bandwidth is 300Hz or higher, the accuracy of the output signal OUT may decrease due to the influence of idle tone.

[0048] In contrast, Figure 9 shows an example of the frequency spectrum obtained by performing a Fast Fourier Transform on a signal sampled with the reference signal CLK from the phase-modulated signal Xpm obtained in Comparative Example A. In the example in Figure 9, the base noise level is increased, but the peaks caused by idle tones around 300 Hz and 700 Hz to 800 Hz are reduced. However, a peak caused by the period of the phase-modulated signal Xpm occurs around 200 Hz. Although not shown in the figure, the frequency spectrum obtained by performing a Fast Fourier Transform on a signal sampled with the reference signal CLK from the phase-modulated signal Xpm obtained in Comparative Example B or Comparative Example C also shows a similar trend to Figure 9.

[0049] On the other hand, Figure 10 shows an example of a frequency spectrum obtained by performing a Fast Fourier Transform on a signal sampled with the reference signal CLK from the phase-modulated signal Xpm obtained in this embodiment. In the example in Figure 10, the base noise level is about the same as in Figure 9, but there are almost no peaks caused by idle tones around 300 Hz and 700 Hz to 800 Hz, nor are there any peaks caused by the period of the phase-modulated signal Xpm.

[0050] Figures 11 to 15 show examples of 1σ variation in the output signal OUT obtained when the modulation method of the signal under test X is changed. Figure 11 corresponds to the case where the phase-modulated signal Xpm is the same as the signal under test X, i.e., the signal under test X is not modulated. Figure 12 corresponds to the case where the phase-modulated signal Xpm obtained in Comparative Example A is used. Figure 13 corresponds to the case where the phase-modulated signal Xpm obtained in Comparative Example B is used. Figure 14 corresponds to the case where the phase-modulated signal Xpm obtained in Comparative Example C is used. Figure 15 corresponds to the case where the phase-modulated signal Xpm obtained in this embodiment is used. In Figures 11 to 15, the vertical axis represents variation, and the horizontal axis represents the operating point, i.e., the fractional part when the frequency of the reference signal CLK is divided by the frequency of the signal under test X. Specifically, the horizontal axis range is the range of the operating point when the frequency of the reference signal CLK is set to 32 MHz and the frequency of the signal under test X is swept around 120300.75 Hz. Since 32MHz ÷ 120300.75Hz ≈ 266, the operating point 0 corresponds to the frequency of the measured signal X being approximately 120300.75Hz.

[0051] In the example in Figure 11, a large variation occurs around the operating point 0 due to the influence of the idle tone. In the examples in Figures 12, 13, or 14, the influence of the idle tone is reduced compared to the example in Figure 11, and the variation around the operating point 0 is reduced. In the example in Figure 15, the influence of the idle tone is further reduced compared to the examples in Figures 12, 13, or 14, and the variation around the operating point 0 is further reduced, resulting in a highly accurate output signal OUT.

[0052] As described above, in the frequency delta-sigma modulation signal output circuit 1 of the first embodiment, the phase modulation circuit 2 generates n delayed signals Xd1 to Xdn by delaying the signal X under test, and generates a phase-modulated signal Xpm by selecting one of the n delayed signals Xd1 to Xdn in synchronization with the signal X under test, and the frequency ratio digital conversion circuit 3 generates a frequency delta-sigma modulation signal Sfdsm using the reference signal CLK and the phase-modulated signal Xpm. As a result, the phase of the phase-modulated signal Xpm changes, reducing the idle tone contained in the signal obtained by sampling one of the reference signal CLK and the phase-modulated signal Xpm with the other, and thus reducing the signal component caused by the idle tone contained in the frequency delta-sigma modulation signal Sfdsm. Furthermore, in the frequency delta-sigma modulation signal output circuit 1 of the first embodiment, the phase-modulated signal Xpm is generated by the phase modulation circuit 2 randomly selecting one of the n delayed signals Xd1 to Xdn, so the phase of the phase-modulated signal Xpm changes irregularly. Therefore, the frequency delta-sigma modulated signal Sfdsm does not contain signal components of predetermined frequencies that may occur when any of the n delay signals Xd1 to Xdn are regularly selected. Consequently, the frequency delta-sigma modulated signal output circuit 1 of the first embodiment can reduce the noise components contained in the frequency delta-sigma modulated signal Sfdsm.

[0053] Furthermore, according to the frequency delta-sigma modulation signal output circuit 1 of the first embodiment, the low-pass filter circuit 4 provided after the frequency ratio digital conversion circuit 3 provides an output signal OUT, which is a frequency delta-sigma modulation signal with further reduced noise components. In addition, the frequency delta-sigma modulation signal Sfdsm generated by the frequency ratio digital conversion circuit 3 does not contain signal components of predetermined frequencies that may occur when any of the n delay signals Xd1 to Xdn are regularly selected, so the constraint on the cutoff frequency of the low-pass filter circuit 4 is small, and the degree of design freedom is high.

[0054] 1-2. Second Embodiment In the following description of the frequency delta-sigma modulation signal output circuit 1 of the second embodiment, the same reference numerals are used for components similar to those in the first embodiment, and explanations that overlap with those of the first embodiment are omitted or simplified. The main points to be described are those that differ from the first embodiment.

[0055] The configuration of the frequency delta-sigma modulated signal output circuit 1 in the second embodiment is the same as in Figure 1, so its illustration and description are omitted. In the frequency delta-sigma modulated signal output circuit 1 of the second embodiment, the function and configuration of the phase modulation circuit 2 differ from those of the first embodiment.

[0056] In the second embodiment, the phase modulation circuit 2 generates n delayed signals by delaying the signal under test X, and generates a phase-modulated signal Xpm by randomly selecting either the signal under test X or one of the n delayed signals in synchronization with the signal under test X. n is any integer greater than or equal to 1, and when n is 2 or greater, the delay times of the n delayed signals relative to the signal under test X are different from each other.

[0057] Similar to the first embodiment, the frequency ratio digital conversion circuit 3 generates a frequency delta-sigma modulated signal Sfdsm using the reference signal CLK and the phase modulation signal Xpm. Furthermore, the low-pass filter circuit 4, which is a filter circuit provided after the frequency ratio digital conversion circuit 3, extracts the low-frequency components contained in the frequency delta-sigma modulated signal Sfdsm and outputs them as the output signal OUT.

[0058] Figure 16 shows an example of the configuration of the phase modulation circuit 2 in the second embodiment. As shown in Figure 16, the phase modulation circuit 2 includes a control circuit 21, a multiplexer 22, and a plurality of delay circuits 23.

[0059] The control circuit 21 receives the signal X to be measured as input. The control circuit 21 generates a control signal Ctrl that is synchronized with the rising and falling edges of the signal X to be measured.

[0060] The multiplexer 22 receives the signal to be measured X, n delay signals Xd1 to Xdn, and a control signal Ctrl. In the example in Figure 16, delay signal Xd1 is the signal obtained when the signal to be measured X has passed through one delay circuit 23, delay signal Xd2 is the signal obtained when the signal to be measured X has passed through two delay circuits 23, and delay signal Xdn is the signal obtained when the signal to be measured X has passed through n delay circuits 23. That is, for each integer i between 1 and n, delay signal Xd is the signal obtained when the signal to be measured X has passed through i delay circuits 23. For example, if the delay times of the n delay circuits 23 are approximately equal, the delay times of the n delay signals Xd1 to Xdn for the signal to be measured X will be different from each other.

[0061] The multiplexer 22 generates a phase-modulated signal Xpm by randomly selecting one of the measured signal X and delay signals Xd1 to Xdn according to the control signal Ctrl.

[0062] In the following explanation, we will assume that the delay time of all n delay circuits 23 is Δt. That is, the delay time of delay signal Xd1 is time Δt, the delay time of delay signal Xd2 is 2×Δt, and the delay time of delay signal Xdn is n×Δt. In other words, for each integer i between 1 and n, the delay time of delay signal Xdi is i×Δt. However, the delay circuits 23 may each have a different configuration, and the delay times of delay signals Xd1 to Xdn must be different from each other.

[0063] Figure 17 is a timing chart illustrating an example of the operation of the phase modulation circuit 2. In the example in Figure 17, the integer n is 2, and the phase modulation signal Xpm is generated based on the signal under test X and two delayed signals Xd1 and Xd2.

[0064] Figure 17 shows an arbitrary reference time T0 within the rising edge of the signal under test X. The control circuit 21 outputs a control signal Ctrl to select the delay signal Xd2 during the period Tc1 from the reference time T0 when the signal under test X rises until the next rising edge of the signal under test X, when the signal under test X is at a high level, and when the signal under test X is at a low level. Therefore, the phase-modulated signal Xpm in period Tc1 rises with a time delay of 2 × Δt relative to the rising edge of the signal under test X, and falls with a time delay of 2 × Δt relative to the falling edge of the signal under test X.

[0065] Furthermore, during the period Tc2 following period Tc1 until the next rising edge of the signal under test X, the control circuit 21 outputs a control signal Ctrl to select the signal under test X when it is at a high level, and outputs a control signal Ctrl to select the delayed signal Xd2 when it is at a low level. Therefore, the phase-modulated signal Xpm in period Tc2 rises almost without delay to the rising edge of the signal under test X and falls with a time delay of 2 × Δt to the falling edge of the signal under test X.

[0066] Furthermore, during the period Tc3, which follows the period Tc2 and continues until the next rising edge of the signal under test X, the control circuit 21 outputs a control signal Ctrl to select the delay signal Xd1 when the signal under test X is at a high level, and outputs a control signal Ctrl to select the signal under test X when the signal under test X is at a low level. Therefore, the phase-modulated signal Xpm in period Tc3 rises with a time delay Δt relative to the rising edge of the signal under test X, and falls with almost no delay relative to the falling edge of the signal under test X.

[0067] Furthermore, during the period Tc4 following the period Tc3 until the next rising edge of the signal X under test, the control circuit 21 outputs a control signal Ctrl to select the signal X under test when the signal X under test is at a high level, and outputs a control signal Ctrl to select the signal X under test when the signal X under test is at a low level. Therefore, the phase-modulated signal Xpm in period Tc4 rises with almost no delay to the rising edge of the signal X under test, and falls with almost no delay to the falling edge of the signal X under test.

[0068] As shown in the example in Figure 17, during periods Tc1 to Tc4, the multiplexer 22 generates the phase-modulated signal Xpm by randomly selecting either the signal under test X or one of the two delay signals Xd1 and Xd2 according to the control signal Ctrl. Although not explained in detail, as shown in Figure 17, the multiplexer 22 also generates the phase-modulated signal Xpm during each period Tc5 to Tc12 after period Tc4, until the signal under test X rises sequentially, by randomly selecting either the signal under test X or one of the two delay signals Xd1 and Xd2 according to the control signal Ctrl.

[0069] As described above, in the frequency delta-sigma modulation signal output circuit 1 of the second embodiment, the phase modulation circuit 2 generates n delayed signals Xd1 to Xdn by delaying the signal under test X, and generates a phase-modulated signal Xpm by selecting one of the signal under test X and the n delayed signals Xd1 to Xdn in synchronization with the signal under test X. The frequency ratio digital conversion circuit 3 uses the reference signal CLK and the phase-modulated signal Xpm to generate a frequency delta-sigma modulation signal Sfdsm. As a result, the phase of the phase-modulated signal Xpm changes, reducing the idle tone contained in the signal obtained by sampling one of the reference signal CLK and the phase-modulated signal Xpm with the other, and thus reducing the signal component caused by the idle tone contained in the frequency delta-sigma modulation signal Sfdsm. Furthermore, in the frequency delta-sigma modulation signal output circuit 1 of the second embodiment, the phase modulation circuit 2 generates the phase-modulated signal Xpm by randomly selecting one of the signal under test X and the n delayed signals Xd1 to Xdn, so the phase of the phase-modulated signal Xpm changes irregularly. Therefore, the frequency delta-sigma modulated signal Sfdsm does not contain signal components of predetermined frequencies that may occur when one of the measured signal X and any of the n delay signals Xd1 to Xdn is regularly selected. Accordingly, the frequency delta-sigma modulated signal output circuit 1 of the second embodiment can reduce the noise components contained in the frequency delta-sigma modulated signal Sfdsm.

[0070] Furthermore, according to the frequency delta-sigma modulation signal output circuit 1 of the second embodiment, the low-pass filter circuit 4 provided after the frequency ratio digital conversion circuit 3 provides an output signal OUT, which is a frequency delta-sigma modulation signal with further reduced noise components. In addition, the frequency delta-sigma modulation signal Sfdsm generated by the frequency ratio digital conversion circuit 3 does not contain signal components of predetermined frequencies that may occur when one of the measured signal X and n delay signals Xd1 to Xdn is regularly selected, so the constraint on the cutoff frequency of the low-pass filter circuit 4 is small, and the degree of design freedom is high.

[0071] Furthermore, in the frequency delta-sigma modulation signal output circuit 1 of the second embodiment, the measured signal X is included in the selection target of the phase modulation circuit 2, which makes it possible to reduce the total number of delay signals Xd1 to Xdn by one compared to the first embodiment, and also makes it possible to miniaturize the frequency delta-sigma modulation signal output circuit 1.

[0072] 1-3. Third Embodiment In the following description of the frequency delta-sigma modulation signal output circuit 1 of the third embodiment, the same reference numerals are used for components similar to those in the first or second embodiment, and explanations that overlap with those in the first or second embodiment are omitted or simplified. The main focus will be on the differences from the first and second embodiments.

[0073] The configuration of the frequency delta-sigma modulation signal output circuit 1 in the third embodiment is the same as in Figure 1, so its illustration and description are omitted. In the frequency delta-sigma modulation signal output circuit 1 of the third embodiment, the function and configuration of the frequency ratio digital conversion circuit 3 differ from those of the first and second embodiments. The phase modulation circuit 2 is configured, for example, as shown in Figure 3 or Figure 16, and its function is the same as in the first or second embodiment.

[0074] In the third embodiment, the frequency ratio digital conversion circuit 3 includes a plurality of frequency delta-sigma modulation circuits connected in parallel, and generates a frequency delta-sigma modulated signal Sfdsm based on the output signals of the plurality of frequency delta-sigma modulation circuits.

[0075] Figure 18 shows an example of the configuration of the frequency ratio digital conversion circuit 3 in the third embodiment. As shown in Figure 18, the frequency ratio digital conversion circuit 3 includes a plurality of frequency delta-sigma modulation circuits 5 and an adder 6.

[0076] Each of the multiple frequency delta-sigma modulation circuits 5 receives a reference signal CLK and a phase modulation signal Xpm output from the phase modulation circuit 2.

[0077] The frequency delta-sigma modulation circuit 5 generates and outputs a frequency delta-sigma modulated signal that indicates the timing of the rising or falling edge of the input phase-modulated signal Xpm. The configuration of the frequency delta-sigma modulation circuit 5 is the same as in Figure 2, so its illustration and description are omitted.

[0078] The adder 6 receives the output signals from multiple frequency delta-sigma modulation circuits 5, adds the multiple input signals, and outputs a frequency delta-sigma modulated signal Sfdsm.

[0079] The frequency delta-sigma modulated signal Sfdsm is input to the low-pass filter circuit 4. The low-pass filter circuit 4 extracts the low-frequency components from the signal output from the adder 6 and outputs them as the output signal OUT.

[0080] The frequency delta-sigma modulation signal output circuit 1 of the third embodiment described above provides the same effects as the first or second embodiment.

[0081] Furthermore, according to the frequency delta-sigma modulation signal output circuit 1 of the third embodiment, the frequency delta-sigma modulation signal output circuit 1 generates a frequency delta-sigma modulation signal Sfdsm by adding the output signals of a plurality of frequency delta-sigma modulation circuits 5 connected in parallel. As a result, signal components caused by idle tones included in the frequency delta-sigma modulation signal Sfdsm are smoothed, and noise components included in the frequency delta-sigma modulation signal Sfdsm can be further reduced.

[0082] In this embodiment, a phase adjustment unit, such as a delay circuit, may be provided between the multiple frequency delta-sigma modulation circuits 5 to shift the phase of at least one of the input reference signal CLK and the signal under test X. In this case, examples include a configuration in which only the phase of the reference signal CLK is shifted, a configuration in which only the phase of the signal under test X is shifted, and a configuration in which the phases of both the reference signal CLK and the signal under test X are shifted. With this configuration, signal components caused by idle tones contained in the frequency delta-sigma modulation signal Sfdsm can be smoothed more efficiently, and noise components contained in the frequency delta-sigma modulation signal Sfdsm can be further reduced.

[0083] 1-4. Fourth Embodiment Hereinafter, regarding the frequency delta-sigma modulation signal output circuit 1 of the fourth embodiment, the same reference numerals are used for components that are the same as those in any of the first to third embodiments, and explanations that overlap with any of the first to third embodiments will be omitted or simplified. The explanation will mainly focus on aspects that differ from any of the first to third embodiments.

[0084] Figure 19 is a block diagram showing the configuration of the frequency delta-sigma modulation signal output circuit 1 of the fourth embodiment. As shown in Figure 19, the frequency delta-sigma modulation signal output circuit 1 of the fourth embodiment includes a phase modulation circuit 2 and a frequency ratio digital conversion circuit 3. In the frequency delta-sigma modulation signal output circuit 1 of the fourth embodiment, the function and configuration of the frequency ratio digital conversion circuit 3 differ from those of the first to third embodiments. The phase modulation circuit 2 is configured, for example, as shown in Figure 3 or Figure 16, and its function is the same as that of any of the first to third embodiments.

[0085] In the fourth embodiment, the frequency ratio digital conversion circuit 3 generates a time digital value corresponding to the phase difference between the reference signal CLK and the phase modulation signal Xpm, and generates a frequency delta-sigma modulated signal based on this time digital value. The frequency delta-sigma modulated signal output circuit 1 outputs the frequency delta-sigma modulated signal generated by the frequency ratio digital conversion circuit 3 as an output signal OUT.

[0086] As shown in Figure 19, the frequency delta-sigma modulation signal output circuit 1 of the fourth embodiment does not need to include the low-pass filter circuit 4, unlike the first to third embodiments.

[0087] Figure 20 shows an example of the configuration of the frequency ratio digital conversion circuit 3 in the fourth embodiment. As shown in Figure 20, the frequency ratio digital conversion circuit 3 in the fourth embodiment includes a count circuit 41, a D flip-flop circuit 42, a multiplier 51, a subtractor 52, a time digital value generation unit 60, a count value holding control unit 70, a D flip-flop circuit 81, a subtractor 82, and a D flip-flop circuit 83. Note that in Figure 20, for the sake of simplification, only one D flip-flop circuit 42, one D flip-flop circuit 81, and one D flip-flop circuit 83 are shown, but in reality, there are L D flip-flop circuits 42, M D flip-flop circuits 81, and N D flip-flop circuits 83.

[0088] The count circuit 41 counts the number of edges of the reference signal CLK. In this embodiment, the count circuit 41 counts the number of rising edges of the reference signal CLK and outputs a count value CNT1 of L bits.

[0089] L D flip-flop circuits 42 acquire and hold L-bit count values ​​CNT1 in synchronization with the phase-modulated signal Xpm. In this embodiment, L D flip-flop circuits 42 acquire L-bit count values ​​CNT1 in synchronization with the rising and falling edges of the phase-modulated signal Xpm and hold them as L-bit count values ​​DCNT1. Specifically, L D flip-flop circuits 42 acquire the count value CNT1 when the rising edge of the phase-modulated signal Xpm arrives and hold it as count value DCNT1 until the falling edge of the phase-modulated signal Xpm arrives. Also, L D flip-flop circuits 42 acquire the count value CNT1 when the falling edge of the phase-modulated signal Xpm arrives and hold it as count value DCNT1 until the rising edge of the phase-modulated signal Xpm arrives.

[0090] The count circuit 41 and L D flip-flop circuits 42 constitute a first counting unit 40 that counts the edges of the reference signal CLK in synchronization with the phase-modulated signal Xpm and generates a count value DCNT1.

[0091] The time digital value generation unit 60 generates a time digital value TD corresponding to the phase difference between the reference signal CLK and the phase-modulated signal Xpm. In this embodiment, the time digital value generation unit 60 generates an M-bit time digital value TD corresponding to the phase difference between the rising edge of the reference signal CLK and the rising edge of the phase-modulated signal Xpm, and generates an M-bit time digital value TD corresponding to the phase difference between the rising edge of the reference signal CLK and the falling edge of the phase-modulated signal Xpm. A detailed description of the time digital value generation unit 60 will be given later.

[0092] The count value holding control unit 70 generates a clock signal DCLK and a reset signal RST based on a reference signal CLK and a phase-modulated signal Xpm. For example, the count value holding control unit 70 generates a clock signal DCLK that becomes a high pulse when the rising edge of the reference signal CLK arrives a predetermined number of times, for example, 8 times, after the phase-modulated signal Xpm changes from a low level to a high level, or from a high level to a low level. Alternatively, for example, the count value holding control unit 70 generates a reset signal RST that becomes a high pulse when the first rising edge of the reference signal CLK arrives after the phase-modulated signal Xpm changes from a low level to a high level.

[0093] The multiplier 51 multiplies the L-bit count value DCNT1 by the integer k. That is, the multiplier 51 outputs an M-bit value which is k times the count value DCNT1. If the integer k is 2 to the power of n, the multiplier 51 can be implemented as a simple circuit that shifts the count value DCNT1 by n bits.

[0094] The subtractor 52 subtracts the M-bit time digital value TD from the M-bit value output from the multiplier 51 and outputs the M-bit count value CNT3.

[0095] The multiplier 51 and subtractor 52 constitute a reciprocal count integrated value synthesis unit 50 that outputs the difference between an integer k multiple of the count value DCNT1 generated by the first count unit 40 and the time digital value TD generated by the time digital value generation unit 60.

[0096] The M D flip-flop circuits 81 acquire and hold an M-bit count value CNT3 in synchronization with the clock signal DCLK. In this embodiment, when the reset signal RST is low, the M D flip-flop circuits 81 acquire the M-bit count value CNT3 when the rising edge of the clock signal DCLK arrives and hold it as an M-bit count value DCNT3. Also, when the reset signal RST is high, the M D flip-flop circuits 81 initialize the count value DCNT3 to zero.

[0097] The subtractor 82 subtracts the M-bit count value DCNT3 from the M-bit count value CNT3 and outputs the N-bit count value CNTX.

[0098] The N D flip-flop circuits 83 acquire and hold an N-bit count value CNTX in synchronization with the clock signal DCLK. In this embodiment, when the reset signal RST is low, the N D flip-flop circuits 83 acquire the N-bit count value CNTX when the rising edge of the clock signal DCLK arrives and hold it as an N-bit reciprocal count value CNT. Also, when the reset signal RST is high, the N D flip-flop circuits 83 initialize the reciprocal count value CNT to zero. This reciprocal count value CNT corresponds to the time that the phase modulation signal Xpm is high. That is, the reciprocal count value CNT becomes larger the longer the time that the phase modulation signal Xpm is high, and becomes smaller the shorter the time that the phase modulation signal Xpm is high.

[0099] The M D flip-flop circuits 81, the subtractor 82, and the N D flip-flop circuits 83 constitute a reciprocal count value generation unit 80 that generates a reciprocal count value CNT based on the difference between the count value CNT3 output from the reciprocal count integration unit 50 and the count value DCNT3.

[0100] The frequency ratio digital conversion circuit 3 then outputs a reciprocal count value CNT. This reciprocal count value CNT is a frequency delta-sigma modulated signal that indicates the frequency ratio between the signal under test X and the reference signal CLK. Since the reciprocal of frequency is the period, the reciprocal count value CNT can also be said to be a signal that indicates the period ratio between the signal under test X and the reference signal CLK. This reciprocal count value CNT becomes the output signal OUT of the frequency delta-sigma modulated signal output circuit 1 shown in Figure 19.

[0101] Figure 21 shows an example configuration of the time digital value generation unit 60. As shown in Figure 21, the time digital value generation unit 60 includes a control unit 61, an oscillator 62, a count circuit 63, a D flip-flop circuit 64, an adder 65, and a D flip-flop circuit 66. Note that in Figure 21, for the sake of simplicity, only one D flip-flop circuit 64 and one D flip-flop circuit 66 are shown, but in reality, there are K D flip-flop circuits 64 and M D flip-flop circuits 66.

[0102] The control unit 61 detects the rising and falling edges of the phase modulation signal Xpm and activates and outputs the enable signal EN. In this embodiment, the enable signal EN is active when it is high. After setting the enable signal EN to high, the control unit 61 switches the enable signal EN from high to low when the number of rising edges of the clock signal CK output from the oscillator 62 reaches a predetermined number, based on the count value CNT2 output from the count circuit 63. After switching the enable signal EN from high to low, the control unit 61 activates and outputs the reset signal RST when the rising edges of the reference signal CLK arrive a predetermined number of times. In this embodiment, the reset signal RST is active when it is high. After setting the reset signal RST to high, the control unit 61 switches the reset signal RST from high to low after a predetermined time has elapsed. The enable signal EN is supplied to the oscillator 62, and the reset signal RSTX is supplied to the count circuit 63, K D flip-flop circuits 64, and M D flip-flop circuits 66.

[0103] The oscillator 62 oscillates when the enable signal EN is at a high level and stops oscillating when the enable signal EN is at a low level. For example, as shown in Figure 22, the oscillator 62 includes a two-input AND circuit 67 and an inverting circuit 68. The AND circuit 67 receives the enable signal EN and the output signal of the inverting circuit 68 as inputs and outputs the AND signal of the enable signal EN and the output signal of the inverting circuit 68. The inverting circuit 68 receives the output signal of the AND circuit 67 as input and outputs the inverted signal of the output signal of the AND circuit 67.

[0104] The count circuit 63 counts the number of edges of the clock signal CK. In this embodiment, the count circuit 63 counts the number of rising edges of the clock signal CK and outputs a count value CNT2 in K bits.

[0105] The K D flip-flop circuits 64 acquire and hold a K-bit count value CNT2 in synchronization with the reference signal CLK. In this embodiment, when the reset signal RST is low, the K D flip-flop circuits 64 acquire the K-bit count value CNT2 when the rising edge of the reference signal CLK arrives and hold it as a K-bit count value DCNT2. Also, when the reset signal RST is high, the K D flip-flop circuits 64 initialize the count value DCNT2 to zero.

[0106] The count circuit 63 and the K D flip-flop circuits 64 constitute a second counting unit 91 that counts the output signal from the oscillator 62 with reference to the reference signal CLK and generates a count value DCNT2.

[0107] The adder 65 adds the M-bit value held and output by the M D flip-flop circuits 66 and the K-bit count value DCNT2 held by the K D flip-flop circuits 64, and outputs an M-bit calculated value.

[0108] The M D flip-flop circuits 66 acquire and hold a K-bit count value CNT2 in synchronization with the reference signal CLK. In this embodiment, when the reset signal RST is low, the M D flip-flop circuits 66 acquire the M-bit calculated value output from the adder 65 when the rising edge of the reference signal CLK arrives and hold it as an M-bit time digital value TD. Also, when the reset signal RST is high, the M D flip-flop circuits 66 initialize the time digital value TD to zero.

[0109] The adder 65 and the M D flip-flop circuits 66 constitute a count value integration unit 92 that integrates the count value DCNT2 to obtain an integrated value and outputs it as a time digital value.

[0110] Next, the detailed operation of the frequency ratio digital conversion circuit 3 in the fourth embodiment will be explained using Figures 23 and 24. Figures 23 and 24 are timing charts showing an example of the operation of the frequency ratio digital conversion circuit 3. In the example of Figures 23 and 24, the integer k input to the multiplier 51 is 32. Also, in the example of Figures 23 and 24, the phase modulation signal Xpm is assumed to be a signal with a constant period in order to simplify the explanation of the operation of the frequency ratio digital conversion circuit 3, but the operating principle of the frequency ratio digital conversion circuit 3 remains the same even if the period of the phase modulation signal Xpm changes randomly.

[0111] As shown in Figure 23, the count value CNT1 increases by 1 each time the rising edge of the reference signal CLK arrives. At time t0, when the phase modulation signal Xpm transitions from a low level to a high level, the count value CNT1 is 10, so the count value DCNT1 changes to 10, and the count value CNT3 changes to 320. Also, when the phase modulation signal Xpm transitions from a low level to a high level, the oscillator 62 starts oscillating, and the count value CNT2 increases by 1 each time the rising edge of the clock signal CK arrives.

[0112] At time t1, after time P1 has elapsed from time t0, the first rising edge of the reference signal CLK arrives after the phase-modulated signal Xpm has transitioned to a high level, and in synchronization with this edge, the count value DCNT2 changes from 0 to 4. Also in synchronization with this edge, the reset signal RST transitions from a low level to a high level, and the count value DCNT3 and the reciprocal count value CNT are initialized to 0. Subsequently, the reset signal RST transitions from a high level to a low level, and the initialization operation of the count value DCNT3 and the reciprocal count value CNT is canceled.

[0113] At time t2, the second rising edge of the reference signal CLK arrives, and in synchronization with this edge, the count value DCNT2 changes from 4 to 12, and the time digital value TD changes from 0 to 4. Also in synchronization with this edge, the count value CNT3 changes from 320 to 316.

[0114] At time t3, the third rising edge of the reference signal CLK arrives, and in synchronization with this edge, the count value DCNT2 changes from 12 to 20, and the time digital value TD changes from 4 to 16. Also in synchronization with this edge, the count value CNT3 changes from 316 to 304.

[0115] At time t4, the fourth rising edge of the reference signal CLK arrives, and in synchronization with this edge, the count value DCNT2 changes from 20 to 29, and the time digital value TD changes from 16 to 36. Also in synchronization with this edge, the count value CNT3 changes from 304 to 284. Subsequently, when the count value CNT2 reaches 32, the oscillation of the oscillator 62 stops, and the count value CNT2 is held at 32.

[0116] At time t5, the fifth rising edge of the reference signal CLK arrives, and in synchronization with this edge, the count value DCNT2 changes from 29 to 32, and the time digital value TD changes from 36 to 65. Also in synchronization with this edge, the count value CNT3 changes from 284 to 255.

[0117] At time t6, the sixth rising edge of the reference signal CLK arrives, and in synchronization with this edge, the time digital value TD changes from 65 to 97, and the count value CNT3 changes from 255 to 223. The count value DCNT2 remains unchanged at 32.

[0118] At time t7, the seventh rising edge of the reference signal CLK arrives, and in synchronization with this edge, the time digital value TD changes from 97 to 129, and the count value CNT3 changes from 223 to 191. The count value DCNT2 remains unchanged at 32.

[0119] At time t8, the eighth rising edge of the reference signal CLK arrives, and in synchronization with this edge, the clock signal DCLK transitions from a low level to a high level, changing the count value DCNT3 and the reciprocal count value CNT from 0 to 191. Also in synchronization with this edge, the reset signal RSTX transitions from a low level to a high level, initializing the count value CNT2, the count value DCNT2, and the time digital value TD to 0. Because the time digital value TD has changed to 0, the count value CNT3 changes from 191 to 320. Subsequently, the reset signal RSTX transitions from a high level to a low level, and the initialization of the count value CNT2, the count value DCNT2, and the time digital value TD is reset.

[0120] Subsequently, as time passes, as shown in Figure 24, at time t9, the 11th rising edge of the reference signal CLK arrives, and the count value CNT1 changes from 20 to 21. Then, at time t10, when the phase modulation signal Xpm transitions from a high level to a low level, the count value CNT1 is 21 at this time, so the count value DCNT1 changes from 10 to 21, and the count value CNT3 changes from 320 to 672. Also, when the phase modulation signal Xpm transitions from a high level to a low level, the oscillator 62 starts oscillating, and the count value CNT2 increases by 1 each time the rising edge of the clock signal CK arrives.

[0121] At time t11, after time P2 has elapsed from time t10, the 12th rising edge of the reference signal CLK arrives, and the count value DCNT2 changes from 0 to 6 in synchronization with this edge.

[0122] At time t12, the 13th rising edge of the reference signal CLK arrives, and in synchronization with this edge, the count value DCNT2 changes from 6 to 14, and the time digital value TD changes from 0 to 6. Also in synchronization with this edge, the count value CNT3 changes from 672 to 666.

[0123] At time t13, the 14th rising edge of the reference signal CLK arrives, and in synchronization with this edge, the count value DCNT2 changes from 14 to 22, and the time digital value TD changes from 6 to 20. Also in synchronization with this edge, the count value CNT3 changes from 666 to 652.

[0124] At time t14, the 15th rising edge of the reference signal CLK arrives, and in synchronization with this edge, the count value DCNT2 changes from 22 to 31, and the time digital value TD changes from 20 to 42. Also in synchronization with this edge, the count value CNT3 changes from 652 to 630. Subsequently, when the count value CNT2 reaches 32, the oscillation of the oscillator 62 stops, and the count value CNT2 is held at 32.

[0125] At time t15, the 16th rising edge of the reference signal CLK arrives, and in synchronization with this edge, the count value DCNT2 changes from 31 to 32, and the time digital value TD changes from 42 to 73. Also in synchronization with this edge, the count value CNT3 changes from 630 to 599.

[0126] At time t16, the 17th rising edge of the reference signal CLK arrives, and in synchronization with this edge, the time digital value TD changes from 73 to 105, and the count value CNT3 changes from 599 to 567. The count value DCNT2 remains unchanged at 32.

[0127] At time t17, the 18th rising edge of the reference signal CLK arrives, and in synchronization with this edge, the time digital value TD changes from 105 to 137, and the count value CNT3 changes from 567 to 535. The count value DCNT2 remains unchanged at 32.

[0128] At time t18, the 19th rising edge of the reference signal CLK arrives. Synchronized with this edge, the clock signal DCLK transitions from a low level to a high level, changing the count value DCNT3 from 191 to 535, and the reciprocal count value CNT from 191 to 344. Also synchronized with this edge, the reset signal RSTX transitions from a low level to a high level, initializing the count values ​​CNT2, DCNT2, and time digital value TD to 0. Because the time digital value TD has changed to 0, the count value CNT3 changes from 535 to 672. Subsequently, the reset signal RSTX transitions from a high level to a low level, and the initialization of the count values ​​CNT2, DCNT2, and time digital value TD is reset.

[0129] Here, the time P2 from time t10 to time t11 shown in Figure 24 is longer than the time P1 from time t0 to time t1 shown in Figure 23. Also, the time digital value TD at each time from time t12 to time t18 transitions to a value greater than the time digital value TD at each time from time t2 to time t8. Therefore, the longer the time interval between the edge of the phase modulation signal Xpm and the rising edge of the reference signal CLK, the larger the time digital value TD becomes. The time digital value TD after the change at time t7, i.e., 129, corresponds to time P1, and the time digital value TD after the change at time t17, i.e., 137, corresponds to time P2.

[0130] In the examples in Figures 23 and 24, if T is the time of one period of the reference signal CLK, then the time when the phase-modulated signal Xpm is at a high level is T × (21 - 10) + P1 - P2 = (T × 21 - P2) - (T × 10 - P1). Here, the count value CNT3 after the change at time t7, i.e., 191 (= 32 × 10 - 129), corresponds to (T × 10 - P1), and the count value CNT3 after the change at time t17, i.e., 535 (= 32 × 21 - 137), corresponds to (T × 21 - P2). Therefore, the reciprocal count value CNT after the change at time t18, i.e., 344 (= 535 - 191), corresponds to the time when the phase-modulated signal Xpm is at a high level.

[0131] In the examples shown in Figures 23 and 24, the oscillator 62 stops after 32 oscillations, and the count value DCNT2 is held at 32. Therefore, after the oscillator 62 stops, the time digital value TD increases by 32 each time the rising edge of the reference signal CLK arrives. On the other hand, since the integer k is the same as the number of oscillations, 32, the k-fold count value DCNT1 of the first count unit 40 and the time digital value TD are matched, thus increasing the accuracy of the reciprocal count value CNT obtained from the difference between them. Thus, it is preferable that the number of oscillations of the oscillator 62 is equal to the integer k. Furthermore, it is preferable that the number of oscillations of the oscillator 62, i.e., the integer k, is 2 to the power of n (where n is a positive integer). In this way, the multiplier 51 can be realized as a simple circuit that shifts the count value DCNT1 by n bits.

[0132] According to the frequency delta-sigma modulation signal output circuit 1 of the fourth embodiment described above, the frequency ratio digital conversion circuit 3 generates a reciprocal count value CNT corresponding to the time when the phase modulation signal Xpm is high level, thereby generating a frequency delta-sigma modulation signal that indicates the frequency ratio between the signal under measurement X and the reference signal CLK. The frequency ratio digital conversion circuit 3 may also generate a reciprocal count value CNT corresponding to the time when the phase modulation signal Xpm is low level, or it may generate a reciprocal count value CNT corresponding to the time interval between two rising edges or two falling edges of the phase modulation signal Xpm.

[0133] Furthermore, according to the frequency ratio digital conversion circuit 3 in the fourth embodiment, the frequency ratio digital conversion circuit 3 can be realized with a simple configuration using a first counting unit 40, a reciprocal count integrated value synthesis unit 50, a time digital value generation unit 60, and a reciprocal count value generation unit 80. The time digital value generation unit 60 can also be realized with a simple configuration using an oscillation unit 62 and a second counting unit 91, thus reducing the circuit area of ​​the frequency ratio digital conversion circuit 3. Therefore, according to the frequency delta-sigma modulation signal output circuit 1 in the fourth embodiment, it is possible to generate a frequency delta-sigma modulation signal with the same accuracy as the frequency delta-sigma modulation signal output circuit 1 in the third embodiment, with a smaller circuit size than the frequency delta-sigma modulation signal output circuit 1 in the third embodiment.

[0134] In this embodiment, a reciprocal counting method is employed, where the frequency of the phase-modulated signal Xpm is lower than the frequency of the reference signal CLK. However, a similar effect can be obtained by employing a direct counting method in which the reference signal CLK and the phase-modulated signal Xpm are swapped.

[0135] 2. Sensor module The sensor module of this embodiment includes a frequency delta-sigma modulation signal output circuit 1 according to any of the embodiments described above, and a physical quantity sensor that outputs a frequency signal of the object to be measured, which is the input signal to the frequency delta-sigma modulation signal output circuit 1, and outputs packet data incorporating the detected physical quantity. For example, the physical quantity sensor is a frequency-changing type sensor in which the frequency of the output signal changes according to the physical quantity to be detected. The signal under measurement X in each of the embodiments described above is a signal based on the output signal of the physical quantity sensor. For example, the signal under measurement X may be the output signal of the physical quantity sensor itself, or it may be the output signal of an oscillator circuit (not shown) that causes the physical quantity sensor to oscillate. In the following, a sensor module 100 in which the physical quantity sensor is an acceleration sensor that detects acceleration as a physical quantity will be described as an example.

[0136] Figure 25 is a perspective view showing the configuration of the sensor module 100 as seen from the mounting surface side to which the sensor module 100 is fixed. In the following description, the direction along the long side of the sensor module 100, which forms a rectangle in plan view, will be described as the X-axis direction, the direction perpendicular to the X-axis direction in plan view will be described as the Y-axis direction, and the thickness direction of the sensor module 100 will be described as the Z-axis direction.

[0137] The sensor module 100 has a rectangular shape in plan view, for example, with a length of approximately 50 mm along the long side in the X-axis direction, a length of approximately 24 mm along the short side in the Y-axis direction perpendicular to the X-axis direction, and a thickness of approximately 16 mm. Screw holes 103 are formed at two locations near each end of one long side and at one location in the center of the other long side. Fixing screws are passed through each of these three screw holes 103 to fix the module to the mounting surface of a structure such as a bridge or a billboard.

[0138] As shown in Figure 25, an opening 121 is provided on the surface of the sensor module 100 as viewed from the mounting surface. A plug-type connector 116 is located inside the opening 121. The connector 116 has multiple pins arranged in two rows, with multiple pins arranged in the Y-axis direction in each row. A socket-type connector (not shown) is connected to the mounting object to the connector 116, and electrical signals such as the drive voltage and detection data of the sensor module 100 are transmitted and received.

[0139] Figure 26 is an exploded perspective view of the sensor module 100. As shown in Figure 26, the sensor module 100 consists of a container 101, a lid 102, a sealing member 141, and a circuit board 115. More specifically, the sensor module 100 has a configuration in which the circuit board 115 is mounted inside the container 101 with a fixing member 130 interposed therebetween, and the opening of the container 101 is covered by the lid 102 via a cushioning sealing member 141.

[0140] The container 101 is a housing for the circuit board 115, formed in a box shape with an internal space, for example, using aluminum. The container 101 can be formed by machining aluminum or by die-casting. The material of the container 101 is not limited to aluminum; other metals such as zinc or stainless steel, resin, or composite materials of metal and resin may also be used. The external shape of the container 101 is a rectangular prism with a roughly rectangular planar shape, similar to the overall shape of the sensor module 100 described above, and fixing protrusions 104 are provided at two locations near both ends of one long side and at one location in the center of the other long side. Screw holes 103 are formed in each of these fixing protrusions 104. Here, the fixing protrusions 104 provided at the two locations near both ends of one long side include the intersection of the short side and the long side, and in plan view they form a roughly triangular shape. Furthermore, the fixed projection 104 located at one point in the center of the other long side has a roughly trapezoidal shape when viewed from above, facing towards the internal space of the container 101.

[0141] The container 101 is a box-shaped container with a rectangular parallelepiped exterior and an opening on one side. The interior of the container 101 is an internal space enclosed by a bottom wall 112 and a side wall 111. In other words, the container 101 is a box-shaped container with an opening 123 on one side opposite the bottom wall 112, and the outer edge of the circuit board 115 is positioned along the inner surface 122 of the side wall 111, with a lid 102 fixed to cover the opening. Here, the opening 123 opposite the bottom wall 112 is the surface on which the lid 102 is placed. Fixing protrusions 104 are erected on the opening 123 at two locations near both ends of one long side of the container 101 and at one location in the center of the other long side. The upper surface of the fixing protrusions 104, i.e., the surface exposed in the -Z direction, is flush with the top surface of the container 101.

[0142] Furthermore, within the internal space of the container 101, a projection 129 is provided in the center of one of the long sides opposite to the fixing projection 104 provided in the center of the other long side, and protrudes from the side wall 111 into the internal space from the bottom wall 112 to the opening surface 123. A female screw 174 is provided on the upper surface of the projection 129. The lid 102 is fixed to the container 101 via a sealing member 141 by a screw 172 and a female screw 174 inserted through a through hole 176. Here, the fixing projection 104 provided in the center of the other long side may be configured to protrude from the side wall 111 into the internal space from the bottom wall 112 to the opening surface 123, similar to the projection 129. Note that the projection 129 and the fixing projection 104 are provided in positions opposite to the constricted portions 133 and 134 of the circuit board 115, which will be described later.

[0143] The internal space of the container 101 is provided with a first base 127 and a second base 125 that protrude in a stepped manner from the bottom wall 112 toward the opening surface 123. The first base 127 is positioned opposite the area where the plug-type connector 116 attached to the circuit board 115 is located, and as shown in Figure 25, it is provided with an opening 121 into which the plug-type connector 116 is inserted. The first base 127 functions as a base for fixing the circuit board 115 to the container 101. The opening 121 penetrates from the inside to the outside of the container 101.

[0144] The second base 125 is located on the opposite side of the first base 127 from the fixing projection 104 and projection 129 located in the center of the long side, and is provided in the vicinity of the fixing projection 104 and projection 129. The second base 125 may be connected to either the fixing projection 104 or projection 129. The second base 125 functions as a base for fixing the circuit board 115 to the container 101 on the opposite side of the first base 127 from the fixing projection 104 and projection 129.

[0145] Although the external shape of container 101 has been described as a box-like shape with a roughly rectangular planar shape and no lid, it is not limited to this, and the planar shape of the external shape of container 101 may be a square, hexagon, octagon, or other shape. Furthermore, the planar shape of the external shape of container 101 may have chamfered corners at the vertices of the polygon, and may also have a planar shape in which at least one of the sides is curved. In addition, the planar shape of the interior of container 101 is not limited to the shapes described above, and may be other shapes. Furthermore, the planar shapes of the external and interior of container 101 may or may not be similar.

[0146] The circuit board 115 is a multilayer substrate with multiple through-holes formed on it, and uses a glass epoxy substrate. However, the circuit board 115 is not limited to a glass epoxy substrate; any rigid substrate capable of mounting multiple physical quantity sensors, electronic components, connectors, etc., may be used, for example, a composite substrate or a ceramic substrate.

[0147] The circuit board 115 has a second surface 115r on the bottom wall 112 side and a first surface 115f which is the front and back of the second surface 115r. The first surface 115f of the circuit board 115 is equipped with a control IC 119 as a processing unit and acceleration sensors 118x, 118y, and 118z as physical quantity sensors. The second surface 115r of the circuit board 115 is equipped with a connector 116. Although not shown in the illustration and its description, the circuit board 115 may also be provided with other wiring, terminal electrodes, etc.

[0148] In a plan view, the circuit board 115 has constricted portions 133 and 134 at the center of the X-axis direction along the long side of the container 101, where the outer edge of the circuit board 115 is narrowed. In a plan view, the constricted portions 133 and 134 are provided on both sides of the circuit board 115 in the Y-axis direction, and narrow from the outer edge of the circuit board 115 toward the center. The constricted portions 133 and 134 are also provided opposite the projection 129 and the fixed projection 104 of the container 101.

[0149] The circuit board 115 is inserted into the internal space of the container 101 with its second surface 115r facing the first base 127 and the second base 125. The circuit board 115 is then supported by the container 101 through the first base 127 and the second base 125.

[0150] The acceleration sensors 118x, 118y, and 118z each detect acceleration in one axis direction. Specifically, acceleration sensor 118x is mounted so that the front and back surfaces of the package face the X-axis direction and its side faces the first surface 115f of the circuit board 115. Acceleration sensor 118x detects acceleration applied in the X-axis direction. Acceleration sensor 118y is mounted so that the front and back surfaces of the package face the Y-axis direction and its side faces the first surface 115f of the circuit board 115. Acceleration sensor 118y detects acceleration applied in the Y-axis direction. Acceleration sensor 118z is mounted so that the front and back surfaces of the package face the Z-axis direction, that is, so that the front and back surfaces of the package face the first surface 115f of the circuit board 115. Acceleration sensor 118z detects acceleration applied in the Z-axis direction.

[0151] The control IC 119, acting as a processing unit, is electrically connected to the acceleration sensors 118x, 118y, and 118z via wiring (not shown). IC stands for Integrated Circuit. The control IC 119 is also an MCU, incorporating the frequency delta-sigma modulation signal output circuit 1 and a storage unit including non-volatile memory as described in the above embodiment. It controls each part of the sensor module 100, generates detection data based on the output signals of the acceleration sensors 118x, 118y, and 118z, and generates packet data incorporating the detection data. MCU stands for Micro Controller Unit. The storage unit stores a program that defines the order and content for detecting acceleration, a program that incorporates the detection data into the packet data, and other associated data. Although not shown, the circuit board 115 may also be mounted with several other electronic components.

[0152] Here, the configuration of the accelerometers 118x, 118y, and 118z will be explained using Figures 27 and 28.

[0153] Figure 27 is a perspective view illustrating the schematic configuration of a sensor element for detecting acceleration. Figure 28 is a cross-sectional view illustrating the schematic configuration of an acceleration detector using an acceleration detection sensor element.

[0154] In Figure 27, the x-axis, y'-axis, and z'-axis are shown as three mutually orthogonal axes. Each axis corresponds to a so-called quartz z-plate, which is cut along a plane defined by the x-axis and y'-axis and processed into a flat plate, and has a predetermined thickness t in the z'-axis direction perpendicular to the plane perpendicular to the z'-axis. In a Cartesian coordinate system consisting of the x-axis as the electrical axis, the y-axis as the mechanical axis, and the z-axis as the optical axis of the piezoelectric material quartz used as the base material for the acceleration sensor, the z'-axis is defined as the axis obtained by tilting the z-axis by a rotation angle φ so that the +z side rotates in the -y direction of the y-axis, and the y'-axis is defined as the axis obtained by tilting the y-axis by a rotation angle φ so that the +y side rotates in the +z direction of the z-axis. The example described here uses a z'-plate, which is a so-called quartz z-plate, as the base material. The rotation angle φ is preferably -5°≦φ≦15°. The z'-axis is defined as the axis aligned with the direction in which gravity acts in the acceleration sensors 118x, 118y, and 118z.

[0155] First, the configuration of the sensor element 200 for detecting acceleration will be explained using Figure 27. The sensor element 200 has a substrate structure 201 including a base 210, an acceleration detection element 270 connected to the substrate structure 201 for detecting physical quantities, and mass parts 280 and 282.

[0156] The substrate structure 201 of the sensor element 200 comprises a base portion 210, a movable portion 214 connected to the base portion 210 via a joint portion 212, a connecting portion 240, and first support portions 220, second support portion 230, third support portion 250, and fourth support portion 260 provided connected to the base portion 210. Here, the third support portion 250 and the fourth support portion 260 are connected on the side where the connecting portion 240 is located.

[0157] The substrate structure 201 uses a quartz substrate, specifically a z' plate, which is a quartz z plate cut at a predetermined angle as described above from a quartz crystal or similar material that is a piezoelectric material. By patterning this quartz substrate, these components are integrally formed as the substrate structure 201. For example, photolithography and wet etching techniques can be used for the patterning.

[0158] The base 210 is connected to the movable part 214 via the joint 212 and supports the movable part 214. The base 210 is connected to the movable part 214 via the joint 212, to the connecting part 240 located on the opposite side of the movable part from the side where the joint 212 is located, to the first support part 220 and the second support part 230, and to the third support part 250 and the fourth support part 260 which are connected on the side of the connecting part 240.

[0159] The joint portion 212 is provided between the base portion 210 and the movable portion 214 and is connected to both the base portion 210 and the movable portion 214. The thickness of the joint portion 212 is made thinner than the thickness of the base portion 210 and the thickness of the movable portion 214, and it is formed in a constricted shape when viewed in cross-section from the x-axis direction. The joint portion 212 is formed as a thin-walled portion by, for example, so-called half-etching of the substrate structure 201 including the joint portion 212. The joint portion 212 functions as a pivot point and a rotation axis along the x-axis direction when the movable portion 214 is displaced relative to the base portion 210.

[0160] The movable part 214 is connected to the base part 210 via a joint part 212. The movable part 214 has a plate-like shape and has main surfaces 214a and 214b that face each other along the z' axis and are in a front-back relationship. The movable part 214 is displaced in the direction intersecting the main surfaces 214a and 214b, i.e., in the z' axis direction, with the joint part 212 as a pivot point, in response to acceleration, which is a physical quantity applied in the direction intersecting the main surfaces 214a and 214b, i.e., in the z' axis direction.

[0161] The connecting portion 240 extends from the base portion 210 on the +x direction side, where the third support portion 250 (described later) is provided, along the x-axis direction so as to surround the movable portion 214, and is connected to the base portion 210 on the -x direction side, where the fourth support portion 260 (described later) is provided.

[0162] The first support portion 220 and the second support portion 230 are provided symmetrically around the acceleration detection element 270. The third support portion 250 and the fourth support portion 260 are also provided symmetrically around the acceleration detection element 270. The substrate structure 201 is supported by the first support portion 220, the second support portion 230, the third support portion 250, and the fourth support portion 260.

[0163] The acceleration detection element 270 is connected to the base 210 and the movable part 214. In other words, the acceleration detection element 270 is provided so as to straddle the base 210 and the movable part 214. The acceleration detection element 270 has vibrating beam sections 271a and 271b as vibrating parts, and a first base 272a and a second base 272b. In the acceleration detection element 270, where the first base 272a and the second base 272b are connected to the base 210, for example, when the movable part 214 is displaced according to a physical quantity, stress is generated in the vibrating beam sections 271a and 271b, and the physical quantity detection information generated in the vibrating beam sections 271a and 271b changes. In other words, the vibration frequency of the vibrating beam sections 271a and 271b changes. In this embodiment, the acceleration detection element 270 is a double tuning fork type vibrating element having two vibrating beam sections 271a, 271b, a first base section 272a, and a second base section 272b. Here, the vibrating beam sections 271a, 271b, which are the vibrating parts, may also be referred to as vibrating arms, vibrating beams, or columnar beams.

[0164] The acceleration detection element 270 uses a quartz substrate, specifically a z' plate, which is a quartz z plate cut at a predetermined angle from a piezoelectric material such as a quartz crystal, similar to the substrate structure 201 described above. The acceleration detection element 270 is formed by patterning the quartz substrate using photolithography and etching techniques. This allows the vibration beam portions 271a, 271b, the first base portion 272a, and the second base portion 272b to be formed integrally.

[0165] The material of the acceleration detection element 270 is not limited to the aforementioned quartz substrate. For example, piezoelectric materials such as lithium tantalate (LiTaO3), lithium tetraborate (Li2B4O7), lithium niobate (LiNbO3), lead zirconate titanate (PZT), zinc oxide (ZnO), and aluminum nitride (AlN) can be used as the material of the acceleration detection element 270, or semiconductor materials such as silicon with a piezoelectric coating of zinc oxide (ZnO) or aluminum nitride (AlN). In this case, it is preferable that the substrate structure 201 and the acceleration detection element 270 are made of the same material.

[0166] Although not shown in the illustrations and descriptions, the acceleration detection element 270 may be provided with lead electrodes and excitation electrodes.

[0167] The mass parts 280 and 282 are provided on the main surface 214a of the movable part 214 and on the main surface 214b, which is the back surface in a front-back relationship with the main surface 214a. More specifically, the mass parts 280 and 282 are provided on the main surface 214a and the main surface 214b via a mass bonding material (not shown). Examples of materials for the mass parts 280 and 282 include metals such as copper (Cu) and gold (Au).

[0168] Furthermore, in this embodiment, the acceleration detection element 270 is configured as a double tuning fork type vibrating element in which the vibrating part is composed of two columnar beams, vibrating beams 271a and 271b, but it can also be configured with a single columnar beam.

[0169] Next, using Figure 28, the configuration of the acceleration detector 300 using the acceleration detection sensor element 200 described above will be explained.

[0170] As shown in Figure 28, the acceleration detector 300 is equipped with the sensor element 200 described above. The acceleration detector 300 has the sensor element 200 and a package 310. The package 310 has a package base 320 and a lid 330. The sensor element 200 is housed in the package 310 of the acceleration detector 300. Specifically, the sensor element 200 is housed in a space 311 provided by the connection between the package base 320 and the lid 330.

[0171] The package base 320 has a recess 321, and the sensor element 200 is provided within the recess 321. The shape of the package base 320 is not particularly limited, as long as it can accommodate the sensor element 200 within the recess 321. For example, the package base 320 in this embodiment can be made of materials such as ceramics, quartz, glass, or silicon.

[0172] The package base 320 has a stepped portion 323 that protrudes toward the lid 330 from the inner bottom surface 322, which is the inner bottom surface of the recess of the package base 320. The stepped portion 323 is provided, for example, along the inner wall of the recess 321. Multiple internal terminals 340b are provided on the stepped portion 323.

[0173] The internal terminal 340b is positioned opposite the fixing terminal 379b, which is provided on the fixing parts of the first support part 220, second support part 230, third support part 250, and fourth support part 260 of the sensor element 200, in a position that overlaps with it in a plan view. The internal terminal 340b is electrically connected to the fixing terminal 379b using a silicone resin-based conductive adhesive 343 containing a conductive material such as a metal filler. In this way, the sensor element 200 is mounted on the package base 320 and housed in the package 310.

[0174] In the package base 320, the outer bottom surface 324, which is the surface opposite the inner bottom surface 322, is provided with an external terminal 344 used when mounting to an external component. The external terminal 344 is electrically connected to the internal terminal 340b via internal wiring (not shown).

[0175] The internal terminal 340b and the external terminal 344 are composed of a metal film, for example, a metallized layer of tungsten (W) with a coating of nickel (Ni), gold (Au), etc., laminated on top of it by a method such as plating.

[0176] The package base 320 is provided with a sealing portion 350 at the bottom of the recess 321 that seals the inside of the package 310. The sealing portion 350 is located within a through hole 325 formed in the package base 320. The through hole 325 penetrates from the outer bottom surface 324 to the inner bottom surface 322. In the example shown in Figure 28, the through hole 325 has a stepped shape in which the diameter of the hole on the outer bottom surface 324 side is larger than the diameter of the hole on the inner bottom surface 322 side. The sealing portion 350 is formed by placing a sealing material, such as a gold (Au) and germanium (Ge) alloy or solder, into the through hole 325, heating and melting it, and then allowing it to solidify. The sealing portion 350 is provided to hermetically seal the inside of the package 310.

[0177] The lid 330 is provided to cover the recess 321 of the package base 320. The shape of the lid 330 is, for example, plate-like. For the lid 330, for example, the same material as the package base 320, or a metal such as an alloy of iron (Fe) and nickel (Ni), or stainless steel can be used. The lid 330 is joined to the package base 320 via a lid joining member 332. For the lid joining member 332, for example, a seam ring, low-melting-point glass, or an inorganic adhesive can be used.

[0178] After joining the lid 330 to the package base 320, the inside of the package 310 is depressurized, i.e., under high vacuum conditions, and a sealing material is placed in the through-hole 325. After heating and melting, the material is solidified to form a sealing portion 350, thereby providing an airtight seal inside the package 310. The inside of the package 310 may be filled with an inert gas such as nitrogen, helium, or argon.

[0179] In the acceleration detector 300, when a drive signal is applied to the excitation electrode of the sensor element 200 via the external terminal 344, internal terminal 340b, fixed part connection terminal 379b, etc., the vibrating beam portions 271a and 271b of the sensor element 200 vibrate at a predetermined frequency. The acceleration detector 300 then outputs the resonant frequency of the sensor element 200, which changes according to the applied acceleration, as an output signal. The acceleration detector 300 can be used as the acceleration sensors 118x, 118y, and 118z of the aforementioned sensor module 100, and each of the acceleration sensors 118x, 118y, and 118z outputs a measured signal X with a frequency corresponding to the applied acceleration.

[0180] As described above, the sensor module 100 of this embodiment includes a frequency delta-sigma modulation signal output circuit 1, which provides a frequency delta-sigma modulation signal with reduced noise components, thereby improving the measurement accuracy of physical quantities.

[0181] In the above explanation, a sensor module 100 equipped with acceleration sensors 118x, 118y, and 118z was used as an example of a physical quantity sensor. However, a sensor module equipped with a physical quantity sensor that detects at least one of the following physical quantities: mass, angular velocity, angular acceleration, capacitance, and temperature may also be used.

[0182] Among mass sensors that detect mass as a physical quantity, the quartz crystal microbalancing method is known as a technique for measuring minute changes in mass. This type of mass sensor utilizes the fact that an increase in the amount of material attached to the electrode surface of the quartz crystal reduces the oscillation frequency, and a decrease in the amount of material increases the oscillation frequency. The detection sensitivity of such a mass sensor can be calculated using Sauerbrey's equation. For example, in the case of an AT-cut quartz crystal with a fundamental frequency of 27 MHz, a decrease in frequency of 1 Hz corresponds to an increase in mass of 0.62 ng / cm² on the electrode surface.

[0183] Furthermore, angular velocity sensors, which detect angular velocity or angular acceleration as a physical quantity, utilize the fact that when an object rotating at a constant angular velocity ω is observed from an observation point rotating at an angular velocity Ω, the object's angular velocity appears to be ω-Ω. In such angular velocity sensors, the apparent resonant frequency observed from the electrodes changes when the sensor element receives angular acceleration while a wave with a natural frequency is circulating by electrostatically driving a disk-shaped mass using electrodes. In principle, such angular velocity sensors have no bandwidth limitations, and for example, improving the precision of technologies related to frequency measurement and nonlinearity correction directly leads to increased detection sensitivity.

[0184] Furthermore, in a capacitance sensor that detects capacitance as a physical quantity, the capacitance to be measured can be measured by generating an RC oscillation using a reference resistor and the capacitance to be measured, and then measuring the oscillation frequency. This method utilizes the fact that when the capacitance to be measured changes, the time constant given by RC changes, causing a shift in the oscillation frequency. In addition, in a capacitance sensor, if a reference capacitance is prepared separately from the capacitance to be measured, and an RC oscillation is generated using the reference resistor and the reference capacitance, and this is used as the reference oscillation frequency, and a mechanism is implemented to detect the difference between this and the previous oscillation frequency, various error factors can be eliminated.

[0185] Furthermore, in temperature sensors that detect temperature as a physical quantity, temperature can be measured by using a thermistor and a reference capacitance to generate an RC oscillation and measuring the oscillation frequency. This method utilizes the fact that when the resistance value of the thermistor changes with temperature, the time constant given by RC changes, causing a shift in the oscillation frequency. In addition, in a temperature sensor, a reference resistor is prepared separately from the thermistor, and an RC oscillation is generated using the reference resistor and reference capacitance. This is used as the reference oscillation frequency, and a mechanism is implemented to detect the difference between this and the previously mentioned oscillation frequency, thereby eliminating various error factors.

[0186] Even in a sensor module 100 equipped with physical quantity sensors that detect various physical quantities as described above, by including a frequency delta-sigma modulation signal output circuit 1, a frequency delta-sigma modulation signal with reduced noise components can be obtained, thereby improving the measurement accuracy of physical quantities.

[0187] Although embodiments and modified examples have been described above, the present invention is not limited to these embodiments and can be implemented in various forms without departing from its spirit. For example, the above embodiments can be combined as appropriate.

[0188] The present invention includes configurations substantially identical to those described in the embodiments, for example, configurations with the same function, method, and results, or configurations with the same purpose and effect. Furthermore, the present invention includes configurations in which non-essential parts of the configurations described in the embodiments are replaced. Furthermore, the present invention includes configurations that produce the same effects or achieve the same purpose as those described in the embodiments. Finally, the present invention includes configurations that add known technology to the configurations described in the embodiments.

[0189] The following can be derived from the embodiments and modifications described above.

[0190] One embodiment of a frequency delta-sigma modulated signal output circuit is: A phase modulation circuit generates n delayed signals by delaying the signal under test, where n is an integer of 2 or more, and generates a phase-modulated signal by randomly selecting one of the n delayed signals in synchronization with the signal under test. The system includes a frequency ratio digital conversion circuit that generates a frequency delta-sigma modulated signal using a reference signal and the phase-modulated signal.

[0191] This frequency delta-sigma modulation signal output circuit generates a phase-modulated signal in which the phase of the signal under test is modulated by randomly selecting one of n delay signals. This phase-modulated signal is then generated using the reference signal and the phase-modulated signal. As a result, the phase of the phase-modulated signal changes, reducing the idle tone contained in the signal sampled from either the reference signal or the phase-modulated signal, and thus reducing the signal component caused by the idle tone contained in the frequency delta-sigma modulation signal. Furthermore, since this frequency delta-sigma modulation signal output circuit generates the phase-modulated signal by randomly selecting one of n delay signals, the phase of the phase-modulated signal changes irregularly. Therefore, the frequency delta-sigma modulation signal does not contain signal components of a predetermined frequency that may occur if one of the n delay signals were regularly selected. Consequently, this frequency delta-sigma modulation signal output circuit can reduce the noise component contained in the frequency delta-sigma modulation signal.

[0192] Another aspect of the frequency delta-sigma modulation signal output circuit is: A phase modulation circuit generates n delayed signals by delaying the signal under test, where n is any integer greater than or equal to 1, and generates a phase-modulated signal by randomly selecting either the signal under test or the n delayed signals in synchronization with the signal under test. The system includes a frequency ratio digital conversion circuit that generates a frequency delta-sigma modulated signal using a reference signal and the phase-modulated signal.

[0193] This frequency delta-sigma modulation signal output circuit generates a phase-modulated signal by randomly selecting either the signal under test or one of n delay signals, thereby modulating the phase of the signal under test. This phase-modulated signal is then generated using the reference signal and the phase-modulated signal. As a result, the phase of the phase-modulated signal changes, reducing the idle tone contained in the signal sampled from either the reference signal or the phase-modulated signal, and thus reducing the signal component caused by the idle tone in the frequency delta-sigma modulation signal. Furthermore, since this frequency delta-sigma modulation signal output circuit generates the phase-modulated signal by randomly selecting either the signal under test or one of n delay signals, the phase of the phase-modulated signal changes irregularly. Therefore, the frequency delta-sigma modulation signal does not contain signal components of predetermined frequencies that may occur when either the signal under test or one of the n delay signals is regularly selected. Consequently, this frequency delta-sigma modulation signal output circuit can reduce the noise component contained in the frequency delta-sigma modulation signal.

[0194] Furthermore, in this frequency delta-sigma modulation signal output circuit, the measured signal is included in the selection target of the phase modulation circuit, which reduces the total number of delay signals by one and enables miniaturization.

[0195] In one embodiment of the frequency delta-sigma modulation signal output circuit, The aforementioned frequency ratio digital conversion circuit is The system may include a plurality of frequency delta-sigma modulation circuits connected in parallel, and the frequency delta-sigma modulation signal may be generated based on the output signals of the plurality of frequency delta-sigma modulation circuits.

[0196] This frequency delta-sigma modulation signal output circuit smooths out the signal components caused by idle tones in the frequency delta-sigma modulation signal, thereby further reducing the noise components in the frequency delta-sigma modulation signal.

[0197] One embodiment of the frequency delta-sigma modulation signal output circuit is: A filter circuit may be included after the frequency ratio digital conversion circuit.

[0198] This frequency delta-sigma modulation signal output circuit allows for the acquisition of a frequency delta-sigma modulated signal with further noise reduction through a filter circuit. Furthermore, because this frequency delta-sigma modulation signal output circuit does not include signal components of a predetermined frequency in the frequency delta-sigma modulated signal generated by the frequency ratio digital conversion circuit, the constraints on the cutoff frequency of the filter circuit are small, resulting in greater design flexibility.

[0199] In one embodiment of the frequency delta-sigma modulation signal output circuit, The aforementioned frequency ratio digital conversion circuit is A time digital value corresponding to the phase difference between the reference signal and the phase-modulated signal may be generated, and the frequency delta-sigma modulated signal may be generated based on the time digital value.

[0200] This frequency delta-sigma modulation signal output circuit allows for the implementation of a frequency ratio digital conversion circuit with a simple configuration, thereby reducing the circuit area of ​​the frequency ratio digital conversion circuit 3.

[0201] One embodiment of a sensor module is: One embodiment of the frequency delta-sigma modulation signal output circuit is described above, Equipped with a physical quantity sensor, The signal being measured is a signal based on the output signal of the physical quantity sensor.

[0202] This sensor module, by incorporating a frequency delta-sigma modulation signal output circuit, can obtain a frequency delta-sigma modulation signal with reduced noise components, thereby improving measurement accuracy.

[0203] In one embodiment of the sensor module, The physical quantity sensor may detect any of the following: mass, acceleration, angular velocity, angular acceleration, capacitance, and temperature. [Explanation of Symbols]

[0204] 1…Frequency delta-sigma modulation signal output circuit, 2…Phase modulation circuit, 3…Frequency ratio digital conversion circuit, 4…Low-pass filter circuit, 5…Frequency delta-sigma modulation circuit, 6…Adder, 21…Control circuit, 22…Multiplexer, 23…Delay circuit, 31,32…D flip-flop circuits, 33…Exclusive OR circuit, 40…First counting unit, 41…Counting circuit, 42…D flip-flop circuit, 50…Reciprocal count integrated value synthesis unit, 51…Multiplier, 52…Subtractor, 60…Time digital value generation unit, 61…Control unit, 62…Oscillator 63...Counting circuit, 64...D flip-flop circuit, 65...Adder, 66...D flip-flop circuit, 67...Logic AND circuit, 68...Logic inverting circuit, 70...Count value holding control unit, 80...Reciprocal count value generation unit, 81...D flip-flop circuit, 82...Subtractor, 83...D flip-flop circuit, 91...Second counting unit, 92...Count value integration unit, 100...Sensor module, 101...Container, 102...Lid, 103...Screw hole, 104...Fixing projection, 111...Side wall, 112...Bottom wall, 115...Circuit board, 115f...First surface ,115r…Second surface, 116…Connector, 118x,118y,118z…Accelerometer, 119…Control IC, 121…Opening, 122…Inner surface, 123…Opening surface, 125…Second base, 127…First base, 129…Protrusion, 130…Fixing member, 133,134…Constricted part, 141…Sealing member, 172…Screw, 174…Female thread, 176…Through hole, 200…Sensor element, 201…Substrate structure, 210…Base, 212…Joint part, 214…Movable part, 214a,214b…Main surface, 220…First support part, 230…Second support part, 24 0...Connecting part, 250...Third support part, 260...Fourth support part, 270...Accelerometer detection element, 271a,271b...Vibration beam part, 272a...First base part, 272b...Second base part, 280,282...Mass part, 300...Accelerometer, 310...Package, 311...Space, 320...Package base, 321...Recess, 322...Inner bottom surface, 323...Step part, 324...Outer bottom surface, 325...Through hole, 330...Lid, 332...Lid joining member, 340b...Internal terminal, 343...Conductive adhesive, 344...External terminal, 350...Sealing part, 379b...Fixing part connection terminal

Claims

1. A phase modulation circuit generates n delayed signals by delaying the signal under test, where n is an integer of 2 or more, and generates a phase-modulated signal by randomly selecting one of the n delayed signals in synchronization with the rising edge at which the high-level period of the signal under test begins and the falling edge at which the low-level period of the signal under test begins. The system includes a frequency ratio digital conversion circuit that generates a frequency delta-sigma modulated signal using a reference signal and the phase-modulated signal, The aforementioned frequency ratio digital conversion circuit is The unit includes a time digital value generation unit that generates a time digital value corresponding to the phase difference between the reference signal and the phase modulated signal, The time digital value generation unit has an oscillator that starts oscillating when it detects the rising edge or falling edge of the phase modulation signal, and stops oscillating when the number of oscillations reaches a predetermined number. The reciprocal count integration value synthesis unit includes a multiplier that multiplies a first count value obtained by counting the reference signal by an integer k, and a subtractor that outputs a second count value which is the difference between the first count value multiplied by an integer k and the time digital value. The frequency delta-sigma modulated signal is generated based on the difference between the second count value and a third count value obtained by holding the second count value in synchronization with a clock signal generated based on the phase modulation signal and the reference signal. A frequency delta-sigma modulation signal output circuit, wherein the predetermined number of times is set to 2 to the power of m (where m is a positive integer), which is equal to the integer k.

2. A phase modulation circuit generates n delayed signals by delaying the signal under test, where n is any integer greater than or equal to 1, and generates a phase-modulated signal by randomly selecting either the signal under test or the n delayed signals in synchronization with the rising edge at which the high-level period of the signal under test begins and the falling edge at which the low-level period of the signal under test begins. The system includes a frequency ratio digital conversion circuit that generates a frequency delta-sigma modulated signal using a reference signal and the phase-modulated signal, The aforementioned frequency ratio digital conversion circuit is The unit includes a time digital value generation unit that generates a time digital value corresponding to the phase difference between the reference signal and the phase modulated signal, The time digital value generation unit has an oscillator that starts oscillating when it detects the rising edge or falling edge of the phase modulation signal, and stops oscillating when the number of oscillations reaches a predetermined number. The reciprocal count integration value synthesis unit includes a multiplier that multiplies a first count value obtained by counting the reference signal by an integer k, and a subtractor that outputs a second count value which is the difference between the first count value multiplied by an integer k and the time digital value. The frequency delta-sigma modulated signal is generated based on the difference between the second count value and a third count value obtained by holding the second count value in synchronization with a clock signal generated based on the phase modulation signal and the reference signal. A frequency delta-sigma modulation signal output circuit, wherein the predetermined number of times is set to 2 to the power of m (where m is a positive integer), which is equal to the integer k.

3. In claim 1 or 2, The aforementioned frequency ratio digital conversion circuit is A frequency delta-sigma modulation signal output circuit that includes a plurality of frequency delta-sigma modulation circuits connected in parallel, and generates the frequency delta-sigma modulation signal based on the output signals of the plurality of frequency delta-sigma modulation circuits.

4. In any one of claims 1 to 3, A frequency delta-sigma modulated signal output circuit that includes a filter circuit after the frequency ratio digital conversion circuit.

5. A frequency delta-sigma modulation signal output circuit according to any one of claims 1 to 4, Equipped with a physical quantity sensor, The signal to be measured is a signal based on the output signal of the physical quantity sensor, in the sensor module.

6. In claim 5, The aforementioned physical quantity sensor is a sensor module that detects one of the following: mass, acceleration, angular velocity, angular acceleration, capacitance, and temperature.

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