Vector instruction processing method

Abstract

To efficiently use computational resources and power consumption in vector instruction processing.SOLUTION: A vector instruction processing apparatus 100 includes: a setting unit 101 which sets, for each of vector instructions registered on a reservation station, on the basis of contents and operands of the vector instruction, the number of first cycles which is the number of cycles required for completing the vector instruction, and the number of second cycles which is the number of cycles required until the vector instruction is used by subsequent vector instructions; and an issuance control unit 102 which controls issuing the vector instruction from the reservation station, on the basis of the number of first cycles and the number of second cycles set forth above.SELECTED DRAWING: Figure 8

Description

Technical Field

[0001] The present invention relates to a vector instruction processing method, a vector instruction processing device, and a program.

Background Art

[0002] Instructions in a vector processor are selected from a reservation station where the instructions are stored and instruction issuance is performed. Each instruction is overtaking-capable, and if dependencies such as WAR (Write After Read) and WAW (Write After Write) between each register are resolved, the instruction is issued from the older instruction among the instructions stored in the reservation station. For example, Patent Document 1 describes analyzing the dependencies between instructions and issuing instructions by overtaking.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] At this time, since the instructions are issued from the older instructions in the order in which the dependencies are resolved, the execution results of the issued instructions are not immediately used by subsequent instructions. Therefore, by issuing instructions that do not immediately use the execution results with subsequent instructions, the computing resources are wasted.

[0005] Furthermore, issuing instructions that do not immediately use the results of subsequent instructions results in wasted power consumption. Executing unnecessary instructions prevents other, higher-priority instructions from being issued, leading to a decrease in performance. For example, PCIe card devices have a power consumption limit of 300W, and power throttling functions were used to limit instruction issuance to that limit, but this had the disadvantage of reducing performance.

[0006] Thus, there was a problem in vector instruction processing where computational resources and power consumption could be wasted.

[0007] Therefore, the object of the present invention is to provide a vector instruction processing method, a vector instruction processing device, and a program that can solve the above-mentioned problems. [Means for solving the problem]

[0008] One embodiment of the present invention is a vector instruction processing method, For each vector instruction registered in the reservation station, based on the content and operands of the vector instruction, the first cycle count, which is the number of cycles until the vector instruction is completed, and the second cycle count, which is the number of cycles until the vector instruction is used in a subsequent vector instruction, are set. Based on the set first cycle count and second cycle count, the issuance of vector commands from the reservation station is controlled. This is the structure it takes.

[0009] Furthermore, a vector instruction processing device, which is one embodiment of the present invention, For each vector instruction registered in the reservation station, a setting unit sets, based on the content and operands of the vector instruction, the first cycle count, which is the number of cycles until the vector instruction is completed, and the second cycle count, which is the number of cycles until the vector instruction is used in a subsequent vector instruction. An issuance control unit that controls the issuance of vector commands from the reservation station based on the set first cycle count and second cycle count, Equipped with, This is the structure it takes.

[0010] A program which is one embodiment of the present invention, In the processor, For each vector instruction registered in the reservation station, based on the content and operands of the vector instruction, the first cycle count, which is the number of cycles until the vector instruction is completed, and the second cycle count, which is the number of cycles until the vector instruction is used in a subsequent vector instruction, are set. Based on the set first cycle count and second cycle count, the issuance of vector commands from the reservation station is controlled. To execute the process This is the structure it takes. [Effects of the Invention]

[0011] With the configuration described above, the present invention enables efficient use of computing resources and power consumption in vector instruction processing. [Brief explanation of the drawing]

[0012] [Figure 1] This figure shows the configuration of a vector instruction processing device in Embodiment 1 of the present invention. [Figure 2] This figure shows the processing in the vector instruction processing unit disclosed in Figure 1. [Figure 3] This figure shows a comparative example with the processing in the vector instruction processing device disclosed in Figure 1. [Figure 4] This figure shows the processing in the vector instruction processing unit disclosed in Figure 1. [Figure 5] This figure shows the processing in the vector instruction processing unit disclosed in Figure 1. [Figure 6]It is a diagram showing the state of processing in the vector instruction processing apparatus disclosed in FIG. 1. [Figure 7] It is a diagram showing the state of processing in the vector instruction processing apparatus disclosed in FIG. 1. [Figure 8] It is a block diagram showing the configuration of the vector instruction processing apparatus in Embodiment 2 of the present invention. [Figure 9] It is a flowchart showing the operation of the vector instruction processing apparatus in Embodiment 2 of the present invention. [Embodiment for Carrying Out the Invention]

[0013] [Embodiment 1] The first embodiment of the present invention will be described with reference to FIGS. 1 to 7. FIGS. 1 to 2 are diagrams for explaining the configuration of the present invention, and FIGS. 3 to 7 are diagrams for explaining the operation of the present invention.

[0014] [Configuration] The vector instruction processing apparatus in the present invention is configured by an information processing apparatus including a vector processor that processes vector instructions, and includes an instruction registration unit 11, a reservation station 12, and an instruction execution unit 13.

[0015] The instruction registration unit 11 registers the vector instructions in the vector program in the reservation station 12 according to a preset issue order. The reservation station 12 selects the registered vector instructions and issues them to the instruction execution unit 13. The instruction execution unit 13 executes the issued vector instructions.

[0016] In this embodiment, when a vector instruction is registered in the reservation station 12, it is configured to set the "number of cycles until operand instruction completion" and the "number of cycles until instruction issue" for each instruction. For example, these two values may be set by the instruction registration unit 11 or the reservation station 12.

[0017] Specifically, the "operand instruction completion cycle count" (first cycle count) is the number of cycles until the operand of that vector instruction becomes available, that is, the number of cycles until that vector instruction is completed. The "instruction issuance cycle count" (second cycle count) is the number of cycles until that vector instruction is used in a subsequent vector instruction. Note that a cycle represents one processing unit by the vector processor, and the cycle count represents the number of processing operations.

[0018] Figure 2 shows the setting criteria for the "number of cycles to complete the operand instruction" and the "number of cycles until the instruction is issued," which are defined for each instruction. As shown in this figure, the "number of cycles to complete the operand instruction" and the "number of cycles until the instruction is issued" are defined to be set based on the content of the vector instruction and its operand.

[0019] First, let's explain the criteria for setting the "number of cycles required to complete the operand instruction." For the vector instruction: VLD Va, set the number of cycles required to complete the Va instruction. In other words, set the number of cycles until Va becomes available. For the VLD instruction, which is a long-latency instruction, when the instruction is issued, set the number of cycles of latency from the external memory to the vector register. In this embodiment, the number of cycles of latency from the external memory to the vector register is set to 100. For the vector instruction: VADD Vb = Vc + Vd, set the larger of the two operand instruction completion cycles for the vector instruction where Vc and Vd are destinations. For the vector instruction: VST Vb, set the number of cycles required to complete the operand instruction for the vector instruction where Vb is the destination.

[0020] Next, we will explain the criteria for setting the "number of cycles until instruction issuance". For vector instructions: In the case of VLD Va, it is a long-latency instruction and is issued immediately, so no value is set. However, for convenience, 0 is set in the explanation below. In the case of VADD Vb = Vc + Vd, when a vector instruction using Vb is registered, the number of cycles required to complete the operand instruction of that vector instruction is set. In the case of VST Vb, when a vector instruction using Vb is registered, the number of cycles required to complete the operand instruction of that vector instruction is set. However, in the case of VST instructions, since the instruction itself uses Vb, the same value as the number of cycles required to complete the operand instruction of that instruction is set.

[0021] The reservation station 12 then controls the issuance order of vector instructions based on the values ​​of "operand instruction completion cycle count" and "number of cycles until instruction issuance" set for the registered vector instructions. For example, the reservation station 12 decreases the values ​​of "operand instruction completion cycle count" and "number of cycles until instruction issuance" set for the registered vector instructions by the number of cycles that have elapsed as the cycle progresses. In other words, the set values ​​of "operand instruction completion cycle count" and "number of cycles until instruction issuance" are counted down. Then, vector instructions for which the values ​​of "operand instruction completion cycle count" and "number of cycles until instruction issuance" have become 0 are sequentially issued to the instruction execution unit 13. In addition, for example, the reservation station 12 also issues vector instructions for which "operand instruction completion cycle count" is 0 but "number of cycles until instruction issuance" is not 0. However, since it can determine that such instructions do not need to be issued immediately, it issues them slowly using less computing resources than normally used. At this time, the reservation station 12 determines, for example, the amount of computing resources to be used for a vector instruction that is issued slowly, based on the number of cycles until the instruction is issued. For example, it determines the minimum amount of computing resources required to complete the processing of the vector instruction before the number of cycles set for the instruction issuance elapses, and issues the vector instruction so that it is executed using that amount of computing resources.

[0022] Thus, the instruction registration unit 11 and the reservation station 12 have a function (setting unit) to set the "number of cycles to complete the operand instruction" and the "number of cycles until instruction issuance" for a vector instruction, and a function (issuance control unit) to control the issuance order according to these values. These functions may be composed of electronic circuits, or they may be realized by the execution of a program by the processor.

[0023] [Operation] Next, we will explain the operation of the vector instruction processing unit 100, specifically how multiple instructions are registered sequentially with the reservation station 12 and the order in which the instructions are issued. We will illustrate the case where instructions 1, 2, 3, 4, 5, and 6 are registered with the reservation station 12 in that order, with each instruction being: Instruction 1: VLD VR0, Instruction 2: VADD VR1 = VR10 + VR11, Instruction 3: VADD VR2 = VR0 + VR1, Instruction 4: VST VR2, Instruction 5: VADD VR3 = VR12 + VR13, and Instruction 6: VST VR3.

[0024] First, a comparative example with the present invention will be described with reference to Figure 3. In other words, the following will describe the instruction issuance sequence when, unlike the present invention, the "number of cycles to complete the operand instruction" and the "number of cycles until instruction issuance" are not set as described above.

[0025] First, instruction 1 is issued (issue 1). Instruction 1 transfers data from external memory to VR0. Because the transfer is from external memory, the latency will be long. Next, issue instruction 2 (issue 2). Since the operands VR10 and VR11 of instruction 2 are available, issue them immediately. Next, the program attempts to issue instruction 3, but since the operand of instruction 3 uses the result of instruction 1's execution, it needs to wait for instruction 1 to complete. Therefore, instruction 3 remains pending issuance. Next, the program attempts to issue instruction 4, but since the operand of instruction 4 uses the result of instruction 3, it needs to wait for instruction 3 to complete. Therefore, instruction 4 remains pending issuance. Next, instruction 5 is issued. Since the operands VR12 and VR13 of instruction 5 are available, they are issued immediately (issue 3). Next, instruction 6 is issued. Since the operand of instruction 6 uses the result of the execution of instruction 5, it is issued immediately (issue 4). Then, once instruction 1 is completed, instruction 3, which was awaiting issuance, is issued (issue 5). Next, once instruction 3 is completed, instruction 4, which was awaiting issuance, is issued (issue 6).

[0026] Looking at the instruction issuance order in the above comparative example, instruction 2's execution result is used as an operand for instruction 3, but instruction 3 also uses the execution result of instruction 1 as an operand. Therefore, it is sufficient for instruction 2 to complete before instruction 1, which makes instruction 3 executable, is completed. Thus, although instruction 2 is issued second in this instruction sequence, there is no need to rush its execution; it can be executed slowly using minimal computing resources. Furthermore, if it were executed using normal computing resources instead of minimal resources, instructions that do not need to be executed quickly would be consuming unnecessary power.

[0027] Next, the instruction issuance sequence in this embodiment will be described with reference to Figures 4 to 7. In this example, each instruction is set to have an "operand instruction completion cycle count" and a "cycle count until instruction issuance".

[0028] (Figure 4: S1) First, instruction 1 is registered with reservation station 12. Since instruction 1 is a long-latency instruction, it is issued immediately. The operand instruction completion cycle count is set to a fixed value of 100. The number of cycles until instruction issuance is set to 0 because it has already been issued. The operand instruction completion cycle count and the number of cycles until instruction issuance are counted down every cycle.

[0029] (Figure 4: S2) Next, when instruction 2 is registered with reservation station 12, the number of operand instruction completion cycles for instruction 2 is first checked. Since the operands VR10 and VR11 of instruction 2 are not destinations of the preceding instruction and are already available in the vector register, the number of operand instruction completion cycles for instruction 2 is set to 0. Next, the number of cycles until instruction 2 is issued is checked. Instruction 2 can be issued immediately because the number of operand instruction completion cycles is 0, but since there are no instructions that use the execution result of instruction 2, it is not issued immediately and is put into a waiting state.

[0030] (Figure 4: S3) Next, when instruction 3 is registered with the reservation station 12, the number of operand instruction completion cycles for instruction 3 is first checked. The operands VR0 and VR1 of instruction 3 are the destinations of the preceding instructions 1 and 2. Therefore, the larger of the operand instruction completion cycles of instructions 1 and 2, which is 80, is set as the operand instruction completion cycle number for instruction 3. Next, the number of cycles until instruction 3 is issued is checked. Since no instruction that uses the execution result of instruction 3 is registered, it remains in a waiting state for issuance.

[0031] At this point, looking at instruction 2, which is already registered in reservation station 12, we see that the following instruction 3 uses VR1, the destination of instruction 2. Therefore, the number of cycles until instruction 2 is issued is set to the value of the number of cycles until the operand instruction is completed for instruction 3. Looking at instruction 2, the number of cycles until the operand instruction is completed is 0, and the number of cycles required for instruction issuance is a non-zero value. In this case, the operands are ready and the instruction can be issued immediately, but it can be determined that the instruction does not need to be issued immediately. In such cases, the instruction is issued slowly using a small amount of computing resources. The amount of computing resources used by instruction 2 is then determined based on the number of cycles until instruction 2 is issued. For example, the minimum amount of computing resources required to complete the processing of instruction 2 is determined so that the number of cycles until instruction 2 is issued has elapsed, and instruction 2 is issued using that amount of computing resources.

[0032] (Figure 5: S4) Next, when instruction 4 is registered with the reservation station 12, the number of cycles required to complete the operand instruction of instruction 4 is first checked. Since VR2, the operand of instruction 4, is the destination of the preceding instruction 3, the number of cycles required to complete the operand instruction of instruction 3 is set to 70. Next, the number of cycles required until instruction 4 is issued is checked. Since instruction 4 is a vector store instruction, it uses VR2. Therefore, the number of cycles required until instruction 4 is issued is set to the value of the number of cycles required to complete the operand instruction of instruction 4.

[0033] At this point, looking at instruction 3, which is already registered in reservation station 12, we see that the subsequent instruction 4 uses VR2, which is the destination of instruction 3. Therefore, the number of cycles until instruction 3 is issued is set to the value of the number of cycles until the operand instruction of instruction 4 is completed.

[0034] (Figure 5: S5) Next, when instruction 5 is registered with the reservation station 12, the number of operand instruction completion cycles for instruction 5 is checked. Since the operands VR12 and VR13 of instruction 5 are not destinations of preceding instructions, the number of operand instruction completion cycles for instruction 5 is set to 0. Next, the number of cycles until instruction 5 is issued is checked. Since no instructions using the destination VR3 of instruction 5 are registered, instruction 5 is put into a waiting state for issuance.

[0035] (Figure 6: S6) Next, when instruction 6 is registered with the reservation station 12, the number of cycles required to complete the operand instruction of instruction 6 is checked. Since VR3, which is the operand of instruction 6, is the destination of the preceding instruction 5, the number of cycles required to complete the operand instruction of instruction 5 is set as the number of cycles required to complete the operand instruction of instruction 6. Next, the number of cycles until instruction 6 is issued is checked. Since instruction 6 is a vector store instruction, it uses VR3. For this reason, the value of the number of cycles required to complete the operand instruction of instruction 6 is set as the number of cycles until instruction 6 is issued.

[0036] At this point, looking at instruction 5, which is already registered in reservation station 12, there is a subsequent instruction 6 that uses VR3, the destination of instruction 5. Therefore, the operand instruction completion cycle count of instruction 6 is set to the number of cycles until instruction 5 is issued. As a result, both instruction 5 and instruction 6 are issued because both the operand instruction completion cycle count and the number of cycles until instruction is issued are 0.

[0037] (Figure 7: S7) After a certain number of cycles have elapsed, when both the number of cycles required to complete the operand instructions for instructions 3 and 4, and the number of cycles required to issue the instructions, instructions 3 and 4 are issued.

[0038] Comparing the instruction issuance order of the comparative example in Figure 3 with that of the method in the present invention shown in Figures 4 to 7, it can be seen that in the method of the present invention, instruction 2 can be executed using fewer computing resources, and instruction 5 can be issued second, thus prioritizing the execution of necessary instructions. In this way, instruction 2 does not need to be executed immediately and is executed with a lower priority than other instructions using fewer computing resources, thus avoiding wasted computing resources and unnecessary power consumption. Furthermore, since the instruction is executed using fewer computing resources until it is needed, performance degradation can also be suppressed.

[0039] As described above, in this invention, the reservation station issues instructions while considering, in addition to existing dependency analysis, whether the execution result of the issued instruction will be immediately used in a subsequent instruction. In this way, because instructions are issued after determining whether the execution result will be used in a subsequent instruction, computing resources are not wasted on instructions whose execution results are not used in subsequent instructions, and unnecessary power consumption is not recorded. Furthermore, in this invention, instructions whose calculation results are not immediately used in subsequent instructions are executed slowly using fewer computing resources. This makes it possible to allocate computing resources to other instructions that should take priority, and unnecessary power consumption is not recorded.

[0040] For example, as explained above, in the case of a vector processor, a vector load instruction involves transferring a large amount of data from external memory to a vector register, resulting in long latency. Therefore, when adding the result of this vector load instruction to the result of another instruction, the other instruction can be executed slowly until the vector load instruction is completed.

[0041] Furthermore, vector processors possess numerous computing resources and perform many calculations in parallel. Therefore, instructions whose results are immediately used by subsequent instructions can be executed using the full computing resources, while instructions whose results are not immediately used by subsequent instructions can be executed slowly using fewer computing resources. In this way, even with a power consumption limit, instructions whose results are not immediately used are executed using fewer computing resources, thus avoiding wasted power consumption and preventing performance degradation.

[0042] <Embodiment 2> Next, a second embodiment of the present invention will be described with reference to Figures 8 and 9. Figure 8 is a block diagram showing the configuration of the vector instruction processing device in this embodiment, and Figure 9 is a flowchart showing the operation of the vector instruction processing method in this embodiment. In this embodiment, the configuration of the vector instruction processing device and vector instruction processing method described in Embodiment 1 is shown in outline.

[0043] As shown in Figure 8, the vector instruction processing device 100 in this embodiment includes a setting unit 101 that sets, for each vector instruction registered in the reservation station, a first cycle count, which is the number of cycles until the vector instruction is completed, and a second cycle count, which is the number of cycles until the vector instruction is used in a subsequent vector instruction, based on the content and operands of the vector instruction; and an issuance control unit 102 that controls the issuance order of vector instructions from the reservation station based on the set first cycle count and second cycle count. Note that the setting unit 101 and the issuance control unit 102 may be implemented by the vector instruction processing device 100 executing a program.

[0044] Then, as shown in Figure 9, the vector instruction processing device 100 with the above configuration sets, for each vector instruction registered in the reservation station, a first cycle count, which is the number of cycles until the vector instruction is completed, and a second cycle count, which is the number of cycles until the vector instruction is used in a subsequent vector instruction, based on the content and operands of the vector instruction (step S101). Based on the set first cycle count and second cycle count, it controls the issuance order of vector instructions from the reservation station (step S102).

[0045] As described above, the present invention makes it possible to control the issuance order of instructions whose execution results are not immediately used in subsequent instructions, thereby enabling efficient use of computing resources and power consumption.

[0046] <Note> Some or all of the above embodiments may also be described as follows. The following outlines the configuration of the vector instruction processing method, vector instruction processing device, and program in the present invention. However, the present invention is not limited to the following configuration.

[0047] (Note 1) For each vector instruction registered in the reservation station, based on the content and operands of the vector instruction, the first cycle count, which is the number of cycles until the vector instruction is completed, and the second cycle count, which is the number of cycles until the vector instruction is used in a subsequent vector instruction, are set. Based on the set first cycle count and second cycle count, the issuance of vector commands from the reservation station is controlled. Vector instruction processing method. (Note 2) The vector instruction processing method described in Appendix 1, Based on the operand of the vector instruction to be set and the operand of another vector instruction, the first cycle count and / or the second cycle count of the vector instruction to be set are set. Vector instruction processing method. (Note 3) A vector instruction processing method as described in Appendix 1 or 2, The number of first cycles of a vector instruction whose destination is the operand of the vector instruction to be set is set as the number of first cycles of the vector instruction to be set. Vector instruction processing method. (Note 4) The vector instruction processing method described in Appendix 3, When there are multiple vector instructions whose destination is the operand of the vector instruction to be configured, the larger of the first cycle counts of those multiple vector instructions is set as the first cycle count of the vector instruction to be configured. Vector instruction processing method. (Note 5) A vector instruction processing method described in any of Appendix 1 to 4, Based on the first cycle count of the set vector instruction, the second cycle count of the vector instruction to be set is set. Vector instruction processing method. (Note 6) The vector instruction processing method described in Appendix 5, The number of cycles of the first vector instruction whose operand is the destination of the vector instruction to be set is set as the number of cycles of the vector instruction to be set. Vector instruction processing method. (Note 7) A vector instruction processing method described in any of Appendix 1 to 6, A vector instruction, in which the first cycle count is 0 and the second cycle count is not 0, is issued to be executed using an amount of computing resources set based on the second cycle count. Vector instruction processing method. (Note 8) A vector instruction processing method described in any of Appendix 1 to 7, A vector instruction is issued in which both the first cycle count and the second cycle count are 0. Vector instruction processing method. (Note 9) For each vector instruction registered in the reservation station, a setting unit sets, based on the content and operands of the vector instruction, the first cycle count, which is the number of cycles until the vector instruction is completed, and the second cycle count, which is the number of cycles until the vector instruction is used in a subsequent vector instruction. An issuance control unit that controls the issuance of vector commands from the reservation station based on the set first cycle count and second cycle count, A vector instruction processing unit equipped with the following features. (Note 9.1) The vector instruction processing device described in Appendix 9, The setting unit sets the first cycle count and / or the second cycle count of the vector instruction to be set based on the operand of the vector instruction to be set and the operand of another vector instruction. Vector instruction processing unit. (Appendix 9.2) A vector instruction processing device as described in Appendix 9 or 9.1, The setting unit sets the number of first cycles of the vector instruction whose destination is the operand of the vector instruction to be set as the number of first cycles of the vector instruction to be set. Vector instruction processing unit. (Appendix 9.3) A vector instruction processing device according to claim 9.2, The setting unit, when there are multiple vector instructions whose destination is the operand of the vector instruction to be set, sets the largest of the first cycle counts of the multiple vector instructions as the first cycle count of the vector instruction to be set. Vector instruction processing unit. (Appendix 9.4) A vector instruction processing device as described in any of Appendix 9 to 9.3, The setting unit sets the second cycle number of the vector instruction to be set based on the first cycle number of the set vector instruction. Vector instruction processing unit. (Note 9.5) A vector instruction processing device according to claim 9.4, The setting unit sets the number of first cycles of the vector instruction whose operand is the destination of the vector instruction to be set as the number of second cycles of the vector instruction to be set. Vector instruction processing unit. (Appendix 9.6) A vector instruction processing method described in any of Appendix 9 to 9.5, The issuing control unit issues a vector instruction in which the first cycle count is 0 and the second cycle count is not 0, so as to be executed using an amount of computing resources set based on the second cycle count. Vector instruction processing method. (Note 9.7) A vector instruction processing device according to any one of claims 9 to 9.6, The issuing control unit sequentially issues vector instructions for which both the first cycle count and the second cycle count are 0. Vector instruction processing unit. (Note 10) In the processor, For each vector instruction registered in the reservation station, based on the content and operands of the vector instruction, the first cycle count, which is the number of cycles until the vector instruction is completed, and the second cycle count, which is the number of cycles until the vector instruction is used in a subsequent vector instruction, are set. Based on the set first cycle count and second cycle count, the order in which vector commands are issued from the reservation station is controlled. A program to execute a process.

[0048] The above program can be stored and supplied to a computer using various types of non-transitory computer-readable medium. Non-transitory computer-readable medium includes various types of tangible storage medium. Examples of non-transitory computer-readable medium include magnetic recording media (e.g., flexible disks, magnetic tapes, hard disk drives), magneto-optical recording media (e.g., magneto-optical disks), CD-ROMs (Read Only Memory), CD-Rs, CD-R / Ws, and semiconductor memory (e.g., mask ROMs, PROMs (Programmable ROMs), EPROMs (Erasable PROMs), flash ROMs, and RAMs (Random Access Memory)). The program may also be supplied to a computer using various types of transient computer-readable medium. Examples of transient computer-readable medium include electrical signals, optical signals, and electromagnetic waves. Transitory computer-readable medium can be supplied to a computer via wired communication channels such as electric wires and optical fibers, or via wireless communication channels.

[0049] Although the present invention has been described above with reference to the embodiments described above, the present invention is not limited to the embodiments described above. Various modifications to the structure and details of the present invention can be made within the scope of the present invention as can be understood by those skilled in the art. [Explanation of Symbols]

[0050] 1. Vector Instruction Processing Unit 11. Command Registration Unit 12 Reservation Stations 13. Instruction Execution Unit

Claims

1. For each vector instruction registered in the reservation station, based on the content and operands of the vector instruction, the first cycle count, which is the number of cycles until the vector instruction is completed, and the second cycle count, which is the number of cycles until the destination of the vector instruction is used for a subsequent vector instruction, are set. When controlling the issuance of all vector instructions from the reservation station based on the set first cycle count and second cycle count, vector instructions for which both the first cycle count and the second cycle count are 0 are issued sequentially. Vector instruction processing method.

2. For each vector instruction registered in the reservation station, based on the content and operands of the vector instruction, the first cycle count, which is the number of cycles until the vector instruction is completed, and the second cycle count, which is the number of cycles until the destination of the vector instruction is used for a subsequent vector instruction, are set. When controlling the issuance of all vector instructions from the reservation station based on the set first and second cycle counts, vector instructions for which the first cycle count is 0 and the second cycle count is not 0 are issued in such a way that they are executed using the minimum amount of computing resources necessary to complete the processing of the vector instruction before the second cycle count elapses. Vector instruction processing method.

3. A vector instruction processing method according to claim 1 or 2, Based on the operands of a predetermined vector instruction and the operands of other vector instructions, the first cycle count and / or the second cycle count of the predetermined vector instruction are set. Vector instruction processing method.

4. A vector instruction processing method according to any one of claims 1 to 3, The number of first cycles of a vector instruction whose destination is the operand of a predetermined vector instruction is set as the number of first cycles of the predetermined vector instruction. Vector instruction processing method.

5. A vector instruction processing method according to claim 4, When there are multiple vector instructions whose destination is the operand of a predetermined vector instruction, the larger of the first cycle counts of the multiple vector instructions is set as the first cycle count of the predetermined vector instruction. Vector instruction processing method.

6. A vector instruction processing method according to any one of claims 1 to 5, The number of cycles of the first vector instruction whose operand is the destination of a predetermined vector instruction is set as the number of cycles of the predetermined vector instruction. Vector instruction processing method.

7. For each vector instruction registered in the reservation station, a setting unit sets, based on the content and operands of the vector instruction, the first cycle count, which is the number of cycles until the vector instruction is completed, and the second cycle count, which is the number of cycles until the destination of the vector instruction is used for a subsequent vector instruction. When controlling the issuance of all vector instructions from the reservation station based on the set first cycle count and second cycle count, the issuance control unit sequentially issues vector instructions for which both the first cycle count and the second cycle count are 0. A vector instruction processing unit equipped with the following features.

8. For each vector instruction registered in the reservation station, a setting unit sets, based on the content and operands of the vector instruction, the first cycle count, which is the number of cycles until the vector instruction is completed, and the second cycle count, which is the number of cycles until the destination of the vector instruction is used for a subsequent vector instruction. When controlling the issuance of all vector instructions from the reservation station based on the set first cycle count and second cycle count, an issuance control unit issues vector instructions where the first cycle count is 0 and the second cycle count is not 0, so as to be executed using the minimum amount of computing resources necessary to complete the processing of the vector instruction before the second cycle count elapses. A vector instruction processing unit equipped with the following features.

9. In the processor, For each vector instruction registered in the reservation station, based on the content and operands of the vector instruction, the first cycle count, which is the number of cycles until the vector instruction is completed, and the second cycle count, which is the number of cycles until the destination of the vector instruction is used for a subsequent vector instruction, are set. When controlling the issuance of all vector instructions from the reservation station based on the set first cycle count and second cycle count, vector instructions for which both the first cycle count and the second cycle count are 0 are issued sequentially. A program to execute a process.

10. In the processor, For each vector instruction registered in the reservation station, based on the content and operands of the vector instruction, the first cycle count, which is the number of cycles until the vector instruction is completed, and the second cycle count, which is the number of cycles until the destination of the vector instruction is used for a subsequent vector instruction, are set. When controlling the issuance of all vector instructions from the reservation station based on the set first and second cycle counts, vector instructions for which the first cycle count is 0 and the second cycle count is not 0 are issued in such a way that they are executed using the minimum amount of computing resources necessary to complete the processing of the vector instruction before the second cycle count elapses. A program to execute a process.

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