Semiconductor stacked structure and method for fabricating the same, and method for manufacturing a semiconductor device.
Patent Information
- Authority / Receiving Office
- JP · JP
- Patent Type
- Patents
- Current Assignee / Owner
- NIPPON TELEGRAPH & TELEPHONE CORP
- Filing Date
- 2022-05-16
- Publication Date
- 2026-05-15
Smart Images
Figure 0007859491000001 
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Figure 0007859491000003
Abstract
Description
[Technical Field]
[0001] This invention relates to a semiconductor stacked structure made of nitride semiconductors, a method for producing the same, and a method for manufacturing a semiconductor device. [Background technology]
[0002] Heterojunction field-effect transistors (HFETs) and high electron mobility transistors (HEMTs) are transistors that switch ON / OFF by changing the carrier density of the channel layer using an electric field generated by the gate voltage. When using GaN, stacking AlGaN / GaN layers often results in the formation of a two-dimensional electron gas (2DEG) at the interface, where electrons accumulate to compensate for the difference in polarization magnitude between AlGaN and GaN. In HEMTs using typical Ga polarity (Group III polarity) GaN, the gate electrode is formed on an AlGaN layer of several nanometers to tens of nanometers in size, and the 2DEG concentration at the AlGaN / GaN interface is controlled.
[0003] HEMTs using GaN are being developed for high-frequency devices that take advantage of their high mobility of 2DEG. In Ga-polarized HEMTs, a large bandgap AlGaN layer is placed on the device surface. As a result, this type of transistor has two main challenges: firstly, high contact resistance; and secondly, the inability to thin the AlGaN layer to maintain carrier density, which leads to short-channel effects.
[0004] These challenges hinder the improvement of high-frequency characteristics of HEMTs using nitride semiconductors such as GaN. To address these challenges, techniques are being investigated, firstly, to reduce contact resistance by regrowing the region directly beneath the ohmic electrode, and secondly, to suppress short-channel effects by increasing the Al composition and thinning the AlGaN layer. However, there are limitations to reducing ohmic contact resistance.
[0005] A GaN layer with a primary surface polarity of N (Group V polarity) is a crystalline layer obtained by inverting a GaN layer with a primary surface polarity of Ga, and it has the following three advantages when used to fabricate HEMTs.
[0006] Firstly, the AlGaN layer, which requires a high Al composition and a thickness of about 20 nm to supply carriers and has high resistance, is located beneath the GaN channel layer and is not positioned between the electrode and the channel. Therefore, contact resistance can be reduced.
[0007] Secondly, since the thickness of the GaN layer on the surface does not significantly affect the carrier density, it can be made thinner to suppress the short-channel effect.
[0008] Thirdly, the AlGaN layer directly beneath the channel acts as a back barrier, suppressing the short-channel effect.
[0009] These advantages suggest that fabricating HEMTs using an N-polarity GaN layer can lead to further improvements in the high-frequency characteristics of HEMTs (Non-Patent Document 1).
[0010] As mentioned above, it is known that the high-frequency characteristics of HEMTs can be improved by using a nitride semiconductor layer with an N-polarity main surface (N-polarity nitride semiconductor layer), but there are challenges in crystal growth of N-polarity nitride semiconductor layers.
[0011] N-polar nitride semiconductor layers are known to have problems such as lower surface flatness and higher dislocation density compared to Ga-polar nitride semiconductor layers (Non-Patent Literature 2). There are examples of transistors being fabricated by growing crystals on substrates with a large off-angle to solve these problems to some extent. However, in this case, it has been found that the sheet resistance differs depending on the relationship between the direction of the off-angle and the direction of the current flowing through the channel (Non-Patent Literature 3), which imposes limitations on device fabrication.
[0012] To avoid the challenges of crystal growth in N-polar nitride semiconductors, a technique is being considered in which a nitride semiconductor grown in Ga polarity is inverted and bonded to another substrate, exposing the N-polarity surface to fabricate a device (Non-Patent Literature 4). In this technique, since a group III nitride semiconductor that forms the device structure is grown in Ga polarity, the crystal-specific qualities such as dislocation density and anisotropy of sheet resistance are expected to be equivalent to those of existing Ga-polar transistors.
[0013] Furthermore, by using substrate transfer technology, it becomes possible to fabricate high-quality HEMTs using N-polar nitride semiconductors on substrates where it is difficult to grow N-polar nitride semiconductors. For example, it is difficult to grow GaN crystals on a Si substrate with a main surface orientation of (100), which is used for CMOS fabrication. However, by using the substrate transfer technology described above, it is possible to form an N-polar GaN layer on the Si substrate. This makes it possible to integrate HEMTs with excellent high-frequency characteristics and CMOS on the same substrate. [Prior art documents] [Non-patent literature]
[0014] [Non-Patent Document 1] MH Wong et al., "INVITED REVIEW N-polar GaN epitaxy and high electron mobility transistors", Semiconductor Science and Technology, vol. 28, 074009, 2013. [Non-Patent Document 2] M. Sumiya et al., "Growth mode and surface morphology of a GaN film deposited along the N-face polar direction on c-plane sapphire substrate", American Institute of Physics, vol. 88, no. 2, pp. 1158-1165, 2000. [Non-Patent Document 3] S. Keller et al., "Influence of the substrate misorientation on the properties of N-polar InGaN / GaN and AlGaN / GaN heterostructures", Journal of Applied Physics, vol. 104, no. 9, 093510, 2008. [Non-Patent Document 4] JW Chung et al., "N-Face GaN / AlGaN HEMTs Fabricated Through Layer Transfer Technology", IEEE Electron Device Letters, vol. 30, no. 2, pp. 113-116, 2009. [Overview of the project] [Problems that the invention aims to solve]
[0015] As described above, by using substrate transfer technology, it is possible to form an N-polar nitride layer on a Si substrate, enabling device fabrication on CMOS process lines using large-diameter Si substrates and integration with CMOS circuits on the same substrate.
[0016] For example, in Non-Patent Literature 4, a Si substrate and a group III nitride semiconductor epitaxial wafer are bonded by hydrogen silsesquioxane (HSQ). However, since HSQ only has heat resistance up to about 900°C, it can withstand annealing of ohmic electrodes (about 850°C), but processes exceeding 1000°C cannot be performed after bonding. Processes at temperatures exceeding 1000°C include, for example, GaN regrowth and etching by selective pyrolysis. GaN regrowth is an important process for reducing the contact resistance of HEMTs using N-polarity GaN layers, and high temperatures are necessary to produce high-quality GaN crystals during regrowth. Selective pyrolysis is a method for etching GaN with a high selectivity ratio and is a necessary process for controlling the etching of thin films.
[0017] To enable high-temperature processes, firstly, direct bonding can be considered. Secondly, to enable high-temperature processes, a method using an adhesive layer that can withstand higher temperatures can be considered.
[0018] When using direct bonding, the presence of Ga in the nitride semiconductor layer in contact with the Si substrate becomes a problem at high temperatures. Ga and Si react at high temperatures, and the GaN is etched by melt-back etching. This can cause the Ga-containing nitride semiconductor layer to peel off from the Si substrate. Furthermore, if a device composed of a Ga-containing nitride semiconductor layer is close to the substrate, the layer on which the device is formed may be etched, potentially significantly degrading the device's characteristics.
[0019] On the one hand, it is conceivable to use AlN as an adhesive layer that can withstand higher temperatures. It is difficult to grow AlN epitaxially on a Si(100) substrate, and when growing epitaxially on GaN, only a few nanometers can grow from the perspective of the critical film thickness. Therefore, the AlN used as the adhesive layer is, for example, formed by sputtering. However, the AlN film formed by sputtering has more defects than epitaxially grown AlN, and since atomic diffusion through the defects is easy, the effect of suppressing the reaction caused by the diffusion of Ga and Si is not sufficient.
[0020] As described above, in the prior art, there was a problem that a device with good characteristics using a nitride semiconductor containing Ga could not be formed on a Si layer having a main surface plane orientation of (100).
[0021] The present invention has been made to solve the above problems, and an object thereof is to enable the formation of a device with good characteristics using a nitride semiconductor containing Ga on a Si layer having a main surface plane orientation of (100).
Means for Solving the Problems
[0022] The semiconductor laminated structure according to the present invention includes a substrate whose main surface is composed of a Si(100) plane, an oxide layer composed of an oxide containing no Si and formed on the main surface of the substrate, an adhesive layer composed of AlN and formed on the oxide layer, and a nitride semiconductor layer composed of a nitride semiconductor containing Ga and formed on the adhesive layer.
[0023] The present invention provides a method for manufacturing a conductive laminated structure, comprising: a bonding step of bonding a substrate whose main surface is composed of a (100) plane of Si and on which an oxide layer composed of an oxide that does not contain Si is formed, and another substrate on which a nitride semiconductor layer is formed by crystal growth of a nitride semiconductor containing Ga in the +c axis direction, with the side of the other substrate where the nitride semiconductor layer is formed facing the oxide layer formed on the substrate; an adhesive layer formation step of forming an adhesive layer composed of AlN on the side of the substrate that is bonded to the other substrate before the bonding step; and a removal step of removing the other substrate from the nitride semiconductor layer after the bonding step.
[0024] The semiconductor device manufacturing method according to the present invention comprises a bonding step of bonding a substrate whose main surface is composed of a (100) plane of Si and on which an oxide layer composed of an oxide that does not contain Si is formed, and another substrate on which a nitride semiconductor layer is formed by crystal growth of a nitride semiconductor containing Ga in the +c axis direction, with the side on which the nitride semiconductor layer of the other substrate is formed facing the oxide layer formed on the substrate; an adhesive layer formation step of forming an adhesive layer composed of AlN on the side of the substrate that is bonded to the other substrate before the bonding step; a removal step of removing the other substrate from the nitride semiconductor layer after the bonding step; a first element formation step of forming a recess on the surface of the nitride semiconductor layer after the removal step; a second element formation step of selectively regrowing n-type GaN in the recess to form an n-GaN layer; and a third element formation step of forming an electrode that is ohmic connected to the n-GaN layer.
[0025] The semiconductor device manufacturing method according to the present invention comprises a bonding step of bonding a substrate whose main surface is composed of a (100) plane of Si and on which an oxide layer is formed on the main surface, and another substrate on which a nitride semiconductor layer is formed by crystal growth of a nitride semiconductor containing Ga in the +c axis direction, with the nitride semiconductor layer formation surface of the other substrate facing the oxide layer formation surface of the substrate; an adhesive layer formation step of forming an adhesive layer made of AlN on the side of the substrate that will be bonded to the other substrate before the bonding step; and before the bonding step, forming an element formation layer on the other substrate by crystal growth of a nitride semiconductor containing Ga in the +c axis direction, and on the element formation layer, Al The device comprises a first element formation step in which a nitride semiconductor containing a GaN and having a higher thermal decomposition temperature than GaN is crystal-grown in the +c axis direction to form an etching stop layer, and then a nitride semiconductor containing Ga is crystal-grown on the etching stop layer to form a buffer layer, thereby forming a nitride semiconductor layer including an element formation layer, an etching stop layer, and a buffer layer; a removal step in which, after the bonding step, another substrate is removed from the nitride semiconductor layer; and a second element formation step in which, after the removal step, the buffer layer is removed by selectively thermally decomposing the buffer layer relative to the etching stop layer by heating in a hydrogen atmosphere containing ammonia, thereby exposing the etching stop layer. [Effects of the Invention]
[0026] As described above, according to the present invention, a substrate whose main surface is composed of a (100) plane of Si and another substrate on which a nitride semiconductor layer formed by crystal growth of a nitride semiconductor containing Ga in the +c axis direction are bonded together via an oxide layer composed of oxide and an adhesive layer composed of AlN. Therefore, a device with good properties using a nitride semiconductor containing Ga can be formed on a Si layer with a main surface orientation of (100). [Brief explanation of the drawing]
[0027] [Figure 1A] Figure 1A is a cross-sectional view showing the state of a semiconductor stacked structure during an intermediate step to illustrate the method for manufacturing a semiconductor stacked structure according to Embodiment 1 of the present invention. [Figure 1B]Figure 1B is a cross-sectional view showing the state of a semiconductor stacked structure during an intermediate step to illustrate the method for manufacturing a semiconductor stacked structure according to Embodiment 1 of the present invention. [Figure 1C] Figure 1C is a cross-sectional view showing the state of a semiconductor stacked structure during an intermediate step in the manufacturing process for illustrating the method for producing a semiconductor stacked structure according to Embodiment 1 of the present invention. [Figure 1D] Figure 1D is a cross-sectional view showing the state of a semiconductor stacked structure during an intermediate step in the manufacturing process for illustrating the method for producing a semiconductor stacked structure according to Embodiment 1 of the present invention. [Figure 1E] Figure 1E is a cross-sectional view showing the state of a semiconductor stacked structure during an intermediate step in the manufacturing process for illustrating the method for producing a semiconductor stacked structure according to Embodiment 1 of the present invention. [Figure 1F] Figure 1F is a cross-sectional view showing the state of a semiconductor stacked structure during an intermediate step in the process of explaining the method for manufacturing a semiconductor stacked structure according to Embodiment 1 of the present invention. [Figure 2A] Figure 2A is a cross-sectional view showing the state of a semiconductor device during an intermediate step in the manufacturing process of a semiconductor device according to Embodiment 2 of the present invention. [Figure 2B] Figure 2B is a cross-sectional view showing the state of a semiconductor device during an intermediate step in the manufacturing process for a semiconductor device according to Embodiment 2 of the present invention. [Figure 2C] Figure 2C is a cross-sectional view showing the state of a semiconductor device during an intermediate step in the manufacturing process of a semiconductor device according to Embodiment 2 of the present invention. [Figure 3A] Figure 3A is a cross-sectional view showing the state of a semiconductor device during an intermediate step in the manufacturing process of a semiconductor device according to Embodiment 3 of the present invention. [Figure 3B] Figure 3B is a cross-sectional view showing the state of a semiconductor device during an intermediate step in the manufacturing process of a semiconductor device according to Embodiment 3 of the present invention. [Figure 3C] Figure 3C is a cross-sectional view showing the state of a semiconductor device during an intermediate step in the manufacturing process of a semiconductor device according to Embodiment 3 of the present invention. [Figure 3D]Figure 3D is a cross-sectional view showing the state of a semiconductor device during an intermediate step in the manufacturing process of a semiconductor device according to Embodiment 3 of the present invention. [Modes for carrying out the invention]
[0028] The following describes a method for fabricating a semiconductor stacked structure according to an embodiment of the present invention.
[0029] [Embodiment 1] First, the method for fabricating a semiconductor stacked structure according to Embodiment 1 of the present invention will be described with reference to Figures 1A to 1F.
[0030] First, as shown in Figure 1A, a substrate 101 is prepared, whose main surface is composed of (100) planes of Si. The substrate 101 can be, for example, an SOI (Silicon on Insulator) substrate having a surface silicon layer whose main surface orientation is (100) planes. Alternatively, the substrate 101 can be made from bulk single-crystal Si.
[0031] Next, as shown in Figure 1B, an oxide layer 102 composed of an oxide that does not contain Si is formed on the substrate 101. Subsequently, an adhesive layer 103 composed of AlN is formed on the oxide layer 102 (adhesive layer formation step). The oxide layer 102 can be formed by depositing oxides such as Al2O3 or HfO2 using a deposition technique such as the well-known ALD (Atomic Layer Deposition) method. SiO2 is undesirable because it contains Si.
[0032] The adhesive layer 103 can be formed, for example, by a deposition technique such as the well-known sputtering method. Alternatively, the adhesive layer 103 can be formed by a CVD (Chemical Vapor Deposition) method using ECR (Electron Cycrotron Resonance) plasma.
[0033] The oxide layer 102 and the adhesive layer 103 are layers designed to prevent melt-back etching by Si and Ga in high-temperature environments above 1000°C, and the thicker they are, the more effective they are at preventing the diffusion and reaction of Ga and Si.
[0034] On the other hand, increasing the thickness of these layers leads to higher costs and increases the step difference between the device formed on the substrate 101 and the device formed on the nitride semiconductor layer described later, thereby limiting the device configuration. For this reason, it is desirable to make the oxide layer 102 and the adhesive layer 103 as thin as possible while still achieving a certain level of effectiveness.
[0035] Based on the above, it is desirable that the thickness of the oxide layer 102 be in the range of several nanometers to several tens of nanometers. Furthermore, it is assumed that the adhesive layer 103 will be ground by CMP (chemical mechanical polishing) to ensure the surface flatness required in the bonding process. The thickness of the layer removed by CMP depends on the surface flatness before CMP, but can be several tens of nanometers or more. For this reason, it is desirable that the thickness of the adhesive layer 103 be in the range of several tens of nanometers to several hundred nanometers.
[0036] Next, as shown in Figure 1C, a nitride semiconductor layer 105 is formed on the other substrate 104 by crystal growth of a Ga-containing nitride semiconductor in the +c axis direction. At this stage, the main surface of the formed nitride semiconductor layer 105 becomes the +c plane and has Ga polarity (Group III polarity). The other substrate 104 can be any substrate on which a Ga-containing nitride semiconductor such as GaN or AlGaN can be crystal grown, and can be, for example, a Si substrate, a sapphire substrate, a SiC substrate, or a GaN substrate. Considering the ease of removing the other substrate 104 from the nitride semiconductor layer 105, which will be described later, a Si substrate or a sapphire substrate is preferable. Here, for example, the other substrate 104 is a sapphire substrate.
[0037] Furthermore, the nitride semiconductor layer 105 can be formed by epitaxial growth of the target nitride semiconductor, for example, by metal-organic chemical vapor deposition (MOCVD) or molecular beam epitaxy (MBE). The nitride semiconductor layer 105 can be a laminated structure in which multiple nitride semiconductor layers are stacked. In the case of a laminated structure, each layer can be a layer for constituting a transistor, such as a HEMT. The outermost surface of the laminated structure can be a layer made of GaN, for example. It is desirable to determine the material and thickness of the outermost layer considering that chemical mechanical polishing (CMP) will be performed to ensure surface flatness for bonding, as described later, and that damage may occur near the bonding interface due to pressure during bonding.
[0038] Next, as shown in Figure 1D, the other substrate 104 on which the nitride semiconductor layer 105 is formed is bonded to the substrate 101 with the nitride semiconductor layer 105 facing the substrate 101 (bonding process). This bonding is carried out by joining the respective bonding surfaces using a known direct bonding technique. Direct bonding requires high flatness, with the surface roughness Ra of each bonding surface being 1 nm or less.
[0039] As mentioned above, the outermost surface of the nitride semiconductor layer 105 immediately after formation may have insufficient flatness for direct bonding, with an Ra of only a few nanometers. In this case, it is important to planarize the outermost surface of the nitride semiconductor layer 105 by CMP (Chemical Polishing). By bonding using this direct bonding technique, the use of adhesives (bonding materials) made of organic materials is eliminated, improving resistance to high-temperature processing. Furthermore, improved heat dissipation of the device can be expected.
[0040] After the bonding process described above, the other substrate 104 is removed from the nitride semiconductor layer 105 (removal process). As shown in Figure 1E, the nitride semiconductor layer 105 is formed on the substrate 101 via the oxide layer 102 and the adhesive layer 103, and the surface of the nitride semiconductor layer 105 is exposed. For example, if the other substrate 104 is a sapphire substrate, the above removal can be performed by the laser lift-off method. Alternatively, if the other substrate 104 is a Si substrate, the above removal can be performed by the backgrinding method or dry etching. At this stage, the main surface of the nitride semiconductor layer 105 is the surface that faced the other substrate 104, which becomes the -c plane and has N polarity (Group V polarity). Also, as viewed from the substrate 101, the nitride semiconductor layer 105 is the same as if it had been crystallized in the -c axis direction.
[0041] As explained using Figure 1C, after forming the nitride semiconductor layer 105 on the other substrate 104, first, as shown in Figure 1F, an AlN layer is formed on the nitride semiconductor layer 105 to form an adhesive layer (other adhesive layer) 103a composed of the AlN layer. An oxide layer composed of an oxide that does not contain Si can also be provided between the adhesive layer 103a and the nitride semiconductor layer 105. Next, the adhesive layer 103a on the other substrate 104 is bonded to the adhesive layer 103 on the substrate 101 shown in Figure 1B, thereby bonding the substrate 101 and the other substrate 104 together. After this, the other substrate 104 can be removed from the nitride semiconductor layer 105.
[0042] Furthermore, as explained using Figure 1B, after forming the oxide layer 102 and the adhesive layer 103 on the substrate 101, a layer of nitride semiconductor containing Ga can be formed on the adhesive layer 103, and then the bonding with the other substrate 104 described above can be carried out. If the oxide layer 102 and the adhesive layer 103 are formed, the Si layer and the nitride semiconductor layer containing Ga will not come into contact, and melt-back etching will not occur.
[0043] The semiconductor stacked structure produced by the above-described semiconductor stacked structure fabrication method comprises a substrate 101 whose main surface is composed of a (100) plane of Si, an oxide layer 102 made of oxide and formed on the substrate 101, an adhesive layer 103 made of AlN and formed on the oxide layer 102, and a nitride semiconductor layer 105 made of a nitride semiconductor containing Ga and formed on the adhesive layer 103. Furthermore, the main surface of the nitride semiconductor layer 105 is made N polar. In addition, the nitride semiconductor layer 105 is bonded to the adhesive layer 103.
[0044] The semiconductor stacked structure obtained by the semiconductor stacked structure fabrication method described above can be used as a template substrate for manufacturing semiconductor devices using nitride semiconductors. It can be used as a template substrate even with the other substrate 104 removed, but generally, the nitride semiconductor layer 105 near the other substrate 104 is composed of a buffer layer including a nucleation layer in the early stages of crystal (epitaxial) growth, resulting in low crystal quality. The buffer layer is generally composed of GaN. For this reason, it is desirable to grow the device layer that constitutes the nitride semiconductor layer 105 for forming the device structure by inserting a buffer layer of sufficient thickness.
[0045] Furthermore, depending on the method of removing the other substrate 104, the nitride semiconductor layer 105 near the other substrate 104 is often removed along with the other substrate 104. Therefore, the buffer layer described above also has the effect of preventing the device layer from being removed together with the substrate. When a buffer layer is inserted, the desired layer will not be exposed even after removing the other substrate 104. Therefore, a process is required to remove the buffer layer portion using removal techniques such as CMP or dry etching, and expose the desired layer (device layer) on the surface. If the device layer is thin, etching with a high selectivity ratio is required, and it is advisable to form an etch stop layer in advance along with the device layer. In addition, a buffer layer made of GaN can be removed by a well-known selective pyrolysis method.
[0046] The semiconductor stacked structure template described above can be used to fabricate N-polar nitride semiconductor devices on a Si substrate. Furthermore, the semiconductor stacked structure template can be used as a wafer for integrating Si devices and N-polar nitride semiconductor devices onto the same substrate. For example, when fabricating an N-polar GaN device integrated with a CMOS circuit using the above template, the N-polar GaN layer (nitride semiconductor layer) in the area where the Si device is to be fabricated is first removed by etching, exposing the Si on the surface. Then, the Si device can be fabricated in the exposed area. The nitride semiconductor layer can be removed by general dry etching. Also, unlike cases where the main surface is Group III polar, a nitride semiconductor layer with an N-polar main surface can also be removed by wet etching with KOH or the like. The CMOS process on the exposed Si substrate can be carried out using known semiconductor device manufacturing techniques.
[0047] [Embodiment 2] Next, a method for manufacturing a semiconductor device according to Embodiment 2 of the present invention will be described with reference to Figures 1A to 1F and 2A to 2C. First, as described using Figures 1A to 1F, a nitride semiconductor layer 105 is formed on a substrate 101 via an oxide layer 102 and an adhesive layer 103, and the surface of the nitride semiconductor layer 105 is exposed.
[0048] Next (after the removal step), recesses 106 are formed on the surface of the nitride semiconductor layer 105, as shown in Figure 2A (first element formation step). Here, two recesses 106 are formed. For example, recesses 106 can be formed by using a mask pattern formed by known lithography techniques and removing the nitride semiconductor layer 105 from the surface to a predetermined depth by known etching techniques (e.g., dry etching).
[0049] Next, as shown in Figure 2B, n-type GaN with a high concentration of n-type impurities is selectively regrown in the recess 106. +- A GaN layer 107 is formed (second element formation step). Here, in each of the two recesses 106, n + -Forms a GaN layer 107.
[0050] Next, as shown in Figure 2C, n + - An electrode 108 is formed to make an ohmic connection to the GaN layer 107 (third element formation step). Here, two n + - An electrode 108 is formed on each of the GaN layers 107. For example, one of the two formed electrodes 108 can be used as a source electrode and the other as a drain electrode.
[0051] For example, a field-effect transistor can be formed by subsequently creating a Schottky junction gate electrode on the surface of the nitride semiconductor layer 105 between the two electrodes 108.
[0052] For example, in the formation of the nitride semiconductor layer 105 as explained using Figure 1C, a device layer (element formation layer) is formed on the nitride semiconductor layer 105 by growing a GaN layer which will be the channel layer and an AlGaN layer which will be the barrier layer for generating 2DEG in that order. Also, as mentioned above, the GaN layer and AlGaN layer are grown after the buffer layer is grown. When the nitride semiconductor layer 105 formed in this way is viewed from the substrate 101 side, after the other substrate 104 has been removed, the GaN layer which will be the channel layer is formed on top of the AlGaN layer which will be the barrier layer. Furthermore, the direction of the crystal axis of each layer is the -c axis direction when viewed from the substrate 101 side in which each layer is formed.
[0053] By forming two electrodes 108 on the nitride semiconductor layer 105 configured in this way, as described above, and forming a gate electrode (not shown) between the two electrodes 108, a field-effect transistor can be formed with the 2DEG generated in the barrier layer as the channel. As is well known, nitride semiconductors have polarization in the c-axis direction, so by forming the heterojunction between the AlGaN layer and the GaN layer described above, the polarization effect spontaneously generates 10 13 cm -3This allows for the formation of 2DEG with a certain degree of density.
[0054] By the way, n + -Formation of the GaN layer 107 is a common technique to reduce the contact resistance of the electrode 108, but regrowth is carried out at high temperatures of 1000°C or higher, which is the typical growth temperature for GaN. For this reason, the aforementioned bonding cannot be applied if adhesives with low heat resistance are used. In contrast, the oxide layer 102 and adhesive layer 103 have a heat resistance exceeding 1000°C, which is higher than that of GaN. Therefore, even when exposed to high temperatures during GaN regrowth, the oxide layer 102 and adhesive layer 103 do not deteriorate, and problems such as delamination in these areas do not occur. Furthermore, since the Si of the substrate 101 and the Ga contained in the nitride semiconductor layer 105 do not come into direct contact, reactions do not progress at the bonding interface due to melt-back etching, and delamination does not occur.
[0055] [Embodiment 3] Next, a method for manufacturing a semiconductor device according to Embodiment 3 of the present invention will be described with reference to Figures 1A to 1F and 3A to 3D. First, as explained using Figure 1A, a substrate 101 is prepared, and then, as explained using Figure 1B, an oxide layer 102 composed of an oxide such as Al2O3 or HfO2 and an adhesive layer 103 composed of AlN are formed on the substrate 101.
[0056] Next, as shown in Figure 3A, a buffer layer 151 is formed on the substrate 104 by crystal growth of a nitride semiconductor containing Ga in the +c axis direction. The buffer layer 151 can be made of, for example, GaN. Subsequently, an etching stop layer 152 is formed on the buffer layer 151 by crystal growth of a nitride semiconductor containing Al and having a higher thermal decomposition temperature than GaN in the +c axis direction. The etching stop layer 152 can be made of AlGaN.
[0057] Next, a nitride semiconductor containing Ga is crystallized on the etching stop layer 152 in the +c axis direction to form a device formation layer 153. The device formation layer 153 can be a stacked structure of, for example, a GaN layer that will be a channel layer, an AlGaN layer that will be a barrier layer, and a GaN layer that will be a protective layer. At this stage, as viewed from another substrate 104, the GaN layer that will be a channel layer, the AlGaN layer that will be a barrier layer, and the GaN layer that will be a protective layer are stacked in this order to form the device formation layer 153. The uppermost layer of the device formation layer 153 is a GaN layer that will be a protective layer. The device formation layer 153 is the layer on which the basic structure of a device (semiconductor device) such as a transistor is formed.
[0058] These steps form a nitride semiconductor layer 105a including a buffer layer 151, an etching stop layer 152, and an element formation layer 153 (first element formation step). The formation of the nitride semiconductor layer 105a is carried out before the bonding step and before the adhesive layer formation step.
[0059] Next, as shown in Figure 3B, the substrate 101 and the other substrate 104 on which the nitride semiconductor layer 105a is formed are bonded together such that the side of the other substrate 104 on which the nitride semiconductor layer 105a is formed faces the substrate 101 (bonding process). The bonding is the same as the bonding process described using Figure 1D. As mentioned above, if the uppermost layer of the device formation layer 153 is a GaN layer that serves as a protective layer, the GaN layer that serves as a channel layer, the AlGaN layer that serves as a barrier layer, etc., can be protected from the pressure applied during the bonding process described above.
[0060] Next, the other substrate 104 is removed from the nitride semiconductor layer 105a, and as shown in Figure 3C, the buffer layer 151 is exposed in a removal process. This process forms the nitride semiconductor layer 105a on the substrate 101 via the oxide layer 102 and the adhesive layer 103, exposing the surface of the nitride semiconductor layer 105a (buffer layer 151). The removal of the other substrate 104 is the same as described using Figure 1E. At this stage, the main surface of the nitride semiconductor layer 105a (buffer layer 151) is the side that faced the other substrate 104, which becomes the -c plane and has N polarity (group V polarity). Also, as viewed from the substrate 101, the nitride semiconductor layer 105a (device formation layer 153, etching stop layer 152, buffer layer 151) is the same as if it had been crystallized in the -c axis direction.
[0061] Next, the buffer layer 151 is removed by selectively thermally decomposing the buffer layer 151 relative to the etching stop layer 152 by heating in a hydrogen atmosphere containing ammonia, exposing the etching stop layer 152 as shown in Figure 3D (second element formation step). Since AlGaN has a higher thermal decomposition temperature than GaN, etching can be performed by selectively thermally decomposing GaN using the selective thermal decomposition method described above. The selectivity ratio of the selective thermal decomposition method can be 10 depending on the conditions. 3 It is highly effective when exposing a thin layer to the surface by etching.
[0062] The device formation layer 153, including the AlGaN layer which serves as a barrier layer and the GaN layer which serves as a channel layer, may have a total thickness of several tens of nanometers. In contrast, the buffer layer 151, which is placed on the side of the other substrate 104 during growth, can have a thickness of several hundred nanometers to several micrometers in order to sufficiently reduce the dislocation density generated by the lattice matching difference between it and the other substrate 104. For this reason, a high selectivity ratio in etching is important between the etching stop layer 152 and the buffer layer 151.
[0063] Furthermore, by performing selective pyrolysis in a hydrogen atmosphere containing ammonia, it is possible to selectively control the etching rate of the buffer layer 151. Without ammonia, the etching rate (etching speed) is too fast, making it difficult to stop etching in the etching stop layer 152, which is made of AlGaN. By controlling the etching rate using ammonia, it becomes easy to control etching so that it is stopped at the etching stop layer 152.
[0064] Furthermore, in the etching process using the selective pyrolysis method described above, the processing temperature is high, around 1000°C. However, since an oxide layer 102 composed of oxides such as Al2O3 and HfO2, and an adhesive layer 103 composed of AlN are formed, the substrate 101 and the nitride semiconductor layer 105a (device formation layer 153) do not come into contact. This prevents melt-back etching due to the reaction between Ga and Si, and prevents roughening of the bonding interface and even delamination. In addition, since oxides and AlN have higher thermal decomposition temperatures than GaN, the adhesive layer 103 and oxide layer 102 are hardly decomposed even under conditions that cause GaN to decompose.
[0065] As described above, by removing the buffer layer 151, the main surface of the etching stop layer 152 becomes the -c plane, which is the side facing the substrate 104, and thus has N polarity (V group polarity). Also, as viewed from the substrate 101, the device formation layer 153 and the etching stop layer 152 are the same as those grown by crystal growth in the -c axis direction. Furthermore, in the device formation layer 153, as viewed from the substrate 101, for example, a GaN layer that serves as a protective layer, an AlGaN layer that serves as a barrier layer, and a GaN layer that serves as a channel layer are stacked in this order, and each layer has an N polarity on the upper surface as viewed from the substrate 101.
[0066] After this (after the second element formation step), electrodes (not shown) and the like can be formed on the element formation layer 153 to create a semiconductor device such as a transistor (third element formation step). For example, the etching stop layer 152 on the element formation layer 153 can be used as a gate insulating layer, and a gate electrode can be formed on it. Alternatively, after removing the etching stop layer 152, a gate electrode that is Schottky connected can be formed on the uppermost channel layer of the element formation layer 153. Furthermore, source electrodes and drain electrodes that are ohmic connected to a channel made of a two-dimensional electron gas formed near the heterointerface between the channel layer and the barrier layer of the element formation layer 153 can be formed with the gate electrode in between.
[0067] As described above, according to the present invention, a substrate whose main surface is composed of a (100) plane of Si and another substrate on which a nitride semiconductor layer formed by crystal growth of a nitride semiconductor containing Ga in the +c axis direction are bonded together via an oxide layer composed of oxide and an adhesive layer composed of AlN. Therefore, a device with good properties using a nitride semiconductor containing Ga can be formed on a Si layer with a main surface orientation of (100).
[0068] According to the present invention, firstly, direct contact between GaN and Si can be prevented. When a wafer is placed in a high-temperature environment with GaN and Si in direct contact, the GaN and Si are etched by melt-back etching, which can lead to problems such as the GaN epitaxial film peeling off from the Si substrate, or etching progressing to the vicinity of the GaN device layer, resulting in deterioration of device characteristics or even device malfunction.
[0069] An oxide layer composed of oxides and an adhesive layer composed of AlN can suppress the aforementioned problems. In this configuration, the oxide layer and AlN each have the following roles. The adhesive layer made of AlN suppresses the diffusion and reaction of Ga and Si in GaN and can also be used as a sacrificial layer in CMP for surface planarization before direct bonding. By using the sputtering method, an adhesive layer made of AlN can be easily formed to a thickness of more than 100 nm. During CMP, layers of several tens of nanometers to about 100 nm are ground away, so it is important to be able to easily form an adhesive layer thicker than this.
[0070] While the desired effect can be achieved with an adhesive layer alone, adhesive layers deposited by sputtering have a higher defect density compared to epitaxially grown AlN layers, making them more susceptible to diffusion of Ga and Si through defects. To prevent this, it is necessary to form an adhesive layer thick enough so that Ga and Si do not react even if diffusion occurs. To prevent this and achieve a high effect while keeping the adhesive layer inserted at the bonding interface thin, an oxide layer is introduced. Oxide layers can be obtained with a lower defect density using CVD or ALD methods, making them less prone to atomic diffusion. Therefore, even a thin oxide layer can effectively prevent the diffusion of Ga and Si.
[0071] Furthermore, according to the present invention, limitations in the device process and degradation of device characteristics due to bonding can be reduced. To avoid direct contact between GaN and Si, it is conceivable to insert an adhesive layer. Generally, organic materials are used for the adhesive layer in wafer bonding, but these materials cannot withstand high-temperature processes, which limits the device process and device characteristics after substrate transfer. An adhesive layer made of AlN or an oxide layer made of oxide has high heat resistance and enables wafer bonding without imposing the above-mentioned limitations on the substrate-transferred N-polarity GaN device.
[0072] Furthermore, according to the present invention, it becomes easier to integrate a CMOS circuit realized on a Si(100) substrate and an N-polarity nitride semiconductor device. Epitaxially growing a nitride semiconductor on a Si(100) substrate has many problems, and it is difficult to integrate a nitride semiconductor device on a Si(100) substrate. According to the present invention, as described above, it is possible to realize a GaN device having high device characteristics and a CMOS circuit on the same chip.
[0073] Note that the present invention is not limited to the embodiments described above, and it is obvious that many modifications and combinations can be implemented by those having ordinary knowledge in the art within the technical idea of the present invention.
Explanation of Reference Numerals
[0074] 101... substrate, 102... oxide layer, 103... adhesive layer, 103a... adhesive layer (other adhesive layer), 104... other substrate, 105... nitride semiconductor layer, 105a... nitride semiconductor layer, 106... recess, 107... n + -GaN layer, 108... electrode, 151... buffer layer, 152... etching stop layer, 153... element formation layer.
Claims
1. A bonding step involves bonding a substrate whose main surface is composed of (100) planes of Si and on which an oxide layer composed of an oxide that does not contain Si is formed, and another substrate on which a nitride semiconductor layer is formed by crystal growth of a nitride semiconductor containing Ga in the +c axis direction, such that the surface on which the nitride semiconductor layer of the other substrate is formed faces the oxide layer formation surface of the substrate. Prior to the bonding step, an adhesive layer forming step is performed on the side of the substrate that will be bonded to the other substrate, in which an adhesive layer made of AlN is formed. After the bonding process, a removal process is performed to remove the other substrate from the nitride semiconductor layer. A method for fabricating a semiconductor stacked structure comprising [a specific feature].
2. In the method for producing a semiconductor stacked structure according to claim 1, The method for manufacturing a semiconductor laminated structure is characterized in that the adhesive layer formation step further comprises a step of forming another adhesive layer composed of an AlN layer on the side of the nitride semiconductor layer that is bonded to the substrate, prior to the bonding step.
3. A bonding step involves bonding a substrate whose main surface is composed of (100) planes of Si and on which an oxide layer composed of an oxide that does not contain Si is formed, and another substrate on which a nitride semiconductor layer is formed by crystal growth of a nitride semiconductor containing Ga in the +c axis direction, such that the surface on which the nitride semiconductor layer of the other substrate is formed faces the oxide layer formation surface of the substrate. Prior to the bonding step, an adhesive layer forming step is performed on the side of the substrate that will be bonded to the other substrate, in which an adhesive layer made of AlN is formed. After the bonding process, a removal process is performed to remove the other substrate from the nitride semiconductor layer, After the removal step, a first element formation step is performed in which a recess is formed on the surface of the nitride semiconductor layer, A second element formation step involves selectively regrowing n-type GaN in the recess to form an n-GaN layer, A third element formation step involves forming an electrode that is ohmic connected to the n-GaN layer. A method for manufacturing a semiconductor device comprising the same equipment.
4. A bonding step involves bonding a substrate whose main surface is composed of (100) planes of Si and on which an oxide layer is formed on the main surface, and another substrate on which a nitride semiconductor layer is formed by crystal growth of a nitride semiconductor containing Ga in the +c axis direction, such that the surface on which the nitride semiconductor layer is formed on the other substrate faces the side of the substrate on which the oxide layer is formed. Prior to the bonding step, an adhesive layer forming step is performed on the side of the substrate that will be bonded to the other substrate, in which an adhesive layer made of AlN is formed. A first element formation step in which, before the bonding step, a nitride semiconductor containing Ga is crystal-grown on the other substrate in the +c axis direction to form a buffer layer, an etching stop layer is formed on the buffer layer by crystal-grown a nitride semiconductor containing Al with a higher thermal decomposition temperature than GaN in the +c axis direction, an element formation layer is formed on the etching stop layer by crystal-grown a nitride semiconductor containing Ga in the +c axis direction, and the nitride semiconductor layer including the buffer layer, the etching stop layer, and the element formation layer is formed. After the bonding process, a removal process is performed to remove the other substrate from the nitride semiconductor layer, A second element formation step is performed after the removal step, in which the buffer layer is removed by selectively thermally decomposing the buffer layer relative to the etching stop layer by heating in a hydrogen atmosphere containing ammonia, thereby exposing the etching stop layer. A method for manufacturing a semiconductor device comprising the same equipment.
5. In the method for manufacturing a semiconductor device according to claim 4, A method for manufacturing a semiconductor device, characterized by comprising a third element formation step of forming electrodes in the element formation layer after the second element formation step.
6. In the method for manufacturing a semiconductor device according to any one of claims 3 to 5, The method for manufacturing a semiconductor device is characterized in that the adhesive layer formation step further comprises a step of forming an additional adhesive layer composed of an AlN layer on the side of the nitride semiconductor layer that is bonded to the substrate, prior to the bonding step.
7. A substrate whose main surface is composed of a (100) plane of Si, An oxide layer formed on the main surface of the substrate, composed of an oxide that does not contain Si, An adhesive layer made of AlN and formed on the oxide layer, A nitride semiconductor layer formed on the adhesive layer, which is composed of a nitride semiconductor containing Ga, A semiconductor stacked structure comprising the features described above.
8. In the semiconductor stacked structure according to claim 7, The nitride semiconductor layer has an N polarity on its main surface. A semiconductor stacked structure characterized by the following features.
9. In the semiconductor stacked structure according to claim 7 or 8, The semiconductor stacked structure is characterized in that the nitride semiconductor layer is bonded to the adhesive layer.