Imaging device, imaging method, and electronic device

Abstract

An imaging device according to one aspect of the present disclosure comprises: a control unit; a power source unit; a switch; and a regulator. The control unit controls an imaging unit on the basis of commands and data from a host, the commands and data being obtained according to an I2C / I3C communication protocol. The power source unit supplies a voltage to, in the control unit, a digital block serving as the target of Dynamic Voltage Frequency Scaling (DVSF) within one frame. The switch and the regulator are disposed between the digital block and the power source unit, and are connected in parallel.

Description

Technical Field

[0001] The present disclosure relates to an imaging device, an imaging method, and an electronic device.

Background Art

[0002] In recent years, in imaging devices, the development of MOS type image sensors such as CMOS (Complementary Metal Oxide Semiconductor) has been underway. For example, in Patent Document 1, an imaging device in which a semiconductor wafer having a pixel array portion and a semiconductor wafer having a logic circuit are stacked has been proposed.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

[0004] In such an imaging device, it is desirable to reduce power consumption.

[0005] Therefore, it is desirable to provide an imaging device, an imaging method, and an electronic device capable of reducing power consumption.

[0006] An imaging device according to one aspect of the present disclosure includes a control unit, a power supply unit, a switch, and a regulator. The control unit controls an imaging unit based on commands and data from a host obtained by an I2C / I3C communication protocol. The power supply unit supplies a voltage to a digital block that is a target of DVFS (Dynamic Voltage Frequency Scaling) within one frame in the control unit. The switch and the regulator are provided between the digital block and the power supply unit and are connected in parallel to each other.

[0007] An imaging method according to one aspect of the present disclosure includes the following steps. (1) In the control unit that controls the imaging unit based on commands and data from the host obtained by the I2C / I3C communication protocol, voltage is supplied to the digital blocks subject to DVFS (Dynamic Voltage Frequency Scaling) within one frame via regulators and switches connected in parallel to each other.

[0008] One aspect of the present disclosure relates to an electronic device comprising a host and an imaging device capable of communication using the I2C / I3C communication protocol. The imaging device comprises a control unit, a power supply unit, a switch, and a regulator. The control unit controls the imaging device based on commands and data from the host obtained via the I2C / I3C communication protocol. The power supply unit supplies voltage to the digital block of the control unit that is subject to DVFS (Dynamic Voltage Frequency Scaling) within one frame. The switch and regulator are provided between the digital block and the power supply unit and are connected in parallel to each other. [Brief explanation of the drawing]

[0009] [Figure 1] This figure shows an example of the change in clock frequency over time when Dynamic Frequency Scaling (DFS) is performed on a COMS image sensor. [Figure 2] This diagram summarizes the clock control shown in Figure 1. [Figure 3] This figure shows an example of the time-dependent change in the clock voltage when DVS (Dynamic Voltage Scaling) is performed on a COMS image sensor. [Figure 4] Figure 3 is a diagram summarizing the power control. [Figure 5] This figure shows an example of a functional block of an imaging device according to one embodiment of the present disclosure. [Figure 6] Figure 5 shows an example of a control method for DFS in the imaging device. [Figure 7]Figure 5 shows an example of a circuit configuration that supplies power to the power domain PDa. [Figure 8] Figure 7 shows an example of a DVS control method in α. [Figure 9] This figure shows an example of a schematic configuration of an imaging system equipped with the imaging device shown in Figure 5. [Modes for carrying out the invention]

[0010] The forms for implementing this disclosure will be described in detail below with reference to the drawings.

[0011] <1. About In-Frame DFS and DVS> Dynamic Frequency Scaling (DFS) is a technology that reduces power consumption by dynamically changing the clock frequency according to the operating mode, thereby avoiding running the circuit at unnecessarily high clock frequencies. DFS differs from a clock gate, which simply turns the clock ON / OFF, in that it raises or lowers the frequency. The means of changing the clock frequency include changing the output frequency of the oscillator that generates the clock, changing the division ratio by adding a frequency divider after the oscillator, or using multiple oscillators with different oscillation frequencies and switching between their multiple clock outputs. The oscillator referred to here may be an oscillator that takes a reference clock as input, such as a PLL, or it may be a standalone oscillator.

[0012] DVS (Dynamic Voltage Scaling) is a technology that, when combined with DFS (Dynamic Voltage Frequency Scaling), can further reduce power consumption than when DFS alone is applied by operating at a higher power supply voltage when the clock frequency is high and at a lower power supply voltage when the clock frequency is low. When DFS and DVS are applied together, it is sometimes called DVFS (Dynamic Voltage Frequency Scaling). DVS differs from Power Gate, which simply turns the power ON / OFF, in that it changes the power supply voltage.

[0013] The CMOS image sensor (CIS) of this disclosure applies DFS and DVS within a single frame of operation to reduce power consumption in the Always-ON mode and in the viewing mode with a small image size. In the CIS of this disclosure, Always-ON mode refers to a mode in which motion detection is performed within 32x10 (mono) size image data, and viewing mode refers to a mode in which image data of 320x120 (color) or larger is output from the MIPI (Mobile Industry Processor Interface) block.

[0014] One frame of CIS operation consists of the following repetition of (1) to (4). (1) Resetting the Pixel's Photo Diode during Shutter Time (2) Photoelectric conversion in the Photodiode during the Integration (or Exposure) period (3) A / D conversion of the charge amount of the photodiode during the read period (4) V-blank period, which is the waiting time until the start of the next frame.

[0015] When the image size is small, such as in Always-ON mode or viewing modes smaller than VGA size, or when the frame rate is low, periods (1) and (3) are relatively short, and period (4) accounts for most of the time of a frame. Therefore, reducing the power consumption during the V-blank period (4) leads to a reduction in the average power consumption of the CIS.

[0016] The function required during the V-blank period is simply to wait for the timing when the next frame starts. Therefore, during the V-blank period, the necessary functions can be satisfied by simply operating with a low-frequency clock supplied to limited blocks. Regarding the period (2), when the exposure time is short in the Rolling Shutter CIS, the Read of the first line may start earlier than the end of the Shutter of the last line. Therefore, there may be cases where the period (2) does not exist. Here, the Integration period of (2) refers to the period that only waits for the time elapsed until the Read operation starts after the Shutter operation of all pixels is completed as the operating state of the sensor, rather than the exposure period of individual pixels.

[0017] In cases where the image size is small and the ADC accuracy can be low, such as in the Always-ON mode, since the Shutter period of (1) and the Read period of (3) are short, there are often cases where the Integration period of (2) remains. Even during the Integration period of (2), since it only measures the time elapsed until the Read starts, it can be operated by supplying a low-frequency clock to limited blocks. Therefore, even during the Integration period of (2), it is effective in reducing power consumption similar to the V-blank of (4).

[0018] In the CIS of the present disclosure, during the V-blank period of (4) and the Integration period of (2), only a clock with a frequency of 422 kHz is supplied to the circuit, and it is a period of waiting until the next frame starts or until Read starts. During that period, the clock is also stopped for the CPU and the buses connected thereto. Fig. 1 conceptually shows the change in the clock frequency within one frame. Fig. 1 shows the CIS of the present disclosure in comparison with the conventional CIS. In this conceptual diagram, the case where the Integration period of (2) does not remain is illustrated. In the conventional CIS, frame-in Clock Gate is performed in the SIF block (described later), and inter-mode DFS is performed in the CU block, PM / CK block, and SYS block (described later), respectively. In the CIS of the present disclosure, frame-in Clock Gate is performed in the SIF block and SYS block, and frame-in DFS is performed in the CU block and PM / CK block. Performing not only inter-mode DFS but also frame-in DFS in the CU block and PM / CK block is a newly introduced technology in the CIS of the present disclosure.

[0019] Fig. 2 shows a summary of the clock control incorporated in the CIS of the present disclosure. Regarding clock control, DFS within one frame is newly introduced in the CIS of the present disclosure.

[0020] During the V-blank period and the Integration period, since the operation is performed only with a 422 kHz clock, the power supply voltage can operate even at a voltage lower than the standard 1.05V. In the CIS of the present disclosure, regarding the SYSTOP block with built-in SRAM, during the V-blank period and the Integration period, all clocks are stopped, and the operation specification is changed to supply only the power supply voltage necessary to maintain the previous state until the next operation.

[0021] Figure 3 conceptually represents the change in power supply voltage within a single frame. In conventional CIS, intermode power gates are performed in the DU block and IFD block, intraframe power gates are performed in the SIF block, and a standard voltage of 1.05V is constantly supplied to the CU block, PM / CK block, and SYS block. In the CIS of this disclosure, instead of a constantly supplied standard voltage, intermode DVS and intraframe DVS may be performed. Performing intermode DVS and intraframe DVS instead of a constantly supplied standard voltage in the CU block, PM / CK block, and SYS block is a new technology introduced in the CIS of this disclosure.

[0022] Figure 4 summarizes the power control features that can be incorporated in this disclosure. Regarding power control, inter-mode and intra-frame DVS are newly introduced in the CIS of this disclosure.

[0023] By the way, when applying DVS, multiple logical block hierarchies within a digital block are divided into multiple power domains. In this case, the division can be approached in the following way, for example. (1) The number of power domains should be kept to a minimum. This is because an increase in the number of power domains reduces the flexibility of the implementation layout, which can lead to an increase in chip size and, consequently, an increase in power consumption. (2) Blocks that are capable of power gates from a functional standpoint are assigned a separate power domain from the power domains of blocks that are not capable of power gates. (3) For blocks that require constant power, DVS will be implemented whenever possible. Blocks that require constant power and for which DVS can be implemented can be classified into the following two types: • Blocks that can operate even with low-frequency (422kHz) clocks and are unaffected by lower voltages. • Blocks that require power to maintain their state when the clock is stopped.

[0024] An embodiment of an imaging device equipped with a digital block designed based on this concept will be described below.

[0025] <2. Embodiments> Figure 5 shows an example of the functional block of an imaging device 100 according to one embodiment of the present disclosure. The imaging device 100 is a low-power image sensor and comprises a controller 110, an imaging unit 120, and a power supply unit 130. The imaging unit 120 acquires image data by imaging and outputs the acquired image data to the controller 110. The controller 110 is a chip that controls imaging by the imaging unit 120 and outputs the image data obtained by the imaging unit 120 to the host application processor 200. The power supply unit 130 supplies various voltages to the controller 110 and the imaging unit 120.

[0026] The controller 110 includes a digital block 110A and an analog block. The digital block 110A includes a SYS block 10, a CU block 20, a PM / CK block 30, a SIF block 40, a DU block 50, and a mipi block 60.

[0027] The SIF block 40 is an interface for receiving image data obtained by the imaging unit 120. The SIF block 40 outputs the image data input from the imaging unit 120 to the DU block 50. The DU block 50 performs predetermined image processing on the image data input from the imaging unit 120 via the SIF block 40 and outputs the resulting image data to the mipi block 60. The mipi block 60 communicates with the application processor 200 according to the mipi protocol. For example, the mipi block 60 transmits the image data obtained from the DU block 50 to the application processor 200 via terminal t4 using the mipi protocol.

[0028] The SYS block 10 communicates with the application processor 200. The SYS block 10 controls the imaging unit 120 based on I2C / I3C signals from the application processor 200 obtained via the I2C / I3C communication protocol. In this specification, I2C / I3C refers to either I2C or I3C. I2C / I3C is a communication protocol between the imaging unit 120 and the application processor 200 for controlling the imaging unit 120.

[0029] The SYS block 10 includes, for example, a CPU 11 and an I2C / I3C block 12. The CPU 11 controls the imaging unit 120 based on commands and data obtained from the application processor 200 via the I2C / I3C block 12. The I2C / I3C block 12 communicates with the application processor 200 via terminal t3 according to the I2C / I3C protocol. The I2C / I3C block 12 acquires commands and data from I2C / I3C signals obtained from the application processor 200, for example, and outputs the acquired commands and data to the CPU 11. The CPU 11 and the I2C / I3C block 12 operate based on multiple types of clock signals input from the PM / CK block 30. The SYS block 10, CU block 20, and PM / CK block 30 transmit and receive data from each other via a bus, for example.

[0030] The CU block 20 generates an imaging unit control signal in response to the control signal input from the SYS block 10 and outputs it to the imaging unit 120. The CU block 20 and the PM / CK block 30 cooperate to control the start and end timings of each operating state. The operating states controlled by the CU block 20 and the PM / CK block 30 include, for example, the Shutter period, Integration period, Read period, and V-blank period.

[0031] The PM / CK block 30 sets the frequency of a clock signal used for the operation of the SYS block 10 (hereinafter simply referred to as "clock frequency") based on the GPI signal input from the application processor 200 via the GPI terminal t1. The PM / CK block 30 determines, for example, the polarity of the GPI signal input from the application processor 200 via the GPI terminal t1. The PM / CK block 30 determines, for example, the polarity of the GPI signal at the start timing of a predetermined operating state (e.g., Integration period, V-blank period). Based on the determination result, the PM / CK block 30 sets the frequency of the clock signal used for the operation of the SYS block 10 (clock frequency). The PM / CK block 30 sets the clock frequency in a predetermined operating state (e.g., Integration period, V-blank period) based on the determination result. For example, when the polarity of the GPI signal is High, the PM / CK block 30 sets the clock frequency to a relatively high frequency. For example, when the polarity of the GPI signal is Low, the PM / CK block 30 sets the clock frequency to a relatively low frequency.

[0032] The PM / CK block 30 has internal control signals corresponding to the set clock frequency. The PM / CK block 30 has, for example, a control register that stores control information corresponding to the set clock frequency. The PM / CK block 30 may also generate and store internally a control signal that means to stop the clock signal when the polarity of the GPI signal is low. In this case, the PM / CK block 30 may have, for example, a control register that stores control information that means to stop the clock signal. The PM / CK block 30 may also have internal control signals corresponding to a voltage set for each operating state. In this case, the PM / CK block 30 may have, for example, an operating state register that stores control information corresponding to a voltage set for each operating state.

[0033] The PM / CK block 30 generates a control signal indicating whether or not to apply DFS within a frame based on a GPI signal input via a different path (GPI terminal t1) than the I2C / I3C communication protocol. The SYS block 10, for example, at the start timing of a predetermined operating state (e.g., Integration period, V-blank period), determines the polarity of the control signal generated by the PM / CK block 30 indicating whether or not to apply DFS within a frame, and if the result is that DFS within a frame is not to be applied, generates a control signal with a low polarity. The SYS block 10 outputs the generated low control signal as a GPO signal to the application processor 200 via a different path (GPO terminal t2) than the I2C / I3C communication protocol.

[0034] Figures 6(A) to 6(F) illustrate an example of how DFS is controlled within a single frame using GPI and GPO. Figure 6(A) shows an example of the input value of the GPI signal input to GPI terminal t1. Figure 6(B) shows an example of the operating state. In Figure 6(B), "V" and "V-blank" refer to the V-blank period, "S" refers to the Shutter period, "I" refers to the Integration period, and "R" refers to the Read period. Figure 6(C) shows an example of the clock frequency. Figure 6(D) shows an example of the output value of the GPO signal output from GPO terminal t2. Figure 6(E) shows an example of whether or not DFS is applied mode. Figure 6(F) shows an example of whether or not communication from the application processor 200 via I2C / I3C block 12 is permitted. Figures 6(A) to 6(F) show an example of a DFS control method that transitions from a DFS non-applied mode to a DFS applied mode, and then back to a DFS non-applied mode.

[0035] The SYS block 10 operates regardless of whether DFS is applied or not when the operating state is in the Shutter period or Read period, for example as shown in Figure 6(C). The application processor 200 instructs the PM / CK block 30 to apply DFS by setting the polarity of the GPI signal to low, for example as shown in Figure 6(A) (#1). At this time, the PM / CK block 30 does not immediately apply DFS. However, since the application processor 200 does not know when the application of DFS will begin, it does not communicate via the I2C / I3C block 12 from the time the GPI signal is set to negative polarity (low).

[0036] The PM / CK block 30 reads the GPI signal at a predetermined timing (e.g., #2), and if the polarity of the read GPI signal is low, it transitions to DFS application mode. At this time, the PM / CK block 30 sets the clock frequency to a relatively low frequency, generates a control signal internally corresponding to the set clock frequency, and outputs a low-frequency clock according to that signal, or generates a control signal that means to stop the clock signal, and stops the clock according to that signal.

[0037] The application processor 200 instructs the PM / CK block 30 to disable DFS by setting the polarity of the GPI signal to high, for example, as shown in Figure 6(A) (#3). At this point, the PM / CK block 30 does not immediately disable DFS. Therefore, the application processor 200 does not yet communicate via the I2C / I3C block 12 at this stage.

[0038] The PM / CK block 30 reads the GPI signal at a predetermined timing (e.g., #4), and if the polarity of the read GPI signal is high, it transitions to the DFS non-applied mode. At this time, the PM / CK block 30 sets the clock frequency to a relatively high frequency, generates a control signal corresponding to the set clock frequency internally, and outputs a high-frequency clock according to that signal.

[0039] The SYS block 10 outputs to the application processor 200 via a different path (GPO terminal t2) than the I2C / I3C communication protocol, according to the control signal generated by the PM / CK block 30 indicating whether or not to apply DFS within a single frame. For example, the SYS block 10 generates a signal with low polarity and outputs the generated low signal as a GPO signal to the application processor 200 via GPO terminal t2 (#5). In other words, the SYS block 10 toggles the GPO signal at the timing of transitioning to the DFS non-applied mode. The application processor 200 recognizes that DFS has been deactivated by the toggle of the GPO signal obtained via GPO terminal t2 and starts communication via the I2C / I3C block 12.

[0040] The controller 110 further includes a regulator 70 and switches 81, 82, and 83. The regulator 70 and switch 81 are connected to power lines VDDLSC and VDDLSC_LV, respectively, as shown, for example, in Figure 7. The regulator 70 and switch 81 are connected in parallel to each other between power lines VDDLSC and VDDLSC_LV. Power line VDDLSC is connected to the power supply unit 130 and is located outside the controller 110. Power line VDDLSC_LV is located inside the controller 110.

[0041] Switch 81 disconnects the connection between power line VDDLSC and power line VDDLSC_LV. Regulator 70 and switch 81 are connected to power line VDDLSC and power domain PDa (described later), respectively, as shown, for example, in Figures 5 and 7. Power domain PDa is connected to power lines VDDLSC_LV and VSSLSC_SC. Power line VSSLSC_SC is supplied from power supply unit 130 via terminal t5, for example, the reference voltage of controller 110 (e.g., 0V).

[0042] The regulator 70 is a so-called LDO (Low Dropout) and has a circuit that stably outputs a voltage lower than the power line VDDLSC. The power line VDDLSC is supplied from the power supply unit 130 with a power supply voltage Vdd1 (e.g., 1.05V) which is necessary for normal read / write operations on the SRAM. The regulator 70 supplies the power line VDDLSC_LV with the lowest power supply voltage Vdd2 (e.g., 0.80V) that allows for SRAM retention operation (operation of holding data without reading / writing). The power supply voltage Vdd2 may be sized to account for the output voltage error of the regulator 70.

[0043] In controller 110, the digital blocks subject to DFS and DVS (subject to DVFS) (SYS block 10, CU block 20, and PM / CK block 30) are included in a common power domain PDa. CU block 20 and PM / CK block 30 operate at a low frequency (422kHz) clock due to DFS execution, and therefore can operate without problems even with reduced voltage. SYS block 10 is a block that requires power to maintain its state when the clock is stopped.

[0044] Even if SYS block 10 were operated at a low frequency (422kHz) clock like the other blocks, the impact on total power consumption would not be significant. Nevertheless, the reason for stopping the clock for SYS block 10 is that it contains SRAM. Unlike CMOS standard cells, SRAM has a circuit configuration in which an intermediate potential is transiently generated in the bit lines inside the SRAM when reading / writing, and therefore it is inherently susceptible to low-voltage operation. However, SRAM has the property of being able to retain data even at relatively low voltages if no reading / writing is performed. In this CIS, DVS is performed on SYS block 10, which has built-in SRAM, using the retention function that can retain data even at low voltages.

[0045] In the controller 110, a digital block (SIF block 40) that operates only during the Read period is included in power domain PDb, which is different from power domain PDa. In power domain PDb, power gates are performed within one frame in Always-On mode. Switch 82 is connected to power line VDDLSC and power domain PDb, for example, as shown in Figure 5. Switch 82 disconnects the connection between power line VDDLSC and power domain PDb, for example. Power domain PDb is connected to power lines VDDLSC_LV,VSSLSC_SC.

[0046] In controller 110, digital blocks (DU block 50 and mipi block 60) that are not operated in Always-On mode are included in power domain PDc, which is different from power domains PDa and PDb. Power gate is performed in power domain PDc in Always-On mode. Switch 83 is connected to power line VDDLSC and power domain PDc, for example, as shown in Figure 5. Switch 83 disconnects the connection between power line VDDLSC and power domain PDc, for example. Power domain PDc is connected to power lines VDDLSC_LV and VDDLSC_SC.

[0047] Furthermore, the regulator 70 has a circuit that switches between a low voltage (power supply voltage Vdd2) and a normal voltage (power supply voltage Vdd1) as the output voltage. As can be seen from Figures 1 and 3, the clock frequency is low at 422 kHz during low-voltage operation. However, during normal voltage operation, the maximum clock frequency becomes a high-speed clock of 153 MHz. Therefore, during normal voltage operation, the current consumption is large, and in order to supply the current consumption of the power supply domain PDe with only the current supply capacity of the regulator 70, it is necessary to use a regulator 70 with a large area that has a large current supply power. In this case, the chip size becomes large. To avoid this, switch 81 is connected in parallel with regulator 70. Switch 81 is turned on during the period when the clock frequency is high and the current consumption is large during normal voltage operation. This allows normal voltage operation without using regulator 70.

[0048] Figures 8(A) to 8(E) illustrate an example of a DVS control method (DVFS control method) performed when the clock waveform transition (DFS control) shown by α in Figure 6 occurs. Figure 8(A) illustrates the current I_total supplied to the power supply domain PDa. Figure 8(B) illustrates the clock frequency. Figure 8(C) illustrates the signal that controls the on / off state of switch 81. Figure 8(D) illustrates the signal that sets the output voltage of regulator 70. Figure 8(E) illustrates the voltage of the power supply line VDDLSC_LV.

[0049] When the operating state is in the Read period, the PM / CK block 30 sets the clock frequency to High. At this time, the PM / CK block 30 outputs a signal to switch 81 to turn it ON. Therefore, since switch 81 is ON when the operating state is in the Read period, the voltage of power line VDDLSC (power supply voltage Vdd1) is supplied to power line VDDLSC_LV (power domain PDe) via switch 81. When the operating state is in the Read period, the PM / CK block 30 outputs a signal to switch 81 to turn it ON, and at the same time outputs a signal to regulator 70 to set the output voltage of regulator 70 to the normal voltage (power supply voltage Vdd1). Therefore, even if the current required to supply power domain PDe exceeds the current supply capacity of regulator 70, the required current is supplied from power line VDDLSC to power line VDDLSC_LV (power domain PDe) via switch 81.

[0050] When the operating state of the PM / CK block 30 changes from the Read period to the V-blank period, it changes the clock frequency from High to Low via DFS control (#11). Consequently, the current I_total supplied to the power domain PDe decreases. Then, the PM / CK block 30 outputs a signal to switch 81 to turn it off (#12). As a result, switch 81 turns off. At this time, the output voltage of regulator 70 is set to the normal voltage (power supply voltage Vdd1) as described above. Therefore, when switch 81 is turned off, the voltage of the power line VDDLSC_LV does not change and maintains the normal voltage (power supply voltage Vdd1).

[0051] Subsequently, the PM / CK block 30 outputs a signal to the regulator 70 that sets the output voltage of the regulator 70 to a low voltage (power supply voltage Vdd2) (#13). As a result, the output voltage of the regulator 70 changes from the normal voltage (power supply voltage Vdd1) to a low voltage (power supply voltage Vdd2), and the voltage of the power line VDDLSC_LV becomes a low voltage (power supply voltage Vdd2).

[0052] Subsequently, after a predetermined period of time has elapsed, the PM / CK block 30 outputs a signal to the regulator 70 to set its output voltage to the normal voltage (power supply voltage Vdd1) (#14). As a result, the output voltage of the regulator 70 changes from a low voltage (power supply voltage Vdd2) to the normal voltage (power supply voltage Vdd1), and the voltage of the power line VDDLSC_LV becomes the normal voltage (power supply voltage Vdd1).

[0053] Subsequently, the PM / CK block 30 outputs a signal to switch 81 to turn it on (#15). As a result, switch 81 turns on. At this time, the voltage of the power line VDDLSC is the normal voltage (power supply voltage Vdd1). Then, when the operating state of the PM / CK block 30 changes from the V-blank period to the Shutter period, the clock frequency is changed from Low to High by DFS control (#16). Consequently, the current I_total supplied to the power supply domain PDe increases. At this time, the output voltage of regulator 70 and the voltage of the power line VDDLSC are equal to each other, so when switch 81 is turned on, the voltage of the power line VDDLSC_LV does not change and maintains the normal voltage (power supply voltage Vdd1).

[0054] Thus, in this embodiment, the clock frequency change and the on / off timing of the switch 81 are controlled so as not to require the regulator 70 to supply a current that exceeds its current supply capacity.

[0055] In this embodiment, DFS can be controlled from the application processor 200 using GPO signals and GPI signals. This enables efficient low-power consumption using DFS.

[0056] Furthermore, in this embodiment, voltage is supplied to the power supply domain PDa via regulators 70 and switches 81 that are connected in parallel with each other. This enables efficient low power consumption using DVFS.

[0057] Furthermore, in this embodiment, the regulator 70 is provided with a circuit that outputs a low voltage (power supply voltage Vdd2) lower than the normal voltage (power supply voltage Vdd1) supplied from the power supply unit 130, and a circuit that switches between the low voltage (power supply voltage Vdd2) and the normal voltage (power supply voltage Vdd1) as the output voltage. As a result, by controlling the setting of the output voltage of the regulator 70 and the on / off state of the switch 81, DVFS can be performed within one frame. Consequently, efficient power consumption reduction using DVFS can be achieved.

[0058] Furthermore, in this embodiment, when DVFS is executed within one frame, after the frequency of the clock signal used in the power domain PDa changes from High to Low, switch 81 changes from On to Off, and subsequently, the output voltage setting of regulator 70 is changed from normal voltage (power supply voltage Vdd1) to low voltage (power supply voltage Vdd2). In addition, in this embodiment, when DVFS is executed within one frame, the output voltage setting of regulator 70 is changed from normal voltage (power supply voltage Vdd1) to low voltage (power supply voltage Vdd2), and after a predetermined period of time has elapsed, the output voltage setting of regulator 70 is changed from low voltage (power supply voltage Vdd2) to normal voltage (power supply voltage Vdd1), and subsequently, switch 81 changes from Off to On, and the frequency of the clock signal used in the power domain PDa changes from Low to High. In this way, the timing of the clock frequency change and the On / Off switching of switch 81 are controlled so as not to require the regulator 70 to supply current exceeding its current supply capacity. This makes it possible to achieve efficient low power consumption using DVFS.

[0059] Furthermore, in this embodiment, the PM / CK block 30, regulator 70, and switch 81 are provided within a single chip. This is because the switch 81 is connected in parallel to the regulator 70, and the clock frequency can be changed and the on / off timing of the switch 81 can be controlled so as not to require the regulator 70 to supply a current that exceeds its current supply capacity. Therefore, efficient low power consumption can be achieved using DVFS.

[0060] <3. Variant> In the above embodiment, the CIS was controlled from the application processor 200 by communication using the I2C / I3C communication protocol. However, in the above embodiment, a method of control using a different communication protocol instead of communication using the I2C / I3C communication protocol may be applied.

[0061] <4. Application Examples> The imaging device 100 according to the above embodiment and its modified form is applicable to imaging devices such as digital still cameras and video cameras, portable terminal devices with imaging functions, and photocopiers that use an image sensor in the image reading unit, as well as electronic devices in general that use an image sensor in the image acquisition unit. Furthermore, the embodiments of this disclosure are also applicable to robots, drones, automobiles, medical devices (endoscopes), etc., that include the imaging device 100. The imaging device 100 according to the above embodiment and its modified form may be formed as a single chip, or it may be in the form of a module having an imaging function in which the imaging unit and the signal processing unit or optical system are packaged together. Below, an example of an imaging system equipped with the imaging device 100 according to the above embodiment and its modified form will be described with reference to Figure 9. Figure 9 is an explanatory diagram showing an example of an imaging system 1 equipped with the imaging device 100 according to the above embodiment and its modified form.

[0062] As shown in Figure 9, the imaging system 1 includes, for example, an imaging device 100, an optical system 310, a shutter device 320, a control circuit 330, a DSP circuit 340, a frame memory 350, a display unit 360, a storage unit 370, an operation unit 380, and a power supply unit 390, according to the above embodiment and its modified form. In the imaging system 1, the imaging device 100, the DSP circuit 340, the frame memory 350, the display unit 360, the storage unit 370, the operation unit 380, and the power supply unit 390, according to the above embodiment and its modified form, are interconnected via a bus line 400. The DSP circuit 340 corresponds to a specific example of the application processor 200 according to the above embodiment and its modified form.

[0063] The optical system 310 is composed of one or more lenses and guides light from the subject (incident light) to the imaging device 100, where it forms an image on the light-receiving surface of the imaging device 100. The shutter device 320 is positioned between the optical system 310 and the imaging device 100 and controls the light illumination period and light shielding period for the imaging device 100 according to the control circuit 330. The imaging device 100 accumulates signal charge for a certain period of time in response to the light formed on the light-receiving surface via the optical system 310 and the shutter device 320. The signal charge accumulated in the imaging device 100 is transferred as a pixel signal (image data) to the DSP circuit 340 according to the drive signal (timing signal) supplied from the control circuit 330. In other words, the imaging device 100 receives the incident image light (incident light) through the optical system 310 and the shutter device 320 and outputs a pixel signal corresponding to the received image light (incident light) to the DSP circuit 340. The control circuit 330 drives the imaging device 100 and the shutter device 320 by outputting drive signals that control the transfer operation of the imaging device 100 and the shutter operation of the shutter device 320.

[0064] The DSP circuit 340 is a signal processing circuit that processes pixel signals (image data) output from the imaging device 100. The frame memory 350 temporarily holds the image data processed by the DSP circuit 340 in frame units. The display unit 360 consists of a panel-type display device such as a liquid crystal panel or an organic EL (Electro Luminescence) panel, and displays moving images or still images captured by the imaging device 100. The storage unit 370 records the image data of moving images or still images captured by the imaging device 100 onto a recording medium such as a semiconductor memory or a hard disk. The operation unit 380 issues operation commands for various functions of the imaging system 1 according to user operations. The power supply unit 390 appropriately supplies various power supplies to the imaging device 100, DSP circuit 340, frame memory 350, display unit 360, storage unit 370, and operation unit 380, which serve as power sources for their operation.

[0065] In this application example, the imaging device 1 according to the above embodiment and its modified form is applied to the imaging system 1. This makes it possible to reduce the power consumption of the imaging device 100, thereby providing an imaging system 1 with low power consumption.

[0066] The present disclosure has been described above with reference to embodiments, modifications, and application examples, but the present disclosure is not limited to the above embodiments, and various modifications are possible. The effects described herein are merely illustrative. The effects of the present disclosure are not limited to those described herein. The present disclosure may have effects other than those described herein.

[0067] Furthermore, for example, this disclosure can take the following configuration. (1) A control unit that controls the imaging unit based on commands and data from the host obtained via the I2C / I3C communication protocol, The control unit includes a power supply unit that supplies voltage to the digital blocks subject to DVFS (Dynamic Voltage Frequency Scaling) within one frame, A regulator and a switch are provided between the digital block and the power supply unit, and are connected in parallel to one another. Equipped with Imaging device. (2) The regulator is an LDO (Low Dropout) that includes a circuit that outputs a second voltage lower than the first voltage supplied from the power supply unit, and a circuit that switches between the first voltage and the second voltage as the output voltage. (1) The imaging device described above. (3) The control unit performs DVFS within one frame by controlling the output voltage setting of the LDO and the on / off state of the switch. (2) The imaging device described above. (4) When the control unit performs DVFS within one frame, it changes the frequency of the clock signal used by the control unit from High to Low, then changes the switch from On to Off, and subsequently changes the output voltage setting of the LDO from the First Voltage to the Second Voltage. (3) The imaging device described above. (5) When the control unit performs DVFS within one frame, the output voltage setting of the LDO is changed from the first voltage to the second voltage, and after a predetermined period of time has elapsed, the output voltage setting of the LDO is changed from the second voltage to the first voltage, and then the switch is changed from off to on, and the frequency of the clock signal is changed from low to high. (4) The imaging device described above. (6) The digital block, the regulator, and the switch are all located on a single chip. An imaging device as described in any one of (1) to (5). (7) The control unit, which controls the imaging unit based on commands and data from the host obtained via the I2C / I3C communication protocol, includes supplying voltage to digital blocks subject to DVFS (Dynamic Voltage Frequency Scaling) within one frame via regulators and switches connected in parallel to each other. Imaging method. (8) The regulator is an LDO (Low Dropout) that includes a circuit that outputs a second voltage lower than the first voltage supplied from the power supply unit, and a circuit that switches between the first voltage and the second voltage as the output voltage. This includes controlling the output voltage setting of the LDO and the on / off state of the switch to perform DVFS within one frame. The imaging method described in (7). (9) When executing DVFS within a single frame, the control unit changes the frequency of the clock signal used from High to Low, then changes the switch from On to Off, and subsequently changes the output voltage setting of the LDO from the First Voltage to the Second Voltage. The imaging method described in (8). (10) When DVFS is executed within one frame, the output voltage setting of the LDO is changed from the first voltage to the second voltage, and after a predetermined period of time has elapsed, the output voltage setting of the LDO is changed from the second voltage to the first voltage, and then the switch is changed from off to on, and the frequency of the clock signal is changed from low to high. The imaging method described in (9). (11) A host capable of communication using the I2C / I3C communication protocol, A control unit that controls the imaging unit based on commands and data from the host obtained by the I2C / I3C communication protocol, The control unit includes a power supply unit that supplies voltage to the digital blocks subject to DVFS (Dynamic Voltage Frequency Scaling) within one frame, A regulator and a switch are provided between the digital block and the power supply unit, and are connected in parallel to one another. Equipped with electronic equipment.

[0068] In the imaging apparatus, imaging method, and electronic equipment relating to one aspect of this disclosure, a voltage is supplied to the digital block (power domain) subject to DVFS within one frame via regulators and switches connected in parallel. This enables efficient low power consumption using DVFS. The effects of this disclosure are not necessarily limited to those described herein, but may be any of the effects described herein.

[0069] This application claims priority based on U.S. Patent Application No. 17 / 466,522, filed with the U.S. Patent and Trademark Office on 3 September 2021, and all the contents of that application are incorporated herein by reference.

[0070] Those skilled in the art will understand that various modifications, combinations, subcombinations, and changes can be conceived depending on design requirements and other factors, and that these fall within the scope of the attached claims and their equivalents.

Claims

1. A control unit that controls the imaging unit based on commands and data from the host obtained via the I2C / I3C communication protocol, The control unit includes a power supply unit that supplies voltage to the digital blocks subject to DVFS (Dynamic Voltage Frequency Scaling) within one frame, A regulator and a switch are provided between the digital block and the power supply unit, and are connected in parallel to one another. Equipped with Imaging device.

2. The regulator is a Low Dropout (LDO) that includes a circuit that outputs a second voltage lower than a first voltage supplied from the power supply unit, and a circuit that switches between the first voltage and the second voltage as the output voltage. The imaging apparatus according to claim 1.

3. The control unit performs DVFS within one frame by controlling the output voltage setting of the LDO and the on / off state of the switch. The imaging apparatus according to claim 2.

4. When the control unit performs DVFS within one frame, it changes the frequency of the clock signal used by the control unit from High to Low, then changes the switch from On to Off, and subsequently changes the output voltage setting of the LDO from the First Voltage to the Second Voltage. The imaging device according to claim 3.

5. When the control unit performs DVFS within one frame, the output voltage setting of the LDO is changed from the first voltage to the second voltage, and after a predetermined period of time has elapsed, the output voltage setting of the LDO is changed from the second voltage to the first voltage, and then the switch is changed from off to on, and the frequency of the clock signal is changed from low to high. The imaging apparatus according to claim 4.

6. The digital block, the regulator, and the switch are all located within a single chip. The imaging apparatus according to claim 1.

7. The control unit, which controls the imaging unit based on commands and data from the host obtained via the I2C / I3C communication protocol, includes supplying voltage to digital blocks subject to DVFS (Dynamic Voltage Frequency Scaling) within one frame via regulators and switches connected in parallel to each other. Imaging method.

8. The regulator is an LDO (Low Dropout) that includes a circuit that outputs a second voltage lower than the supplied first voltage, and a circuit that switches between the first voltage and the second voltage as the output voltage. This includes controlling the output voltage setting of the LDO and the on / off state of the switch to perform DVFS within one frame. The imaging method according to claim 7.

9. When executing DVFS within one frame, the control unit changes the frequency of the clock signal used from High to Low, then changes the switch from On to Off, and subsequently changes the output voltage setting of the LDO from the First Voltage to the Second Voltage. The imaging method according to claim 8.

10. When DVFS is executed within one frame, the output voltage setting of the LDO is changed from the first voltage to the second voltage, and after a predetermined period of time has elapsed, the output voltage setting of the LDO is changed from the second voltage to the first voltage, and then the switch is changed from off to on, and the frequency of the clock signal is changed from low to high. The imaging method according to claim 9.

11. A host capable of communication using the I2C / I3C communication protocol, A control unit that controls the imaging unit based on commands and data from the host obtained by the I2C / I3C communication protocol, The control unit includes a power supply unit that supplies voltage to the digital blocks subject to DVFS (Dynamic Voltage Frequency Scaling) within one frame, A regulator and a switch are provided between the digital block and the power supply unit, and are connected in parallel to one another. Equipped with electronic equipment.

Images