Pre-screening and tuning of heterojunctions for topological quantum computers

Abstract

A method for evaluating a semiconductor-superconductor heterojunction for use in a qubit register of a topological quantum computer includes: (a) measuring one or both of a radio frequency (RF) junction admittance and a sub-RF conductance, including a nonlocal conductance, of the semiconductor-superconductor heterojunction to obtain mapping data and refinement data; (b) analyzing the mapping data to find one or more regions of parameter space consistent with a complete topological phase of the semiconductor-superconductor heterojunction; and (c) analyzing the refinement data to find a boundary of the complete topological phase in the parameter space and a topological gap of the semiconductor-superconductor heterojunction for at least one of the one or more regions of the parameter space.

Description

Background Art

[0001] A quantum computer is a physical machine configured to perform logical operations based on or affected by quantum mechanical phenomena. Such logical operations may include, for example, mathematical calculations. Current interest in quantum computer technology is motivated by analyses suggesting that the computational efficiency of a properly configured quantum computer may exceed that of any practical non-quantum computer when applied to certain types of problems. Such problems include computer modeling of natural and synthetic quantum systems, integer factorization, data search, and function optimization applied to systems of linear equations and machine learning. Further, the continued miniaturization of conventional computer logic structures is expected to ultimately lead to the development of nanoscale logic components that exhibit quantum effects, and thus must be addressed according to the principles of quantum computing.

[0002] Different types of quantum computers operate based on different quantum mechanical phenomena. A "topological" quantum computer is a quantum computer whose operation is based on a non-Abelian topological phase of matter that can support "braidable" quasiparticles. This type of quantum computer is expected to be less prone to the problem of quantum decoherence than other types of quantum computers, and thus may function as a relatively fault-tolerant quantum computing platform.

Summary of the Invention

[0003] One aspect of the present disclosure relates to a method for evaluating a semiconductor-superconductor heterojunction for use in a qubit register of a topological quantum computer. The method includes (a) measuring one or both of the radio frequency (RF) junction admittance and / or sub-RF conductance, including the nonlocal conductance of the semiconductor-superconductor heterojunction, to obtain mapping data and refined data; (b) analyzing the mapping data to find one or more regions of the parameter space that coincide with the unbroken topological phase of the semiconductor-superconductor heterojunction; and (c) analyzing the refined data to find the boundary of the unbroken topological phase in the parameter space and the topological gap of the semiconductor-superconductor heterojunction to at least one of the one or more regions of the parameter space.

[0004] This summary of the invention is provided to introduce, in a simplified form, a selection of concepts that will be further described in the detailed description. This summary of the invention is not intended to identify any major or essential features of the claimed subject matter, nor is it intended to be used to limit the scope of the claimed subject matter. The claimed subject matter is not limited to implementations that resolve any or all of the defects described in any part of this disclosure. [Brief explanation of the drawing]

[0005] [Figure 1] This figure shows an exemplary configuration of a quantum computer.

[0006] [Figure 2] This figure shows a Bloch sphere, which graphically represents the quantum state of one qubit in a quantum computer.

[0007] [Figure 3]This figure shows an exemplary signal waveform for performing quantum gate operations in a quantum computer.

[0008] [Figure 4] This figure shows an exemplary qubit architecture that includes a linear tetron array.

[0009] [Figure 5] This figure shows an exemplary embodiment of a semiconductor-superconductor heterojunction device, evaluated according to the method described herein.

[0010] [Figure 6] This figure shows an exemplary method for evaluating semiconductor-superconductor heterojunctions for use in qubit registers of topological quantum computers.

[0011] [Figure 7] This figure shows an exemplary configuration of a radio frequency (RF) reflectometry test circuit.

[0012] [Figure 8] This figure shows an exemplary method for measuring the RF junction admittance of a semiconductor-superconductor heterojunction.

[0013] [Figure 9] Figure 8 shows an exemplary method for finding a region of parameter space that coincides with the complete topological phase of a semiconductor-superconductor heterojunction by analyzing data from the method.

[0014] [Figure 10] This figure shows the method of analyzing mapping data using the method shown in Figure 9.

[0015] [Figure 11] This figure shows an exemplary configuration of a sub-RF conductance test circuit.

[0016] [Figure 12] This figure shows an exemplary method for measuring the sub-RF conductance of a semiconductor-superconductor heterojunction.

[0017] [Figure 13] Figure 12 shows an exemplary method for finding the boundary of the complete topological phase in parameter space and the topological gap of a semiconductor-superconductor heterojunction by analyzing data from the method.

[0018] [Figure 14] This figure shows the method used to analyze refined data.

[0019] [Figure 15] This shows the effect of the smooth potential at the right end of the semiconductor wire in a 1D model of a semiconductor-superconductor heterojunction.

[0020] [Figure 16] This shows the effect of a smooth potential at the center of a semiconductor wire in a 1D semiconductor-superconductor heterojunction.

[0021] [Figure 17] This figure shows the results of a data analysis across the field / plunger parameter space for a 1D semiconductor-superconductor heterojunction with a potential bump at the center of a semiconductor wire.

[0022] [Figure 18] This figure shows the results of data analysis across the field / plunger parameter space for a strongly disordered 1D model of a semiconductor-superconductor heterojunction.

[0023] [Figure 19]This figure shows an exemplary apparatus configured to evaluate semiconductor-superconductor heterojunctions for use in qubit registers of a topological quantum computer.

[0024] [Figure 20] This figure shows an exemplary method for constructing a topological quantum computer.

[0025] [Figure 21] This figure shows an embodiment of another exemplary method for evaluating semiconductor-superconductor heterojunctions for use in qubit registers of topological quantum computers. [Modes for carrying out the invention]

[0026] Quantum computer architecture Figure 1 shows an exemplary embodiment of a quantum computer 10 configured to perform quantum logic operations (see below). While conventional computer memory holds digital data in an array of bits and performs bitwise logic operations, a quantum computer holds data in an array of qubits and acts quantum mechanically on the qubits to implement the desired logic. Thus, the quantum computer 10 in Figure 1 includes at least one qubit register 12 containing an array of qubits 14. The illustrated qubit register has a length of 8 qubits, but qubit registers containing longer and shorter qubit arrays are also conceivable, as is the case with quantum computers containing two or more qubit registers of arbitrary lengths.

[0027] The qubits 14 of the qubit register 12 may take various forms depending on the desired architecture of the quantum computer 10. While this disclosure relates to qubits embodied as quasiparticles in a non-abelian topological phase, the qubits may alternatively include, as non-limiting examples, superconducting Josephson junctions, trapped ions, trapped atoms coupled in high-finesse cavities, atoms or molecules confined in fullerenes, ions or neutral dopant atoms confined in host lattices, quantum dots exhibiting discrete space or spin-electron states, electron-holes in semiconductor junctions tuned via electrostatic traps, coupled quantum wire pairs, nuclei addressable by magnetic resonance, free electrons in helium, molecular magnets, or metal-like carbon nanospheres. More generally, each qubit 14 may include any particle or system of particles that can exist in two or more discrete quantum states that can be experimentally measured and manipulated. For example, qubits may be implemented in multiple processing states corresponding to different modes of light propagation through linear optical elements (e.g., mirrors, beam splitters, and phase shifters), as well as in a state where they are stored within a Bose-Einstein condensate.

[0028] Figure 2 is a diagram of the Bloch sphere 16, which provides a graphical description of several quantum mechanical aspects of the individual qubits 14. In this description, the north and south poles of the Bloch sphere correspond to the standard basis vectors |0> and |1>, respectively. The set of points on the surface of the Bloch sphere contains all possible pure states |ψ> of the qubits, while the points inside correspond to all possible mixed states. Mixed states of a given qubit can arise from decoherence, which can occur due to undesirable coupling to external degrees of freedom.

[0029] Returning to Figure 1, the quantum computer 10 includes a controller 18A. The controller includes at least one processor 20A and associated computer memory 22A. The processor 20A of the controller 18A may be operably coupled to peripheral components such as network components, enabling remote operation of the quantum computer. The processor 20A of the controller 18A may take the form of a central processing unit (CPU), a graphics processing unit (GPU), etc. Thus, the controller may include classical electronic components. The terms “classical” and “non-quantum” apply herein to any component that can be accurately modeled as a whole particle without considering the quantum state of any individual particle. Classical electronic components include, for example, integrated and microlithographed transistors, registers, and capacitors. The computer memory 22A may be configured to hold program instructions 24A that cause the processor 20A to execute any function or process of the controller. The computer memory may also be configured to hold additional data 26A. In an example where the qubit register 12 is a cryogenic device, the controller 18A may include a control component capable of operating at low or very low temperatures—for example, a field-programmable gate array (FPGA) operating at 77K. In such an example, the cryogenic control component may be operably coupled to an interface component capable of operating at room temperature.

[0030] The controller 18A of the quantum computer 10 is configured to receive a plurality of inputs 28 and provide a plurality of outputs 30. Each input and output may include digital and / or analog lines. At least some of the inputs and outputs may be data lines from which data is supplied to and / or extracted from the quantum computer. Other inputs may include control lines from which the operation of the quantum computer can be tuned or otherwise controlled.

[0031] The controller 18A is operably coupled to the qubit register 12 via a quantum interface 32. The quantum interface is configured to exchange data bidirectionally with the controller. The quantum interface is further configured to exchange signals corresponding to the data bidirectionally with the qubit register. Depending on the architecture of the quantum computer 10, such signals may include electrical signals, magnetic signals, and / or optical signals. Through signals transmitted via the quantum interface, the controller may query and otherwise influence the quantum states held in the qubit register, as defined by the collective quantum state of the array of qubits 14. For this purpose, the quantum interface includes at least one modulator 34 and at least one demodulator 36, each operably coupled to one or more qubits in the qubit register. Each modulator is configured to output a signal to the qubit register based on the modulated data received from the controller. Each demodulator is configured to sense the signal from the qubit register and output data to the controller based on that signal. The data received from the demodulator may, in some examples, be an observable estimate of a measurement of the quantum state held in the qubit register.

[0032] In some examples, a well-configured signal from modulator 34 may physically interact with one or more qubits 14 of qubit register 12 to trigger a measurement of the quantum state held by one or more qubits. Demodulator 36 may then sense the resulting signal emitted by one or more qubits according to the measurement and supply data corresponding to the resulting signal to controller 18A. In other words, demodulator may be configured to output an estimate of one or more observables reflecting the quantum state of one or more qubits of qubit register based on the received signal and supply the estimate to controller. In one non-limiting example, modulator may initiate a measurement by providing appropriate voltage pulses or pulse trains to the electrodes of one or more qubits based on data from controller. Briefly, demodulator may sense photon emission from one or more qubits and assert the corresponding digital voltage level on the quantum interface line to controller. Generally speaking, any measurement of a quantum mechanical state is defined by an operator O corresponding to the observable thing to be measured, and the result of the measurement, R, is guaranteed to be one of the allowed eigenvalues ​​of O. In quantum computers, R is statistically related to the qubit register state before measurement, but is not uniquely determined by the qubit register state.

[0033] Depending on the appropriate input from the controller 18A, the quantum interface 32 may be configured to implement one or more quantum logic gates to act on the quantum states held in the qubit register 12. While the function of each type of logic gate in a classical computer system is described by a corresponding truth table, the function of each type of quantum gate is described by a corresponding operator matrix. The operator matrix acts on (i.e., multiplies) a complex vector representing the qubit register state, resulting in a specified rotation of that vector in Hilbert space.

[0034] For example, Hadamard gate (HAD) is defined as follows:

number

[0035] The HAD gate acts on a single qubit, mapping the ground state |0> to (|0>+|1>) / √2 and |1> to (|0>-|1>) / √2. Thus, the HAD gate creates a superposition of states that, when measured, have an equal probability of revealing either |0> or |1>.

[0036] A phase gate S is defined by:

number

[0037] The S gate does not change the ground state |0>, but changes |0> to e iπ / 2 It maps to |1>. Therefore, the probability of measuring either |0> or |1> is not changed by this gate, and the phase of the qubit's quantum state is shifted. This is equivalent to rotating ψ by 90° along the circle of latitude on the Bloch sphere in Figure 2.

[0038] Some quantum gates act on two or more qubits. For example, the SWAP gate acts on two separate qubits and swaps their values. This gate is defined by:

number

[0039] The above list of quantum gates and associated operator matrices is not exhaustive, but is provided for the sake of clarity. Other quantum gates, as non-restrictive examples, include the Pauli-X, -Y, and -Z gates.

number

number

[0040] Following Figure 1, a well-configured signal from the modulator 34 of the quantum interface 32 can physically interact with one or more qubits 14 of the qubit register 12 to assert any desired quantum gate operation. As described above, the desired quantum gate operation is a specially defined rotation of a complex vector representing the qubit register state. To perform the desired rotation O, one or more modulators of the quantum interface 32 assert a predetermined period T i During this time, a predetermined signal level S i This may be applied. In some examples, as shown in Figure 3, it may be applied to a period in which multiple signal levels are sequenced or otherwise associated, and a quantum gate operation may be asserted on one or more qubits of a qubit register. In general, each signal level S i and each period T i This is a control parameter that can be adjusted by proper programming of the controller 18A.

[0041] The term "oracle" is used herein to describe a given sequence of elementary quantum-gate and / or measurement operations that can be performed by the quantum computer 10. An oracle may be used, for example, to transform the quantum state of the qubit register 12 to perform classical or non-elemental gate operations, or to apply density operators. In some examples, an oracle may be used to perform a predefined "black-box" operation f(x), which may be incorporated into a complex sequence of operations. To ensure adjoint operation, an oracle that maps n input qubits |x> to m output or ancilla qubits may act on n+m qubits.

number

number

[0042] Implicitly stated in this specification is that each qubit 14 in the qubit register 12 may be queried via the quantum interface 32 to reliably reveal the standard basis vector |0> or |1> characterizing the quantum state of that qubit. However, in some implementations, measuring the quantum state of a physical qubit can be error-prone. Therefore, any qubit 14 may be implemented as a logical qubit, which involves grouping physical qubits that are measured according to an error-correcting oracle to reliably reveal the quantum state of that logical qubit.

[0043] Topological quantum computer In a topological quantum computer, the quantum state held in each qubit is the state of two or more braidable quasiparticles, or "anyons," observed within the non-abelian topological phase of matter. Different anyon worldlines are forbidden from intersecting or merging quantum mechanically. This feature forces their paths to form a stable braid that passes through each other in spacetime. Compared to trap particles used in other types of quantum computers, anyon braids are more resistant to quantum decoherence, a source of errors in quantum computation. However, realizing a topological quantum computer requires the ability to engineer a suitable topological phase and manipulate the anyons within it.

[0044] Early experiments in topological quantum computing focused on a two-dimensional "electron gas" of supercooled gallium arsenide (GaAs) thin layers sandwiched between layers of aluminum gallium arsenide (AlGaAs) and manipulated in a strong magnetic field. Implementing a quantum computer using this architecture would require a braiding of individual quasiparticle excitations combined with any-on interference-based measurements, involving coherent quasiparticle transport over considerable distances.

[0045] More recently proposed is a one-dimensional topological qubit architecture, which appears to be more suitable for practical implementation. The proposed system uses a semiconductor-superconductor heterostructure in which superconductivity, strong spin-orbit coupling, and a magnetic field work together to form a topological superconducting state that supports Majorana zero modes (MZM). This novel architecture eliminates the need to move quasiparticles by employing a "measurement-only" method, in which case the sequence of measurements has the same effect as a braiding operation. This architecture does not require quasiparticles to move through interference loops, but rather utilizes the distinction between a "fermion parity-protected topological phase" (the actual genus of the proposed heterostructure) and a true topological phase. Advantageously, the topological charge in the fermion parity-protected topological phase can be manipulated by the process of electron tunneling into the MZM. Transport through a pair of MZMs can provide a measurement of their coupled topological charge in the presence of large charge energies.

[0046] Considering these and other useful properties, MZMs can be used as the basis for qubits in topological quantum computers. MZMs are generated at the edges of semiconductor-superconductor heterostructures tuned to a topological regime by appropriate magnetic fields and gate voltages. A series of practical implementations are described in Scalable Designs for Quasiparticle-Poisoning-Protected Topological Quantum Computation with Majorana Zero Modes by Karzig et al., arXiv:1610.05289v4 [cond-mat.mes-hall] (June 21, 2017). Suitable heterostructure materials and material properties are described in Majorana Fermions and a Topological Phase Transition in Semiconductor-Superconductor Heterostructures by Lutchyn et al., arXiv:1002.4033v2 [cond-mat.supr-con] (August 13, 2010).

[0047] An exemplary implementation includes at least two topological superconducting segments within a qubit, totaling at least four Majorana zero modes per qubit. In contrast to non-degenerate quantum computing architectures where the two states of a qubit have different energies, the state used for quantum computation is the degenerate ground state of the qubit. The degeneracy of the qubit states and the spatial isolation of the Majorana zero modes ensure long coherence times and the feasibility of precise application of a pair of Clifford gates.

[0048] Figure 4 shows an example of a topological qubit architecture including a linear tetron array 38. The linear tetron array includes segments 40 and 42 containing classical superconductors such as aluminum (Al), segment 44 containing semiconductors such as indium arsenide (InAs) or indium antimonide (InSb), and multiple MZM46. The length of the non-topological segments

number

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[0049] Qubit structures like the one shown in Figure 4 are difficult to manufacture with the degree of reproducibility required for practical quantum computing. Due to material or manufacturing defects, some candidate structures may not be able to operate in the desired topological regime. Even candidate structures that operate in the desired topological regime cannot necessarily predict in advance the appropriate terminal bias and magnetic field levels required for qubit operation. Therefore, candidate semiconductor-superconductor heterojunctions must be "pre-screened" for appropriate topological behavior, and successful heterojunctions must be "tuned" to discover appropriate operating parameters before being incorporated into a qubit register.

[0050] Method Overview This disclosure provides a method for pre-screening and tuning candidate semiconductor-superconductor heterojunctions for topological qubits. The method includes a procedure for extracting “topological gaps” (see below) of candidate heterojunctions using at least two steps of measurement followed by analysis. The measurements are performed on a device having three current-carrier contacts, one of which is superconducting (referred to herein as a “three-terminal device”). The “mapping” phase of the method includes rapid measurements to roughly identify promising regions. The subsequent “refinement” phase includes slower measurements performed for each of the promising regions identified in the mapping phase. In some examples, the method uses a density-based clustering algorithm on two-sided zero-bias peak (ZBP) data and extracts classifications of predicted topological regions and bias traces using peak discovery or machine learning. This improves the accuracy of conventional methods by checking the stability of ZBP against cutter gate voltage fluctuations and checking for gap closing at the boundaries of suspicious topological regions. Meta-analysis of ZBP data is used to extract the probability of discovering topological regions across many devices of the same preparation. This feature can be used to characterize the growth and / or fabrication methods of topological qubit structures.

[0051] As used herein, a “false positive” is the identification of a trivial system as topological, while a “false negative” is the identification of a topological system as trivial. The technique herein is an improvement over a basic ZBP search by including separate ZBP searches on both sides of a three-terminal device, thereby reducing the probability of false positives. It also includes non-local measurements to extract energy gaps within candidate systems, providing additional information for detecting topological gaps. Finally, it includes non-discriminant measurements within a region of parameter space with predefined boundaries, thereby excluding false positives resulting from confirmation and selection bias (which can occur when the measurement region is selected by a human).

[0052] Figure 5 shows an embodiment of an exemplary semiconductor-superconductor heterojunction device 48 evaluated according to the method described herein. Generally speaking, a semiconductor-superconductor heterojunction suitable for testing includes at least three terminals supporting electronic admittance and conductance measurements, in addition to a number of electrostatic control terminals. The device 48 in Figure 5 is a three-terminal device including a topological intermediate segment 50 coupled to a ground probe 52 via a trivial superconductor, and two vertical probes 54R and 54L coupled to both ends of a semiconductor wire. This geometry allows for simultaneous measurement of the tunneling signature of the topological phase at the two ends of the intermediate segment 50 due to correlation with zero-bias features on both sides. Furthermore, a nonlocal signal between the two vertical probes provides information about the lowest energy of the expanded state of the topological segment, which may be used as a proxy for the topological gap (for example, in a sufficiently long semiconductor wire, the nonlocal signal is set to a bias value corresponding to the lowest energy expanded mode in the wire). Therefore, the method here does not directly measure the topological properties of the system, but instead measures a set of proxy variables known to correlate well with topological invariants from analytical calculations and numerical simulations. The proxy criteria for identifying topologically nontrivial regions are as follows:

[0053] 1. Correlated zero-bias differential conductance peaks occur on both sides of the device across a well-separated topological region of Majorana.

[0054] 2. When the magnetic field value is low, there is a gap in the system bulk. As the magnetic field increases, the bulk gap should close and then reopen in the topological region. The energy gap value in the wire bulk can be detected in a three-terminal device via nonlocal conductance measurement.

[0055] Within a region of parameter space that satisfies the criteria for being topological, the size of the bulk gap changes. In the context of this disclosure, the operational meaning of the term "topological gap" is the size of the maximum bulk gap in such a topological region.

[0056] To distinguish between topological and non-topological systems, this method must accurately identify topological regions in an idealized numerical test dataset. Therefore, the method described herein exhibits a high overlap between topologically identified regions and numerically determined topological indices (e.g., as shown in Figure 10). Furthermore, the method must correctly label currently known false-positive signature candidates as non-topological. These include:

[0057] 1. Examples of non-topological zero-bias peaks, such as trivial local bound states induced by cutters, impurities, or smooth potentials (e.g., pairs of quasi-Majorana modes at the edges of a device);

[0058] 2. Disorderly induced low-energy subgap states (featuring non-topological zero-bias peaks and possible accidental gap closure / reopening);

[0059] 3. In a finite-size system (e.g., a Coulomb blockade system), trivial gap closure without proper re-opening occurs, in which the finite-size gap closes with a small magnetic field, causing oscillations in a low-energy state (a characteristic of pseudogap closure / re-opening); and

[0060] 4. A trivial, accidental closure-like feature (pseudogap closure / reopening feature) caused by a set of discrete states crossing zero energy.

[0061] The way this method reduces such false positives is by using data collected over a wide range of parameter values. Accidental or fine-tuned points should not persist during changes in parameter values, as they do in the topological phase. Furthermore, since both of the above criteria should be validated, this method correlates different indicators of the topological phase; that is, zero-bias conductance peaks must be present at both ends simultaneously, and the system must exhibit gap closure and re-opening characteristics in non-local conductance. Considering these criteria, the above false positives can be correctly identified for the following reasons:

[0062] 1. False positives 1 and 2 in the above enumeration lack the gap closure / re-opening characteristics in nonlocal conductance; and

[0063] 2. False positives 3 and 4 lack correlated, stable zero-bias peaks at both ends of the semiconductor wire.

[0064] The simultaneous occurrence of different types of false positives is not expected to be stable with respect to variations across the parameter space.

[0065] The remaining concern of this method is preventing false negatives, which will be discussed further below. In particular, specially constructed examples combining features 1 and 4 with the false positive region will be discussed, along with examples for strongly disordered systems. Disorder may lead to zero bias peaks, but generally does not result in an expansion of the correlated ZBP region. Similar stability requirements eliminate potential false positives 3 in the above enumeration.

[0066] This method is derived from the following principles:

[0067] 1. This method must ensure that it can verify both of the above criteria.

[0068] 2. For the following reasons, it is required to measure as wide a range of the device's parameter space as possible:

[0069] a. There may be high initial uncertainty regarding the existence and location of topological phases.

[0070] b. Checking the stability of zero-bias peaks in the parameter space helps to rule out potential false positives.

[0071] c. Reduce unnecessary selection bias.

[0072] 3. This method should be completed within a reasonable timeframe (a few days at most) and should require minimal human decision-making during its implementation.

[0073] 4. Bias-dependent nonlocal conductance measurements in DC are currently slow. Therefore, these can be replaced with either nonlocal RF measurements or nonlocal DC measurements at or near zero bias to determine the existence of a gap.

[0074] 5. For a given implementation of this method, especially in the case of a large parameter space, the measurement sequence should be predetermined and of finite length to prevent open-ended searches, which can be time-consuming and introduce selection bias. It is still possible to improve the measurement sequence over time, for example, by applying lessons learned from previous implementations.

[0075] 6. For a given execution of this method, the data analysis procedure should be determined before the data is collected and examined, and should have predetermined outputs to avoid overfitting and confirmation bias and to ensure that the method produces results. It is still possible to improve the data analysis code over time, for example, by using improved algorithms and applying lessons learned from previous executions.

[0076] Considering the above considerations, Figure 6 shows an embodiment of an exemplary method 56 for evaluating semiconductor-superconductor heterojunctions for use in qubit registers of a topological quantum computer. Method 56 includes a mapping phase 58 and a refinement phase 60. In some examples, the mapping and refinement phases may be performed separately, for example, to evaluate a new experimental setup or implementation change.

[0077] The mapping phase 58 and the refinement phase 60 each include measurements and subsequent analysis. The mapping phase includes a high-speed RF measurement 62 of the normal-superconductor (NS) junction admittance to provide mapping data. In other examples, the measurement may be a DC measurement. The quantities measured include local conductance at each end of the semiconductor wire across a broad parameter space in bias, field, plunger, and left / right cutter gate voltages. In some examples, the mapping data may also include non-local conductance data. In some examples, the “mapping data” from the measurement 62 includes RF signal-to-field and two 5D datasets of left cutter, right cutter, plunger, and left or right bias. Next, the related data analysis 64 searches for extended regions in the parameter space where correlated ZBPs exist. In some examples, the output of the analysis 64 includes a list of “promising” regions in the 4D parameter space (field, left cutter, right cutter, plunger), which are ranked by the likelihood of a full topological phase with a finite topological gap existing within that region.

[0078] Each promising region identified in this way is then iteratively investigated further in refinement phase 60. The refinement phase includes slower sub-RF measurements 66 of the full conductance matrix within each promising region, including local and non-local conductances, using a lock-in amplifier. In other examples, more detailed measurements may be RF measurements. In some examples, the "refined data" from measurements 66 includes the full conductance matrix for each promising region as a function of bias. Relevant data analysis 68 of the full conductance matrix, particularly non-local conductances, provides information about the behavior of the bulk gap to identify regions as topological according to the above criteria. It is also possible to quantitatively evaluate the size of the gap within each topological region. In some examples, analysis 68 includes determining the boundary of the topological phase (or absence of a topological phase) within each measured region based on a joint analysis of local and non-local conductances. Furthermore, the value of the topological gap (if any) is determined for each region. In refinement phase 60, measurements over a promising region may be repeated with adjusted range and resolution, for example, only under appropriate but not infinite conditions. Therefore, refinement phase 60 may include a tightly controlled feedback loop that adjusts the bias range and / or resolution in the parameter space. The feedback loop may include, for example, up to two iterations.

[0079] Upon completion of refinement phase 60, a region possessing optimal topological characteristics is identified. This region may be defined, for example, by a combination of a large gap and high reliability of the topological characteristics. To further enhance reliability, an additional validation phase 70 may be optionally performed, in which case the stability of the optimal region is subjected to additional testing. In some examples, validation phase 70 includes validating the ZBP in the region identified in refinement phase 60 by checking the stability of the ZBP against variations in cutter gate voltage. Such variations can be of any desired magnitude, including large variations. Furthermore, in examples where the semiconductor-superconductor heterojunction is one of a series of analogously prepared semiconductor-superconductor heterojunctions, the validation phase may include a meta-analysis of ZBP data across that series. The meta-analysis may be performed to calculate the probability of finding a topological region in other analogously prepared semiconductor-superconductor heterojunctions.

[0080] As shown previously, the measurements in method 56 are performed on a three-terminal device, as shown in FIG. 5. Some of the constraints regarding the device to be measured will be described here while referring to the drawings. The device 48 in FIG. 5 includes a semiconductor wire 72, which is typically a nanowire and, in some examples, includes a gate region of a two-dimensional semiconductor. In some implementations, the semiconductor wire may include a selectively area grown (SAG) nanowire. In device 48, the semiconductor nanowire 72 is in proximity to a superconductor 74. The superconductor extends away from the hybrid wire. FIG. 5 shows a representative position of the MZM 75 in a scenario where device 48 is operating in a topological regime. The "T" shape of the superconductor is not necessarily required, and the width of the vertical superconducting section can extend over the entire length L of the device. The vertical contacts 54R and 54L contact the semiconductor wire at each end of the device. The contact 52 is coupled to the superconductor 74 to form a device having three terminals suitable for electrical transport measurements. The entire device is covered with a dielectric layer (not shown). The electrostatic cutter gates 76R and 76L are used to form tunnel barriers at each end of the semiconductor wire 72. The electrostatic plunger gate 78 tunes the chemical potential inside the device.

[0081] In the illustrated example, the important dimensions include the following:

[0082] L: The maximum length of the topological region

[0083] L S : The length of the superconducting segment connecting the topological region to the lead-grounded superconductor 74

[0084] W: The width W (more generally, the cross-section) of the semiconductor wire 72

[0085] L C : The distance between the cutter gate 76 and the superconductor 74

[0086] W C : The width of each cutter gate 76

[0087] L N : The space between each cutter gate 76 and the associated vertical lead 54.

[0088] The distance from the semiconductor wire 72 to the plunger gate 78 can also be important for the lever arm and the potential profile within the semiconductor wire, depending on the dielectric material used. Another variable is the geometry of the plunger gate 78 relative to the semiconductor wire (wrapped gate vs. side gate). If the plunger gate wraps around the semiconductor (wrapped gate), the lever arm becomes larger, which allows for a greater variation in the chemical potential inside the semiconductor wire. Subsequently, if the coupling of the plunger gate to the semiconductor wire is too strong, even small voltage noise on the plunger gate will have a greater effect, potentially artificially widening the chemical potential inside the semiconductor wire 72.

[0089] One of the most important parameters is the length L of the proximity-enhanced semiconductor wire. Here, two effects compete with each other. On the one hand, the semiconductor wire needs to be long enough to avoid finite-size effects and to clearly define the signature of the topological phase transition and correlated ZBP. On the other hand, longer wires increase the practical difficulty of growing or fabricating the working device and can reduce nonlocal signals. In particular, as the length of the semiconductor wire increases, it becomes difficult to ensure sufficient uniformity of the semiconductor wire and to eliminate strong defects (such as poor contact with the superconductor that suppress proximity effects). There is currently little data available for devices longer than 2 μm. From a theoretical standpoint, 5ξ (where ξ is the topological coherence length) represents the minimum length scale at which finite-size effects are sufficiently suppressed. Even in the case of clean wires, nonlocal signals will be suppressed as the length of the semiconductor wire increases. The above problems lead to an upper limit at L that depends on the device quality for successful extraction of nonlocal information.

[0090] Length L SThe value is selected to suppress leakage to the central lead of the quasiparticle. The actual estimate is L S >10ξ s And here, ξ s This is the coherence length of the superconductor 74 (ξ relative to disordered Al). s (=200nm). In a typical experiment, L S This can reach a scale of millimeters, and therefore exceed the minimum value by several orders of magnitude.

[0091] Experimental evidence shows that the distance L to cutter gate 76 C However, this indicates that the wavelength must be well below 100 nm to avoid spurious edge conditions and enable high-resolution tunneling spectroscopy. C The optimal selection and cutter gate design may be determined by combining simulations from electrostatics, realistic transport, and manufacturing capabilities. As a placeholder, requirement L C <40nm may be used. Cutter width W c It should be noted that cutter designs can vary regarding the distance between the cutter and the vertical lead. In the case of InSb wires, these wires are normally-off, and the cutter must also open this segment of the wire, so a reduced space between the cutter and the vertical lead may be desirable.

[0092] It should be noted that the wire width W parameter is not necessarily important for the feasibility of the disclosed method, but it does affect the likelihood of obtaining positive results from the method. For example, the width controls the number of channels, and numerical simulations show that fewer channels are beneficial for reaching the topological phase.

[0093] Table 1 summarizes current estimates of various requirements for the device geometry for the materials currently in use, and shows estimated material-specific requirements for the device dimensions. For these values, the following estimates for coherence length at the point of maximum gap were used: ξ(InSb / Al)=400nm, ξ(InAs / Al)=300nm, and ξs=200nm. [Table 1]

[0094] Appropriate material selection is necessary to obtain a system with a sufficiently large topological gap. However, Method 56 is independent of semiconductor wire material. Although material stacks are still under investigation (both theoretically and experimentally), current results indicate that InAs with a barrier material and InSb without a barrier are promising choices for obtaining a topological gap within a suitable energy range. In some examples, topological gaps in the range of 25 to 200 μeV may be suitable for supporting the operation of a topological quantum computer. Narrower and wider ranges are also conceivable.

[0095] The current choice of superconductor is aluminum because it generates a hard induced gap in heterostructures that do not have subgap states at zero magnetic field. Again, this method is largely independent of the superconductor choice, as long as the measurement parameters are adapted accordingly, for example, by extending the bias scanning range for larger gap superconductors, or by adjusting the device dimensions based on the values ​​shown in Table 1.

[0096] The choice of dielectric material largely depends on the material stack used. Hybrid systems impose limitations on the temperature to which a given material stack can be exposed. The maximum gate voltage (breakdown voltage) that can be applied to the electrostatic gate before the dielectric material breaks down is V. break) is a critical material quantity, which is preferably known for a given dielectric layer and SAG material system, as it sets fundamental limits on device operation. The breakdown voltage can be measured on the test device or determined by standard electrical characterization (SEC) measurements. A realistic V is available if experimentally feasible. break To enable measurement, it is recommended to manufacture an identical device to the device under test in a nearby location on the same chip.

[0097] Returning to Figure 6, before the device undergoes detailed measurements, it may be qualified to determine that it meets a set of criteria. Thus, Method 56 includes an initial qualification phase 80. The initial qualification phase may include preliminary assessments of conductance, tunneling spectroscopy, and time stability, as described below.

[0098] Regarding the device's conductance, the resistance passing through the device is determined by the high bias voltage V. bias,high If measured with >2Δ and <25kΩ between all three terminals, the device is considered to conduct, where Δ is the superconducting gap. For InSb-based devices, this may require opening the channel first by applying a positive voltage to the cutter gate. With regard to gate pinch-off, all gate resistances should be >500MΩ relative to ground. All gates used to form the tunnel barrier (cutter) must pinch off the device individually. To test gate pinch-off, the conductance between the superconducting terminal and the corresponding normal-conducting terminal is measured as a function of the cutter gate voltage at high bias. Conductance <0.005e 2The device is considered pinched off when it reaches / h. The plunger gate used to tune the chemical potential in the topological segment should be capable of tuning the conductance through the device to some extent. The effect of the plunger gate can be most easily tested in a tunneling regime using tunneling spectroscopy, as further described below. Hysteresis in both cutter gates and plunger gates may be acceptable, as all measurements can be performed in the same sweep direction. However, after a hysteresis loop on either gate, it is required that the state in gate space does not shift measurably, as described below.

[0099] Regarding tunneling spectroscopy, the cutter gate has a high bias conductance of 0.1e. 2 When tuned to a regime of approximately / h, conductance as a function of bias and gate voltage (either plunger or tunnel gate) is measured at zero magnetic field. The differential conductance versus bias peak should be clearly identifiable at the bias near the expected inductive superconducting gap and should not change position with small gate voltage changes (given that high-bias conductance does not change significantly). At zero magnetic field and below the superconducting gap, the number of finite conductance features should be low to reduce the probability of false positives. Ideally, the zero-field conductance trace should lack discrete subgap state features. This can be quantified by requiring that the average subgap conductance is less than 1 / 4 of the high-bias conductance.

[0100] Regarding time stability, high bias conductance should be stable in a tunneling regime. This is because the conductance Δg ~ 0.2e on a timescale of t = 10 minutes. 2This means that it should not jump or drift beyond / h. Regarding the RF response, the resonance used for high-speed RF measurements should be identified for a particular device by comparing, for example, the resonance in the open state versus the pinch-tiofrezim. For all terminals requiring high-speed measurement, a clear response of one resonance should be visible as a function of the corresponding tunnel gate. Effective impedance matching is necessary to obtain optimal sensitivity to changes in conductance. Typical device resistance is

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[0101] Briefly returning to Figure 6, the measurement 62 in mapping phase 58 may include benchmarking for electrical noise and energy broadening. This step is useful because the energy broadening due to the measurement setup provides a lower limit for the detectable topological gap. To allow the broadening due to electrical noise to be negligible, the integrated voltage noise RMS amplitude between 1 Hz and 500 Hz should be less than 3 μV.

[0102] Figure 7 shows an exemplary measurement setup for RF reflectance measurement. In RF reflectance measurement, the sample is coupled to the transmission line via a resonator. The sample resistance changes the impedance matching of the resonator to the transmission line, thereby changing the reflectance coefficient of the RF signal sent to that line. Each of the two normal-conducting leads of the device is coupled to a resonator for RF reflectance measurement, with resonant frequencies fl, res and f for the left and right sides, respectively. r,resThe frequency difference between these resonators on the left and right should be greater than the linewidth of each resonator. An intermediate frequency (IF) source generates RF pulses within the frequency bandwidth of the readout system. These pulses are upconverted to the frequency range of the resonators coupled to the device. For this purpose, a mixer with high (>30dB) carrier suppression mixes the IF signal with the local oscillator (LO) signal. The LO frequency is the frequency of the acquired system f ADC The bandwidth and both resonator frequencies f l,res and f r,res The frequency difference between them must be bridged.

[0103] If the RF source does not have separate I and Q outputs, one of the upconverted sidebands must be filtered out. This is because f LO >maximum f l,res ,f r,res Select cutoff frequency = f LO A low-pass filter can be implemented by placing it between the upconversion mixer and the input port of the fridge. After the signal is reflected from the sample, it passes through a low-noise amplifier. It is then downconverted in the mixer using the original LO signal, low-pass filtered to the bandwidth of the acquisition system, and sent to the input of the acquisition system.

[0104] To measure local conductance in RF reflectance measurements, the reflected RF signal value must be calibrated against the directly measured differential conductance, for example, using a low-frequency lock-in amplifier. Since this is a sample-dependent procedure that can be performed in parallel with the actual measurement, it will be described below along with the measurement operation.

[0105] To benefit from high acquisition speeds, gate and bias voltage scanning on the device is hardware-triggered, minimizing the time spent on software communication (typically around 10ms). This can be done with hardware-triggered two-dimensional scanning synchronized with the acquisition system. One voltage is ramped with a saw-tooth function and sampled N times between each ramp, while a second voltage is slower during M cycles of the faster ramp, resulting in an N×M point scan. To match the DC values ​​of the voltages applied to the contacts and gate, these voltage scans are applied to a low-pass filtered DC line. The fastest ramp speed must be lower than the cutoff frequency of the low-pass filter on the fridge line, typically 1kHz. Due to the fast acquisition speed in sub-RF / DC measurements, it is possible to measure a narrow bias range close to zero bias, or to measure the second and third harmonics of the signal in 2-ohm / 3-ohm settings, for example, using a lock-in amplifier. In this way, bias scanning is replaced only with the target information regarding the presence of zero bias peaks and / or gaps within the device bulk.

[0106] Details of Mapping Phase 58 Figure 8 shows an additional embodiment of measuring radio frequency (RF) junction admittance of a semiconductor-superconductor heterojunction to acquire mapping data. Method 62A in Figure 8 shows a rapid measurement of local conductance by RF reflectance measurement, which is performed to satisfy the first of the two topological gap criteria specified above, in order to enable rapid characterization of the device and identification of candidate topological regions based on ZBP correlation. Identification of these regions sets the stage for non-local measurements in refinement phase 60. Rapid local measurements of three-terminal devices are closely related to rapid measurements of conventional NS junctions.

[0107] In step 82 of Method 62A, the magnetic field is set to 0T. In step 84, the reflected RF signal is measured for each side of the three-terminal device with a large bias voltage (e.g., 1mV) as a function of frequency around the estimated resonant frequency (100MHz on each side), and with the corresponding cutter voltage from the open-channel setpoint (i.e., typically 0V for InAs and 1V for InSb) up to 100mV beyond the full pinch-off voltage. Resonant frequency f res This refers to the cutter gate voltage and the cutter voltage V tunn,res Identified as a function of the frequency with the sharpest change in the signal, where the dip in the reflected signal, as a function of frequency, has the smallest absolute value.

[0108] In 86, the frequency is f res The cutter voltage range V is identified as such and satisfies the following three conditions. c,min From V c,max The decision is made:

[0109] a. The range is hysteresis-free, as can be measured by the reproducibility of the measurements after the hysteresis loop.

[0110] b. Local conductance measured well above the superconducting gap (e.g., 1 mV for Al) is 0.05e 2 / h and 0.2e 2 It is within the / h period.

[0111] c. The nonlocal conductance signal measured with standard low-frequency lock-in amplifier techniques exceeds the noise level.

[0112] In the case of significant electrostatic crosstalk between the plunger and the cutter (geometric and material-specific), this step may be repeated for different values ​​of the plunger-gate voltage.

[0113] In step 88, the RF readout power is optimized. In some examples, this operation involves finding a region in the cutter space that exhibits a clear gap with a well-defined coherence peak. For this purpose, the RF readout power on each side is scanned and measured in 1 dB steps from -80 dBm to -130 dBm at the sample (bottom of the fridge). For each RF power, a fast scan of the bias voltage is performed on each side from -1.5Δ0 to 1.5Δ0 (Δ0 is the gap of the parent superconductor that gives a bias range of -350 μV to 350 μV for Al) with a maximum step size of 5 μV to measure the reflected RF signal. For each side, the maximum RF power that does not broaden the features in the measurement, e.g., the coherence peak, is found and set as the operating RF power.

[0114] At 90, the magnetic field angle is calibrated to be parallel to the semiconductor wire. For this purpose, the magnetic field is set to a value such that the superconducting gap is not closed for a magnetic field parallel to the semiconductor wire, but its size is significantly reduced for a magnetic field perpendicular to the semiconductor wire, for example, 500 mT for InAs and InSb SAGs. The magnetic field angle is scanned near the expected value from the wire geometry, and for each value of the angle, the bias on one side of the device is scanned from -1.5Δ0 to +1.5Δ0 (-350 μV to +350 μV for Al) with a maximum step size of 5 μV. Next, the reflected RF signal is measured. The magnetic field angle is set to the angle at which the maximum gap is obtained. The goal here is to obtain a alignment accuracy better than 2° in both the azimuthal and polar angles.

[0115] At point 92, the maximum magnetic field B occurs when the superconductor bulk gap closes. max This is determined. At 94, the magnetic field is set from 0T to B in 100mT steps to perform RF-DC calibration. max The scan continues until the end. For each field value, the following additional calibrations are performed:

[0116] In step 96, the optimal RF readout frequency is measured. This can be done as a repetition of step 84. However, once the readout frequency is identified, a quicker method can be followed. In one example, the cutter gate voltage is V c,res The setting is configured such that the dip in the reflected RF signal as a function of frequency has its minimum absolute value at zero magnetic field. The reflected RF signal is measured as a function of RF frequency from 50 MHz to each side of the resonant frequency found for the most recent magnetic field value. The dip with the magnitude of the RF signal closest to the previously found dip is found and set as the RF readout frequency. The results of this measurement may be stored in a database.

[0117] At 98, the RF-DC calibration curve is measured. On both sides, the bias voltage is set to a high bias (e.g., 1mV for Al) so that it is above the superconducting gap. Each cutter gate voltage is scanned from the open-channel setpoint (i.e., typically 0V for InAs and 1V for InSb) past the pinch-off voltage up to 100mV. For each cutter voltage, the local conductance is measured at the lock-in amplifier on each side, as well as the reflected RF signal. The results of this measurement are later stored in a database to establish a calibration function between the reflected RF signal and the conductance.

[0118] At 100, the magnetic field is set back to 0T. At 102, the magnetic field is changed from 0T to B in steps of ΔB. max The ramp is performed up to this point. The magnetic field step ΔB is dependent on the g factor and is such that the state moving with the magnetic field can be tracked. A reasonable range for InAs or InSb SAG is 10mT ≤ ΔB ≤ 50mT. For each value of the magnetic field, the following additional steps are performed.

[0119] At 104, the cutter gate potential is N c = V in 15 steps c,min From V c,max Each side is scanned independently up to a total of 2N cThe configuration is obtained. Such independent scanning is justified for local conductance measurements when the range of the lever arm and cutter gate scanning for cutter-plunger crosstalk is small enough that it does not cause the effective plunger voltage to change the size of the plunger voltage step too much. For each cutter gate configuration, the following measurement is performed: Voltage limit V c,min and V c,max This is determined in 86.

[0120] In 106, high-speed scanning of the plunger voltage and bias voltage on each side is performed. The plunger voltage is V p,max From V p,min It is scanned up to this point. The plunger boundary is material-specific, and the upper and lower breakdown voltages (breakdown voltage V) break The range is limited by the (stopping at 80%) and the possible range of the region of interest. The latter ranges from a completely gapless regime to complete depletion and requires theoretical input. The resolution of the plunger scan must be sufficient to resolve individual subgap states across the gap (depending on the lever arm). For each value of the plunger gate, the bias voltage at its terminal is scanned with a resolution of 5 μV or less, from -1.5Δ0 to +1.5Δ0 (-350 μV to +350 μV for Al). The reflected RF signal is measured as a function of the plunger and bias voltage. The resulting two-dimensional scan is stored in a database. In other examples, the RF can be replaced with DC measurements over a narrow bias range close to zero bias.

[0121] The mapping data generated as the output of Method 62A includes the following:

[0122] 1. A calibration dataset consisting of two 2D cutter field scans, one on the left and one on the right. For each point in this scan, three parameters are measured: the in-phase component, the out-of-phase component, and the conductance on each side.

[0123] 2. This is a measurement dataset including two 5D fields, a left cutter, a right cutter, a plunger, and bias scans, where the bias scans are performed on the left and right. For each point in these scans, two parameters are measured: the RF in-phase component and the RF out-of-phase component.

[0124] The goal of data analysis at this stage is to identify promising regions in the parameter space that may contain a complete topological phase. Figure 9 shows an additional aspect of finding one or more regions in the parameter space that coincide with a complete topological phase of a semiconductor-superconductor heterojunction through analysis of mapping data.

[0125] In step 108 of Method 64A, the RF signal input is converted to conductance using a calibration dataset to define the transfer function. In step 110, each point in the (field, plunger, cutter) parameter space is taken from the bias trace measured at that point, and the local conductance G of the respective left and right terminals is taken from that point. ll , G rr The input is used to classify the result as (potentially) topological or trivial. For example, the classification may check for the presence of ZBP in both conductance traces.

[0126] The analysis of the mapping data involves density-based clustering of bilateral ZBP data obtained from either RF or sub-RF measurements. In 112, clusters of points classified as topological are found, and clusters whose volume or shape in parameter space is considered incompatible with the topological phase are filtered out. In some examples, the cluster volume must be greater than 0.03 V × T in the plunger voltage-magnetic field space. Clusters that survive the filtering are promising regions for the presence of the topological phase. In some examples, this step may be implemented using density-based clustering for any 2D plunger field scan, excluding regions extending into zero magnetic field. In 114, promising regions are ranked by their likelihood of containing the topological phase. In some examples, the ranking score is determined by the average plunger gate voltage of each cluster, with priority associated with more negative gate voltages.

[0127] Figure 10 illustrates an aspect of the analysis of mapping data by Method 64A. This analysis is illustrated and validated using a simulated dataset of InSb / Al nanowires with length L=3μm and mean free path of 3μm. As a function of plunger gate (in V units) and magnetic field (in T units), the figure shows from left to right: a binary array with a topological index Q calculated from the scattering matrix; a cluster color corresponding to the ZBP present on both sides of the device, where 1 corresponds; and clustered ZBP Boolean data with cluster colors corresponding to the score of the corresponding clusters (smaller values ​​correspond to better results). Using such data, it is possible to find regions containing true topological regions for further analysis.

[0128] The results of the data analysis performed in the mapping phase 58 of Method 56 determine the measurements to be performed in the subsequent refinement phase 60. For each promising region in the ranking above, the range of field, plunger, and cutter values ​​surrounding that region is specified as input for the refinement phase. In some examples, the refinement phase may be performed on various identified regions in the order of ranking. To minimize the impact of gate drift, gate jump, and other issues that may occur while the device is idle, the latency between the end of measurements in the mapping phase and the start of measurements in the refinement phase must be minimized. For this reason, it is important to perform the data analysis outlined above in a time-efficient manner. Note that the raw data generated in the RF measurement phase can be very large: existing RF datasets of this type can exceed 100GB in total size and take several hours to reduce and analyze.

[0129] Details of refinement phase 60 A refinement phase is performed to investigate promising areas in more detail. Depending on the implementation, the refinement phase may be performed using either RF or DC / sub-RF measurements. In one example, the differential conductance of the device being evaluated can be measured using a standard low-frequency lock-in amplifier technique, as shown in Figure 11. The total conductance matrix is ​​obtained by two different AC excitation frequencies f l and f r Then, the DC bias voltage V is applied at the left and right terminals 54 respectively. bias,l / r and AC voltage δV l / r These frequencies are measured by applying a voltage. These frequencies must be lower than the cutoff value of the low-pass filter in the system and low enough to minimize the effects of parasitic capacitance. To ensure this, the phase shift of the current relative to the voltage excitation must be less than 10°. Common-mode AC current δI flowing to the left or right. l / rThe measurement is taken with the central superconducting lead grounded. To suppress spurious voltage divider effects, the connection to ground must have a low ohm resistance (i.e., typically less than a few kΩ) compared to the resistance of the other two lines. To achieve this, a low-pass filter may be designed as appropriate, or the superconducting lead may be grounded at the PCB level (cold ground).

[0130] This three-terminal setup allows us to measure all four elements of the conductance matrix G between the left (l) terminal and the right (r) terminal:

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[0131] Element G of the conductance matrix ll =dI l / dV l and G rr =dI r / dV r This is called "local conductance," and element G lr =dI l / dV r and G rl =dI l / dV r This is called "nonlocal conductance".

[0132] The input for the refinement measurement 66 includes regions in space (cutter gate, plunger gate, field) that are candidates for further investigation. In some examples, the size of the regions in the plunger gate / field space is increased by only 20% to ensure that the refinement measurement fully captures the topological phase transitions surrounding each region.

[0133] Figure 12 illustrates an additional embodiment for obtaining refined data by measuring the sub-RF conductance of a semiconductor-superconductor heterojunction in each of one or more mapped regions of the parameter space. In particular, Method 66A describes local and non-local conductance measurements suitable for extracting the energy gap of a semiconductor-superconductor heterojunction.

[0134] In step 116 of Method 66A, the magnetic field is set to the minimum field value in the candidate region. This magnetic field must be low enough that the induced gap remains open, for the purpose of observing whether it is closed in the candidate region. In step 118, the cutter gate is set, for example, to the median value within the candidate region. In step 120, V L and V R A correction is applied to the small bias voltage offset (see Figure 11) to ensure that the extraction of the antisymmetric components of the local and non-local signals is straightforward. L -V R Total absolute current in parameter space (|I L |+|I R This can be achieved by finding the minimum value of |). At 122, the magnetic field is ramped within the candidate region in steps of ΔB. For each value of the magnetic field, a bias plunger scan is performed as described immediately below.

[0135] In 124, the plunger voltage is the maximum plunger voltage (V) in the region being searched. p,max The plunger voltage is set to ΔV. p In step V max The minimum plunger voltage V in the region searched from p,min The scan continues until the specified value. In other examples, the plunger voltage may be scanned in the opposite direction. For each plunger voltage value, the bias voltage of the left terminal is scanned in 5 μV steps from -50 μV to +50 μV. If the data indicates that the topological gap is outside this window, the scan is then repeated with a larger window size. The resulting two-dimensional scan is stored in the database.

[0136] The refined data generated by slower total conductance matrix measurements is a dataset per candidate region. Each dataset consists of two 3D field-plunger-bias scans, where the bias is scanned separately on the left and right sides. At each scan point, two parameters are measured: the conductance on the left side and the conductance on the right side. In some examples, the dimensionality of the dataset can be increased to include, for example, a scan of the cutter voltage. In some examples, each conductance may include the total conductance matrix on the corresponding side of the device.

[0137] Figure 13 shows an additional embodiment in which, by analysis of refined data, the boundary of the complete topological phase in the parameter space and the topological gap of the semiconductor-superconductor heterojunction are found for at least one of the one or more regions of the parameter space investigated in Method 66A. In some examples, the illustrated method is performed iteratively for each promising region.

[0138] In step 126 of Method 68A, step 110 of Method 64A is repeated to verify that the measured region is still promising and to refine the boundaries of the potentially candidate topological region. At this point, the analysis of the refined data includes verifying gap closure at the boundaries of each of one or more regions in the parameter space. In step 128, a check is performed to determine which parts of the boundary of the promising region are gap-free based on the nonlocal conductance signal. In step 130, the gap Δ for each point i in region j is determined. (j) The size is extracted by thresholding the nonlocal conductance. In 132, a score is assigned to the region based on the extent of the gapless boundary and the value of the gap within the candidate topological region. The score reflects the likelihood that the promising region is indeed topological and has gaps. In some examples, the score S is S i =X·Median i (Δ (j)Defined by ). In 134, the maximum gap within each topological domain is obtained along with an estimate of the error. In some examples, the error bars are determined by the uncertainty in the thresholding of the nonlocal conductance at the point of the maximum gap. This score is one of the possible scores in which the median gap is replaced by the maximum value, as an example of an alternative score.

[0139] The output of this analysis includes a set of probabilities corresponding to the regions identified in mapping phase 58 of Method 56, i.e., the probabilities of hosting a complete topological phase. Associated with each probability is the maximum (topological) gap inside each (non-trivial) region. Figure 14 shows an aspect of the analysis of refined data according to Method 68A, using the same simulation as in Figure 10. From left to right: gaps extracted from non-local data; ZBP cluster scores defined as the product of the mean gap within a region and the percentage of gapless boundaries; the ZBP cluster scores are the same as in the middle figure, but the mean gap is replaced with the median of the gaps within the region. The maximum gap within a region is 175 μeV. Thus, the output of the entire Method 56 is an estimate of the topological gap value and its location in the explored parameter space for each promising region.

[0140] Detailed examples of false positives and false negatives One potential problem with quasi-majorana regimes is that they can arise as precursors to true topological regimes. This means that a topological region may be directly adjacent (in the parameter space) to a non-topological quasi-majorana regime. In this case, the current algorithm for clustering regions of correlated ZBPs may identify regions that are too large in the mapping phase. In other words, the identified region may extend much further, containing some of the quasi-majorana regimes, while also containing a topological region. In this case, the current analysis in the elaboration phase is set to fail by identifying too much of the parameter space as topological, or by failing to recognize the topological region due to the lack of gap closure / reopening in the quasi-majorana regimes.

[0141] The solution to this problem involves implementing a different clustering algorithm in the elaboration phase to identify lines of gap closure / reopen features in the parameter space (particularly the field-plunger space), and then determining the intersections of these lines with the correlated ZBP regions to find the topological phase. It should be noted that this is primarily a data analysis problem in the elaboration phase. The mapping phase is still suitable for identifying promising regions of data that will be examined in more detail in the elaboration phase.

[0142] Unstable behavior in data analysis may be due to data cutting relative to a fixed cutter voltage. Stability can be improved by using one or both cutter gate potentials as additional dimensions in refined data analysis.68 This will improve clustering and allow for better use of available datasets.

[0143] The following example deals with smooth potentials at the ends of semiconductor wires, associated with quasi-Majorana and false negatives. The presence of long-range heterogeneity (smooth potential fluctuations) makes it more difficult to observe gap closure / reopening features, resulting in false negatives. Interestingly, smooth potential fluctuations are also the regime in which quasi-Majorana modes are expected. Here, we discuss the interaction between the two effects.

[0144] A typical scenario in which quasi-Majorana modes emerge is when the system is tuned outward, but near the topological phase. Specifically, consider an example where the chemical potential μ is smaller than the critical chemical potential μc required to enter the topological phase at a fixed magnetic field. A smooth potential fluctuation can be interpreted as a spatially varying chemical potential μ(x) = μ0V(x), where V(x) is the potential. In the above scenario, as shown in Figure 15, a potential dip near the (right-hand) end of the semiconductor wire makes it possible to locally tune the system to the topological regime μ(x) > μc, which results in a local pair of Majorana modes. The latter appears as a topological phase transition in the bulk of the semiconductor wire at the local conductance of the right end at a much lower magnetic field (this can be read via the local conductance of the other (left) end, where no smooth potential fluctuation exists).

[0145] Figure 15 shows the effect of a smooth potential at the right end of a 1D model semiconductor wire. The left panel shows the spatial dependence of the potential (lower panel) and position of the superconducting shell implemented via the self-energy of the semiconductor wire (orange, upper panel). The right panel shows the conductance matrix including the antisymmetric portion of the nonlocal conductance. Note that the nonlocal conductance lacks gap re-opening features. The only feature of the phase transition is the onset of weak Majorana oscillations.

[0146] Specifically, in the example in Figure 15, the phase transition at a fixed chemical potential is BC ≈ 2.7T. The ZBP due to the quasi-Majorana mode appearing around B ≈ 1T would be correctly labeled as non-topological in Method 56 because the nonlocal conductance lacks gap closure and re-opening features. However, even in the topological phase transition, gap closure / re-opening features are not visible. The reason for this is that the part of the system below the smooth potential on the right has already undergone a phase transition, and therefore B is B C This is because a gap is created when crossing the gap. This suppresses the bulk mode signal in the phase transition, as the bulk mode is only transiently coupled to the right lead. Note that in this particular model, the topological gap is 100 μeV, which is therefore larger than expected in realistic systems. For smaller gaps, nonlocal signals become larger, and therefore the intensity of gap closure / reopening features increases. Nevertheless, since signals for finite-size oscillations also become stronger, observing gap closure / reopening may still remain difficult.

[0147] In conclusion, quasi-Majorana modes at the ends of semiconductor wires do not result in false positive characteristics in nonlocal conductance, but the presence of quasi-Majorana modes increases the chance of false negatives when the system is tuned in the topological phase.

[0148] The second example deals with a smooth potential at the center of a semiconductor wire, associated with false positives. Here we discuss the only example where the system bulk is non-topological, but it can be identified that it can have ZBPs at both ends of the semiconductor wire and non-trivial features of nonlocal conductance that can be interpreted as gap closure (and potentially re-opening).

[0149] This setup is shown in Figure 16. The bulk of the semiconductor wire is tuned to be non-topological, but a smooth potential bump at the center of the semiconductor wire reaches a topological regime of potential. Thus, we can consider a pair of Majorana zero modes nucleating at the center of the semiconductor wire. The central region is too small for well-separated Majorana modes, but the smoothness of the potential can result in a quasi-Majorana mode that is close to the center of the semiconductor wire but weakly coupled.

[0150] Due to finite-size effects, the corresponding zero modes can be probed as correlated ZBPs in the conductance at each end, as shown in Figure 16. Furthermore, the central low-energy modes overlap with those on both sides and contribute to nonlocal conductance, which can be mistaken for gap closure.

[0151] Figure 16 shows the effect of a smooth potential at the center of a semiconductor wire in a 1D model. The left panel shows the spatial dependence of the potential (lower panel) and position of the superconducting shell implemented via the self-energy of the semiconductor wire (orange, upper panel). The right panel shows the conductance matrix including the antisymmetric portion of the nonlocal conductance. Note that due to finite-size effects, quasi-Majorana modes nucleated in the central region appear as correlated ZBPs and contribute to the nonlocal conductance.

[0152] Figure 17 shows the data analysis across the field / plunger parameter space of the gap method for a 1D model with a potential bump at the center of a semiconductor wire. The left is the detected ZBP. The right is the gap determined from the data. In this case, the ZBP finder detects two overlapping regions: one centered at plunger = 0 (bulk topological region) and another centered at plunger = 0.0025 (central bump topological). It is unclear whether this case represents a false positive (outside the bulk topological region) because a small topological region exists at the center and finite size effects are important. In fact, finite size effects result in gap closure features for each region (central and bulk) in the estimated gap extracted from the data.

[0153] This problematic example demonstrates the value of continued development of the data analysis used in the methods described herein. Note that the ZBP clustering algorithm identifies both regions (central and bulk) as a single region. This example shows that separating non-topological regions adjacent to topological regions can be relatively difficult, and that further refinement may be required in data analysis.

[0154] The third example concerns non-topological ZBPs resulting from strong disorder. An example of a one-dimensional model with strong disorder is shown here. To illustrate, Figure 18 shows a data analysis across the field / plunger parameter space of a strongly disordered one-dimensional model. On the left are correlated ZBP points (red). On the right are the extracted gaps at each point in the parameter space. While ZBPs are present, the data in Figure 18 shows that the regions of correlated ZBPs are sparse and largely disconnected. Therefore, regions of strong disorder can be excluded by the gap method by adding requirements regarding the size and continuity of the identified regions.

[0155] Equipment and additional methods The features and embodiments disclosed herein relate to a method for evaluating semiconductor-superconductor heterojunctions for use in qubit registers of topological quantum computers, but such features and embodiments are also applicable to related instruments. Figure 19 shows an embodiment of exemplary instrument 136 configured to evaluate semiconductor-superconductor heterojunctions for use in qubit registers of topological quantum computers. The instrument includes a controller 18B. The controller includes at least one processor 20B and computer memory 22B operably coupled to the processor. The computer memory is configured to hold instructions 24B that cause the processor to perform various measurement and analysis methods described herein. To this end, the processor may be operably coupled to an RF admittance measurement device 138 and a sub-RF conductance measurement device 140. The RF admittance measurement device may include features as shown in Figure 7, and the sub-RF conductance measurement device may include features as shown in Figure 11. In the illustrated example, the device 136 includes an interface 142 that couples the processor to the measuring device and also provides control signals to the electrostatic gate and magnet 144 of the device 48.

[0156] The features and examples disclosed herein are equally relevant to methods for constructing a topological quantum computer. Figure 20 shows an embodiment of an exemplary method 146 for constructing a topological quantum computer.

[0157] In step 148 of Method 146, a semiconductor-superconductor heterojunction having at least three terminals configured to support an electronic admittance test is fabricated. In step 62, the RF junction admittance of the semiconductor-superconductor heterojunction is measured and mapping data is obtained. In step 64, analysis of the mapping data is used to find one or more regions in the parameter space that coincide with the complete topological phase of the semiconductor-superconductor heterojunction. In step 66, the sub-RF conductance of the semiconductor-superconductor heterojunction is measured in each of the one or more regions in the parameter space and refined data is obtained. In step 68, analysis of the refined data is used to find the boundary of the complete topological phase in the parameter space and the topological gap of the semiconductor-superconductor heterojunction for at least one of the one or more regions in the parameter space. In step 150, the semiconductor-superconductor heterojunction is incorporated into the qubit register of a topological quantum computer if the found boundary and topological gap are within their respective predetermined ranges. In the operation of a topological quantum computer constructed in this manner, one or more values ​​characterizing the boundaries in the parameter space may be used as tuning parameters for addressing semiconductor-superconductor heterojunctions in qubit registers.

[0158] Numerous additions, omissions, and modifications are conceivable, and therefore, no aspect of the above drawings or descriptions should be understood in a limited sense. As described above in the context of Figure 6, ff, the Majorana zero mode, can be found in two phases using a three-terminal device (e.g., device 48 in Figure 5), where the first phase (i.e., mapping phase 58 in Figure 6) is performed in RF, and the second phase (i.e., refinement phase 60) is performed at a lower frequency or DC. Data analysis of the output data from the first phase effectively "transforms" the output of the first phase into an input suitable for the second phase. Final analysis of the output data from the second phase then forms the basis for predicting the existence and extent of topological regions useful for topological quantum computing. However, in other examples, discrete and full phases of RF and DC measurements and corresponding discrete and full phases of data analysis may not always be necessary.

[0159] An example of a hypothetical deformation is shown in Figure 21, which illustrates an exemplary method 56' for evaluating a semiconductor-superconductor heterojunction for use in a qubit register of a topological quantum computer. Method 56' includes a mapping phase 58' and a refinement phase 60'. In 62', mapping data is obtained by measuring the RF admittance and / or sub-RF conductance of the semiconductor-superconductor heterojunction as described herein. In 64', the mapping data is analyzed to find regions of parameter space that coincide with the topological phases. In 66', refinement data is obtained by focusing on any, some, or all of the regions found in 64' and measuring the RF admittance and / or sub-RF conductance of the semiconductor-superconductor heterojunction. In 68', the refinement data is analyzed to find the corresponding topological phase boundaries and topological gaps in each focal region.

[0160] For example, similar (e.g., equivalent) hardware and extraction methods may enable high-speed RF or DC measurements across the entire parameter space of a heterojunction device or a given region thereof, so operationally similar measurements can be performed without separation into discrete and complete phases. In this case, the data analysis of the second measurement phase (68 in Figure 6) described above may be applied to a single measurement phase. The advantage of this variation may be either speed (when RF techniques are used) or completeness (when sub-RF or DC measurements are applied across the entire parameter space or a given region thereof). If only a small bias window close to zero bias is measured with sub-RF techniques, or if the second and third harmonics of the signal are measured (see above), another advantage may be a combination of speed and additional information.

[0161] In some examples, the two-stage protocol may still be performed in first and second phases, but both phases may be either RF or DC. Here, the second phase may be a high-resolution scan of a sub-region revealed in the first phase. The data analysis performed on the results of each phase may be similar to the data analysis from the second phase (68 in Figure 6), and the output region defined by the analysis of the first phase serves as the input region for the measurement of the second phase.

[0162] In some cases, real-time analysis of data from the first phase of measurement may trigger an abrupt transition to the second phase of measurement when a promising area is identified, rather than waiting for the entire parameter space to be covered before refinement. This variation can reduce the overall evaluation time, especially when the parameter space to be covered is very large and / or when the first phase of measurement is a low-frequency or DC measurement.

[0163] In some examples, a bidirectional transition between first-phase and second-phase measurements may be enabled, such that the data acquisition mode alternates between the two phases. In this way, adaptive measurements of the parameter space are performed, and refinement of the found parameter values, i.e., high-resolution scanning, is performed only when necessary. This method can result in efficient scanning of a large parameter space. In more specific examples, the initial first-phase measurements may be coarse-grained in the magnetic field and gate voltage, but may be refined following intermittent second-phase data analysis to map the region of interest with higher resolution. Similarly, the bias voltage range can be dynamically adjusted to enable bulk gap extraction after initial gap closure is detected.

[0164] In some examples, any of the measurement and analysis sequences considered herein may be performed on a Tetron qubit device having an additional grounding terminal. By grounding the Tetron, it is possible to measure transport through two regions that are simultaneously tuned to a topological regime. In these examples, the tuning of the plunger and cutter gate in the two regions may be performed separately, but the magnetic field may be applied holistically. Here, the loop for the parameters is defined such that the outer loop is the magnetic field loop, enabling simultaneous measurement of the two regions. The data analysis here may be performed as in the approach shown in Figure 13, for example, but success is claimed only if the topological regimes of the two regions overlap in magnetic field values. For such tuned qubit operation, the Tetron qubit may operate in an ungrounded state.

[0165] In examples similar to the Tetron qubit example described above, any of the measurement and analysis sequences considered herein may be performed on a hexon qubit or on a set of many qubits, i.e., Tetron or more. One difference from the Tetron qubit example above is that success may only be claimed if three or more topological regimes overlap in magnetic field values.

[0166] In further modifications of the two examples above, one of the existing (i.e., native) Tetron and / or Hexon terminals may be used as the ground terminal. Here, the current path through the device is used to ground the individual qubits for measurements such as three-terminal measurements. In this modification, any of the measurement and analysis sequences considered herein may be performed in series on different segments within the same qubit, or in parallel across different qubits. Parallel queries of qubits may be used to further define the regions of interest identified by the individual queries. In either method, the ends of one segment are used for installation by opening the cutter gate as wide as possible, and the other segment is measured. For either Tetron or Hexon qubits, such an approach involves running the protocol at least twice over a subset of regions tuned to a topological regime.

[0167] In some scenarios, these additional examples could improve the tuning speed of topological quantum computers and also increase the reliability of the topological phases obtained.

[0168] For additional context, interested readers should refer to the following references.

[0169] TO Rosdahl, A. Vuik, M. Kjaergaard, and AR Akhmerov, Andreev rectifier: A nonlocal conductance signature of topological phase transitions, Phys. Rev. B 97, 045421 (2018).

[0170] Jeroen Danon, Anna Birk Hellenes, Esben Bork Hansen, Lucas Casparis, Andrew P. Higginbotham, and Karsten Flensberg, Nonlocal conductance spectroscopy of Andreev bound states: Symmetry relations and BCS charges, arXiv:1905.05438 [cond-mat] (2019), arXiv:1905.05438 [cond-mat].

[0171] GC Menard, GLR Anselmetti, EA Martinez, D Puglia, FK Malinowski, JS Lee, S Choi, M Pendharkar, CJ Palmstrom, K Flensberg, CM Marcus, L Casparis, and AP Higginbotham [cond-mat] (2019), arXiv:1905.05505 [cond-mat].

[0172] Davydas Razmadze, Deividas Sabonis, Filip K. Malinowski, Gerbold C. Menard, Sebastian Pauka, Hung Nguyen, David M.T. van Zanten, Eoin C.T. O’Farrell, Judith Suter, Peter Krogstrup, Ferdinand Kuemmeth, and Charles M. Marcus, Radio-Frequency Methods for Majorana-Based Quantum Devices: Fast Charge Sensing and Phase-Diagram Mapping, Phys. Rev. Applied 11, 064011 (2019).

[0173] MITEQ AFS4-00100800-14-10P-4.

[0174] Appendix A - Protocol to find a topological phase in a three-terminal proximitized nanowire device.

[0175] conclusion In conclusion, one aspect of the present disclosure is directed toward a method for evaluating semiconductor-superconductor heterojunctions for use in qubit registers of a topological quantum computer. The method includes: measuring one or both of the radio-frequency (RF) junction admittance and the sub-RF conductance, including the non-local conductance of the semiconductor-superconductor heterojunction, to obtain mapping data and refinement data; analyzing the mapping data to find one or more regions of the parameter space that coincide with the full topological phase of the semiconductor-superconductor heterojunction; and analyzing the refinement data to find the boundary of the full topological phase in the parameter space and the topological gap of the semiconductor-superconductor heterojunction to at least one of the one or more regions of the parameter space. The method provides many advantageous technical effects in the construction of a topological quantum computer and in a topological quantum computer constructed in such a way. Among these technical effects is the effect that the qubits of the topological computer are accurately screened and tuned, improving performance.

[0176] In some implementations, the measurement of this method is performed in two phases, where mapping data is acquired in the first phase and refined data in the second phase, and the second phase involves scanning sub-regions of one or more regions of the parameter space found by the analysis of the mapping data. This variation provides the additional technical benefit of improved efficiency in the screening / tuning process. In some implementations, the method further includes a step of abruptly transitioning from the first phase to the second phase depending on the analysis of the mapping data. In some implementations, the measurement is performed alternately between the first and second phases to perform adaptive measurements of the parameter space. These features provide the additional technical benefits of effective simultaneous exploration of the parameter space and pinpointing of topological gaps in the region of interest for improved screening and tuning performance. In some implementations, the measurement is coarsely grained in the magnetic field and / or gate voltage in the first phase compared to that in the second phase. In some implementations, the method further includes a step of dynamically adjusting the bias voltage range between the first and second phases to allow bulk gap extraction after initial gap closure is detected. In some implementations, the analysis of mapping data includes density-based clustering of zero-bias peak data from both ends of the semiconductor-superconductor heterojunction. In some implementations, the method further includes a step of validating the zero-bias peak (ZBP) in each of one or more regions by checking the stability of the zero-bias peak (ZBP) with respect to variations in cutter gate voltage. In some implementations, the analysis of refined data includes verifying gap closure at the boundary of each of one or more regions in the parameter space. In some implementations, the semiconductor-superconductor heterojunction is one of a series of similarly prepared semiconductor-superconductor heterojunctions, and the method further includes a meta-analysis of zero-bias peak data across the series to calculate the probability of finding a topological region in another similarly prepared semiconductor-superconductor heterojunction.These modifications offer additional technical benefits by integrating additional useful processes in the screening and tuning of topological qubits. In some implementations, measuring sub-RF conductance involves performing local and non-local conductance measurements suitable for identifying and / or extracting the energy gap of a semiconductor-superconductor heterojunction. In some implementations, the semiconductor-superconductor heterojunction includes a semiconductor wire and at least three terminals at both ends of the semiconductor wire that support admittance and conductance measurements. In some implementations, the semiconductor-superconductor heterojunction includes multiple electrostatic control terminals. These modifications offer additional technical benefits by performing qubit screening and tuning through accessible features of the qubit structure.

[0177] Another aspect of the present disclosure is directed to an instrument configured to evaluate semiconductor-superconductor heterojunctions for use in qubit registers of a topological quantum computer. The instrument comprises a controller having a processor and computer memory operably coupled to the processor, the controller configured to: measure one or both of the radio frequency (RF) junction admittance and sub-RF conductance, including the nonlocal conductance of the semiconductor-superconductor heterojunction, to acquire mapping and refinement data; find one or more regions of parameter space that coincide with the full topological phase of the semiconductor-superconductor heterojunction by analyzing the mapping data; and find the boundary of the full topological phase in the parameter space and the topological gap of the semiconductor-superconductor heterojunction to at least one of the one or more regions of the parameter space by analyzing the refinement data. This provides the technical effect of improving the efficiency of the screening / tuning instrument.

[0178] In some implementations, the instrument is operably coupled to an RF admittance measuring device and / or a sub-RF conductance measuring device.

[0179] Another aspect of the present disclosure relates to a method for constructing a topological quantum computer. The method includes: fabricating a semiconductor-superconductor heterojunction having at least three terminals configured to support an electronic admittance test; measuring one or both of the radio frequency (RF) junction admittance and / or sub-RF conductance of the semiconductor-superconductor heterojunction, including the nonlocal conductance of the semiconductor-superconductor heterojunction, to obtain mapping data and refinement data; analyzing the mapping data to find one or more regions in the parameter space that coincide with the full topological phase of the semiconductor-superconductor heterojunction; analyzing the refinement data to find the boundary of the full topological phase in the parameter space and the topological gap of the semiconductor-superconductor heterojunction to at least one of the one or more regions in the parameter space; and incorporating the semiconductor-superconductor heterojunction into the qubit register of a topological quantum computer, provided that the found boundary and topological gap are within their respective predetermined ranges. The method provides a technical effect of improved screening and tuning of the qubits of the quantum computer being constructed.

[0180] In some implementations, one or more values ​​characterizing the boundary in parameter space are used as tuning parameters for handling the semiconductor-superconductor heterojunction in the qubit register. In some implementations, the semiconductor-superconductor heterojunction is placed in a tetron-qubit device with an additional ground terminal, and transport through a topologically tuned opposing region is measured simultaneously. In some implementations, the semiconductor-superconductor heterojunction is placed in a hexon-qubit device. In some implementations, the semiconductor-superconductor heterojunction is placed in a tetron or hexon-qubit device with a native terminal used as the ground terminal in this method, where the current path through the device is used to ground the individual qubits for three-terminal-like measurements. These variations provide additional technical effects that extend this method to topological quantum computer architectures, which are of particular interest in this field today.

[0181] Another aspect of this disclosure is directed to a two-stage approach to the extraction of topological phases. Importantly, this involves staged separation, where a mapping phase then allows for a broad exploration of the parameter space, while still generating false positives, and a refinement stage allows for the removal of false positives by slowly scanning the region of interest from the mapping phase. Another aspect of this disclosure is directed to the use of a density-based clustering algorithm on bilateral ZBP data to extract predictive topological regions. Importantly, this includes the clustering algorithm used for this purpose. This is considered a first systematic approach to finding promising regions. Another aspect of this disclosure is directed to mapping between RF and DC conductance for the purpose of fast conductance extraction in RF measurements. Importantly, this bypasses DC conductance measurements and still involves the use of mapping to extract the same data, but is much faster due to faster RF techniques. Another aspect of this disclosure is directed to the classification of bias traces using peak discovery or machine learning. Importantly, this includes machine learning of topological traces and statistical characterization of how well peak discovery performs. Another aspect of this disclosure is directed, in particular, to extract gaps from nonlocal conductance traces using bias traces with experimental noise or using filtering and smoothing of bias / field scans. Importantly, this includes automated gap extraction. Another aspect of this disclosure is directed to improve the accuracy of conventional methods by checking gap closure at the boundaries of questionable topological regions. Importantly, this includes applying gap extraction from data to classify regions as topological / trivial. Another aspect of this disclosure is directed to meta-analysis of ZBP data to extract the probability of finding topological regions across many devices of the same preparation. This can be used to characterize growth / fabrication methods via topological phase diagrams. Another aspect of this disclosure is directed to use any of the above to tune up qubits in a topological quantum computer.

[0182] The configurations and / or approaches described herein are illustrative in nature and many variations are possible; therefore, it should be understood that these specific embodiments or examples should not be considered in an restrictive sense. The specific routines or methods described herein may represent one or more of any number of processing strategies. Thus, the various operations illustrated and / or described may be performed in the illustrated and / or described sequences, in other sequences, in parallel, or in abbreviation. Similarly, the order of the processing described above may be changed.

[0183] The subject matter of this disclosure includes all novel and non-trivial combinations and secondary combinations thereof of the various processes, systems and configurations disclosed herein, as well as other features, functions, operations and / or characteristics, and all equivalents thereof.

Claims

1. A method for evaluating semiconductor-superconductor heterojunctions for use in qubit registers of topological quantum computers, The steps include measuring either or both the radio frequency (RF) junction admittance of the semiconductor-superconductor heterojunction and the sub-RF conductance including the nonlocal conductance of the semiconductor-superconductor heterojunction to obtain mapping data and refined data, The steps include: finding one or more regions of the parameter space that coincide with the complete topological phase of the semiconductor-superconductor heterojunction by analyzing the mapping data; The steps include: finding the boundary of the complete topological phase in the parameter space and the topological gap of the semiconductor-superconductor heterojunction for at least one of the one or more regions of the parameter space by analyzing the refined data; Methods that include...

2. The measurement is performed in a first phase and a second phase, the mapping data is acquired in the first phase, the refinement data is acquired in the second phase, the second phase includes scanning sub-regions of one or more regions of the parameter space found by the analysis of the mapping data. The method according to claim 1.

3. The step further includes a sudden transition from the first phase to the second phase in response to the analysis of the mapping data, The method according to claim 2.

4. The measurement is performed alternately between the first phase and the second phase in order to perform adaptive measurement of the parameter space. The method according to claim 2.

5. The measurement is performed with a coarser grain in the magnetic field and / or gate voltage in the first phase than in the second phase. The method according to claim 2.

6. The method further includes the step of dynamically adjusting the bias voltage range between the first phase and the second phase in order to enable bulk gap extraction after initial gap closure is detected. The method according to claim 2.

7. The analysis of the mapping data includes density-based clustering of zero-bias peak data from both ends of the semiconductor-superconductor heterojunction. The method according to claim 1.

8. The method further includes the step of validating the zero bias peak (ZBP) in each of the one or more regions by checking the stability of the zero bias peak (ZBP) with respect to fluctuations in the cutter gate voltage. The method according to claim 1.

9. The analysis of the refined data includes verifying gap closure at the boundaries of each of the one or more regions of the parameter space. The method according to claim 1.

10. The semiconductor-superconductor heterojunction is one of a series of similarly prepared semiconductor-superconductor heterojunctions, and the method further includes a meta-analysis of zero-bias peak data across the series to calculate the probability of finding a topological region in another similarly prepared semiconductor-superconductor heterojunction. The method according to claim 1.

11. Measuring the sub-RF conductance includes performing local and non-local conductance measurements suitable for identifying and / or extracting the energy gap of the semiconductor-superconductor heterojunction. The method according to claim 1.

12. The semiconductor-superconductor heterojunction includes a semiconductor wire and at least three terminals at both ends of the semiconductor wire that support admittance and conductance measurements. The method according to claim 1.

13. The semiconductor-superconductor heterojunction includes a plurality of electrostatic control terminals, The method according to claim 1.

14. An instrument configured to evaluate semiconductor-superconductor heterojunctions for use in qubit registers of a topological quantum computer, wherein the instrument: A controller comprising a processor and computer memory operably coupled to the processor, the controller The radio frequency (RF) junction admittance of the semiconductor-superconductor heterojunction and the sub-RF conductance including the nonlocal conductance of the semiconductor-superconductor heterojunction, or both, are measured to obtain mapping data and refined data. By analyzing the aforementioned mapping data, one or more regions of the parameter space that coincide with the complete topological phase of the semiconductor-superconductor heterojunction are found. By analyzing the refined data, the boundaries of the complete topological phases in the parameter space and the topological gap of the semiconductor-superconductor heterojunction to at least one of the one or more regions of the parameter space are found. A device configured in such a way.

15. The device is operably coupled to an RF admittance measuring device and / or a sub-RF conductance measuring device. The apparatus according to claim 14.

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