Information processing system, information processing device, server device, program, reconfigurable device, or method

Abstract

To provide an information processing system, an information processing apparatus, a server device, a reconfigurable device, a program, and a method that more appropriately utilize a reconfigurable device.SOLUTION: A system includes: an acquisition unit that acquires information indicating a first resource from a user; a specification unit that specifies a first reconfigurable device corresponding to the information indicating the first resource; and an instruction unit that instructs the first reconfigurable device to write a first partition shell corresponding to the information indicating the first resource. The acquisition unit further acquires information indicating a second resource that is different from the information indicating the first resource, and the instruction unit instructs the first reconfigurable device to write a second partition shell different from the first partition shell corresponding to the information indicating the second resource.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The technology disclosed in the present application relates to an information processing system, an information processing apparatus, a server apparatus, a reconfigurable device, a program, or a method.

Background Art

[0002] In recent years, programmable logic devices with modifiable circuits have begun to be introduced in various fields.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Patent Document 2

Patent Document 3

Summary of the Invention

Problems to be Solved by the Invention

[0004] However, there are situations where the technology of using reconfigurable devices for distributed processing has not been utilized. Therefore, various embodiments of the present invention provide an information processing system, an information processing apparatus, a server apparatus, a program, a reconfigurable device, or a method to solve the above problems.

Means for Solving the Problems

[0005] One embodiment according to the present application is an acquisition unit that acquires information indicating a first resource from a user, a specifying unit that specifies a first reconfigurable device corresponding to the information indicating the first resource, An instruction unit that instructs the first reconfigurable device to write a first partition shell corresponding to information indicating the first resource, A system equipped with these features.

[0006] Other embodiments relating to this application are, The system Steps include obtaining information from the user that indicates the first resource, The steps include identifying a first reconfigurable device corresponding to information indicating the first resource, The steps include instructing the first reconfigurable device to write a first partition shell corresponding to information indicating the first resource, How to do it.

[0007] Other embodiments relating to this application are, The system A means of obtaining information from the user indicating the first resource, Means for identifying a first reconfigurable device corresponding to information indicating the first resource, Means for instructing the first reconfigurable device to write a first partition shell corresponding to information indicating the first resource, A program to make it work as such. [Effects of the Invention]

[0008] One embodiment of the present invention enables more appropriate use of reconfigurable devices. [Brief explanation of the drawing]

[0009] [Figure 1] Figure 1 is a block diagram illustrating an example of the relationship between a system according to one embodiment and a reconfigurable device. [Figure 2] Figure 2 is an example block diagram showing the relationship between a system according to one embodiment and a reconfigurable device. [Figure 3]FIG. 3 is a block diagram showing the functions of a system according to an embodiment. [Figure 4] FIG. 4 is a diagram showing the flow of processing of an example of a system according to an embodiment. [Figure 5] FIG. 5 is a diagram showing the data format of an example of a system according to an embodiment. [Figure 6] FIG. 6 is a diagram showing the data format of an example of a system according to an embodiment. [Figure 7] FIG. 7 is a diagram showing the data format of an example of a system according to an embodiment. [Figure 8] FIG. 8 is a diagram showing the flow of processing of an example of a system according to an embodiment. [Figure 9] FIG. 9 is a diagram showing the data format of an example of a system according to an embodiment. [Figure 10] FIG. 10 is a block diagram showing the functions of a system according to an embodiment. [Figure 11] FIG. 11 is a block diagram showing the functions of a system according to an embodiment. [Figure 12] FIG. 12 is a diagram for explaining a part of the processing of an example of a system according to an embodiment. [Figure 13] FIG. 13 is a diagram for explaining a part of the processing of an example of a system according to an embodiment. [Figure 14] FIG. 14 is a diagram for explaining a part of the processing of an example of a system according to an embodiment. [Figure 15] FIG. 15 is a diagram for explaining a part of the processing of an example of a system according to an embodiment. [Figure 16] FIG. 16 is a diagram for explaining a part of the processing of an example of a system according to an embodiment. [Figure 17] FIG. 17 is a diagram for explaining a part of the processing of an example of a system according to an embodiment. [Figure 18] FIG. 18 is a diagram for explaining a part of the processing of an example of a system according to an embodiment. [Figure 19] FIG. 19 is a diagram for explaining a part of the processing of an example of a system according to an embodiment. [Figure 20] Figure 20 is a diagram illustrating a part of the processing of an example of a system according to one embodiment. [Figure 21] Figure 21 is a diagram illustrating a part of the processing of an example of a system according to one embodiment. [Figure 22] Figure 22 is a block diagram showing the functions of a system according to one embodiment. [Figure 23] Figure 23 is a diagram showing the processing flow of an example of a system according to one embodiment. [Figure 24] Figure 24 is a block diagram showing the configuration of an example of a system according to one embodiment.

[0010] 1. Overview One example of the technology disclosed in this application relates to a rewritable circuit. However, this example of the technology may also utilize an information processing device that includes a non-rewritable circuit. In this application, rewritable circuits are also referred to as programmable logic devices, etc., but in this application, they are collectively referred to as reconfigurable logic devices. On the other hand, non-rewritable circuits are sometimes referred to as instruction decoding schemes, von Neumann type devices, etc., but in this application, they are collectively referred to as program variable devices.

[0011] Examples of reconfigurable devices include PAL (Programmable Array Logic), PLA (Programmable Logic Array), GAL (Generic Array Logic), CPLD (Complex Programmable Logic Device), FPGA (Field Programmable Gate Array), and CGRA (Coarse-Grained Reconfigurable Array).

[0012] In the following sections of this application, FPGAs will be used as the primary example of a reconfigurable device, but it goes without saying that the same principles can be applied to other reconfigurable devices as well. In particular, any reconfigurable device that offers partial reconfiguration, that is, the ability to independently write to multiple regions (e.g., PR regions) within a single programmable logic device, may be capable of the region-specific processing described later. Here, "independently writable" may include the ability to write to other regions within the same programmable logic device while processing is being performed in one region of the same programmable logic device.

[0013] In this application, the term "information processing device" is used as a broader concept encompassing both reconfigurable devices and programmable devices.

[0014] Furthermore, although the following first to fourth systems are independent inventions, in the following descriptions of the second to fourth systems, explanations of terms identical to those used in the first system will be omitted unless there are circumstances specific to each system.

[0015] 2. Example of the first system The system in this example relates to a system that provides the user with hardware resources on which a hypervisor shell and partition shell, including communication functions, are written, before the user writes an application. Such a system has the advantage of being able to appropriately provide the user with hardware resources for a reconfigurable device.

[0016] The system in this example may consist of one or more information processing devices. Such one or more information processing devices may consist of one or more FPGAs and / or one or more programmable devices.

[0017] Furthermore, the system in this example may be connected to one or more FPGAs. In this case, there is the advantage of being able to manage one or more FPGAs.

[0018] Figure 1 shows an example of the system in this example being connected to one or more FPGAs. It shows the system (001) in this example being connected to FPGA1 (0021) through FPGA4 (0024). Such connections may be made via Ethernet or via a bus such as PCI Express. Note that the system in this example may be connected to only one or more FPGAs as the computing function for executing user applications. In this case, hardware resources that perform functions other than the computing function for executing user applications may be connected to programmable devices.

[0019] Furthermore, the system in this example may be connected to one or more FPGAs, and may also be connected to one or more programmable devices. In this case, the system in this example has the advantage of being able to manage distributed processing and other functions, including the programmable devices, in addition to managing the FPGAs.

[0020] In the system of this example, if it is connected to one or more FPGAs and / or one or more programmable devices, the connection may be direct or indirect via a network. One or more FPGAs may be installed in the same facility as the system of this example, or in different facilities. Furthermore, the specific location of the installation of one or more FPGAs may be anything. For example, one or more FPGAs may be installed inside a building (indoors) or outside a building (outdoors). IoT devices such as sensors may operate inside and / or outside a building, and these may be implemented by FPGAs. The network may be wired, wireless, or a combination of both.

[0021] Figure 2 shows the system in this example connected to an FPGA and a programmable device via a network (000). In this figure, the FPGA group (002) includes multiple FPGAs and a programmable device. Here, the programmable devices are referred to as CPU1 and CPU2, and for convenience, they are also shown as part of the FPGA group. The FPGA group (003) includes multiple FPGAs and an information processing device that includes FPGA writer functionality. Such an FPGA writer may be capable of writing bitstreams to both the FPGA group (003) and the FPGA group (002). The network within these FPGA groups (002) and (003) may be a bus or Ethernet, etc.

[0022] The system in this example, the one or more FPGAs described above, and / or the one or more programmable devices described above may be information processing devices on the cloud.

[0023] 2.1. System Functions The system in this example may include a database unit containing FPGA information and a management unit that manages the information in the database unit. Figure 3 illustrates an example of such a function.

[0024] 2.1.1. Management Department The management unit has the function of managing processing. Here, processing may include, for example, the function of providing information, the function of receiving information, the function of transmitting information, and / or the function of receiving information. Furthermore, the information that is the subject of these provision, reception, transmission, and reception may be the same or different.

[0025] For example, the management unit may have a function to provide information to the user. In this case, the system in this example has the advantage of providing information to the user and enabling the user to make meaningful decisions. The management unit may also have a function to receive information entered by the user. In this case, the system in this example has the advantage of being able to utilize the information received from the user. The management unit may also have a function to transmit information to the FPGA. In this case, the system in this example has the advantage of being able to influence the FPGA with the information transmitted to it. The management unit may also have a function to receive information from the FPGA. In this case, the system in this example has the advantage of being able to manage the status of the FPGA with the information received from the FPGA. These details will be described later.

[0026] 2.1.2. Database Section The database section has the function of storing information about the FPGA. In particular, the database may store one or more resource information, as described later. The database section may also store other information. The system in this example has the advantage of being able to use the FPGA information managed by this system because it includes a database section.

[0027] 2.2. Processing Flow This system example will be explained in two stages: the preparation stage and the operation stage. The preparation stage may be the stage performed when a new FPGA is connected to the system. Examples of such cases include when an FPGA is added or when an existing FPGA is changed. Changing an existing FPGA may include changing the configuration within the existing FPGA. The operation stage may be the stage performed after the preparation stage has been completed.

[0028] 2.2.1. Preparation Phase The preparation stage will be explained with reference to Figure 4.

[0029] Step 1 First, the system in this example and the FPGA may be connected in a way that enables signal communication. Such a connection may be made via wired or wireless means to enable signal communication.

[0030] Such connections may occur when a new FPGA is added, or when the physical configuration of the FPGA is changed due to repairs, etc., but are not limited to these cases.

[0031] Furthermore, such connections may include connecting FPGAs to each other via a network, or connecting FPGAs to other information processing devices including CPUs via a network.

[0032] Step 2 The system in this example may assist in the process of writing the hypervisor shell to the connected FPGA. The FPGA writing technique itself may utilize publicly known techniques.

[0033] The hypervisor shell can be written automatically by the system in this example, or it can be done manually.

[0034] The hypervisor shell may be written in any programming language. When the hypervisor shell is to be written, it may be converted to a bitstream and written to the FPGA using known techniques. For example, the means of writing may be via JTAG or USB.

[0035] The hypervisor shell that is written can be one that corresponds to the type and function of the target FPGA.

[0036] The hypervisor shell only needs to be able to provide the FPGA with communication functionality with the management unit when written to the FPGA; it does not need to have all the functions of the hypervisor shell described later. Once the hypervisor shell is written in this step, the system in this example becomes able to communicate with the FPGA on which the hypervisor shell has been written.

[0037] Step 3 The system in this example may assist in registering information about physically connected FPGAs in a database. By pre-registering FPGA information in the database, the system in this example has the advantage of being able to utilize FPGA information through the information held in that database.

[0038] Such a database only needs to be capable of storing the information described below, and may or may not utilize a database management system. If the database has a data model on which it is based, it may be of various types, such as hierarchical, network, relational, or object data models, and the type is not limited. Furthermore, the hardware resources that implement such a database may be dedicated devices, general-purpose devices, or various information processing devices such as clouds and servers.

[0039] In this example, if the system uses a database, it is sufficient that it can access the database. The system in this example may or may not have a database. In the latter case, it is sufficient that the system in this example can connect to the database directly or indirectly via a network or the like.

[0040] The database may store information that actually identifies an FPGA and information about the functions of such FPGA (sometimes referred to as "resource information" in this application) in association with each other. Resource information may include, for example, the type of reconfigurable device, attributes related to the arithmetic unit, attributes related to the memory device, and / or attributes related to the communication device. Attributes related to the arithmetic unit may include the type of arithmetic unit, the number of arithmetic units such as the number of cells, the capabilities of the arithmetic unit such as the clock frequency, and / or the power used by the arithmetic unit. The arithmetic unit may include, for example, logic elements (LEs), logic cells (LCs), and / or LUTs (look-up tables). Attributes related to the memory device may include the type of memory device, the capacity of the memory device, the read / write speed of the memory device, and / or the power used by the memory device. The memory device may be, for example, an on-chip memory device within the reconfigurable device, but it may also be another memory device installed outside the reconfigurable device. The attributes relating to the communication device may include attributes relating to the internal communication device and / or attributes relating to the external communication device. Furthermore, the attributes relating to the internal communication device may be information about communication within the FPGA. The attributes relating to the external communication device may include the network bandwidth and / or bandwidth speed of communication with the outside.

[0041] Furthermore, an FPGA may contain one or more PR regions. A PR region is a section whose circuit configuration can be changed independently. For each PR region, the FPGA may perform one or more independent operations using partial reconfiguration, or it may perform one or more independent operations without using partial reconfiguration. Because they are independent, for example, if an FPGA contains PR region A and PR region B, PR region A and PR region B may operate independently in terms of circuit rewriting and circuit execution. Therefore, it may be possible to rewrite PR region B while PR region A is executing.

[0042] In this application, "one" resource information may refer to a single unit that a user can use as a hardware resource. Therefore, if an FPGA is not managed on a PR region basis, one resource information may refer to one FPGA; however, if an FPGA is managed on a PR region basis and each PR region has its own usable hardware resource, one resource information may refer to a single PR region within one FPGA.

[0043] The database described above may store the resource information associated with each of the one or more PR regions contained within a single FPGA.

[0044] Furthermore, there may be multiple ways to configure PR regions for a single FPGA. For example, a single FPGA may be divided into two PR regions, PR region A and PR region B, or it may be divided into four PR regions, PR region A through PR region D. Since the resource information for each PR region will also differ depending on the division method, resource information may be associated with and stored for a specific PR region in a particular division method.

[0045] Figure 5 shows an example of a logical organization of information held in a database where FPGA resource information is registered. FPGAID indicates the ID assigned to the FPGA actually connected to the system in this example. Since resource information may have the classifications described above, resource information may be associated and stored corresponding to the ID of each FPGA.

[0046] Figure 6 is another example of how the information in a database containing FPGA resource information is logically organized. This figure shows an example where multiple PR regions are set for a single FPGA. For example, FPGAID 001 has two PR regions, and FPGAID 002 has three PR regions. Resource information is set for each PR region. This is because each PR region may have the same resources or different resources. In the latter case in particular, there is an advantage in being able to set resource information corresponding to each PR region.

[0047] Furthermore, Figure 7 is another example of how the information held in a database where FPGA resource information is registered is logically organized. This figure shows a case where there are multiple methods for dividing the PR region for a single FPGA. For example, for FPGAID 001, there are PR region division methods 1 and division method 2. Division method 1 divides the PR region into two, and division method 2 divides the PR region into four. As mentioned above, each PR region may have the same resources or different resources, so resource information for each PR region may be stored in association with information that identifies each PR region.

[0048] Furthermore, although not shown in Figures 5 to 7 above, the database may also store information identifying the type of FPGA, associated with information identifying each actual FPGA. This is because the user needs the type of FPGA to target when programming with hardware description languages ​​(HDLs) such as VHDL, Verilog, or high-level synthesis languages ​​such as C, or when generating bitstreams.

[0049] Furthermore, the database may store information indicating whether each PR region is in use, associated with the corresponding PR region. This information has the advantage of allowing management of whether the corresponding PR region is being used by a user.

[0050] Furthermore, the database may store information indicating the PR region being used and information indicating the user using it, in association with each PR region being utilized. In this case, there is the advantage of being able to manage users when a PR region is being utilized.

[0051] The database may store information relating to a user, including information that identifies the user and information relating to that user. User-related information may include information that identifies the user in the real world, such as the user's address and email address, the user's ID, the password corresponding to the ID, and / or information relating to the services the user uses. Service-related information may include information about the service courses the user has paid for, and / or information about options the user can subscribe to.

[0052] Furthermore, the database may be associated with each FPGA and store information related to the licenses for each FPGA. For example, the database may store information indicating whether a license is required for each FPGA. The database may also be associated with each FPGA and store information indicating the type of license required for each FPGA. The advantage of storing such license information is that it is possible to verify whether a license is required and what type of license is needed when using each FPGA. Note that the licenses may be specific to each FPGA type, arithmetic function, memory function, and / or communication function, because licenses may differ for each FPGA type, arithmetic function, memory function, and / or communication function. In particular, the licenses may be able to store various types of licenses, such as low-cost versions, high-cost versions, and licenses for special applications. Also, depending on their nature, the licenses may be licenses for a single FPGA or licenses for a package of multiple FPGAs.

[0053] Furthermore, the database may also contain information relating to licenses held by such users, associated with the user information described above. For example, it may contain information identifying whether a user has a license and / or the type of license. In this case, there is the advantage of being able to generate or verify information indicating what FPGA licenses a user has that are available.

[0054] Furthermore, the database may store physical information about the FPGA, associated with information indicating the FPGA. This physical information may include, for example, geographical information about the FPGA's location. It may also include, for example, the FPGA's latitude and longitude, the name of the facility where the FPGA is installed, the name of the facility manager managing the FPGA, and / or information about the management level of the facility where the FPGA is managed. Such information can be useful as reference information when considering security and incident response capabilities regarding the FPGA's location and management.

[0055] The database may consist of a single database or multiple databases for all connectable FPGAs. The latter may be managed separately, for example, by separating the database for FPGAs with pre-programmed partition shells (described later) from the database for FPGAs without pre-programmed partition shells. The latter has the advantage of allowing quick access when the number of pre-programmed FPGAs is small.

[0056] Resource information for such FPGAs may be manually registered in the database by a person, or it may be recorded and registered in the database as information corresponding to the FPGA.

[0057] 2.2.2. Operational Phase The operational phase will be explained with reference to Figure 8. Step 1 The system in this example presents the user with a Flavor. The Flavor may be a template for virtual hardware. While "Flavor" is a term used in OpenStack, the virtualization middleware, it may refer to similar functionality in other virtualization middleware. The Flavor may be displayed on a display device provided by the system in this example. The Flavor may contain one or more resource information for one or more FPGAs. One resource information may include the device name, PR shell, PR region, and / or device information. The PR shell is the shell that manages the PR region and may refer to the same thing as the partition shell in this application. The display of the Flavor has the advantage of allowing the user to select resource information suitable for the circuit they intend to write. In particular, as mentioned above, the resource information includes information such as the type of reconfigurable device, attributes related to the arithmetic unit, attributes related to the storage device, and / or attributes related to the communication device, thus offering the advantage of selecting information suitable for the circuit they intend to write.

[0058] Figure 9 shows an example of a flavor. For a device named FPGA1, the PR shell is 1 (displayed as PRS1), and the PR region is displayed as PR1. For a device named FPGA2, a shell capable of managing two PR regions is assigned as the PR shell (displayed as PRS2), and the two PR regions are displayed as PR1 and PR2, respectively. Furthermore, the flavor may include information indicating multiple ways of configuring PR regions for a single physical device. For example, FPGA4 may be divided into two PR regions or into four PR regions. In the former case, the two PR regions are named PR1 and PR2, and PRS2 is the shell that manages them. In the latter case, the four PR regions are named PR1 through PR4, and PRS4 is the shell that manages them. Here, we have described two methods for dividing FPGA4 into two PR regions and four PR regions, but the system is not limited to these. Whenever an FPGA can be divided into any number of PR regions it can handle, the system in this example may be able to manage any number of corresponding PR regions. In this case, the system in this example may be able to manage the combinations of the number of divisible PR regions and include them within the flavor. Thus, by presenting multiple division methods for the same device, the user has the advantage of being able to select one of the multiple division methods permitted for that physical device. The database may store one or more division methods associated with a single FPGA device so that such displays can be presented. Although the diagram includes a PR shell, such a PR shell is not required.

[0059] Furthermore, as described above, the flavor may include the type of FPGA associated with information indicating a particular FPGA as one element of the resource information. In this case, the user has the advantage of being able to select the desired resource information, including the type of FPGA. Also, as described above, the flavor may include the PR region as one element of the resource information. In this case, the user has the advantage of being able to select the desired resource information, including the resource information. For example, the bitstream of an application written to an FPGA may be generated depending on the type of FPGA and / or the PR region. For example, a program written in a hardware description language or high-level synthesis language for rewriting an FPGA has the advantage of being able to utilize the FPGA type and / or PR region information when it is compiled and a bitstream is generated. This has the advantage of avoiding the problem that if the FPGA type and / or PR region of the compiled program for the FPGA provided by the user differs from the FPGA type and / or PR region of the hardware resources related to the resource information provided by the system in this example, a new compilation will be required.

[0060] Furthermore, the resource information presented by the flavor may or may not have a one-to-one relationship with real-world resource information. The former indicates that the resource information presented by the flavor actually exists; for example, if there are two hardware resources with the same resource information α in reality, the flavor can present two identical pieces of information. In this case, there is the advantage of being able to display whether there is essentially only one or multiple hardware resources corresponding to the resource information. On the other hand, in the latter case, the resource information presented by the flavor may have a one-to-many relationship with real-world resource information. For example, if there are two hardware resources with the same resource information α in reality, the flavor will present one such piece of resource information α. ​​In this case, since it is the same resource information, there is the advantage of being able to effectively utilize the display area.

[0061] Furthermore, the flavor may display both of the above. For example, the resource information presented by the flavor may display one aspect of the relationship between the resource information in the real world and the resource information in the real world, while separately presenting different elements as part of the "many." These different elements as part of the "many" may include, for example, the number of hardware resources related to the real resource information, the location where the hardware resources related to the real resource information are installed, or the distance from the system to the location where the hardware resources related to the real resource information are installed. Here, the distance may be a physical distance, as described later, or it may be a distance related to the communication of information.

[0062] Furthermore, the flavor may include and present all resource information available to the database, regardless of whether the user has access to it or not. In this case, the user has the advantage of understanding what hardware resources the database has. For example, the user can understand whether there are more or fewer hardware resources containing certain resource information than a predetermined number.

[0063] Alternatively, the flavor may include and present one or more resource information items that are writable by users, regardless of any specific user. In other words, the flavor may present resource information excluding resource information currently in use. In this case, there is the advantage that resource information already in use is not displayed, making it easier to select resource information. In this case, additionally, the resource information currently being used by the user selecting the resource information may be displayed. In this case, there is the advantage that the user selecting the resource information can choose new resource information while referring to the resource information currently being used.

[0064] Alternatively, instead of this configuration, the flavor may include and present one or more resource information available to a specific user who selects the flavor. For example, the available resource information for a user may be predetermined based on whether or not they have a license, the type of license they possess, or their membership plan and terms of service for the system in this example, and only one or more resource information available to such a user may be presented. In this case as well, the resource information currently being used by the user selecting the resource information may be displayed. In this case, there is an advantage in that the user selecting the resource information can choose new resource information while referring to the resource information currently being used.

[0065] Alternatively, instead of this configuration, the flavor may include and present one or more resource information available to a specific user who selects the flavor, and one or more resource information available if such user satisfies certain conditions. Here, the certain conditions may include, for example, acquiring a new license, changing the membership course of the system in this example, and / or acquiring membership options for the system in this example. These certain conditions may also be presented in association with the resource information available when each condition is met. In this case, the user has the advantage of understanding what conditions must be met to select the corresponding resource information.

[0066] Furthermore, the flavor text may include and present physical information about the FPGA. In this case, the user has the advantage of being able to make a selection based on the physical information of the FPGA.

[0067] Physical information about an FPGA may include, for example, geographical information about where the FPGA is installed. It may also include, for example, the latitude and longitude of the FPGA's installation location, the name of the facility where the FPGA is installed, the name of the facility manager managing the FPGA, and / or information about the management level of the facility where the FPGA is managed. When such information is displayed in association with the physical information corresponding to the resource information, it can be useful as reference information for considering security and incident response capabilities regarding the FPGA's location and management.

[0068] Furthermore, the physical information about FPGAs may include information indicating the distance between FPGAs. The distance between FPGAs may be a physical distance or a distance related to information communication. The former may be a Euclidean distance, and its measurement method may be a straight-line distance between FPGAs or a distance along the communication network between FPGAs. The latter, the distance related to information communication, may use the number of hops or network bandwidth during communication between FPGAs. In this case, there is an advantage in being able to specify a distance that takes into account the communication conditions. Also, the distance between FPGAs mentioned above may be the distance between two FPGAs if there are two FPGAs, or for three or more FPGAs, it may be the sum of the distances between each pair of FPGAs, or the maximum distance when transmitting information between three or more FPGAs. Note that the distance between FPGAs mentioned above may also be calculated and displayed based on the selected multiple resource information, indicating the distance between the selected multiple FPGAs. In this case, the selection may be provisional.

[0069] Furthermore, the distance between devices may be displayed using a two-dimensional or three-dimensional graph. In particular, such a graph may be displayed such that each node in the graph is positioned at a location corresponding to the calculated distance between devices as described above. In this case, the user has the advantage of being able to understand it more intuitively.

[0070] Furthermore, the flavor may include the types and / or number of PR regions that a user can provide for a given FPGA, corresponding to the types and / or number of PR regions that a pre-prepared partition shell for that FPGA can provide. For example, if an administrator has pre-prepared a PR region 2 and a PR region 4 for a given FPGA, the flavor may include resource information for PR region 2 and / or resource information for PR region 4.

[0071] Furthermore, as will be described later, if the system has a function to provide partition shells hierarchically, the flavor may include multiple patterns that can be provided when partition shells are written to unwritten PR regions, even for FPGAs where partition shells have already been written. For example, in an FPGA where a partition shell for providing two PR regions (first partition shell) has been written, if one PR region (first PR region) has already been written, and partition shells cannot be provided hierarchically, the flavor could only provide the remaining PR region (second PR region) (even if a partition shell different from the first partition shell that can provide multiple numbers and types of PR regions to the FPGA is available, provided that the first PR region has already been written and the first PR region and the first partition shell are not deleted). However, when a partition shell (second partition shell) is written to such second PR region, the flavor may provide one or more resource information to the extent that the second partition shell can provide.

[0072] In the above description, the flavors are presented in a table format, but they may be displayed to the user in this manner, or are not limited to this manner, and the flavors may be displayed to the user in various forms of presentation.

[0073] Furthermore, while this step describes the information presented to the user as flavor text, it is not limited to this; all or part of the information stored in the database described in the preparation stage above may also be presented to the user as flavor text.

[0074] Step 2 Next, the user selects one or more resource information from the flavors presented by the system in this example, and the system in this example obtains information that identifies the selected one or more resource information, corresponding to the resource information selected by the user.

[0075] In this step, if the system flavor in this example presents resource information that corresponds one-to-one with resource information within physical hardware resources, information can be obtained that identifies the hardware resource that corresponds one-to-one with the resource information selected by the user.

[0076] On the other hand, if the system in this example has a one-to-many relationship between the resource information within the flavor presented in the flavor and the actual resource information relating to the hardware resources, the system in this example may perform a hardware resource identification process to identify one of the many hardware resources.

[0077] Hardware resource identification processing may be performed from various perspectives. For example, hardware resource identification processing may use information relating to the user and / or information relating to the hardware resources used by the user.

[0078] Furthermore, information relating to the user may include information relating to the user's membership and / or information relating to the user's membership period.

[0079] As an example of using information related to a user's membership period, the system in this example may identify hardware resources using the length of the user's membership period. For example, if the remaining length of a user's membership period is longer than a predetermined period, the system in this example may allocate one of the hardware resources intended for long-term use. In this case, the administrator of the system in this example has the advantage of being able to efficiently perform maintenance on the hardware resources. Alternatively, for example, the system in this example may identify hardware resources using the remaining length of a user's membership period and the scheduled hardware replacement schedule. For example, if the remaining length of a user's membership period is longer than a predetermined period, the system in this example may not allocate any hardware resources that have less than a predetermined period remaining until their replacement. Alternatively, if the remaining length of a user's membership period is a first predetermined period, the system in this example may determine the hardware resources to be used if the next replacement date for the hardware resources is longer than the first predetermined period. In such a case, if there is no extension of the user's membership period, there is the advantage of being able to efficiently perform maintenance on the hardware resources. Furthermore, information relating to the membership period may include the remaining period for which hardware resources can be used, and / or the total or continuous period from the time the user joined the system in this example.

[0080] Furthermore, information relating to a user's membership may include information relating to the membership course or status. For example, the system in this example may allocate one of the specified hardware resources if the user's membership course and / or membership status is specified. Such specified hardware resources may be more stable and robust than other hardware resources. In this case, users who are members of a specific membership or course have the advantage of being able to use higher quality hardware resources. Note that information relating to a membership course or status may be something the user selected when using the system in this example. For example, it may be obtained through a contract that stipulates the use of a certain amount of resource information.

[0081] Furthermore, information relating to the hardware resources used by the user may include one or more hardware resources that the user is currently using at the time of the above selection. For example, the system in this example may include, among the actual hardware resources that match the resource information selected by the user, 1) hardware resources within the same FPGA as the FPGA containing one or more hardware resources currently used by the user, 2) hardware resources within the same local area network or bus as one or more hardware resources currently used by the user, and / or 3) resources that are close in distance to one or more hardware resources currently used by the user.

[0082] In the case of 1) above, since it is within the same FPGA, there is an advantage in that it can support the provision of hardware resources that enable more efficient communication by allowing users to utilize hardware resources within the same FPGA as hardware resources for the same or related applications.

[0083] In the case of 2) above, even within the same local area network or bus as in the former, there is an advantage in that it can support the provision of hardware resources that enable more efficient communication because it is within the same network or bus. The identity of the local area network or bus does not need to be such that it reduces the processing required for communication across networks, and it can be at any layer.

[0084] Furthermore, the above-mentioned 2) may be a virtual local network. In this case, although the physical distance may not be shorter than the predetermined distance, and the distance over which information is transmitted may not be shorter than the predetermined distance, it has the advantage of high security.

[0085] Furthermore, in case 3) above, the distance may be the physical distance as described above, or the distance related to the communication of information. By selecting a real hardware resource that matches the resource information selected by the user and is close in distance to one or more hardware resources currently being used by the user, it is possible to support the provision of hardware resources that enable more efficient communication compared to others.

[0086] Step 3 Next, the system in this example checks whether one or more hardware resources corresponding to one or more resource pieces of information selected by the user are available. That is, the system in this example attempts to write a partition shell corresponding to the resource piece of information to the FPGA device, which is a hardware resource corresponding to the resource piece of information. Such writing may be done by writing a bitstream, and the method of transmitting the information may be done using TAGs or USB, and there are no limitations on the manner. Furthermore, the writing technique to the FPGA itself may be a known technique.

[0087] Furthermore, if the system in this example fails to write to the partition shell, the system may display a message indicating that the user-selected resource information, such as the partition shell write failure, is unavailable, and prompt the user to select new resource information.

[0088] The partition shell may be the same as or different from the partition shell described later. The partition shell only needs to have the functionality to help the user utilize the hardware resources within the FPGA on which the partition shell is written, and does not need to have all the functionality of the partition shell described later.

[0089] Step 4 In this example, if the partition shell write operation is successful, the system registers information about the resource that was successfully written to the database.

[0090] Furthermore, the system in this example may provide feedback to the user regarding resource information that has been successfully written. The manner in which this feedback is provided to the user may vary. For example, the information regarding the resource information that has been successfully written may be displayed on a display device, emailed to the user, or stored in a designated location accessible to the user. Such resource information may include information that identifies the hardware resource to which the partition shell was actually written, and such information that identifies the hardware resource may include information that identifies a specific reconfigurable device. In addition, such resource information may include information that identifies the type of FPGA, attributes related to the arithmetic unit, attributes related to the storage device, attributes related to the communication device, PR region, and / or location on the network. The information that identifies the location on the network may be, for example, an IP address for an FPGA, and the PR region within the FPGA may be an IP address or a port number.

[0091] The user may have access to the written PR region using this information. For example, the user may use this information to write an application that they intend to use on the FPGA, which has been compiled into a bitstream, to the corresponding FPGA.

[0092] The system in this example may assist in writing the bitstream prepared by the user to the corresponding FPGA using the information described above. In this case, writing may be done via USB (JTAG), Ethernet, or PCIe.

[0093] Furthermore, in a different manner from the above, the system in this example first has the user select the resource information, and then attempts to write a PR shell, but if it cannot be selected...

[0094] Furthermore, in a stage prior to Step 1 of the operational phase, the system in this example may perform processes to manage user registration. For example, the system in this example may have functions to manage user registration and modification of user information.

[0095] User registration may be a process in which the system in this example obtains the user information described above. For example, the system in this example may present the user with selectable courses and / or service options, and when the user selects a course and / or service option from the presented options, the system in this example may obtain the selection and store it in association with information that identifies the user.

[0096] In the system of this example, when acquiring user information, the system may acquire orientation information about the reconfigurable device the user will use and store it in association with user identification information. Orientation information about the reconfigurable device may include, for example, information about the type of reconfigurable device the user plans to use, attributes related to the arithmetic unit, attributes related to the storage device, and / or attributes related to the communication device. This is because if a user has a specific type of reconfigurable device they usually use, they are likely to be familiar with that type of reconfigurable device, and therefore the reconfigurable device used in the system of this example is likely to be the same type of reconfigurable device, and using such information may improve convenience. Similarly, if the attributes related to the arithmetic unit, attributes related to the storage device, and / or attributes related to the communication device are aligned with the user's orientation, it may improve user convenience.

[0097] The above steps may be performed by the user directly inputting information into the system in this example. For example, if the system in this example includes a user terminal used by the user, the above steps may involve interaction with the user within the system in this example, the system may display information directly to the user, and the system may directly obtain user input.

[0098] On the other hand, if the system in this example does not have a display or input mechanism for the user, the system in this example may be directly or indirectly connected to user terminals used by users not included in the system in this example, and the above steps may be carried out by interaction between the system in this example and one or more user terminals. For example, in step 1 above, information including flavor may be transmitted from the system in this example to the user terminal, and such information including flavor may be displayed on the user terminal. In step 2 above, resource information selected on the user terminal may be transmitted from the user terminal to the system in this example, and such resource information may be received on the system in this example. In step 3 above, the system in this example may check whether the hardware resources corresponding to such resource information are available. In step 4 above, the system in this example may register the information in a database.

[0099] Furthermore, whether or not the system in this example includes a user's terminal, the reconfigurable device to which the partition shell in step 3 is written may be part of the system in this example or be external to it. Similarly, the database registered in step 4 may also be part of the system in this example or be external to it.

[0100] 3. Second System The second system may relate to a reconfigurable device. For example, the second system may be the reconfigurable device itself, on which the functions described below are implemented as functions written to the FPGA; a bitstream that realizes the functions described below when written to the reconfigurable device; or a program written in an HDL description language that is converted into such a bitstream by compilation. As mentioned above, the following explanation will mainly use an FPGA, but the same implementation is possible with a reconfigurable device instead of an FPGA.

[0101] 3.1. System Functions The functions written to the FPGA may include functions processed by the hypervisor shell (hypervisor shell functions) and / or functions processed by the partition shell (partition shell functions). That is, after such functions have been written, the FPGA may have a hypervisor shell section including the hypervisor shell functions and / or a partition shell section including the partition shell functions, as described later. Figure 10 illustrates such functions and examples of the functions they provide.

[0102] A single hypervisor shell may be associated with a single FPGA. Such a single hypervisor shell may be written to that single FPGA. Also, a single partition shell may be associated with a single FPGA. Therefore, for example, even if a single FPGA has multiple PR regions, there may be only one partition shell, and such a partition shell may be written to that single FPGA.

[0103] The hypervisor shell may be determined according to information such as the type of FPGA to be programmed, attributes related to the arithmetic unit, attributes related to the storage device, and / or attributes related to the communication device. On the other hand, the partition shell may be determined according to the type of FPGA to be programmed, attributes related to the arithmetic unit, attributes related to the storage device, attributes related to the communication device, the number of PR regions, attributes related to the arithmetic unit in the PR region, attributes related to the storage device in the PR region, and / or attributes related to the communication device in the PR region.

[0104] Therefore, the database for the system in this example may store hypervisor shells associated with information such as the FPGA type, attributes related to the arithmetic unit, attributes related to the storage device, and / or attributes related to the communication device. In this case, as will be described later, the system in this example has the advantage of being able to obtain the FPGA type and / or function, and identify and use the corresponding hypervisor shell according to the FPGA type and / or function. Furthermore, the database for the system in this example may store partition shells associated with information such as the FPGA type, attributes related to the arithmetic unit, attributes related to the storage device, attributes related to the communication device, and / or the number of PR regions. In this case, as will be described later, the system in this example has the advantage of being able to obtain the FPGA type, function, and / or number of PR regions, and identify and use the corresponding partition shell according to the FPGA type, function, and / or number of PR regions.

[0105] In the following, the hypervisor shell and partition shell may have different functions. However, the hypervisor shell and partition shell may also include the same functions. Dividing the functions written to the FPGA into two has the advantage of distinguishing between functions that change in response to dynamic changes in the PR region (partition shell function) and functions that do not change in response to dynamic changes in the PR region (hypervisor shell function).

[0106] The timing of writing to the FPGA can be simultaneous within a predetermined range for the hypervisor shell and the partition shell, or it can be different. The former may include cases where they are written consecutively, such as the partition shell being written immediately after the hypervisor shell. On the other hand, different timings may include the hypervisor shell being written when the FPGA is registered, and the partition shell being written when the user writes the application data (or immediately before the user writes the application data). Furthermore, the partition shell may be written once, then deleted, and then written again.

[0107] 3.1.1. Hypervisor Shell Section The hypervisor shell may include functions for communication with the management unit, communication with external devices, provision of communication functions to the partition shell, write-related functions, and / or initialization. If the hypervisor shell has some or all of these functions, there is an advantage in that it improves the convenience of the corresponding functions of a reconfigurable device, which becomes executable when a program is written to it.

[0108] Communication with the management unit may include a function to respond to requests from the management unit. For example, if the management unit requests an inquiry about the status of a specific PR region, the FPGA may respond with the status of that specific PR region. The status of such PR region may include information such as whether it has not been written to, whether it has been written to, or whether it is in use, or whether it is not in use. In this way, if the FPGA has the functionality of a hypervisor shell and can communicate with the management unit, the management unit has the advantage of being able to obtain information about the status of the FPGA from the FPGA, which is different from a normal CPU.

[0109] Communication with an external device may include the functions of sending information to and / or receiving information from an external device. The external device may be, for example, a storage medium. In this case, the hypervisor shell may provide an interface to the external device. The external device may also provide an interface for communication with an external storage device via the partition shell described later.

[0110] Providing communication functionality to the partition shell may include support for PR regions within the FPGA when they communicate. PR regions within the FPGA may send information when communicating with other PR regions within the same FPGA as their own PR region, and / or when communicating with other devices within a different FPGA. In this case, the communication functionality of the partition shell may set and / or change the destination of such information as necessary. The hypervisor shell may include a table of communication destination relationships (sometimes referred to in this application as the "communication destination table") in order to provide communication functionality to the partition shell. Such a communication destination table may include relationships between destinations within applications used by users (sometimes referred to in this application as "user destinations"), PR regions that are processing entities within the FPGA, and / or computing entities outside the FPGA (sometimes referred to in this application as "node destinations"). If the hypervisor shell has such a relationship between user destinations and node destinations, the user destination used by the user within the application is set to the node destination provided by the system relating to this application, and information is transmitted. This has the advantage that users can build applications without worrying about the different computing entities of the FPGA.

[0111] Furthermore, the hypervisor shell may have write-related functions. These write-related functions may include a partition shell writing function. The hypervisor shell may have a function to write the partition shell obtained from the management unit into the FPGA to which the hypervisor shell belongs, or a function to support writing. The function to support writing may utilize code with writing functionality obtained from the management unit. When the hypervisor shell has write-related functions, there is the advantage that administrators and users do not need to manually write the partition shell, thus reducing their workload.

[0112] Furthermore, the write-related functions of the hypervisor shell may include functions related to user permissions. These user permission functions may include a function to verify the permissions of the PR region to which the user is writing. For example, the PR region to which the user is writing may contain information that would otherwise be written to a PR region where the user does not have permission, such as the user's program, the compiled bitstream, or information indicating the destination of such bitstream. In this case, if the write-related functions write as is, the bitstream will be written to a PR region where the user does not have permission, causing problems such as destroying an application running in another user's PR region. Therefore, the hypervisor shell to which the bitstream is written may have a function to verify whether the user has write permission to the PR region to which the bitstream is to be written before processing the writing of the received bitstream. Such a function has the advantage of preventing the writing of bitstreams constituting an application related to that user to a PR region to which the user does not have write permission, either intentionally or negligently.

[0113] If the write-related functions of the hypervisor shell include functions related to user permissions, the following processing may be performed, for example:

[0114] First, the hypervisor shell receives information via the network, including the first bitstream that will be implemented when the first application relating to the first user is written (Step 1).

[0115] Next, in response to receiving information including the first bitstream, the hypervisor shell unit obtains from the information including the first bitstream information that identifies the first PR region to which the first bitstream is to be written, and information that identifies the first application (Step 2).

[0116] Next, the hypervisor shell unit transmits information to the management unit, including information that identifies the first application and information that identifies the first PR region to be written to (step 3).

[0117] In response to receiving information including information identifying the first application and information identifying the first PR region, the management unit uses the information identifying the first application and the information identifying the first PR region to determine whether the first application has the authority to write to the first PR region (Step 4).

[0118] If the management unit determines that it has the aforementioned authority, it transmits permission to perform the write operation to the hypervisor shell unit; otherwise, it does not transmit permission to perform the write operation to the hypervisor shell unit (step 5). In the latter case, it may transmit denial of permission to perform the write operation.

[0119] In addition, instead of information identifying the first application, information identifying the user who issued the instruction to write the first application may be used. For example, in step 4 above, information identifying the first application may be used to identify the first user who issued the instruction to write the first application and / or execute the first application, and information on the hardware resources allocated to such first user may be used to determine whether such first user has write privileges to the first PR region. The above is just one example, and if the information containing the first bitstream acquired by the hypervisor shell unit includes information identifying the first user, such information may be used and transmitted to the management unit to determine whether such first user has write privileges to the first PR region.

[0120] Furthermore, although the above description described the hypervisor shell as writing the bitstream, instead of this configuration, the hypervisor shell may, in response to the acquisition of information including the bitstream, transmit information including the bitstream to the configuration memory within the FPGA to which the hypervisor shell belongs, the configuration memory may acquire information identifying the PR region to be written from the information including the bitstream, and the configuration memory may write the information including the bitstream to the PR region corresponding to the information identifying the PR region.

[0121] Furthermore, the initialization function of the hypervisor shell may include initialization functions for the memory functions and / or communication functions related to the FPGA to which the hypervisor shell belongs. The initialization function may include a function to return to an unused state. Initialization has the advantage of preventing malfunctions. Initialization of the memory function may include, for example, returning the information in the memory function to its initial state. In this case, there is the advantage of avoiding a state where meaningless information is stored. Also, initialization of the communication function may include, for example, deleting the FIFO queue in the communication function, or resetting information that is in the middle of the bus handshake sequence to its initial state. In this case, there is the advantage of removing the intermediate stages of communication.

[0122] In particular, because the hypervisor shell performs the initialization, even if the user's application execution mechanism does not include an initialization function, the distributed processing of this system has the advantage of reducing application malfunctions.

[0123] Initialization may be performed at various times. For example, in response to the above-mentioned writing of a partition shell, the memory and / or communication functions used by such partition shell may be initialized. Writing a partition shell has the advantage of allowing initialization before application use, as the user is scheduled to write applications afterward. However, initialization may take time, which may delay the user's application writing. Also, in response to the user's application writing, the memory and / or communication functions used by such application may be initialized. Writing an application has the advantage of allowing initialization before application use, as the user is scheduled to use the application afterward. However, initialization may take time, which may delay the user's application usage.

[0124] Furthermore, the memory and / or communication functions related to the PR region pertaining to a user may be initialized in response to a change in the user's status. For example, the memory and / or communication functions related to the PR region pertaining to a user may be initialized in response to the termination of a user's membership course or option.

[0125] In this case, the management unit monitors the expiration dates of each user's membership courses and options and / or the PR regions used by such users, and in response to the arrival of these expiration dates, the management unit may use information identifying the PR region used by such users to communicate with the hypervisor shell unit of the FPGA to which such PR region belongs to initialize the memory functions and / or communication functions related to such PR region. The hypervisor shell unit may respond to such communication from the management unit by initializing the memory functions and / or communication functions related to the corresponding PR region.

[0126] Thus, when initialization is performed in response to changes in the user's state, particularly when a user ends their use of a PR region, there is an advantage in that, if there is time between the end of use and the next use, the initialization takes time, but the risk of delaying the next use is low.

[0127] 3.1.2. Partition Shell Section The partition shell has functions to support the functions within the PR region. For example, it may manage the clock frequency function, memory function, and / or communication function used by the functions within the PR region. If the partition shell has some or all of these functions, there is the advantage of improved convenience for the corresponding functions in the PR region supported by the partition shell.

[0128] The partition shell may manage the clock frequency functions used by the functions within the PR region. For example, the partition shell may have the role of supplying clock frequency signals to the PR region.

[0129] The partition shell may have the function of generating one or more clock frequency signals to supply to the PR region. The partition shell may have the function of generating multiple different clock frequency signals. The clock frequencies generated by the partition shell may be usable by the circuits within the PR region. The user has the advantage of being able to use the clock frequency signals in the circuits within the PR region without having to prepare them themselves. Furthermore, if the partition shell generates multiple different clock frequency signals, it is possible to select a clock frequency signal suitable for the circuit being written to the PR region, which has the advantage of broadening the range of clock frequency signals that the circuit can use. For example, if the circuit to which the reconfigurable device is written is simple, a higher clock frequency signal may be set, and if the circuit is complex, a lower clock frequency signal may be set, thus having the advantage of being able to select a clock frequency signal according to the circuit configuration.

[0130] Furthermore, the partition shell may supply one or more clock frequency signals to a single PR region. For example, the partition shell may supply different clock frequency signals to multiple identical or different circuits written within a single PR region. In the above case, even if the user wants to use different clock frequencies for multiple identical or different circuits within a single PR region, depending on the complexity and role of the circuits, there is the advantage of being able to use a clock frequency signal appropriate for each circuit.

[0131] The clock frequency signal used by a circuit may be predetermined by the user who determines which circuit to be written to. To enable the user to determine the clock frequency used by a circuit, the system in this example may support an environment in which the user can specify the clock frequency available to the circuit when programming the circuit using a hardware description language or a high-level synthesis language. Furthermore, if it is desired to supply different clock frequency signals to multiple identical or different circuits within a single PR region, the system in this example may support an environment in which the user can specify the clock frequency available to each identical or different circuit when programming the circuit using a hardware description language or a high-level synthesis language. Support for an environment in which clock frequency signals can be specified may include, for example, a process of displaying one or more clock frequency signals available to each of one or more identical or different circuits, a process of associating and storing the clock frequency signal selected by the user with the target circuit, and / or a process of writing the connection relationship between such associated circuit and clock frequency signal when writing within the PR region.

[0132] The partition shell may have a function to manage the correspondence between the memory functions used by the arithmetic functions within a PR region and the memory functions used by the FPGA to which the PR region belongs. Managing such a correspondence has the advantage of reducing the risk of interfering with memory-related processing in other PR regions. For example, if the memory used by the arithmetic functions within a PR region is at addresses 000 to 999, and these addresses correspond to memory functions 20000 to 20999 used by the FPGA to which the PR region belongs, the partition shell may have a table showing such a correspondence, and the partition shell may use this table to assist in using the corresponding memory of the FPGA to which the PR region belongs in relation to the specific address of the memory used by the arithmetic functions within the PR region. Here, the memory functions used by the FPGA may be storage devices installed within the FPGA, or external storage devices accessible to the FPGA.

[0133] Furthermore, the partition shell may have a function to manage the correspondence between information identifying the communication channels used by communication functions within a PR region and information identifying the communication channels with the outside of the FPGA to which that PR region belongs. Managing such correspondences has the advantage of reducing the risk of interfering with communication-related processing in other PR regions. For example, for communication based on a communication channel used by a certain PR region, information indicating that it is based on that PR region may be attached to the communication information related to the hypervisor shell.

[0134] The partition shell section may be hierarchically located within the PR region.

[0135] The advantages of hierarchically configuring partition shells (for example, configuring another partition shell within a PR region managed by a partition shell) become apparent in the following example: A certain FPGA has two PR regions (two 1 / 2 PR regions), and one PR region (the first 1 / 2 PR region) is already written to and in use. In this case, the remaining 1 / 2 PR region (the second 1 / 2 PR region) can be provided to the user, but consider a case where the user only needs to use a quarter of the PR region. In this case, the partition shell (first partition shell) that already has two PR regions configured is already written to, and the first 1 / 2 PR region is in use. Therefore, by writing a partition shell section (second partition shell section) capable of managing two new 1 / 4 PR regions (the first 1 / 4 PR region and the second 1 / 4 PR region) into the second 1 / 2 PR region, which is still unused, and allowing users to utilize the first 1 / 4 PR region, there is the advantage of being able to use it efficiently.

[0136] The partition shell section may, as described above, communicate with lower-level partition shell sections arranged hierarchically. In this case, the partition shell section may support the circuits within the PR region managed by the lower-level partition shell through the communication function and / or storage function managed by the lower-level partition shell.

[0137] 4. Third System The third system example is an example of a system that supports distributed processing using an FPGA. For example, as shown in Figure 11, the system in this example may include a JOB manager function, a resource manager function, and a TASK manager function. The JOB manager and resource manager functions may be implemented on a programmable device. The TASK manager function may be implemented as a function on a reconfigurable device. As mentioned above, the following explanation will mainly use an FPGA, but it is possible to implement it similarly using a reconfigurable device instead of an FPGA. In addition, in the third system, the hypervisor shell and / or partition shell may or may not be written to the FPGA. Even if the hypervisor shell and / or partition shell are not written, as in the latter case, distributed processing can be executed by writing a bitstream, as described below.

[0138] 4.1. Function 4.1.1. Job Manager The JOB Manager has the function of managing jobs.

[0139] A job may be a single unit defined in advance by the programmer, or it may be a unit defined by the programmer that has been further subdivided by a separate job management technology for distributed processing, or a collection of multiple units defined by the programmer.

[0140] When a job is executed on an FPGA, it can be a bitstream converted from what the programmer has programmed. When a job is executed on a programmable device, it can be in a form executable on the hardware, such as a compiled program or a machine code conversion of what the programmer has programmed.

[0141] A job may be managed using job-identifying information, such as a job ID, that can uniquely identify the job. Therefore, a job manager may have a database that stores information identifying a job in association with the job that is actually executed.

[0142] The JOB manager may perform a data flow analysis on the JOBs and determine the order in which the JOBs are processed based on that data flow. This order may be determined by performing a data flow analysis using the input and output data information of each JOB.

[0143] Furthermore, the JOB manager may manage TASKs, which are processes with a granularity lower than JOB. For example, management by the JOB manager may include processes that break down a JOB into one or more TASKs, processes that acquire information about the processing status of TASKs executed on hardware resources, and processes that issue instructions for the execution of the one or more broken-down TASKs on the allocated hardware resources. Information about the processing status of TASKs may include, for example, initialization for TASKs, start of TASK execution, management of timers for TASK execution, processes that handle TASK errors, and processes that terminate TASKs. Termination processes may include, for example, a function that receives a TASK termination report from a TASK. Furthermore, instructions for execution may include instructions corresponding to the processing status described above.

[0144] 4.1.2. Resource Manager The resource manager has the function of managing hardware resources for one or more tasks that constitute a job. The resource manager may have a database of the aforementioned resource information associated with the hardware resources and manage the hardware resources.

[0145] The resource manager may store in a database information that identifies one or more tasks constituting a job (e.g., an ID) and the hardware resource on which such tasks are written. Such an ID may be assigned to each bitstream. Furthermore, to put it simply in programming language terms, one ID may be assigned to something like a function. Therefore, a function whose output can change depending on various input information (arguments) may be given when the function is executed may be associated with one ID. The input information resource manager may use this database to determine whether the information identifying the task has already been written to the hardware resource. If it has already been written, the circuit with the information written may be used; if it has not been written, it may be written anew before execution. This association has the advantage of reducing unnecessary writes. Note that one task may be assigned to one FPGA as described above, or one task may be assigned to one PR region within one FPGA.

[0146] The resource manager's management functions may include the function of providing hardware resources for a TASK.

[0147] For example, if a resource manager receives a request from a job manager for hardware resources corresponding to a task, the resource manager may select the hardware resources corresponding to the task and communicate this to the job manager.

[0148] Here, the resource manager may obtain TASK-related information from the JOB manager when selecting hardware resources. TASK-related information may include the resource information described above, for example, the type of reconfigurable device, attributes related to the arithmetic unit, attributes related to the storage device, and / or attributes related to the communication device for executing the TASK. The resource manager may select hardware resources corresponding to the TASK-related information, i.e., hardware resources capable of executing the TASK, from the database of resource information. Here, the selection only needs to be for hardware resources capable of executing the TASK; therefore, the type and model of the reconfigurable device, attributes related to the arithmetic unit, attributes related to the storage device, and / or attributes related to the communication device must match, but the functional aspects of the information such as attributes related to the arithmetic unit, attributes related to the storage device, and / or attributes related to the communication device only need to encompass the functions of the TASK-related information. The resource manager may communicate to the job manager information that identifies the actual hardware resources corresponding to the selected resource information. For example, the resource manager may communicate to the job manager information such as the physical ID of the reconfigurable device to be written to, the network location such as the IP address that identifies such device, and / or the FPGA or network location such as the IP address or port number that identifies the PR region to be written to. In addition, the database may store that such a TASK has been assigned, associated with the information that identifies the assigned hardware resources.

[0149] Here, the resource manager may sequentially perform the following three steps when selecting a system with hardware resources capable of executing the TASK. Performing these steps may offer the advantage of potentially reducing processing time.

[0150] (Step 1) If the TASK to which hardware resources are to be allocated has already been written to the hardware resources, the hardware resources of that operator are allocated. If the operator has already been written, there is an advantage in that the time required to write again can be reduced. Whether or not such a write has already occurred is determined using an ID associated with the TASK, as described above. Furthermore, the decision of whether to use such a write or to write a new one may be made by the user via such ID. In addition, in other cases, when a TASK is being executed using other input information, the system may be configured to choose to allocate such hardware resources, or to choose to allocate other hardware resources. In the latter case, the system may proceed to step 2 below. Such a choice may be determined based on a prediction process that predicts a comparison between the time required to write the bitstream corresponding to the new TASK and the expected completion time of other running TASKs. In addition, the latter processing may be performed only if information such as priority TASK is attached to such TASK. This is to prevent delays caused by the execution of other TASKs, even if the bitstream has already been written, if the TASK should be processed with priority.

[0151] (Step 2) If a TASK to which hardware resources are to be allocated is not already written to the hardware resources, and a PR region in the database to which such ASK can be written can be selected, then the bitstream for the TASK is written to that PR region. Compared to the following three steps, this has the advantage of reducing the compilation time, which may take several hours, by using the information of the partition shell and the newly selected PR region. Here, the criteria for selecting the PR region may be the hardware resource identification process described above.

[0152] (Step 3) If a TASK to which hardware resources are to be allocated is not already written to the hardware resources, and a PR region in the database on which such a TASK can be written cannot be selected, a partition shell is written to an FPGA on which a PR region on which a TASK can be written can be secured. After such a partition shell is written, the TASK is written to the PR region based on such a partition shell. In this case, instead of writing a new partition shell, the TASK may be written to an FPGA on which a hypervisor shell has already been written but a partition shell has not been written, without using a PR region. Even if a PR region on which a TASK can be written can be selected, 1) a partition shell may be written to another FPGA on which a PR region on which a TASK can be written can be secured separately, and the TASK may be written to the PR region based on such a partition shell, or 2) the TASK may be written to an FPGA on which a hypervisor shell has already been written but a partition shell has not been written, without using a PR region. Furthermore, if a TASK to which hardware resources are to be allocated is not already written to the hardware resources, and a PR region in the database on which such a TASK can be written cannot be selected, then, instead of writing the partition shell and / or hypervisor shell, the bitstream corresponding to the TASK may be written to the FPGA using a USB cable or JTAG. In this case, the USB cable may be connected in advance, and the bitstream corresponding to the TASK may be automatically written by the program via JTAG, or a person may connect the USB cable and write the bitstream corresponding to the TASK using JTAG.

[0153] 4.1.3. TASK Manager The TASK manager has the function of managing tasks. The TASK manager manages tasks that are executed within the same FPGA on which the TASK manager is programmed, using instructions from the JOB manager. Alternatively, the TASK manager may communicate the processing status of tasks to the JOB manager.

[0154] The TASK manager may have a table showing the relationship between information indicating a JOB to be executed within the FPGA on which the TASK manager is written and the current execution status of such JOB. Such execution status may include states such as running, not running, and / or suspended.

[0155] Instructions from the JOB Manager may include initialization, start, interrupt, or cancel instructions, associated with information that identifies the JOB.

[0156] Initialization includes the initialization of storage information and / or communication information used by the JOB. Instructions for such initialization may be processed when a new operator is written to the FPGA and / or when a new JOB is executed. When a new operator is written, the storage information and / or communication information may be initialized as one step of the write process, but if the initialization is performed again as one step of the distributed processing, it has the advantage of guaranteeing initialization more effectively. In addition, in the case of a new JOB within the same operator, it has the advantage of not being affected by the processing of a previously executed JOB.

[0157] The "Start" command may instruct the start of a TASK. The TASK manager may obtain the "Start" command from the JOB manager, associated with the parameters used by the operator (input information for executing the TASK). The TASK manager may send the "Start" command, along with the input information for executing the TASK, to the PR region that will execute the TASK to which the "Start" command pertains, thereby instructing it to start the TASK.

[0158] Interruption may simply mean temporarily stopping the execution of the task. The task may resume execution when a restart command is received.

[0159] Furthermore, the TASK manager may communicate the processing status of a TASK, such as abnormal processing of a TASK or completion reports of a TASK, to the JOB manager.

[0160] 4.2. Processing Flow 4.2.1. Example of the first aspect of the processing flow Next, we will explain one example of the system's processing flow, but it goes without saying that various other examples can be implemented.

[0161] First, as a preparatory step, the database related to the resource manager stores information about the actual FPGA. For example, it stores information such as the type of FPGA, attributes related to the arithmetic unit, attributes related to the storage device, and / or attributes related to the communication device, associated with information that identifies the connected physical FPGA. With this configuration, as described above, the resource manager can identify the hardware resources capable of executing the requested JOB. This information may be registered in the database manually or automatically.

[0162] Furthermore, the job manager may maintain a table of information related to each job.

[0163] Step 1 The JOB manager performs a data flow analysis of the jobs and determines which jobs to execute. The JOB manager may perform the data flow analysis using information related to each job. This information may include, for example, the job's input data and output data, or any other information necessary for data flow analysis. The data flow analysis itself may utilize publicly known techniques. Furthermore, the jobs may be compiled to be executable on the FPGA and may be in the form of a bitstream.

[0164] Step 2 The JOB manager queries the resource manager for hardware resources capable of executing the job. The JOB manager may already possess the resource information required for each job. This resource information may be pre-registered by the programmer as necessary for executing each job. Furthermore, if the job is compiled as a bitstream as described above, information such as the assumed FPGA and / or PR region may be included in the resource information and used to select hardware resources.

[0165] Step 3 The resource manager determines the hardware resources required for the JOB to be executed and communicates these hardware resources to the JOB manager. In this case, the three steps described above may be performed.

[0166] Step 4 The JOB manager communicates the bitstream related to the JOB and / or the input information for the JOB execution to the hardware resource corresponding to each JOB. In this case, the partition shell and / or the operator related to the JOB may be written to the corresponding hardware resource in the form of a bitstream or the like. In this case, an FPGA writer and / or a partition shell may be used for writing.

[0167] Step 5 The TASK manager within the hardware resources corresponding to each JOB manages the TASKs included in the JOB and proceeds with the execution of those TASKs.

[0168] 4.2.2. Example of a second aspect of the processing flow Next, we will explain a flow that focuses particularly on the JOB Manager and TASK Manager as one aspect of the processing flow described above. In the following flow, the JOB Manager also performs the role of the resource manager mentioned above. This is an example that uses an FPGA programmer, but such functionality can be implemented anywhere except within the reconfigurable device.

[0169] First, as shown in Figure 12, the JOB Manager 01 sends the bitstream information that will be used by FPGAs 03A and 03B to the FPGA Writer 02.

[0170] Next, as shown in Figure 13, FPGA writer 02 sends the bitstream to FPGAs 03A and 03B and writes to them respectively.

[0171] Then, as shown in Figure 14, the JOB manager 01 transmits a task start command to each TASK manager in FPGAs 03A and 03B, which are the execution locations for the tasks, and each TASK manager starts execution in the processing circuit within the same FPGA.

[0172] In the example above, the bitstream was shown as being sent from the JOB manager. However, once the JOB to be executed and the hardware resource where it will be executed are determined within the JOB manager, the bitstream corresponding to that JOB may be stored and used in the storage, database, or storage system of the information processing device on which the FPGA writer is running.

[0173] 4.2.3. Example of the third aspect of the processing flow Next, as an example of distributed processing, we will explain an example of summing numbers from 1 to 1000.

[0174] In this example, as shown in Figure 15, the system may include a server 01 equipped with a JOB manager implemented in a programmable device, a server 02 connected via a network that includes a programmable device implementing an FPGA writer and an FPGA connected to the programmable device via PCIe, and a server 03 equipped with an FPGA. This configuration is just one example, and the number of FPGAs in the servers is not limited to two, but can be one or more. The number of servers containing FPGAs connected to FPGA writers is also not limited to two, but can be one or more. The network configuration can also vary.

[0175] Next, Figure 16 shows the state in which the bitstream to be written to the FPGA is sent from the JOB manager to the FPGA writer in server 02. Here, the bitstreams used for each FPGA may be the same or different. For example, in this example, as will be described later, it is assumed that the sum of 1 to 1000 will be calculated by dividing it into 1 to 250, 251 to 500, 501 to 750, and 751 to 1000. The bitstream for the FPGA that performs the calculation of each of these divided parts and returns the result may be different from the bitstream for the FPGA that performs the calculation of each of these divided parts plus the sum of them. Furthermore, even in the former case, if the type of FPGA to be written to or the functions within the FPGA are different, the bitstream may be appropriate for those.

[0176] Next, Figure 17 shows how the FPGA writer writes a bitstream to each FPGA. Here, the bitstream to each FPGA may be written via an interconnect such as PCIe, USB, JTAG, Ethernet, or Infiniband. Furthermore, these writes may occur on the same server as the FPGA writer, or on a different server.

[0177] Next, Figure 18 shows the state in which a task start command is transmitted from the JOB manager to the task manager in each FPGA. In this step, input information used for the task may also be transmitted. For example, in this example, input information such as 1 to 250, 251 to 500, 501 to 750, and 751 to 1000 may be transmitted.

[0178] Next, Figure 19 shows that, in response to instructions from the TASK manager, the processing circuits in each FPGA, to which the bitstream has been written, execute the task. For example, in this example, calculations may be performed for parts 1 to 250, 251 to 500, 501 to 750, and 751 to 1000.

[0179] Next, Figure 20 shows a state in which the results calculated within each FPGA are transmitted to the processing circuit of a task within a single FPGA, and these results are summed up. For example, each result calculated by FPGA04A to 04C may be transmitted to FPGA04D. In this case, the location of FPGA04D on the network may be determined in advance based on data flow analysis by the JOB manager. Such network locations may be included in the bitstream and written to each FPGA, or they may be transmitted to each FPGA as input information to the task indicating the destination of the transmission of processing results along with the start command for each task.

[0180] Finally, Figure 21 shows the state in which each task manager within the FPGA communicates to the JOB manager that the execution of each task has been completed.

[0181] 4.3. Other Examples One embodiment of this system is A distributed processing management system comprising a JOB manager and a resource manager, The JOB manager retrieves multiple JOBs, including one or more JOBs to be executed on the FPGA. The resource manager selects the resource corresponding to the JOB, The JOB manager is a system that assigns the JOB to the resource, If the resource manager is a bitstream job that is executed by writing a bitstream onto the FPGA, it selects a corresponding bitstream from among multiple bitstreams related to the bitstream job that corresponds to the PR region to which the bitstream job is assigned. It can be a distributed processing system. Furthermore, if the JOB is a bitstream JOB that is executed by writing a bitstream onto the FPGA, The aforementioned resource manager is If the bitstream capable of executing the JOB is written to the FPGA, the information corresponding to the written location is transmitted to the JOB manager. If the bitstream capable of executing the JOB has a writable PR region that has not been written to the FPGA, then information including information indicating the writable PR region is transmitted to the JOB manager. If the bitstream capable of executing the JOB has not been written to the FPGA and there are no writable PR regions, information including information indicating the writable region is transmitted to the JOB manager. It can be a distributed processing system.

[0182] 5. System 4 The fourth system relates to a development tool technology for developing bitstreams that users write to the first system described above. When a user develops a program to be executed on an FPGA and then writes the program to the FPGA, the program written in a hardware description language or high-level synthesis language (sometimes referred to as an "HDL program or HLS program" in this application) must be compiled into a bitstream that can be written to the FPGA. This bitstream must correspond to resource information such as the FPGA type and PR region, and a bitstream that does not correspond to resource information such as the FPGA type and PR region cannot be written to an FPGA with uncorresponding resource information. In this case, the HDL program or HLS program must be compiled into a bitstream for the FPGA to be written to, and depending on the HDL program or HLS program, compilation time may be several hours or more. Therefore, in the first system, if a user has secured hardware corresponding to specific resource information, but a bitstream corresponding to the secured hardware has not been generated, it will take time to generate the bitstream, during which time the secured hardware will remain unused. This is an inefficient use of hardware resources, and if the user is charged by the hour, costs will be incurred even though the hardware is not being used. Therefore, the fourth system addresses these challenges and improves the efficiency of hardware resource utilization. As mentioned above, the following explanation will primarily use FPGAs, but it can also be implemented using reconfigurable devices instead of FPGAs.

[0183] Furthermore, the fourth system may be based on the first system described above and associated with the fourth system. On the other hand, the fourth system may be a system in an environment where the first system is not implemented.

[0184] 5.1. Example Configuration The fourth system may be directly or indirectly connected to the hardware information provider and the compilation device described later, via a network or the like.

[0185] The fourth system may be a system used by a user. The fourth system may be a terminal device used by a user, an information processing device accessed by a terminal used by a user, or a program executed on such devices.

[0186] 5.2. Functional Examples An example of the fourth system may include a user interface unit, a hardware information provider communication unit, and / or a compiler communication unit, as shown in Figure 22.

[0187] 5.2.1. User Interface Section The user interface unit may obtain information from the user. For example, it may obtain instructions from the user to update information about the flavor.

[0188] Furthermore, the user interface may provide information to the user.

[0189] Furthermore, updates to flavor information may be provided not only at the user's request, but also according to predetermined conditions. These predetermined conditions may include, for example, updates at predetermined regular intervals.

[0190] 5.2.2. Hardware Information Provisioning Device Communication Section The hardware information provider communication unit may have the function to communicate with a system capable of providing hardware information, which is different from the fourth system. The device capable of providing hardware information (sometimes referred to as the "hardware information provider" in this application) may be the first system described above, or it may not be the first system described above. The hardware information provider only needs to have the function to provide information that identifies the FPGA or PR region within the FPGA on which the HDL program or HLS program is written.

[0191] The hardware information provider communication unit may, in response to predetermined conditions, request from the hardware information provider information that identifies the FPGA or PR region within the FPGA on which the HDL program or HLS program is written (sometimes referred to as "hardware identification information" in this application). Here, the hardware identification information may be resource information identified to the extent that the bitstream on which the HDL program or HLS program is compiled can be written. For example, the hardware information may be resource information that allows the same bitstream to be written even on different hardware, such as resource information that includes information identifying the PR region. This is because resource information that does not include the PR region cannot write the same bitstream if the PR region is different. The specified conditions may include when information for a flavor update is obtained from the user. Furthermore, the specified conditions may include when a specified temporal condition is met. The specified temporal condition may be at predetermined regular intervals. Furthermore, the specified temporal condition may be a predetermined date and time.

[0192] The hardware information provider communication unit may have a function to acquire hardware-specific information from the hardware information provider. The hardware information provider communication unit may acquire the hardware-specific information in response to the above-mentioned request, or it may acquire it without making the above-mentioned request. In the latter case, for example, the hardware information provider may transmit the hardware-specific information to the fourth system based on predetermined conditions, and the hardware information provider communication unit may acquire the hardware-specific information in response to such transmission.

[0193] The hardware identification information acquired by the hardware information provider's communication unit may be hardware identification information for all hardware that the hardware information provider can provide, or it may be hardware identification information for only a portion of the hardware that the hardware information provider can provide. Such a portion may be selected based on information about the hardware available to the user among the hardware provided by the hardware information provider. For example, such a portion of the hardware identification information may be selected from the hardware available to a member if the user using the compiled HDL program or HLS program is a designated member. Such selection may be based on predetermined criteria. Such predetermined criteria may be, for example, those which allow the administrator of the first system to select the hardware that the user wants to use from among the hardware available to the user.

[0194] 5.2.3. Compiler Communication Section The compiler communication unit has the function of communicating with a compiler outside of the fourth system. The compiler communication unit may have the function of sending compilation instructions to the compiler. The compiler communication unit may send to the compiler information used for compilation in connection with the compilation instructions. Such information may include, for example, the HDL program or HLS program to be compiled, and / or hardware-specific information on which the compiled bitstream is written.

[0195] The compiler communication unit may obtain the compilation result from the compiler after compilation is complete. The compilation result may include an intermediate design file. The intermediate design file may include information on placement and routing with parts other than the target PR region. For example, if the hardware-specific information includes PR region 1 of the first FPGA, the corresponding intermediate design file may include routing information with parts of the first FPGA other than PR region 1 of the first FPGA. If the hardware-specific information includes multiple PR regions, the corresponding intermediate design file may include routing information with parts of the FPGA other than each of the PR regions corresponding to each of the multiple PR regions (parts containing each PR region). Furthermore, the compilation result may include information in the form of a bitstream. The compilation result may include information in the form of multiple partial bitstreams.

[0196] 5.3. Example of a processing flow Next, we will explain the processing flow of one example of the system in this example using Figure 23. However, the processing of the functions of the system in this example is not limited to this flow, and a variety of processing is possible.

[0197] First, the fourth system, which is the system in this example, receives instructions from the user to update hardware-specific information (Step 1).

[0198] Next, the system in this example instructs the hardware information provider to update the hardware-specific information (Step 2).

[0199] Next, the system in this example obtains hardware-specific information from a hardware information provider and updates it (step 3). For example, the system in this example obtains hardware-specific information from a hardware information provider. Note that step 3 may be performed without steps 1 and / or 2, in which case steps 1 and 2 may or may not be performed.

[0200] Next, the system in this example transmits information from the user regarding the HDL program to be compiled (including the HDL program or HLS program, and / or information identifying the HDL program or HLS program; the same applies hereinafter) and hardware identification information to the compilation device (Step 4). Here, the hardware identification information may be all of the hardware identification information that the system in this example possesses, or it may be only a part of it. The advantage is that the more hardware identification information to be compiled, the more writable targets there will be. On the other hand, if only a part is included, the number of writable targets will be smaller, but the total compilation time will be shorter.

[0201] The compilation device performs compilation using information related to the HDL program to be compiled and hardware-specific information (Step 5). In this case, the compilation device may compile for all hardware-specific information, or it may compile using a predetermined range of hardware-specific information. The advantage is that the more hardware-specific information to compile, the more writable targets there will be. On the other hand, if it is limited to a predetermined range, the number of writable targets will decrease, but the advantage is that the total compilation time will be shortened.

[0202] The compilation device sends the compilation results to the system in this example, and the system in this example retrieves the compilation results from the compilation device (step 6).

[0203] Furthermore, the process may be carried out as described in the first system. For example, if the system in this example is connected to the first system, the system in this example may select one or more resource pieces of information within the flavor and request the first system to reserve the corresponding hardware resources. If the first system successfully reserves the corresponding hardware resources, it may register the information in the database and transmit the information of the reserved hardware resources to the system in this example. The information of the reserved hardware resources may include, for example, information on which a partition shell has been written and information that identifies an available PR region. Such information that identifies an available PR region may include a network address relating to the PR region, such as an IP address or MAC address, the ID of the PR region, and / or information that identifies the FPGA containing the PR region.

[0204] An example of a fourth system is: A user interface unit that provides information to and / or obtains information from the user, A hardware-specific information providing device communication unit having the function to communicate with the first system or hardware-specific information providing device, A compiler communication unit having the capability to communicate with a compiler that can convert an HDL program or HLS program into a bitstream writable to an FPGA, It may be provided.

[0205] 6. Various Mechanisms The system according to the first embodiment is: An acquisition unit that obtains information indicating the first resource from the user, A specification unit that identifies a first reconfigurable device corresponding to the information indicating the first resource, An instruction unit that instructs the first reconfigurable device to write a first partition shell corresponding to information indicating the first resource, It is a system equipped with [a specific feature / feature].

[0206] The system according to the second embodiment is as described in the first embodiment above. The acquisition unit acquires information indicating a second resource that is not identical to the information indicating the first resource, The instruction unit instructs the first reconfigurable device to write to a second partition shell, which corresponds to information indicating the second resource and is different from the first partition shell.

[0207] The system according to the third embodiment is, in the first embodiment or the second embodiment described above, The system further includes a presentation unit that presents one or more resource information to the user, The information indicating the first resource is a part of the presented information of one or more reconfigurable device resources.

[0208] A system according to the fourth embodiment is as described in any one of the first to third embodiments above. The aforementioned display unit presents multiple configuration methods for setting the PR region for the first reconfigurable device.

[0209] The system according to the fifth embodiment is one in which, according to any one of the first to fourth embodiments described above, "the one or more resource information includes information relating to a calculation function, information relating to a storage function, and / or information relating to a communication function."

[0210] The system according to the sixth embodiment is as follows in any one of the first to fifth embodiments: The acquisition unit acquires information indicating a third resource that is not the same as the information indicating the first resource and the information indicating the second resource. The identification unit corresponds to information indicating the third resource and identifies a third reconfigurable device that is different from the first reconfigurable device. The instruction unit instructs the third reconfigurable device to write a third partition shell corresponding to the information indicating the third resource.

[0211] The system according to the seventh aspect is described in any one of the first to sixth aspects above as " The system includes a database that stores, in association with at least information indicating the first resource and information indicating the first reconfigurable device corresponding to the information indicating the first resource.

[0212] The system according to the eighth aspect is described in any one of the first to seventh aspects above. The first reconfigurable device is pre-written with a hypervisor shell that has functions not present in the first partition shell.

[0213] A system according to the ninth aspect is, in any one of the first to eighth aspects described above, The system includes a query unit that queries the status of the first PR region corresponding to the hypervisor shell, The hypervisor shell is capable of responding to inquiries from the inquiry unit regarding the status of the first PR region.

[0214] A system according to the tenth embodiment is, in any one embodiment of the first to ninth above, The aforementioned hypervisor shell has a function to verify permissions for the PR region to which the user is writing.

[0215] The system according to the 11th embodiment is such that, in any one of the first to tenth embodiments described above, "the hypervisor shell has a function to verify the authority of a PR region to which a user writes, which may include an initialization function for the storage function and / or communication function related to the first reconfigurable device."

[0216] The method according to the 12th aspect is: The system Steps include obtaining information from the user that indicates the first resource, The steps include identifying a first reconfigurable device corresponding to information indicating the first resource, The steps include instructing the first reconfigurable device to write a first partition shell corresponding to information indicating the first resource, This is "How to execute it."

[0217] The method according to the 13th embodiment is the one in which "the system stores information that identifies a first reconfigurable device corresponding to information indicating the first resource."

[0218] A computer program according to the 14th aspect is: The system A means of obtaining information from the user indicating the first resource, Means for identifying a first reconfigurable device corresponding to information indicating the first resource, Means for instructing the first reconfigurable device to write a first partition shell corresponding to information indicating the first resource, It is a program designed to operate as such.

[0219] A computer program according to the 15th embodiment is such that, in the 14th embodiment, "the system stores information that identifies a first reconfigurable device corresponding to information indicating the first resource."

[0220] 7. Example configuration of a programmable device As shown in Figure 24, the programmable device 10 may include an arithmetic unit 12, a storage device 13, a communication interface 16, and a bus 11 connecting them. The programmable device 10 may also further include an input device 14, a display device 15, and a bus 11 connecting them as well. Furthermore, the programmable device 10 may be directly or indirectly connected to other information processing devices via a network 19.

[0221] The programmable device 10 may be an information processing device such as a server or a cloud. It may be a dedicated device or a general-purpose device. Furthermore, the programmable device 10 itself may be a reconfigurable device in which the circuit has been programmed. In this case, there is an advantage in that the programs of the various embodiments described above can be executed more quickly.

[0222] Although the above description refers to the configuration implemented by the system in this example, these configurations may also be implemented by one or more information processing devices within the system. Furthermore, the system relating to this application may be presented in various forms. For example, presentation may include display. For instance, the system in this example may be displayed by a display device included in the system in this example, or it may be displayed by a display device in another information processing device to which the system in this example is directly or indirectly connected.

[0223] It goes without saying that the examples of the invention described in the embodiments of this application are not limited to those described in this application, but can be applied to various examples within the scope of their technical idea.

[0224] Furthermore, the processes and procedures described in this application may be implemented not only by those explicitly described in the embodiments, but also by software, hardware, or a combination thereof. The processes and procedures described in this application may also be implemented as computer programs and executed by various computers. These computer programs may be stored on storage media. These programs may also be stored on non-transient or temporary storage media.

Claims

1. One or more PR regions, A hypervisor shell written to a reconfigurable device has a function to support communication functions relating to the aforementioned one or more PR regions, A reconfigurable device equipped with, The hypervisor shell includes a table of destination relationships for communications related to the communication function, The hypervisor shell uses the table for the communication function. Reconfigurable device.

2. One or more PR regions, A hypervisor shell written to a reconfigurable device has a function to support communication functions relating to the aforementioned one or more PR regions, A reconfigurable device equipped with, The hypervisor shell includes a table of destination relationships for communications related to the communication function, The hypervisor shell uses the table for the communication function, The aforementioned destination relationship table is: The one or more PR regions within the reconfigurable device, The destination within the user's application relating to the one or more PR regions within the reconfigurable device, and / or The computation entity outside the reconfigurable device, Includes the elements of Reconfigurable device.

3. One or more PR regions, A hypervisor shell written to a reconfigurable device has a function to support communication functions relating to the aforementioned one or more PR regions, A reconfigurable device equipped with, The hypervisor shell has a function related to writing to the partition shell in the reconfigurable device. Reconfigurable device.

4. One or more PR regions, A hypervisor shell written to a reconfigurable device has a function to support communication functions relating to the aforementioned one or more PR regions, A reconfigurable device equipped with, The hypervisor shell has a function relating to write permissions for the PR region within the reconfigurable device. Reconfigurable device.

5. One or more PR regions, A hypervisor shell written to a reconfigurable device has a function to support communication functions relating to the aforementioned one or more PR regions, A reconfigurable device equipped with, The hypervisor shell has an initialization function that initializes at least a portion of the reconfigurable device. Reconfigurable device.

6. One or more PR regions, A hypervisor shell written to a reconfigurable device has a function to support communication functions relating to the aforementioned one or more PR regions, A reconfigurable device equipped with, The hypervisor shell has an initialization function that initializes at least a portion of the reconfigurable device, The initialization includes an initialization function for the storage function and / or communication function relating to the PR region within the reconfigurable device. Reconfigurable device.

7. The reconfigurable device includes rewritable circuitry. A reconfigurable device according to any one of claims 1 to 6.

8. The reconfigurable device includes a circuit, A reconfigurable device according to any one of claims 1 to 6.

9. The hypervisor shell written to the reconfigurable device performs the step of supporting communication functions relating to one or more PR regions within the reconfigurable device. It is a method, The hypervisor shell includes a table of destination relationships for communications related to the communication function, The hypervisor shell uses the table for the communication function. method.

10. The hypervisor shell written to the reconfigurable device performs the step of supporting communication functions relating to one or more PR regions within the reconfigurable device. It is a method, The hypervisor shell includes a table of destination relationships for communications related to the communication function, The hypervisor shell uses the table for the communication function, The aforementioned destination relationship table is: The one or more PR regions within the reconfigurable device, The destination within the user's application relating to the one or more PR regions within the reconfigurable device, and / or The computation entity outside the reconfigurable device, Includes the elements of method.

11. The hypervisor shell written to the reconfigurable device performs the step of supporting communication functions relating to one or more PR regions within the reconfigurable device. It is a method, The hypervisor shell has a function related to writing to the partition shell in the reconfigurable device. method.

12. The hypervisor shell written to the reconfigurable device performs the step of supporting communication functions relating to one or more PR regions within the reconfigurable device. It is a method, The hypervisor shell has a function relating to write permissions for the PR region within the reconfigurable device. method.

13. The hypervisor shell written to the reconfigurable device performs the step of supporting communication functions relating to one or more PR regions within the reconfigurable device. It is a method, The hypervisor shell has an initialization function that initializes at least a portion of the reconfigurable device. method.

14. The hypervisor shell written to the reconfigurable device performs the step of supporting communication functions relating to one or more PR regions within the reconfigurable device. It is a method, The hypervisor shell has an initialization function that initializes at least a portion of the reconfigurable device, The initialization includes an initialization function for the storage function and / or communication function relating to the PR region within the reconfigurable device. method.

15. The reconfigurable device includes rewritable circuitry. The method according to any one of claims 9 to 14.

16. The reconfigurable device includes a circuit, The method according to any one of claims 9 to 14.

17. A identifying unit that identifies a reconfigurable device having one or more PR regions, An instruction unit that instructs the reconfigurable device to write a hypervisor shell having a function to support communication functions related to the one or more PR regions, A system equipped with, The hypervisor shell includes a table of destination relationships for communications related to the communication function, The hypervisor shell uses the table for the communication function. system.

18. A identifying unit that identifies a reconfigurable device having one or more PR regions, An instruction unit that instructs the reconfigurable device to write a hypervisor shell having a function to support communication functions related to the one or more PR regions, A system equipped with, The hypervisor shell includes a table of destination relationships for communications related to the communication function, The hypervisor shell uses the table for the communication function, The aforementioned destination relationship table is: The one or more PR regions within the reconfigurable device, The destination within the user's application relating to the one or more PR regions within the reconfigurable device, and / or The computation entity outside the reconfigurable device, Includes the elements of system.

19. A identifying unit that identifies a reconfigurable device having one or more PR regions, An instruction unit that instructs the reconfigurable device to write a hypervisor shell having a function to support communication functions related to the one or more PR regions, A system equipped with, The hypervisor shell has a function related to writing to the partition shell in the reconfigurable device. system.

20. A identifying unit that identifies a reconfigurable device having one or more PR regions, An instruction unit that instructs the reconfigurable device to write a hypervisor shell having a function to support communication functions related to the one or more PR regions, A system equipped with, The hypervisor shell has a function relating to write permissions for the PR region within the reconfigurable device. system.

21. A identifying unit that identifies a reconfigurable device having one or more PR regions, An instruction unit that instructs the reconfigurable device to write a hypervisor shell having a function to support communication functions related to the one or more PR regions, A system equipped with, The hypervisor shell has an initialization function that initializes at least a portion of the reconfigurable device. system.

22. A identifying unit that identifies a reconfigurable device having one or more PR regions, An instruction unit that instructs the reconfigurable device to write a hypervisor shell having a function to support communication functions related to the one or more PR regions, A system equipped with, The hypervisor shell has an initialization function that initializes at least a portion of the reconfigurable device, The initialization includes an initialization function for the storage function and / or communication function relating to the PR region within the reconfigurable device. system.

23. The reconfigurable device includes rewritable circuitry. The system according to any one of claims 17 to 22.

24. The reconfigurable device includes a circuit, The system according to any one of claims 17 to 22.

25. The system The steps include identifying a reconfigurable device having one or more PR regions, The steps include instructing the reconfigurable device to write a hypervisor shell having a function to support communication functions related to the one or more PR regions, A method for performing the following: The hypervisor shell includes a table of destination relationships for communications related to the communication function, The hypervisor shell uses the table for the communication function. method.

26. The system The steps include identifying a reconfigurable device having one or more PR regions, The steps include instructing the reconfigurable device to write a hypervisor shell having a function to support communication functions related to the one or more PR regions, A method for performing the following: The hypervisor shell includes a table of destination relationships for communications related to the communication function, The hypervisor shell uses the table for the communication function, The aforementioned destination relationship table is: The one or more PR regions within the reconfigurable device, The destination within the user's application relating to the one or more PR regions within the reconfigurable device, and / or The computation entity outside the reconfigurable device, Includes the elements of method.

27. The system The steps include identifying a reconfigurable device having one or more PR regions, The steps include instructing the reconfigurable device to write a hypervisor shell having a function to support communication functions related to the one or more PR regions, A method for performing the following: The hypervisor shell has a function related to writing to the partition shell in the reconfigurable device. method.

28. The system The steps include identifying a reconfigurable device having one or more PR regions, The steps include instructing the reconfigurable device to write a hypervisor shell having a function to support communication functions related to the one or more PR regions, A method for performing the following: The hypervisor shell has a function relating to write permissions for the PR region within the reconfigurable device. method.

29. The system The steps include identifying a reconfigurable device having one or more PR regions, The steps include instructing the reconfigurable device to write a hypervisor shell having a function to support communication functions related to the one or more PR regions, A method for performing the following: The hypervisor shell has an initialization function that initializes at least a portion of the reconfigurable device. method.

30. The system The steps include identifying a reconfigurable device having one or more PR regions, The steps include instructing the reconfigurable device to write a hypervisor shell having a function to support communication functions related to the one or more PR regions, A method for performing the following: The hypervisor shell has an initialization function that initializes at least a portion of the reconfigurable device, The initialization includes an initialization function for the storage function and / or communication function relating to the PR region within the reconfigurable device. method.

31. The reconfigurable device includes rewritable circuitry. The method according to any one of claims 25 to 30.

32. The reconfigurable device includes a circuit, The method according to any one of claims 25 to 30.

33. The system Means for identifying a reconfigurable device comprising one or more PR regions, Means for instructing the reconfigurable device to write a hypervisor shell having a function to support communication functions relating to the one or more PR regions, A computer program for making it work as The hypervisor shell includes a table of destination relationships for communications related to the communication function, The hypervisor shell uses the table for the communication function. Computer program.

34. The system Means for identifying a reconfigurable device comprising one or more PR regions, Means for instructing the reconfigurable device to write a hypervisor shell having a function to support communication functions relating to the one or more PR regions, A computer program for making it work as The hypervisor shell includes a table of destination relationships for communications related to the communication function, The hypervisor shell uses the table for the communication function, The aforementioned destination relationship table is: The one or more PR regions within the reconfigurable device, The destination within the user's application relating to the one or more PR regions within the reconfigurable device, and / or The computation entity outside the reconfigurable device, Includes the elements of Computer program.

35. The system Means for identifying a reconfigurable device comprising one or more PR regions, Means for instructing the reconfigurable device to write a hypervisor shell having a function to support communication functions relating to the one or more PR regions, A computer program for making it work as The hypervisor shell has a function related to writing to the partition shell in the reconfigurable device. Computer program.

36. The system Means for identifying a reconfigurable device comprising one or more PR regions, Means for instructing the reconfigurable device to write a hypervisor shell having a function to support communication functions relating to the one or more PR regions, A computer program for making it work as The hypervisor shell has a function relating to write permissions for the PR region within the reconfigurable device. Computer program.

37. The system Means for identifying a reconfigurable device comprising one or more PR regions, Means for instructing the reconfigurable device to write a hypervisor shell having a function to support communication functions relating to the one or more PR regions, A computer program for making it work as The hypervisor shell has an initialization function that initializes at least a portion of the reconfigurable device. Computer program.

38. The system Means for identifying a reconfigurable device comprising one or more PR regions, Means for instructing the reconfigurable device to write a hypervisor shell having a function to support communication functions relating to the one or more PR regions, A computer program for making it work as The hypervisor shell has an initialization function that initializes at least a portion of the reconfigurable device, The initialization includes an initialization function for the storage function and / or communication function relating to the PR region within the reconfigurable device. Computer program.

39. The reconfigurable device includes rewritable circuitry. A computer program according to any one of claims 33 to 38.

40. The reconfigurable device includes a circuit, A computer program according to any one of claims 33 to 38.

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