Memory copy size determination command and data transfer command

JP7863564B2Active Publication Date: 2026-05-21ARM LTD
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Patent Information

Authority / Receiving Office
JP · JP
Patent Type
Patents
Current Assignee / Owner
ARM LTD
Filing Date
2021-12-13
Publication Date
2026-05-21

AI Technical Summary

Technical Problem

Existing data processing systems face inefficiencies and high overhead when copying data between memory locations due to the complexity of implementing functions like memcpy() in compiled machine code, particularly in load/store architectures, which require numerous branch instructions and are difficult to optimize across different microarchitectures.

Method used

A dedicated memory copy size determination instruction that calculates a subset of bytes to be copied based on source and destination memory addresses, reducing the need for branch instructions and optimizing memory copy operations according to hardware constraints and alignment conditions.

Benefits of technology

This approach significantly reduces the number of instructions required, improves efficiency by aligning memory accesses, and allows for microarchitecture-independent implementations, thus lowering development effort and power consumption.

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Abstract

An apparatus, method, and computer program are described, the apparatus comprising a decode circuit configured to decode instructions, and a processing circuit configured to perform data processing in response to the instructions decoded by the decode circuit. In response to the decode circuit decoding a memory copy size determination instruction specifying as operands a source memory address, a destination memory address, and a total number of bytes to be copied from a source block of a memory location indicated by the source memory address to a destination block of a memory location indicated by the destination memory address, the processing circuit is configured to determine a memory copy size indication value indicative of a subset of the total number of bytes to be copied based on at least one of the source memory address and the destination memory address. A data transfer instruction is also described.
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