Plasma Uniformity Control in Pulsed DC Plasma Chambers

Abstract

The embodiments provided herein generally include apparatus, e.g., plasma processing systems, and methods for plasma processing a substrate in a processing chamber. In some embodiments, aspects of the apparatus and methods are directed to improving process uniformity across a surface of a substrate, reducing the defect rate of the surface of the substrate, or both. In some embodiments, the apparatus and methods provide improved control over the uniformity of the plasma formed on the edge of the substrate and / or the distribution of ion energy at the surface of the substrate. The improved plasma uniformity control can be used in combination with substrate handling methods, e.g., dechucking methods, to reduce particulate-related defects on the substrate surface. In some embodiments, the improved control of plasma uniformity is used to preferentially clean accumulated processing by-products from a portion of an edge ring during an in-situ plasma chamber cleaning process.

Description

[Technical Field]

[0001]

[0001] Embodiments described herein relate to plasma generating gas or vapor-electric space discharge devices used in semiconductor device manufacturing, particularly processing chambers configured to generate capacitively coupled plasma of a gas or vapor material supplied to a chamber space and to process a semiconductor substrate in that space. [Background technology]

[0002]

[0002] Reliably manufacturing high aspect ratio features is one of the key technical challenges for next-generation semiconductor devices. One method for forming high aspect ratio features is to use a plasma-assisted etching process, such as reactive ion etching (RIE), to transfer openings in the masking layer to the exposed portions of the substrate surface beneath.

[0003]

[0003] In a typical plasma-assisted etching process, the substrate is placed on a substrate support such as an electrostatic chuck (ESC) located in a processing chamber, plasma is formed on the substrate, and ions are accelerated from the plasma toward the substrate across a plasma sheath formed between the plasma and the substrate surface, i.e., an electron-depleted region. The openings in the mask layer are transferred to the substrate surface through a combination of chemical and physical interactions with plasma-generated neutrons and colliding ions, which provides anisotropic etching. The processing results on the substrate surface depend, in particular, on the properties of the plasma and plasma sheath formed thereon.

[0004]

[0004] In many cases, a plasma chamber is configured to form a capacitively coupled plasma and to control the plasma sheath using two or more radio frequency (RF) powers. For example, a high-frequency component is used to ignite and maintain the plasma and determine the plasma density and, consequently, the ion flux at the substrate surface, while a low-frequency component is used to control the voltage drop across the plasma sheath.

[0005]

[0005] Unfortunately, non-uniformity in plasma density and / or plasma sheath shape can lead to undesirable variations in etched feature profiles (non-uniform processing from the center to the edges of the substrate). Excessive processing non-uniformity can negatively impact and suppress device yield (the percentage of devices that meet performance specifications out of the total number of devices manufactured on the substrate). Such non-uniformity is often particularly pronounced near the substrate edges and can be caused in particular by non-uniform power distribution, variations in chamber shape dimensions, differences in surface material properties, and / or electrical discontinuities between the substrate edges and the surfaces of ESCs located adjacent to them.

[0006]

[0006] Furthermore, undesirable processing by-products often accumulate on the surface of chamber components, such as in the gap between the substrate edge and the edge ring surrounding the substrate during processing. The accumulated processing by-products can migrate to the bevel edge of the substrate and / or cause undesirable arc discharges between the bevel edge of the substrate and the edge ring, further reducing device yield and / or decreasing chamber productivity.

[0007]

[0007] Therefore, there is a need in the art for apparatus and methods to improve the uniformity of processing and defect rate at the edges of substrates during plasma-assisted processing. Furthermore, there is a need for systems, devices, and methods to solve the above-mentioned problems. [Overview of the Initiative]

[0008]

[0008] Embodiments provided herein generally include apparatus, such as plasma treatment systems, and methods for plasma treatment of substrates in a treatment chamber. In some embodiments, the apparatus and methods are intended to improve uniformity of treatment across the entire surface of the substrate, reduce the defect rate on the surface of the substrate, or both.

[0009]

[0009] In one embodiment, the plasma processing system is a substrate support assembly comprising: a support base; a first electrode disposed on the support base and spaced apart from the support base by a first portion of dielectric material; a second portion of dielectric material disposed on the first electrode and forming a substrate support surface; and a second electrode spaced apart from the center of the first electrode and spaced apart from the support base by a third portion of dielectric material. The substrate support assembly comprises: one or more pulse voltage waveform generators electrically connected to a first electrode and a second electrode; a high-frequency (RF) generator electrically connected to a support base, wherein the RF generator is configured to supply an RF signal to the support base, the RF signal establishing a first RF waveform on the first electrode; and an edge tuning circuit electrically connected to the second electrode, wherein the edge tuning circuit is configured to adjust one or more characteristics of a second RF waveform established on the second electrode with respect to one or more characteristics of a first RF waveform established on the first electrode.

[0010]

[0010] In one embodiment, the plasma processing system is a processing chamber which may include a chamber lid, one or more chamber walls, and a substrate support assembly that collectively define a processing area, wherein the substrate support assembly includes a support base, a first electrode disposed on the support base and spaced away from the support base by a first portion of dielectric material, a second portion of dielectric material disposed on the first electrode and forming a substrate support surface, and a second portion of dielectric material spaced away from the center of the first electrode and spaced away from the support base by a third portion of dielectric material The processing chamber may include electrodes; a radio frequency (RF) generator electrically connected to a support base, the RF generator configured to supply an RF signal to the support base, the RF signal configured to ignite and maintain a plasma of gas or vapor supplied to the processing area, and the RF signal configured to establish a first RF waveform on a first electrode; and an edge tuning circuit electrically connected to a second electrode, the edge tuning circuit configured to adjust one or more characteristics of a second RF waveform established on the second electrode to one or more characteristics of a first RF waveform established on the first electrode.

[0011]

[0011] In one embodiment, the processing method comprises: (i) generating a plasma of a gas or vapor supplied to a processing region defined by a chamber lid and a substrate support assembly by using an RF signal from an RF generator, wherein the substrate support assembly comprises a support base electrically connected to the RF generator, a first electrode disposed on the support base and spaced from the support base by a first portion of a dielectric material, wherein the RF signal establishes a first RF waveform at the first electrode, a second portion of the dielectric material disposed on the first electrode and forming a substrate support surface, and a second electrode disposed at a distance from the center of the first electrode, spaced from the support base by a third portion of the dielectric material, and electrically connected to an edge tuning circuit, and generating a plasma of the gas or vapor; and (ii) establishing a second RF waveform at the second electrode by using the RF signal and a tuning circuit, wherein one or more characteristics of the first RF waveform are different from the characteristics of the second RF waveform.

[0012]

[0012] Other embodiments include corresponding computer systems, apparatuses, and computer programs recorded on one or more computer storage devices, each configured to perform the operations of the method.

[0013]

[0013] However, it should be noted that the accompanying drawings show only exemplary embodiments and should not be considered as limiting the scope of the present disclosure, and other equally valid embodiments may be acceptable. However, it should be noted that the accompanying drawings show only exemplary embodiments and should not be considered as limiting the scope of the present disclosure, and other equally valid embodiments may be acceptable.

Brief Description of the Drawings

[0014] [Figure 1A]

[0014] This is a schematic cross-sectional view of one or more embodiments of a processing system configured to carry out the methods described herein. [Figure 1B] This is a schematic cross-sectional view of one or more embodiments of a processing system configured to perform the methods described herein. [Figure 1C]

[0015] This is a close schematic cross-sectional view of a portion of the processing system shown in Figure 1A, according to one embodiment. [Figure 2]

[0016] This is a simplified schematic diagram of a biasing and edge control scheme that can be used with one or both of the processing systems shown in Figures 1A-1B, according to one or more embodiments. [Figure 3A]

[0017] An exemplary edge tuning circuit, which can be used with one or both of the processing systems shown in Figures 1A-1B, according to one or more embodiments, is schematically shown. [Figure 3B] An exemplary edge tuning circuit, which can be used with one or both of the processing systems shown in Figures 1A-1B, according to one or more embodiments, is schematically shown. [Figure 3C] An exemplary edge tuning circuit, which can be used with one or both of the processing systems shown in Figures 1A-1B, according to one or more embodiments, is schematically shown. [Figure 3D]

[0018] This is a functionally equivalent circuit diagram of an electrostatic chuck (ESC) type that can be used with one or both of the processing systems shown in Figures 1A and 1B. [Figure 3E] These are functionally equivalent circuit diagrams of different electrostatic chuck (ESC) types that can be used with one or both of the processing systems shown in Figures 1A and 1B. [Figure 4]

[0019] Examples of pulse voltage (PV) waveforms that can be established using the embodiments described herein are shown. [Figure 5]

[0020] A to C show examples of pulse voltage (PV) waveforms that can be generated using the embodiments described herein. [Figure 6]

[0021] A and B show exemplary radio frequency (RF) waveforms that can be established using the embodiments described herein. [Figure 7]

[0022] A to D are graphs of simulation results using, for example, the edge tuning circuit configuration according to the embodiments of this specification. [Figure 8]

[0023] Figures A to C show processing methods that can be carried out using embodiments described herein. [Figure 9A]

[0024] Figures 8A to 8C are schematic cross-sectional views of a part of a plasma processing system according to one embodiment, illustrating an aspect of the method described therein. [Figure 9B] Figures 8A to 8C are schematic cross-sectional views of a part of a plasma processing system according to one embodiment, illustrating an aspect of the method described therein. [Figure 9C] Figures 8A to 8C are schematic cross-sectional views of a part of a plasma processing system according to one embodiment, illustrating an aspect of the method described therein. [Figure 9D] Figures 8A to 8C are schematic cross-sectional views of a part of a plasma processing system according to one embodiment, illustrating an aspect of the method described therein. [Modes for carrying out the invention]

[0015]

[0025] Embodiments provided herein include apparatus and methods for plasma processing a substrate in a processing chamber. In some embodiments, aspects of the apparatus and methods address improving the uniformity of the processing across the entire surface of the substrate, reducing the defect rate on the substrate surface, or both. In some embodiments, the apparatus and methods provide improved control over the uniformity of the plasma formed on the edges of the substrate and / or the distribution of ion energy on the substrate surface. In some embodiments, improved control over plasma uniformity is used in combination with a substrate handling method, such as a de-chucking method, to reduce the defect rate related to fine particles on the substrate surface. In some embodiments, improved control over plasma uniformity is used to preferentially clean processing by-products accumulated from portions of the edge ring during an in-situ plasma chamber cleaning process.

[0016]

[0026] Embodiments of the present disclosure may include apparatus and methods for providing pulsed voltage (PV) waveforms supplied from one or more pulsed voltage (PV) generators to multiple electrodes in a processing chamber while biasing and clamping a substrate during a plasma process. In some embodiments, an RF waveform is supplied from a radio frequency (RF) generator to one or more power electrodes in the processing chamber, generating RF to establish and maintain a plasma in the processing chamber, while one or more PV waveforms supplied from one or more PV generators are configured to establish a substantially constant sheath voltage (e.g., a constant difference between the plasma potential and the substrate potential) across the surface of the substrate and the adjacent surface of the substrate support assembly. The established substantially constant sheath voltage provides a desired ion energy distribution function (IEDF) on the surface of the substrate during one or more plasma processing steps performed in the processing chamber.

[0017]

[0027] Some embodiments of the present disclosure include apparatus and methods for controlling plasma uniformity by controlling, for example, the electron density in a bulk plasma across the outer edge region of the substrate and adjacent surfaces of the substrate support assembly with respect to the center of the substrate. In some embodiments, plasma uniformity is controlled using an edge tuning circuit to control one or a combination of the voltage amplitude ratio between an RF waveform established at an edge control electrode and an RF waveform established at a bias electrode, the current amplitude ratio between the RF waveforms at the edge control electrode and the bias electrode, and the phase difference between the RF waveforms at each electrode.

[0018]

[0028] Advantageously, the apparatus and method can be used alone or in combination to control reactive neutral species concentration, ion energy and angular distribution, ion directionality and directionality uniformity, and to provide individual tuning knobs for individually controlling ion flux and / or reactive neutral species uniformity across the entire substrate surface, including the substrate edges. For example, in some embodiments, ion energy and directionality uniformity can be controlled by adjusting the PV waveforms established at the edge electrode and chuck electrode, respectively, to control the thickness profile of the plasma sheath, the shape of the sheath boundary (between the plasma sheath and the plasma) formed over the substrate edge region, and therefore the energy and directionality of ions accelerated toward the substrate surface. Ion flux and / or reactive neutral species uniformity can be controlled individually by adjusting the RF waveforms established at each electrode. Generally, ion energy and directionality affect processing results related to ion interactions at the substrate surface, such as etching profiles at feature openings formed on the substrate surface, while ion flux and reactive neutral species concentration strongly affect processing speed, such as the rate of material removal from feature openings. Thus, the ability to individually control ion energy, ion directionality, ion flux, and reactive neutral species at the processing surface provides desirable tuning parameters. These parameters can be used to optimize both the etching profile required for the tight tolerances of next-generation electronic devices and the processing throughput required for cost-effective manufacturing.

[0019] Examples of plasma processing systems

[0029] Figures 1A and 1B are schematic cross-sectional views of processing systems 10A and 10B, respectively, configured to perform one or more of the plasma processing methods specified herein. Figure 2 is a simplified schematic diagram of a processing scheme that can be used with one or both of processing systems 10A and 10B. Figures 3A–3C are examples of edge tuning circuits 170a, 170b, and 170c that can be used as edge tuning circuits 170 with one or both of processing systems 10A and 10B to control and adjust plasma uniformity.

[0020]

[0030] In some embodiments, the processing systems 10A and 10B shown in Figures 1A and 1B are configured for plasma-assisted etching processes such as reactive ion etching (RIE) plasma processing. However, it should be noted that some embodiments described herein may also be used in conjunction with processing systems configured for use in other plasma-assisted processes, such as plasma deposition processes, e.g., plasma-assisted chemical vapor deposition (PECVD), plasma-assisted physical vapor deposition (PEPVD), plasma-assisted atomic layer deposition (PEALD), plasma processing processes, or plasma-based ion implantation processes (e.g., plasma doping (PLAD) processes).

[0021]

[0031] As shown in Figures 1A-1B, processing systems 10A-10B are configured to form a capacitively coupled plasma (CCP), and the processing chamber 100 includes an upper electrode (e.g., a chamber lid 123) located within the processing space 129, and this upper space faces a lower electrode (e.g., a substrate support assembly 136) also located within the processing space 129. In a typical capacitively coupled plasma (CCP) processing system, a radio frequency (RF) source (e.g., an RF generator 118) is electrically connected to either the upper or lower electrode and supplies an RF signal configured to ignite and maintain the plasma (e.g., plasma 101), which is capacitively coupled to the upper and lower electrodes and placed in the processing area between them. Typically, one of the opposing upper or lower electrodes is connected to ground or a second RF power source. In Figures 1A-1B, one or more components of the substrate support assembly 136, such as the support base 107, are electrically connected to the plasma generator assembly 163, which includes the RF generator 118, and the chamber lid 123 is electrically connected to ground.

[0022]

[0032] As shown in Figures 1A and 1B, each of the processing systems 10A and 10B includes a processing chamber 100, a substrate support assembly 136, a system controller 126, and a plasma control scheme 18. In the embodiments described herein, one or a combination of features, configurations, and / or structural components of the processing system 10A, for example, the structural components of the substrate support assembly 136 and / or the electrical components of the plasma control scheme 18, may be used in the processing system 10B, and vice versa.

[0023]

[0033] The processing chamber 100 typically includes a chamber body 113, which comprises a chamber lid 123, one or more side walls 122, and a chamber base 124, collectively defining a processing space 129. The one or more side walls 122 and the chamber base 124 generally include a material sized and molded to form structural supports for the elements of the processing chamber 100, and configured to withstand the pressure and further energy applied to them. Meanwhile, the plasma 101 is generated in a vacuum environment maintained within the processing space 129 of the processing chamber 100 during processing. In one embodiment, the one or more side walls 122 and the chamber base 124 are formed from a metal such as aluminum, an aluminum alloy, or a stainless steel alloy.

[0024]

[0034] A gas inlet 128, positioned through the chamber lid 123, is used to supply one or more process gases or vapors from a fluid-connected process gas source 119 to the process space 129. In some embodiments, the chamber lid 123 includes a showerhead (not shown), through which the gas or vapor is distributed into the process space. In some embodiments, the gas or vapor is supplied to the process space 129 using a gas inlet positioned through one or more side walls 122 (not shown). The substrate 103 is brought into and out of the process space 129 through an opening (not shown) in one of the side walls 122, which is sealed by a slit valve (not shown) during the plasma treatment of the substrate 103.

[0025]

[0035] In some embodiments, a plurality of lift pins 20, movably positioned through an opening formed in the substrate support assembly 136, are used to facilitate the transfer of the substrate to and from the substrate support surface 105A. In some embodiments, the plurality of lift pins 20 are connected to and / or engageable with a lift pin hoop (not shown) positioned above and located within a processing space 129. The lift pin hoop may be connected to a shaft (not shown) that extends in a sealed manner through the chamber base 124. The shaft may be connected to an actuator (not shown) used to raise and lower the lift pin hoop. When the lift pin hoop is in the raised position, it engages with the plurality of lift pins 20 to raise the upper surface of the lift pins above the substrate support surface 105A, lifting the substrate 103 from there and allowing a robot handler (not shown) to access the inactive (back) side of the substrate 103. When the lift pin hoop is in the lowered position, the multiple lift pins 20 are either coplanar with the substrate support surface 105A or recessed below the substrate support surface 105A, and the substrate 103 is placed on top of them.

[0026]

[0036] The system controller 126, also referred to herein as the processing chamber controller, includes a central processing unit (CPU) 133, memory 134, and support circuitry 135. The system controller 126 is used to control the process sequence (including the substrate biasing method described herein) used to process the substrate 103. The CPU 133 is a general-purpose computer processor configured for use in industrial settings to control the processing chamber and the subprocessors associated with the processing chamber. The memory 134 described herein is generally non-volatile memory and may include random-access memory, read-only memory, floppy or hard disk drives, or other suitable forms of digital storage (local or remote). The support circuitry 135 is conventionally connected to the CPU 133 and includes a cache, clock circuitry, input / output subsystems, power supply, and combinations thereof. Software instructions (programs) and data may be coded and stored in the memory 134 to instruct the processor in the CPU 133. A software program (or computer instruction) readable by the CPU 133 in the system controller 126 identifies which tasks can be performed by components in the processing system 10A and / or 10B.

[0027]

[0037] Typically, the program is readable by the CPU 133 in the system controller 126 and contains code. When executed by the processor (CPU 133), this code performs tasks related to the plasma processing scheme described herein. The program may also contain instructions. These instructions are used to control various hardware and electrical components within the processing system 10A and / or 10B. This is used to perform various process tasks and various process sequences used to implement the methods described herein. In one embodiment, the program contains instructions used to perform one or more of the steps described later in relation to Figures 7 and 8A-8C.

[0028]

[0038] The plasma control scheme 188 illustrated in Figures 1A-1B generally includes a plasma generator assembly 163, a first pulsed voltage (PV) source assembly 196 for establishing a first PV waveform at the bias electrode 104, and a second PV source assembly 197 for establishing a second PV waveform at the edge control electrode 115. In some embodiments, the plasma generator assembly 163 supplies an RF signal to a support base 107 (e.g., a power electrode or cathode), which may be used to generate (maintain and / or ignite) plasma 101 in a processing area located between the substrate support assembly 136 and the chamber lid 123. In some embodiments, the RF generator 118 is configured to supply an RF signal having a frequency greater than about 400 kHz, for example, about 1 MHz or more, or about 2 MHz or more, for example, about 13.56 MHz or more, about 27 MHz or more, about 40 MHz or more, or for example, between about 30 MHz and about 200 MHz, for example, between about 30 MHz and about 160 MHz, between about 30 MHz and about 120 MHz, or between about 30 MHz and about 60 MHz.

[0029]

[0039] In some embodiments, the plasma control scheme 188 further includes an edge tuning circuit 170, which may be used to adjust one or more characteristics of the plasma 101 formed between the substrate support assembly 136 and the chamber lid 123. In some embodiments, the edge tuning circuit 170 may be used to adjust the density of a portion of the plasma 101 formed on the outer peripheral edge of the substrate 103 placed on the substrate support assembly 136 relative to the density of a portion of the plasma 101 formed on the central surface of the substrate 103. Generally, as used herein, plasma density is the number of free electrons in the bulk plasma per unit volume (e.g., number of free electrons / cm³). 3 ) refers to, which in some embodiments is about 10 8 cm -3 ~about 10 11 cm -3This may be within the range. The edge tuning circuit 170 allows manipulation of one or more characteristics of the RF power used to maintain the plasma 101 in the region on the edge of the substrate support assembly 136, with respect to the RF power used to maintain the plasma 101 in the region on the central portion of the substrate support assembly 136. For example, the edge tuning circuit 170 may be used to adjust one or more of the voltage, current, and / or phase of the RF power at the edge of the substrate support assembly 136, with respect to the RF power in the central region 103A of the substrate support assembly 136.

[0030]

[0040] As will be further described later, the edge tuning circuit 170 may be electrically connected to the edge control electrode 115 located in the substrate support assembly 136. In some embodiments, the RF signal used to ignite and / or maintain the plasma 101 is supplied from the plasma generator assembly 163 to the support base 107, which is capacitively coupled to the edge control electrode 115 via a layer of dielectric material placed between them. The edge tuning circuit 170 may be used to adjust one or more characteristics of the RF power used to maintain the plasma within a region on the edge control electrode 115, for example, by adjusting the voltage, current, and / or phase of the RF power at the edge control electrode 115 with respect to the RF power supplied to the support base 107.

[0031]

[0041] In some embodiments, the difference between the voltage, current, and / or phase of the RF power used to ignite and / or maintain the plasma in the region on the edge control electrode 115 and the bias electrode 104 is determined and / or monitored by measuring or determining the respective voltage, current, and / or phase of the RF power at the edge control electrode 115 and / or the bias electrode 104. In some embodiments, one or more characteristics of the RF power at the edge control electrode 115 and / or the bias electrode 104 are measured and / or determined using the signal detection module 187 described below.

[0032]

[0042] As described above, in some embodiments, the plasma generator assembly 163, including the RF generator 118 and the RF matching assembly 160, is generally configured to supply a desired amount of continuous wave (CW) or pulsed RF power at a desired substantially fixed sinusoidal frequency to the support base 107 of the substrate support assembly 136, based on a control signal supplied from the system controller 126. During processing, the plasma generator assembly 163 is configured to supply RF power (e.g., an RF signal) to the support base 107, which is located in close proximity to the substrate support 105 and within the substrate support assembly 136. The RF power supplied to the support base 107 is configured to ignite and maintain the processing plasma 101 of the processing gas located within the processing space 129.

[0033]

[0043] In some embodiments, the support base 107 is an RF electrode electrically connected to the RF generator 118 via an RF matching circuit 162 and a first filter assembly 161, with both the RF matching circuit 162 and the first filter assembly 161 located within the RF matching assembly 160. The first filter assembly 161 includes one or more electrical elements configured to substantially prevent current generated by the output of the PV waveform generator 150 from flowing through the RF power supply line 167 and damaging the RF generator 118. The first filter assembly 161 acts as a high impedance (e.g., high Z) to the PV signal generated from the PV pulse generator P1 in the PV waveform generator 150, thereby suppressing the flow of current to the RF matching circuit 162 and the RF generator 118.

[0034]

[0044] In some embodiments, an RF matching assembly 160 and an RF generator 118 are used to ignite and maintain a processing plasma 101 using a field generated by a processing gas placed in the processing space 129 and RF power (RF signal) supplied to the support base 107 by the RF generator 118. The processing space 129 is in fluid communication with one or more dedicated vacuum pumps through a vacuum outlet 120. One or more dedicated vacuum pumps maintain the processing space 129 at near-atmospheric pressure and exhaust the processing gas and / or other gases from the processing space 129. In some embodiments, a substrate support assembly 136 placed in the processing space 129 is grounded and positioned on a support shaft 138 extending through a chamber base 124. However, in some embodiments, the RF matching assembly 160 is configured to supply RF power to a bias electrode 104 located in the substrate support 105 relative to the support base 107.

[0035]

[0045] In some embodiments, the edge tuning circuit 170 is used to control and / or adjust one or more characteristics of the RF waveform established on the edge control electrode 115 (e.g., the second RF waveform 602 shown in Figure 6) to one or more characteristics of the RF waveform established on the bias electrode 104 (e.g., the first RF waveform 601 shown in Figure 6). In some embodiments, such as those shown in Figures 1A and 2, the edge tuning circuit 170 is electrically connected between the edge control electrode 115 and ground. In other embodiments, such as those shown in Figure 1B and the dotted line in Figure 2, the edge tuning circuit 170 may be electrically connected between the edge control electrode 115 and the plasma generator assembly 163, and thus electrically connected between the edge control electrode 115 and the support base 107.

[0036]

[0046] As briefly described above, the substrate support assembly 136 generally includes a substrate support 105 (e.g., an ESC substrate support) and a support base 107. In some embodiments, the substrate support assembly 136 may further include an insulating plate 111 and a grounding plate 112, which will be described further below. The support base 107 is electrically insulated from the chamber base 124 by the insulating plate 111, and the grounding plate 112 is inserted between the insulating plate 111 and the chamber base 124. The substrate support 105 is thermally coupled to the support base 107 and is positioned on the support base 107. In some embodiments, the support base 107 is configured to regulate the temperature of the substrate support 105 and the substrate 103 positioned on the substrate support 105 during substrate processing. In some embodiments, the support base 107 includes one or more cooling channels (not shown) located inside. One or more cooling channels are fluidly connected to a coolant source (not shown), such as a refrigerant source or water source, which has relatively high electrical resistance. In some embodiments, the substrate support 105 includes a heater (not shown), such as a resistance heating element embedded in the dielectric material of the substrate support 105. Here, the support base 107 is formed of a corrosion-resistant thermal conductive material such as a corrosion-resistant metal (e.g., aluminum, aluminum alloy, or stainless steel) and is connected to the substrate support by adhesive or mechanical means.

[0037]

[0047] Typically, the substrate support 105 is formed of a dielectric material, such as a bulk sintered ceramic material (corrosion-resistant metal oxide or metal nitride material, such as aluminum oxide (Al2O3), aluminum nitride (AlN), titanium oxide (TiO), titanium nitride (TiN), yttrium oxide (Y2O3), mixtures thereof, or combinations thereof). In embodiments herein, the substrate support 105 further includes a bias electrode 104 embedded in its dielectric material. In some embodiments, one or more characteristics of the RF power used to maintain the plasma 101 in the processing area on the bias electrode 104 are determined and / or monitored by measuring an RF waveform established at the bias electrode 104 (e.g., the first RF waveform 601 in Figure 6). Typically, the first RF waveform 601 is established by supplying an RF signal from the plasma generator assembly 163 to the substrate support 105, and the substrate support 105 is capacitively coupled to the bias electrode 104 through a dielectric material layer 105C (Figure 1C) placed between them.

[0038]

[0048] In one configuration, the bias electrode 104 is a chucking pole used to fix (i.e., chuck) the substrate 103 to the substrate support surface 105A of the substrate support 105 and to bias the substrate 103 to the processing plasma 101 using one or more of the pulse voltage bias schemes described herein. Typically, the bias electrode 104 is formed of one or more conductive components, such as one or more metal meshes, foils, plates, or combinations thereof.

[0039]

[0049] In some embodiments, the bias electrode 104 is electrically connected to a clamping network 116. The clamping network 116 supplies a chucking voltage to the bias electrode 104, such as a static DC voltage between approximately -5000V and approximately 5000V, using an electrical conductor such as a coaxial power supply line 106 (e.g., a coaxial cable). As will be further discussed below, the clamping network 116 includes a bias compensation circuit element 116A, a DC power supply source 155, and a bias compensation module blocking capacitor. The bias compensation module blocking capacitor is also referred to herein as the blocking capacitor C5. The blocking capacitor C5 is positioned between the output of the pulse voltage (PV) waveform generator 150 and the bias electrode 104.

[0040]

[0050] Referring to Figures 1A and 1B, the substrate support assembly 136 may further include an edge control electrode 115. The edge control electrode 115 is positioned below the edge ring 114, surrounding the bias electrode 104, and / or at a distance from the center of the bias electrode 104. Generally, in a processing chamber 100 configured to process a circuit board, the edge control electrode 115 is ring-shaped, made from a conductive material, and configured to surround at least a portion of the bias electrode 104. In some embodiments, such as shown in Figure 1A, the edge control electrode 115 is positioned within the region of the substrate support 105. In some embodiments, as shown in Figure 1A, the edge control electrode 115 includes a conductive mesh, foil, and / or plate positioned from the edge ring 114 at a similar distance (i.e., in the Z direction) from the substrate support surface 105A of the substrate support 105 to the bias electrode 104. In some other embodiments, such as those shown in Figure 1B, the edge control electrode 115 includes a conductive mesh, foil, and / or plate positioned on or within the region of the dielectric tube 110. The dielectric tube 110 surrounds at least a portion of the bias electrode 104 and / or the substrate support 105. The dielectric tube 110 can be made of various insulators such as aluminum oxide, aluminum nitride, and quartz. In some embodiments, the dielectric tube 110 may include several components made of the same or different materials. Alternatively, in some other embodiments (not shown), the edge control electrode 115 is positioned within or connected to an edge ring 114 positioned adjacent to the substrate support 105.

[0041]

[0051] The edge control electrode 115 is generally positioned, when used with the edge tuning circuit 170 and / or biased using the pulse bias scheme 140 (Figure 1), to be able to influence or alter a portion of the generated plasma 101 located on or outside the outer peripheral edge of the substrate 103, due to its position relative to the substrate 103. In some embodiments, the edge tuning circuit 170, electrically connected to the edge control electrode 115, can be used to manipulate one or more characteristics of the RF power used to ignite and / or maintain the plasma in the processing area 129A above the edge control electrode 115. For example, in some embodiments, the edge tuning circuit 170 can be used to adjust and / or manipulate one or more of the voltage, current, phase, and / or supplied power of the RF power used to ignite and / or maintain the plasma 101 in the processing area located between the edge control electrode 115 and the chamber lid 123.

[0042]

[0052] In some embodiments, one or more characteristics of the RF power used to maintain the plasma 101 in the processing region on the edge control electrode 115 are determined and / or monitored by measuring one or more differences between a second RF waveform 602 and a first RF waveform 601 established at the edge control electrode 115 and the bias electrode 104, respectively. In some embodiments, the difference in one or more characteristics of the second RF waveform 602 and the first RF waveform 601 can be manipulated by using an edge tuning circuit 170 to adjust the plasma density in the region on the outer peripheral edge of the substrate 103. Thus, the edge tuning circuit 170 can be used to beneficially control the generation of active species in the bulk plasma. This allows for fine control over the flux of ions and / or radicals at the edge of the substrate 103 (edge ​​region 103B) relative to the central region 103A of the substrate 103.

[0043]

[0053] The edge control electrode 115 can be energized using a PV waveform generator 150 different from the PV waveform generator 150 used to energize the bias electrode 104. In some embodiments, the edge control electrode 115 can be energized by using a PV waveform generator 150 that is also used to energize the bias electrode 104 by sharing a portion of the power with the edge control electrode 115. In one configuration, a first PV waveform generator 150 of a first PV source assembly 196 is configured to energize the bias electrode 104, and a second PV waveform generator 150 of a second PV source assembly 197 is configured to energize the edge control electrode 115.

[0044]

[0054] In some embodiments, one or more characteristics of the generated RF power are measured and / or determined by using a signal detection module 187 that is communicatively connected to the system controller 126. The signal detection module 187 is generally configured to receive electrical signals from various components within the processing systems 10A and 10B, for example, electrical signal traces (not shown) electrically connected to node N. The signal detection module 187 may include a plurality of input channels 172, each configured to receive electrical signals from a corresponding electrical signal trace, and a data acquisition module 169. The received electrical signals may include, but are not limited to, one or more characteristics of the RF signal supplied to the support base 107, the RF waveform established on one or both of the bias electrode 104 and the edge control electrode 115, the pulse voltage (PV) waveform established on one or both of the bias electrode 104 and the edge control electrode 115, and the chucking voltage supplied to one or both of the bias electrode 104 and the edge control electrode 115. In some embodiments, the data acquisition module 169 is configured to generate control signals used to automatically control one or more characteristics of the RF signal, RF waveform, PV waveform, and / or chucking voltage during substrate processing. In some embodiments, a desired change in one or more characteristics is transmitted by the system controller to the signal detection module 187, and the data acquisition module 169 may be used to implement the desired change.

[0045]

[0055] In some embodiments, as illustrated, the second PV source assembly 197 includes a clamping network 116 electrically connected to the edge control electrode 115 using an electrical conductor such as a coaxial power supply line 106 (e.g., a coaxial cable). The clamping network 116 can be used to supply a static DC voltage to the edge control electrode, such as between approximately -5000V and approximately 5000V, and may include one or more bias compensation circuit elements 116A, a DC power supply 155, and a blocking capacitor C5. The blocking capacitor C5 is located between the output of the pulse voltage (PV) waveform generator 150 and the edge control electrode 115. Here, the clamping network 116 of the second PV source assembly 197 is controllable independently of the clamping network 116 of the first PV source assembly 196. The clamping network 116 of the second PV source assembly 197 is used to supply the edge control electrode with the same or a different clamping voltage than the clamping voltage supplied to the bias electrode, and may provide an additional process adjustment knob.

[0046]

[0056] In some embodiments, the processing chamber 100 further includes a dielectric pipe 110 or collar that at least partially surrounds a portion of the substrate support assembly 136. The dielectric pipe 110 provides a dielectric barrier between the RF hot substrate support assembly 136 and the ground liner 108 and also protects the substrate support 105 and / or support base 107 from contact with corrosive processing gases or plasma, cleaning gases or plasma, or their by-products. Typically, the liner 108 is in contact with the dielectric pipe 110, an insulating plate 111, and a ground plate 112. In some embodiments, a plasma screen 109 is positioned between the cathode liner 108 and a side wall 122 to prevent plasma from being generated in the space below the plasma screen 109 between the liner 108 and one or more side walls 122.

[0047] Configuration of the substrate support assembly

[0057] Figure 1C is a close-up view of a portion of the substrate support assembly 136 shown in Figure 1A, and includes a simplified electrical schematic diagram of the electrical properties of various structural elements in one or more embodiments of the substrate support assembly 136. The simplified electrical schematic diagram shown in Figure 1C is equally applicable to the corresponding structural elements of the substrate support assembly 136 depicted in Figure 1B. Here, the substrate support assembly 136 is configured as an electrostatic chuck (ESC), and can be either a Coulombic type ESC or a Johnsen-Rahbek type ESC. Simplified equivalent circuit models 191 of the Coulombic type ESC and the Johnsen-Rahbek type ESC are shown in Figures 3D and 3E, respectively, and will be discussed later. In general, in any ESC configuration of the substrate support assembly 136, the substrate 103 is fixed to the substrate support 105 by applying a potential between the substrate 103 and the chuck electrodes, resulting in an electrostatic attraction force between them. In one embodiment, the bias electrode 104 is used as a chuck electrode in addition to facilitating the biasing scheme of the pulse voltage (PV) waveform described herein.

[0048]

[0058] As shown in the figure, the substrate support assembly 136 includes a substrate support 105, a support base 107, an insulating plate 111, and a grounding plate 112, each of which will be described in turn. The substrate support 105 is formed of a dielectric material and provides a substrate support surface 105A including a bias electrode 104 embedded in the dielectric material. The bias electrode 104 functions as a chuck electrode and is spaced apart from the substrate support surface 105A and thus from the substrate 103 by a first dielectric material layer 105B, and from the support base 107 by a second dielectric material layer 105C.

[0049]

[0059] In some embodiments, the ESC configuration may be used to fix the substrate 103 to the substrate support 105 in a relatively low-pressure (e.g., ultra-high vacuum) processing environment. In some embodiments, it may be desirable to heat and / or cool the substrate 103 during processing to maintain the substrate at a desired processing temperature. In these embodiments, the substrate support assembly 136 may be configured to maintain the substrate 103 at a desired temperature by heating or cooling the substrate support 105 and, consequently, the substrate 103 placed thereon. Often, in these embodiments, the substrate support surface 105A is patterned to have a raised portion (e.g., a mesa) that contacts the substrate 103 and a recess that defines a gap region 105D between the substrate 103 and the support surface. During substrate processing, an inert gas, such as helium, can be supplied to the gap region 105D to improve heat transfer between the substrate support surface 105A and the substrate 103 placed thereon.

[0050]

[0060] The bias electrode 104 is electrically connected to a DC power supply 155 (described above in Figures 1A-1B), which is configured to apply a potential between the substrate 103 and the bias electrode 104, thereby generating an electrostatic attraction force (chucking force) between them. The substrate support assembly 136 can be configured as either a Coulomb-type ESC or a Jonssen-Rabek-type ESC. Compared to a Coulomb-type ESC, a Jonssen-Rabek-type ESC provides a higher chucking force and can use a lower chucking voltage. In a Coulomb-type ESC, the dielectric material selected for the first dielectric material layer 105B will typically have a higher electrical resistance than the dielectric material selected for a Jonssen-Rabek-type ESC. As a result, there are differences in the simplified functional equivalent circuit models 191a and 191b shown in Figures 3C and 3E, respectively.

[0051]

[0061] In the simplest case (for example, circuit model 191 of the Coulomb-type ESC shown in Figure 3D), the first dielectric layer 105B is assumed to be a dielectric material that acts as an insulator (e.g., infinite resistance R JRIt is formed with). Therefore, the functionally equivalent circuit model 191a includes the direct capacitance C1 between the bias electrode 104 and the substrate 103 through the first dielectric layer 105B. In some embodiments of the Coulomb-type ESC, the dielectric material and thickness T of the first dielectric material layer 105B DL1 are selected such that the capacitance C1 is between about 5 nF and about 100 nF, for example, between about 7 nF and about 20 nF. For example, the dielectric material layer 105B is formed of a ceramic material (such as aluminum oxide (Al2O3), etc.) and has a thickness T between about 0.1 mm and about 1 mm, for example, between about 0.1 mm and about 0.5 mm, for example, about 0.3 mm DL1 may have.

[0052]

[0062] In a more complex case, as shown in the circuit model 191b of the Johnson-Larbeck type ESC shown in FIG. 3E, the circuit model 191b includes the dielectric material resistance R JR and the capacitance C1 connected in parallel with the gap capacitance C JR ​​​​​​​​​​​​​​​JR This is used. Gap volume C JR It is expected that the capacitance will be slightly larger than capacitance C1. Returning to Figure 1C, the schematic electrical diagram of the circuit formed within the substrate support assembly 136 includes the support base dielectric layer capacitance C2, which represents the capacitance of the second dielectric material layer 105C. In some embodiments, the thickness of the portion of the second dielectric material layer 105C is greater than the thickness of the first dielectric material layer 105B. In some embodiments, the dielectric material used to form the dielectric layers on both sides of the bias electrode is the same material and forms the structural body of the substrate support 105. In one example, the thickness of the second dielectric material layer 105C (e.g., Al2O3 or AlN), measured in the direction extending between the support base 107 and the bias electrode 104, is greater than 1 mm, such as having a thickness between about 1.5 mm and about 100 mm. The support base dielectric layer capacitance C2 typically has a capacitance between about 0.5 nanofarads (nF) and about 10 nF.

[0053]

[0063] As shown in Figure 1C, the schematic electrical diagram of the circuit formed within the substrate support assembly 136 is also shown, along with the support base resistor R. P , insulating plate capacitance C3, and grounding plate resistance R connected to ground at one end. G This includes the support base 107 and the grounding plate 112, which are typically made of metal material, and the support base resistance R P and ground plate resistor R G This is very low, such as less than a few milliohms. The insulator plate capacitance C3 represents the capacitance of the dielectric layer located between the bottom surface of the support base 107 and the top surface of the grounding plate 112. In one example, the insulator plate capacitance C3 has a capacitance between approximately 0.1 nF and approximately 1 nF.

[0054] Bias and edge control scheme

[0064] Figure 2 is a simplified schematic diagram of a bias and edge control scheme that can be used with one or both of the processing systems 10A to 10B shown in Figures 1A and 1B. As shown in Figure 2, the RF generator 118 and the PV waveform generator 150 are configured to supply an RF waveform and a pulsed voltage waveform, respectively, to one or more electrodes located in the processing space 129 of the processing chamber 100. In one embodiment, the RF generator 118 and the PV waveform generator 150 are configured to supply an RF waveform and a pulsed voltage waveform simultaneously to one or more electrodes located in the substrate support assembly 136.

[0055]

[0065] As described above, the edge tuning circuit 170 is generally configured to control the uniformity of the plasma formed between the chamber lid 123 and the substrate support assembly 136, for example, by controlling the plasma density (i.e., the free electron density in the bulk plasma) across the outer edge of the substrate 103. In some embodiments, as shown in Figures 1A and 2, the edge tuning circuit 170 is electrically connected between the edge control electrode 115 (edge ​​bias electrode) and ground. In other embodiments, as shown by the dotted lines in Figures 1B and 2, the edge tuning circuit 170 is electrically connected between the edge control electrode 115 and the plasma generator assembly 163, for example, between the edge control electrode 115 and the RF matching assembly 160.

[0056]

[0066] In some embodiments, the edge tuning circuit 170 is configured as a resonant circuit including an inductor and a capacitor (e.g., an LC circuit) that can be used to adjust the voltage, current, and / or phase of the RF power used to maintain plasma in a region on the edge control electrode. Exemplary electrical circuits 170a, 170b, and 170c that can be used as the edge tuning circuit 170 in any one of the embodiments described herein are illustrated in Figures 3A-3C. Note that in Figures 3A and 3B, the edge tuning circuits 170a and 170b are shown as being electrically connected between the power supply line 158 and ground, such as between the edge control electrode 115 and ground, as shown in Figure 1A. However, the exemplary edge tuning circuits 170a and 170b illustrated in Figures 3A and 3B are also intended to be electrically connected between the power supply line 158 and the plasma generator assembly 163 (shown by a dotted line), such as between the edge control electrode 115 and the RF matching assembly 160, as shown in Figure 1B. In some other embodiments, the edge tuning circuit 170 may be electrically connected to the power supply line 158, the plasma generator assembly 163, and ground simultaneously, such as the edge tuning circuit 170c in Figure 3C.

[0057]

[0067] In one embodiment shown in Figure 3A, the edge tuning circuit 170a includes an inductor L2 and a variable capacitor C7 arranged in parallel (i.e., a parallel LC resonant circuit). In another embodiment shown in Figure 3B, the edge tuning circuit 170b includes an inductor L2 and a variable capacitor C7 arranged in series (i.e., a series LC resonant circuit). In another embodiment shown in Figure 3C, the edge tuning circuit 170c includes an inductor L2 and a variable capacitor C8 arranged in series between the power supply line 158 and the plasma generator assembly 163 (i.e., between the edge control electrode 115 and the RF matching assembly 160) (i.e., a series LC resonant circuit), and a second variable capacitor C7 arranged in series between the power supply line 158 and ground.

[0058]

[0068] In some embodiments, one or both of the variable capacitors C7 or C8 are adjustable from at least about 50pF to about 500pF (e.g., at least about 50pF to at least about 200pF), or from at least about 20pF to about 250pF.

[0059]

[0069] The type of LC resonant circuit selected for the edge tuning circuit 170, such as parallel, series, or other configurations, may depend on the mechanical dimensions of the substrate support assembly 136 and the resulting electrical coupling between conductive components or electrodes, such as the edge ring, edge electrodes, base plate, wafer electrodes, wafer, and ground plate.

[0060]

[0070] In some embodiments, the type of LC resonant circuit can be selected based on the desired ability to control the plasma density distribution, which can be achieved by tuning one or more parameters of the LC resonant circuit so that one or more characteristics of the second RF waveform 602 (Figure 6), established at the edge control electrode 115, can be tuned to one or more characteristics of the first RF waveform 601, established at the bias electrode 104. Simulation results of various control characteristics that can be achieved for an exemplary edge tuning circuit 170 are described below in Figures 7A to 7D.

[0061]

[0071] Returning to Figure 2, in a non-limiting example, the RF generator 118 and the PV waveform generator 150 are configured to supply the RF waveform and pulse voltage waveform, respectively, to the support base 107 and bias electrode 104 located in the substrate support assembly 136. In another embodiment, the RF generator 118, the first PV waveform generator 150, and the second PV waveform generator 150 are configured to supply the RF waveform, the first pulse voltage waveform, and the second pulse voltage waveform, respectively, to the support base 107, bias electrode 104, and edge control electrode 115, all located in the substrate support assembly 136.

[0062]

[0072] As shown in Figure 2, the RF generator 118 is configured to supply an RF signal to one or more electrodes located within the chamber body 113 by supplying sinusoidal RF waveforms, including RF waveforms 601, 602 (Figures 6A-6B), through an RF (plasma) matching assembly 160, which includes an RF matching circuit 162 and a first filter assembly 161. Furthermore, each of the PV waveform generators 150 is configured to supply a PV waveform, typically including a series of voltage pulses (e.g., sub-microsecond voltage pulses including nanosecond voltage pulses), to one or more electrodes located within the chamber body 113 by establishing a PV waveform at the bias electrode 104 or edge electrode 115 through a second filter assembly 151. Components within the clamping network 116 can optionally be placed between each PV waveform generator 150 and the second filter assembly 151. Examples of PV waveforms 401a-c that can be provided by each PV waveform generator 150 are shown in Figures 5A-5C. An example of a PV waveform 401 that can be established with the bias electrode 104 and / or edge control electrode 115 is shown in Figure 4.

[0063]

[0073] During processing, a PV waveform is supplied to the bias electrode 104 by the PV waveform generator 150 of the first PV source assembly 196, and a PV waveform is supplied to the edge control electrode 115 by the PV waveform generator 150 of the second PV source assembly 197. The pulse voltage waveform is supplied to a load located within the processing chamber 100 (for example, the composite load 130 shown in Figures 3D-3E). The PV waveform generators 150 are connected to the bias electrode 104 and the edge control electrode 115 through their respective power supply lines 157 and 158. The supply of PV waveforms from each of the PV waveform generators 150 is controlled using signals supplied by the system controller 126.

[0064]

[0074] In one embodiment, the PV waveform generator 150 is configured to output a periodic voltage function at predetermined time intervals, using a signal from, for example, a transistor-transistor logic (TTL) source (not shown). The periodic voltage function generated by the transistor-transistor logic (TTL) source may be two-state DC pulses between a predetermined negative or positive voltage and zero. In one embodiment, the PV waveform generator 150 is configured to maintain a predetermined substantially constant negative voltage across its output (i.e., relative to ground) while predetermined time intervals are periodically repeated, by repeatedly opening and closing one or more switches at a predetermined rate. In one embodiment, a first switch is used to connect a high-voltage power supply to the bias electrode 104 during a first phase of the pulse interval, and a second switch is used to connect the bias electrode 104 to ground during a second phase of the pulse interval. In another embodiment, the PV waveform generator 150 is configured to maintain a predetermined substantially constant positive voltage across its output (i.e., relative to ground) for a predetermined period of time intervals of a predetermined length by repeatedly opening and closing its internal switch (not shown) at a predetermined rate.

[0065]

[0075] In one configuration, a first switch is used to connect the bias electrode 104 to ground during the first phase of the pulse interval, and a second switch is used to connect the high-voltage power supply to the bias electrode 104 during the second phase of the pulse interval. In another configuration, during the first phase of the pulse interval, the bias electrode 104 is disconnected from the high-voltage power supply and the first switch is positioned open so that the bias electrode 104 is coupled to ground through an impedance network (e.g., an inductor and resistor connected in series). Then, during the second phase of the pulse interval, the first switch is positioned closed to connect the high-voltage source to the bias electrode 104, while the bias electrode 104 remains connected to ground through the impedance network.

[0066]

[0076] The PV waveform generator 150 may include a PV generator and one or more electrical components, such as (but not limited to) a high-repetition-rate switch (not shown), a capacitor (not shown), an inductor (not shown), a flyback diode (not shown), a power transistor (not shown), and / or a resistor (not shown), configured to supply a PV waveform to the output. An actual PV waveform generator 150 that can be configured as a nanosecond pulse generator may include any number of internal components.

[0067]

[0077] The power supply line 157 electrically connects the output of the PV waveform generator 150 of the first PV source assembly 196 to the optional filter assembly 151 and bias electrode 104. In the following discussion, the power supply line 157 of the first PV source assembly 196, used to connect the PV waveform generator 150 to the bias electrode 104, will be described primarily, but the power supply line 158 of the second PV source assembly 197, which connects the PV waveform generator 150 to the edge control electrode 115, will include the same or similar components. One or more electrical conductors in the various parts of the power supply line 157 may include: (a) one or a combination of coaxial cables, such as a flexible coaxial cable connected in series with a rigid coaxial cable; (b) an insulated high-voltage corona-resistant hookup wire; (c) a bare wire; (d) a metal rod; (e) an electrical connector; or (f) any combination of the electrical elements of (a) to (e). The optional filter assembly 151 includes one or more electrical elements configured to substantially prevent current generated by the output of the RF generator 118 from flowing through the power supply line 157 and damaging the PV waveform generator 150. The optional filter assembly 151 acts as a high impedance (e.g., high Z) to the RF signal generated by the RF generator 118, thereby suppressing the flow of current to the PV waveform generator 150.

[0068]

[0078] In some embodiments, as shown in Figures 1A-1B, the PV waveform generator 150 of the first PV source assembly 196 is configured to supply a pulsed voltage waveform signal to the bias electrode 104 and, consequently, the composite load 130 (Figures 3D-3E) by supplying the generated pulsed voltage waveform through a blocking capacitor C5, a filter assembly 151, a power supply line 157, and a capacitor C1 (Figure 1C). In some embodiments, the plasma control scheme 188 may further include a blocking resistor (not shown) located within a component connecting the clamping network 116 to a point in the power supply line 157. The primary function of the blocking capacitor C5 is to protect the PV waveform generator 150 from the DC voltage generated by the DC power supply 155, which is dropped across the blocking capacitor C5 and does not disturb the output of the PV waveform generator 150. The purpose of the blocking resistor in the clamping network 116 is to block the pulsed voltage generated by the PV waveform generator 150 to a degree sufficient to minimize the current induced in the DC power supply 155.

[0069] Waveform example

[0079] Figure 4 shows examples of PV waveforms 401 that can be established on the bias electrode 104 and PV waveforms 402 that are established on the substrate 103 as PV waveform 401 is supplied to the bias electrode 104. PV waveform 401 is based on PV waveform 401a (Figure 5A) generated by a PV waveform generator 150 electrically connected to the bias electrode 104. PV waveforms 401 and 402 can also represent PV waveforms established on the edge control electrode 115 and edge ring 114, respectively.

[0070]

[0080] Here, the PV waveform 401 is established at the bias electrode 104 and / or edge control electrode 115 by using the PV waveform generator 150 in each PV source assembly 196, 197 and the DC voltage source 155 of the corresponding clamping network 116. As shown in Figure 4, the output of the PV waveform generator 150, which can be controlled by the plasma processing recipe settings stored in the memory of the controller 126, is the pulse voltage level V as specified herein.PP A PV waveform 401 is established, which includes a peak-to-peak voltage, also known as a PV waveform 402. Here, the PV waveform 402 is the waveform seen by the substrate 103 for the establishment of the PV waveform 401 at the bias electrode 104, and is characterized as including a sheath collapse and recharge phase 450 (or, for simplicity of discussion, a sheath collapse phase 450) extending between points 420 and 421, a sheath formation phase 451 extending between points 421 and 422, and an ion current phase 452 extending between point 422 and back to the start at point 420 of the next sequentially established pulse voltage waveform period. The sheath collapse phase 450 generally includes a period in which the capacitance of the sheath is discharged and the substrate potential is brought to the level of the local plasma potential 433.

[0071]

[0081] Depending on the desired plasma processing conditions, the PV waveform frequency (1 / T) may be adjusted to achieve the desired plasma processing result on the substrate 103. P ), pulse voltage level V pp It may be desirable to control and set at least the PV waveform characteristics, such as the pulse voltage on time and / or other parameters of the PV waveform 401. In one embodiment, the pulse voltage (PV) on time is the ion current period (e.g., the time between point 422 and the next point 420 in Figure 4) and the waveform period T p It is defined as a ratio greater than 50% or greater than 70%, for example, between 80% and 95%.

[0072]

[0082] In some embodiments, the PV waveform generator 150 is configured to provide a PV waveform 401a having a generally constant negative voltage during the second portion 406, as shown in Figures 4 and 5A. In some embodiments, during the ion current phase 452, the ion current (Ii) deposits a positive charge on the substrate surface, so the voltage on the substrate surface increases over time, as seen by the positive slope of the line between points 422 and 420 (Figure 4). The voltage increase over time on the substrate surface will decrease the sheath voltage and result in a broadening of the ion energy distribution. Therefore, at least the PV waveform frequency (1 / T) P ) controls and sets (where T P (This is the PV waveform period (Figure 5A)), and it is desirable to minimize the effects of sheath voltage reduction and ion energy distribution broadening.

[0073]

[0083] Figures 5A to 5C show the respective PV waveforms 401a to c that can be used to establish a PV waveform at the bias electrode 104 or edge control electrode 115 electrically connected to the PV waveform generator. PV waveforms 401a to c represent pulse voltage waveforms established at nodes connected to the input of the clamping network 116, and therefore may differ from the corresponding pulse voltage waveforms established at the substrate 103 or edge ring 114. The DC offset ΔV observed in each PV waveform 401a to c depends on the bias applied by the DC power supply 155 of the clamping network 116 and various characteristics of the configuration of the PV waveform generator 150 used to establish the PV waveform. Generally, the waveform period of each PV waveform 401a to c is characterized as having a first region 405 corresponding to the sheath collapse phase 450 and a second region 406 corresponding to the sheath formation phase 451 and the ion current phase 452.

[0074]

[0084] Figure 5A shows a PV waveform 401a having a constant negative voltage over at least a portion of the second region 406, for example, during the corresponding ion current phase 452 of the waveform 401 established at the bias electrode 104. Figure 5B shows a shaped pulsed voltage waveform 401b that can be generated by a PV waveform generator 150 and used to establish a shaped PV waveform (not shown) at the bias electrode 104 and / or edge control electrode 115. In some embodiments, the shaped pulsed waveform 401b is formed by a PV waveform generator 150 configured to supply a positive voltage during one or more phases of the voltage pulse (e.g., the first region 405) and a negative voltage during one or more phases of the voltage pulse (e.g., the second region 406) by using one or more internal switches and a DC power supply. Here, the first region 405 generally corresponds to the sheath collapse phase 450, and the second region 406 generally corresponds to the sheath formation phase 451 and the ion current phase 452, and the voltage in the second region 406 may include a negative slope. The negative slope in the second region 406 can be used as a control knob to compensate for the ion current flowing through the substrate 103 or edge ring 114 during the ion current phase, or to adjust the spread of the ion energy distribution on the substrate surface.

[0075]

[0085] In some embodiments, the PV waveform generator 150 is configured to provide a pulse voltage waveform 401c, shown in Figure 5C, to establish a PV waveform (not shown) on the bias electrode 104 and / or edge control electrode 115. In this example, the first region 405 generally corresponds to the sheath collapse phase 450, and the second region 406 generally corresponds to the sheath formation phase 451 and the ion current phase 452, and the voltage in the second region 406 may include a positive slope that provides a control knob for adjusting the spread of the ion energy distribution on the surface of the substrate.

[0076]

[0086] Figures 6A–6B show a first RF waveform 601 established at the bias electrode 104 and a second RF waveform 602 established at the edge control electrode 115, resulting from the capacitive coupling of the RF signal supplied to the support base 107 by the RF generator 118 in the plasma generator assembly 163. The waveform characteristics of the first RF waveform 601 and the second RF waveform 602 are controlled by using a configuration of the edge tuning circuit 170, such as one of the configurations illustrated in Figure 3A (parallel LC resonant circuit), Figure 3B (series resonant circuit), or Figure 3C. The exemplary waveforms shown in Figures 6A–6B and the simulation results shown in Figures 7A–7D below are provided for the sake of simplicity of discussion and are not intended to limit the scope of the disclosure provided herein.

[0077]

[0087] Generally, the RF signals supplied to the support base 107 have relatively high frequencies, so the first RF waveform 601 and the second RF waveform 602 have corresponding high frequencies (1 / T) of about 1 MHz or more, for example, between about 30 MHz and about 60 MHz. RF The edge tuning circuit 170, as described in various embodiments disclosed herein, may be used to tune one or more characteristics of a second RF waveform 602 established at the edge control electrode 115 to one or more characteristics of a first RF waveform 601 established at the bias electrode 104. In some embodiments, one or more relative characteristics are the RF waveform amplitude ratio (e.g., voltage amplitude ratio V) between the second RF waveform 602 and the first RF waveform 601. RF2 / V RF1 The RF current amplitude ratio between the second RF waveform 602 and the first RF waveform 601 (e.g., the current amplitude ratio is not shown), the phase difference (ΔΦ) between the second RF waveform 602 and the first RF waveform 601, and / or the RF supply power ratio between the second RF waveform 602 and the first RF waveform 601 (e.g., the supply power ratio is not shown).

[0078]

[0088] One or more characteristics of the second RF waveform 602 relative to the first RF waveform 601 can be determined and / or monitored by measuring the respective voltages, currents, phases, and / or powers of the RF waveforms established at the edge control electrode 115 and the bias electrode 104. The measured characteristics of the second RF waveform 602 and the first RF waveform 601 correspond to characteristics of the bulk plasma in the portion formed above the edge control electrode 115 and the bias electrode 104, such as plasma density. The difference determined between the second RF waveform 602 and the first RF waveform 601 can be used to monitor and control the difference between the electron density of the portion of bulk plasma formed on the edge ring 114 and the electron density of the portion of bulk plasma formed on the central portion of the substrate 103. The uniformity and / or distribution of plasma density can be controlled and / or adjusted to achieve the desired processing result by using the edge tuning circuit 170, such as by using the system controller 126 to adjust the variable capacitor C7.

[0079]

[0089] Figures 7A to 7B show the non-limiting simulation results of the edge tuning circuit 170 shown in Figures 3A and 3B, and Figures 7C to 7D show the simulation results of the edge tuning circuit 170 combining the series and parallel configurations shown in Figure 3C. In Figures 7A and 7C, the simulation results show that changing the capacitance over a range of approximately 20pF to approximately 250pF (for example, by adjusting the variable capacitors C7 and C8 in the configuration of each edge tuning circuit 170) results in a voltage amplitude ratio (for example, V) between the second RF waveform 602 and the first RF waveform 601. RF2 / V RF1 This provides an example of an LC circuit tuning curve showing the effect on the second RF waveform 602 and the first RF waveform 601 (e.g., Φ). In Figures 7B and 7D, the simulation results show that changing the capacitances of C7 and C8 affects the phase difference (e.g., Φ) between the second RF waveform 602 and the first RF waveform 601. RF2 -Φ RF1 This provides an example of an LC circuit adjustment curve that shows the effect on ( ).

[0080]

[0090] As shown in Figure 7A, the variable capacitance C7 of the edge tuning circuit 170 (configuration shown in Figure 3A), which has a value of approximately 170 pF, corresponds to a voltage amplitude ratio (V) of approximately 1.5. RF2 / V RF1 ) has. As shown in Figure 7B, the phase difference corresponding to the 170pF capacitance of the edge tuning circuit 170, which has the same configuration as in Figure 7A, is relatively small, for example, less than 5 degrees, so as shown in Figure 6A, amplification of the second RF waveform 602 relative to the first RF waveform 601 occurs, and a small phase difference (ΔΦ) occurs between them.

[0081]

[0091] In Figures 7C-7D, the variable capacitance C7 of the edge tuning circuit 170 (configuration as shown in Figure 3C) can be set to a value of approximately 25pF. As a result, the voltage amplitude ratio (V RF2 / V RF1 The value of (ΔΦ) is approximately equal to 0.5 (Figure 7C), and the phase difference (ΔΦ) is approximately zero (about null), as shown in Figure 6D.

[0082]

[0092] As shown in Figure 7A, the simulation results based on the configuration of the edge tuning circuit 170 in Figure 3A (e.g., a parallel LC resonant circuit) show resonance peaks at approximately 100 pF and 120 pF. In Figure 7D, the simulation results for an edge tuning circuit 170 (not shown) show resonance phase transitions at 60 pF and 250 pF. In some embodiments, it may be desirable to operate each edge tuning circuit 170 on either side of the resonance during the period in which the RF plasma is maintained. In some embodiments, the edge tuning circuit 170 may be configured to allow switching operation of the edge tuning circuit 170 between either side of a resonance peak without crossing the resonance region, for example, by using a variable capacitor combining parallel and series LC circuits. As stated above, the simulation results shown in Figures 7A to 7D are not intended to be limiting, because the voltage amplitude ratio (V RF2 / V RF1Other configurations of the edge tuning circuit 170 may be used to provide other desired operating ranges for amplifying, reducing, and / or equalizing the current amplitude ratio and / or the phase difference between the second RF waveform 602 and the first RF waveform 601.

[0083]

[0093] In some embodiments, it may be desirable to select a tuning circuit configuration and / or variable capacitors C7, C8 that create a phase difference between the respective RF waveforms, thereby amplifying the electric field between the edge control electrode 115 and the bias electrode 104. The amplified electric field results in a corresponding increase in plasma density in the portion of the plasma 101 formed on the substrate support assembly 136 at a certain distance between the two electrodes. In some embodiments, it may be desirable to select a tuning circuit configuration and / or variable capacitor C7 that does not create a phase difference between the RF waveforms established at each electrode, so that the plasma density remains substantially uniform over the region extending to the edge of the substrate 103.

[0084]

[0094] Beneficially, the edge tuning circuit 170 may be configured to provide a wide range of desired plasma processing conditions in order to control and / or adjust the plasma density distribution at different points between the center and edge of the substrate 103. The characteristics of the edge tuning circuit 170, and consequently the position of the system on the tuning curve (Figures 7A-7D), can be controlled by adjusting one or more variable capacitors C7, C8 using the system controller 126. Controlled adjustment of the characteristics of the edge tuning circuit by the system controller 126 will make it possible to change plasma processing conditions relatively easily within a single substrate plasma process, between successive substrate plasma processes, and / or for different types of substrates, without the need to manually change hardware-related configurations. Accordingly, embodiments described herein may be used to provide an improved edge-to-center processing uniformity control method, as described below in relation to Figures 8A-8C and 9A-9D.

[0085]

[0095] In some embodiments, the tuning circuit is automatically adjusted to maintain desired processing conditions, such as taking into account plasma uniformity drift due to changes in the shape dimensions and / or materials of various components of the processing chamber 100 over time. For example, the method may be used to automatically adjust the tuning circuit by changing capacitances C7, C8 to account for changes in the thickness of the edge ring 114 that may be caused by erosion of the dielectric material used from the edge ring 114 by ion collisions. For example, in some embodiments, the system controller 126 may be configured to use a signal detection module 187 to detect signals of one or more electrical parameters at corresponding nodes N of the processing systems 10A, 10B, and to determine whether the processing systems 10A, 10B are operating within desired processing conditions by comparing the characteristics of the detected signals with one or more control limits, and to adjust one or more components of the edge tuning circuit 170 if the electrical signal characteristics are outside the control limits. Some embodiments include automatically adjusting the edge tuning circuit, such as adjusting the capacitance C7, to maintain a desired RF voltage amplitude ratio, RF current amplitude ratio, and / or RF phase difference between different RF waveforms at the edge control electrode 115 and the bias electrode 104.

[0086]

[0096] In some embodiments, the system controller 126 is configured to compare one or more processing conditions and / or RF waveforms with predetermined limits, such as control limits, and to automatically adjust the edge tuning circuit 170 based on desired processing conditions and / or desired characteristics between the RF waveforms of the edge control electrode 115 and the bias electrode 104 by changing one or more setpoints, such as the capacitances C7, C8 of the edge tuning circuit 170, based on an algorithm or lookup table stored in the memory 134 of the system controller 126.

[0087]

[0097] In some embodiments, the edge tuning circuit 170 may be manually tuned and / or controlled by adjusting one or more components of the edge tuning circuit 170 to a desired setpoint and / or within a desired control limit. A list of desired setpoints and / or control limits is selected by the user and stored in the instructions used to control the processing systems 10A, 10B. For example, the capacitance C7 of the edge tuning circuit 170 may be determined by the user and controlled to a desired capacitance stored in the memory of the system controller 126.

[0088] Processing applications

[0098] Generally, pulse voltage waveforms established on electrodes 104 and 115, such as negative pulse waveform 401, shaped pulse waveform 441, or positive pulse waveform 431, have a period T above the voltage offset (ΔV). PD It includes a repeating series of periodic pulse voltage (PV) waveforms. In one example, the period TPD of the PV waveform can be between approximately 1 μs and approximately 5 μs, approximately 2.5 μs, for example between approximately 200 kHz and approximately 1 MHz, or approximately 400 kHz, approximately 1 MHz or less, or approximately 500 kHz or less.

[0089]

[0099] As described above, in some embodiments, the processing chamber 100 includes at least one or more RF generators 118 and a first filter assembly 161 associated therewith, and one or more PV generators 314 and a second filter 151 associated therewith, which together are configured to supply a desired waveform to one or more electrodes located in a substrate support assembly 136. Software instructions stored in the memory of the system controller 126 are configured to generate RF waveforms configured to establish, maintain, and control one or more aspects of the plasma formed in the processing chamber. One or more aspects of the controlled plasma may include, but are not limited to, the plasma density, plasma chemistry, and ion energy in the plasma formed in the processing space 129.

[0090]

[0100] Figure 8A is a process flow diagram showing a method 800 for controlling plasma uniformity during substrate processing according to one embodiment. Figures 9A-9D are schematic close cross-sectional views showing parts of a processing system 10 that may be used to carry out embodiments of methods 800, 810, and 820. The parts of the processing system 10 shown in Figures 9A-9D are the edge portion of the substrate support assembly 136 and the corresponding portion of the processing area 129A and the chamber lid 123 located thereon. The processing system 10 illustrated in Figures 9A-9B may include any one or a combination of features of processing systems 10A and 10B described in Figures 1A-1B, respectively.

[0091]

[0101] In step 802, method 800 includes supplying a first radio frequency (RF) signal to the support base 107 of a substrate support assembly 136 located within the processing space 129 of the processing chamber 100. Generally, the RF signal is supplied to the support base 107 using a plasma generator assembly 163 electrically connected to the support base 107. Here, the RF signal is configured to ignite and / or maintain a processing plasma 101 in the processing area 129A of the processing chamber 100. The processing area 129A is located between the substrate support assembly 136 and the chamber lid 123. In some embodiments, the RF signal has a frequency of about 1 MHz or more, for example, about 20 MHz or more.

[0092]

[0102] Typically, the RF signal supplied to the support base 107 establishes a first RF waveform 601 (Figures 6A-6B) at the bias electrode 104. This bias electrode 104 is capacitively coupled to the support base 107 through a first portion of dielectric material (e.g., dielectric material layer 105C) placed between them. The bias electrode 104 is spaced apart from the processing plasma 101 by a second portion of dielectric material (e.g., dielectric material layer 105B) and, in some embodiments, a substrate 103 placed on a substrate support surface 105A. The substrate support surface 105A is formed from the second portion of dielectric material (e.g., dielectric material layer 105B).

[0093]

[0103] In some embodiments, the RF signal supplied to the support base 107 also establishes a second RF waveform 602 (Figures 6A-6B) at the edge control electrode 115 (second electrode), which may be capacitively coupled to the support base 107 through a third portion of dielectric material positioned between them. In some embodiments, such as shown in Figure 1A, the third portion of dielectric material may be formed of the same material and have the same thickness as the first portion of dielectric material that isolates the bias electrode 104 from the support base 107. In some embodiments, such as shown in Figure 9A, the third portion of dielectric material isolates the edge control electrode 115 from the support base 107. In other embodiments, the third portion of dielectric material may be formed of a different dielectric material than the first portion of dielectric material and / or may be isolated from the support base 107 by multiple layers of dielectric material, as shown in Figure 1B.

[0094]

[0104] In some embodiments, Method 800 further includes electrostatically clamping the substrate 103 to the substrate support 105 by supplying a chucking voltage to the bias electrode 104 from a DC power supply 155 electrically connected to the bias electrode 104 using a power supply line 157. The chucking voltage is used to create a potential between the substrate 103 and the bias electrode 104, thereby generating an electrostatic attraction force (chucking force) through the capacitance C1 of a first portion of dielectric material placed between them. In some embodiments, Method 800 further includes electrostatically clamping the edge ring 114 to the substrate support assembly 136 by supplying a chucking voltage to the edge control electrode 115 from a DC power supply 155 electrically connected to the edge control electrode 115 using a power supply line 158. In some embodiments, Method 800 includes introducing an inert gas (e.g., helium) into the gap regions located between the substrate 103 and the substrate support surface 105A and / or between the edge ring 114 and the surface of the substrate support assembly 136 to facilitate heat transfer between them.

[0095]

[0105] In step 804, method 800 includes adjusting one or more characteristics of the second RF waveform 602 established at the edge control electrode 115 to one or more characteristics of the first RF waveform 601 established at the bias electrode 104. In some embodiments, adjusting one or more characteristics of the second RF waveform 602 to one or more characteristics of the first RF waveform 601 is such that the voltage amplitude ratio between the second RF waveform 602 and the first RF waveform 601 is adjusted (for example, the voltage amplitude ratio between the second RF waveform 602 and the first RF waveform 601 (V) as shown in Figure 6A or Figure 6B. RF2 / V RF1 This includes changing the current amplitude ratio between the second RF waveform 602 and the first RF waveform, adjusting the phase difference between the second RF waveform 602 and the first RF waveform 601, for example, delta Φ, adjusting the supplied power ratio between the second RF waveform 602 and the first RF waveform 601, or a combination thereof. Adjusting one or more characteristics of the second RF waveform 602 with respect to the first RF waveform 601 is performed by adjusting one or more electrical characteristics of elements in the edge tuning circuit 170.

[0096]

[0106] In some embodiments, adjusting the second RF waveform 602 relative to the first RF waveform 601 alters the plasma uniformity over at least a portion of the processing region 129A. For example, in one embodiment, the processing region 129A is defined by a chamber lid 123 and a substrate support assembly 136, and the plasma 101 is the bulk plasma formed between them. In some embodiments, the first portion of the plasma 101 is formed in the region located between the chamber lid 123 and the bias electrode 104. The second portion of the plasma 101 is formed in the region located between the chamber lid 123 and the edge control electrode 115. In those embodiments, adjusting the second RF waveform 602 relative to the first RF waveform 601 alters the plasma density in the second portion of the plasma 101 relative to the plasma density in the first portion of the plasma 101.

[0097]

[0107] In some embodiments, tuning one or more characteristics of a second RF waveform 602 established at the edge control electrode 115 to one or more characteristics of a first RF waveform 601 established at the bias electrode 104 involves using an edge tuning circuit electrically connected to the edge control electrode 115, such as the edge tuning circuit 170 shown in Figure 9A and described above. In some embodiments, the edge tuning circuit 170 includes one or more variable capacitors C7, C8, and tuning one or more characteristics of the second RF waveform 602 to one or more characteristics of the first RF waveform 601 involves changing one or more variable capacitors C7, C8. The tuning of the edge tuning circuit 170 may be performed automatically by a system controller 126 to adjust the electrical characteristics of one or more components of the edge tuning circuit 170, such as capacitors C7, C8, based on desired characteristics of the RF waveforms 601, 602 and / or desired difference between them. For example, in some embodiments, the system controller 126 may be configured to determine the characteristics of each waveform by measuring one or more characteristics of electrical signals taken at one or more nodes N using a signal detection module 187, compare the determined characteristics with a desired characteristic, and change the output of the components of the edge tuning circuit 170 based on the comparison. In some embodiments, the edge tuning circuit 170 may be manually tuned when the user changes the setpoint of a component of the edge tuning circuit 170, such as the capacitance of variable capacitors C7, C8 or the inductance L of the circuit. The user may change the setpoint by using the system controller 126 and / or the signal detection module 187 to change, for example, a recipe parameter corresponding to a component or another setting in an instruction used by the system controller 126 to operate processing systems 10A, 10B.

[0098]

[0108] Generally, assuming that a relatively constant RF power is supplied from the plasma generator assembly 163 to the support base 107, the use of the edge tuning circuit 170 allows V RF2 / V RF1As the ratio increases, the ratio of plasma density near the substrate edge to plasma density near the center of the substrate increases. This relative increase in plasma density leads to a corresponding increase in plasma-generated species in the bulk plasma, and therefore, a relative increase in ion flux and activated neutral gas molecule flux at the substrate surface edge below. Similarly, V RF2 / V RF1 As the ratio decreases, the ratio of plasma density near the substrate edge to plasma density near the substrate center decreases, and the ion flux and activated neutral gas molecule flux at the substrate edge decrease in a corresponding manner.

[0099]

[0109] By controlling the relative plasma density between the first and second portions of the plasma, the corresponding distribution of active species within the processing region 129A is also controlled and can be used to improve overall processing non-uniformity, such as in-wafer processing non-uniformity. Advantageously, Method 800 can be implemented as a processing parameter adjustment, for example, by controlling the edge tuning circuit 170 using the system controller 126 to adjust capacities C7, C8. Thus, Method 800 can be implemented without relying on mechanical adjustments or hardware configuration changes, which are typically required to adjust the bulk plasma distribution in a capacitively coupled plasma (CCP) system and therefore hinder its fine control.

[0100]

[0110] In step 806, method 800 (optionally) includes establishing pulse voltage (PV) waveforms in one or both of the bias electrode 104 and the edge control electrode 115. Here, a first PV voltage waveform may be established in the bias electrode 104 using a first PV source assembly 196. A second PV waveform may be established in the edge control electrode 115 using a second PV source assembly 197. As described above, the PV waveform generator 150 can be used to establish a substantially constant sheath voltage (e.g., a substantially constant difference between the substrate potential and the plasma potential) that provides a single peak IEDF for ions accelerating toward the substrate surface, and / or can be operated to provide a desired IEDF profile of ion energy at the substrate surface.

[0101]

[0111] In some embodiments, the first and / or second PV waveforms comprise a series of repeating cycles, the waveform within each cycle having a first portion occurring during a first time interval, e.g., the sheath formation phase 451 and the ion current phase 452 (Figure 4), and a second portion occurring during a second time interval, e.g., the sheath collapse phase 450. In some embodiments, the waveform established on the substrate surface is substantially constant for at least part of the second time interval, and the second time interval is longer than the first time interval. In some embodiments, the first and / or second PV waveforms each have a voltage peak in the first time interval and have a substantially positive or substantially negative slope for at least part of the second time interval. In some embodiments, the second time interval is longer than the first time interval. In other embodiments, the second time interval is shorter than or approximately the same as the first time interval.

[0102]

[0112] In step 808, method 800 optionally includes adjusting one or both of the first PV waveform established at the bias electrode 104 and the second PV waveform established at the edge control electrode 115. In some embodiments, the first and second PV waveforms at each electrode are independently controllable to allow for fine-tuning of the desired relative sheath voltage between the center and edge of the substrate, thereby enabling fine-tuning of the relative ion energy at the substrate surface between them. Thus, in some embodiments, step 808 includes adjusting one or more characteristics of the first PV waveform for one or more characteristics of the second PV waveform. In some embodiments, adjusting one or more characteristics involves adjusting the PV waveform frequencies (1 / T) of the first and / or second PV waveforms established at the bias electrode 104 and the edge control electrode 115, respectively. P This includes adjusting one or a combination of the pulse voltage level Vpp and the pulse voltage on-time.

[0103]

[0113] The ability to independently control the first and second PV waveforms at the bias electrode 104 and the edge control electrode 115 allows control over the direction of ion collisions with the exposed surface of the substrate 103 at its edge. For example, in some embodiments, one or more characteristics may be controlled to provide a plasma sheath with uniform thickness between the central region 103A and the edge region 103B of the substrate, such that the plasma sheath boundary is generally parallel to the surface of the substrate 103 so as to extend across the edge region. Because the plasma sheath thickness is uniform, the ion incidence angle is generally perpendicular to the substrate surface. In some embodiments, one or more characteristics may be controlled to increase or decrease the sheath height on the edge control electrode 115 relative to the sheath height on the bias electrode 104, thereby bending the plasma sheath at the substrate edge to allow for fine-tuning of ion orbitals and ion energy in the substrate edge region.

[0104]

[0114] Advantageously, the independent PV waveform bias schemes at the bias electrode 104 and the edge control electrode 115 can be used separately from and / or in combination with the plasma density uniformity and distribution control provided by the edge tuning circuit 170. Thus, method 800 advantageously provides fine process control over ion energy and directional uniformity across the substrate surface using the PV bias scheme, and fine control over plasma density uniformity and / or plasma density distribution using the radio frequency (RF) edge tuning scheme.

[0105]

[0115] Figure 8B is a process flow diagram showing a method 810 for controlling the plasma density distribution, for example by using an edge tuning circuit 170, to reduce the particulate matter-related defect rate on the surface of the substrate 103 and / or the accumulation of particulate matter-related residue on the surface within the processing space 129. Such particulate matter-related defect rates can originate from any number of sources, including process-generated particulate matter during the etching process in which the material is sputtered from the substrate surface, particulate matter from the surface within the processing space, particulate matter introduced into the processing space during substrate transport, and / or particulate matter introduced into the processing space during system maintenance. Often, such particles, shown as particulate matter 30 in Figures 9A-9C, are charged and remain suspended in the plasma 101 during substrate processing, only settling on the surface of the substrate 103 when the plasma 101 disappears. Therefore, in some embodiments, Method 810 may be used to preferentially adjust the plasma density toward the outer edge of the substrate support assembly 136 before extinguishing the plasma 101 so that suspended particles can be swept away from their position on the substrate surface and exhausted from the processing space 129 through the vacuum outlet 120, rather than settling on the surface of the substrate 103. Method 810 may be used in combination with other methods described herein, such as Methods 800 and 820, or independently thereof.

[0106]

[0116] In step 812, method 810 includes supplying an RF signal to a support base 107, the RF signal being configured to ignite and / or maintain a plasma 101 formed in a processing area 129A of the processing space 129. Here, the RF signal establishes a first RF waveform 601 at the bias electrode 104 and a second RF waveform 602 at the edge control electrode 115.

[0107]

[0117] In step 814, method 810 includes tuning one or both of the second RF waveform 602 and the first RF waveform 601 by tuning the electrical properties of one or more elements in the edge tuning circuit 170 to increase the plasma density in the portion of the plasma formed on the edge control electrode 115 relative to the plasma density in the portion of the plasma formed on the bias electrode 104, as shown in Figure 9B. Increasing the plasma density on the edge control electrode 115 relative to the plasma density on the bias electrode 104 causes particles suspended in the central portion of the plasma to move radially outward toward the peripheral edge of the substrate support assembly 136.

[0108]

[0118] In step 816, method 810 includes lifting the substrate 103 from the substrate support surface 105A, for example, by using a plurality of pins 20. Typically, lifting the substrate 103 from the substrate support surface 105A includes un-chucking the substrate by stopping the supply of a chucking voltage to the bias electrode 104 and stopping the generation of electrostatic chucking force between the substrate 103 and the bias electrode 104, before extending the plurality of pins 20 to extend the substrate above the substrate support surface 105A. In some embodiments, the substrate 103 is lifted from the substrate support surface 105A before step 814. In some embodiments, the inflow of helium into the gap region 105D (Figure 1C) is stopped or reduced before the substrate 103 is un-chucking. In other embodiments, the helium inflow is continued to remove particulate matter from the region located between the outer edge of the substrate 103 and the radially inward surface of the edge ring 114 as the substrate 103 is lifted from the substrate support surface 105A, for example, by blowing it outward. In some embodiments, the flow rate of the process gas flowing into the chamber and / or the vacuum provided by the vacuum pump may be adjusted to increase the radial flow within the chamber to blow or transport the particulate matter radially outward from the substrate surface.

[0109]

[0119] In step 818, method 810 includes extinguishing the processing plasma 101, for example, by stopping the supply of an RF signal to the support base 107 and transferring the substrate 103 from the processing space 129. In some embodiments, the plasma is extinguished in step 816 before the substrate 103 is lifted from the substrate support surface 105A. Advantageously, preferentially adjusting the plasma density toward the outer edge of the substrate 103 by tuning the electrical properties of one or more elements in the edge tuning circuit 170 to move the suspended particulate matter 30 radially outward toward one or more side walls 122 of the processing area 129A (from which the suspended particulate matter 30 can be exhausted through the vacuum outlet 120) is at least reduced, as shown in Figure 9C, when the processing plasma 101 is extinguished.

[0110]

[0120] Figure 8C is a process flow diagram showing an in-situ plasma chamber cleaning method, here referred to as Method 820, which can be used to clean processing byproducts accumulated from the edge ring 114 and / or adjacent portions of the substrate support surface 105A while reducing in-situ plasma base damage to the central region of the substrate support surface 105A. As shown in Figure 9D, Method 820 can be performed between substrate processing, for example, when the substrate is not placed on the substrate support 105.

[0111]

[0121] In step 822, method 820 includes supplying a radio frequency (RF) signal to a support base 107 to ignite and maintain the plasma 101 in the processing area 129A. As shown in Figure 9D, the processing plasma 101 is an in-situ cleaning plasma that can be formed by one or more cleaning gases flowing into the processing area 129A through a gas inlet 128. In some embodiments, the cleaning gases include halogenated gases, e.g., fluorine and / or chlorine-based gases, and oxidizing gases, e.g., oxygen-based gases. Generally, radical species of the plasma-activated cleaning gases react with processing by-products accumulated on the surface in the processing space 129 to form volatile reaction products. These volatile reaction products can then be discharged through the processing space 129 from a vacuum outlet 120.

[0112]

[0122] In step 824, method 820 includes adjusting the plasma density of the portion of plasma formed on the edge control electrode 115 with respect to the plasma density of the portion of plasma formed on the bias electrode 104 by adjusting the electrical characteristics of one or more elements in the edge tuning circuit 170. By preferentially adjusting the plasma density, the flux of cleaning gas radicals increased on the surface of the edge ring 114 and radially adjacent portions of the substrate support surface 105A, for example, the portion of the substrate support assembly 136 that defines the outer peripheral gap between the substrate 103 and the edge ring 114, and during substrate processing. This gap accumulated processing byproduct residue faster than other portions of the substrate support surface 105A, and the substrate support surface 105A is not exposed during plasma processing because the substrate 103 is placed on it. Therefore, method 820 can be used to concentrate cleaning gas radicals in areas where the accumulation of processing by-product residues is higher, while reducing ion-based damage such as ion flux and thus erosion of the dielectric material forming a larger central portion of the substrate support surface 105A.

[0113]

[0123] The embodiments described above can be used individually or in combination to provide fine control over the generation and distribution of active species within the processing area of ​​a capacitively coupled plasma (CCP) chamber. Advantageously, these embodiments can be implemented using a system controller without adjusting or modifying individual chamber components. Thus, easily adjustable processing recipe parameters are provided for processing a single substrate and / or between continuously processed substrates. Compared to conventional RF-biased CCP systems, the RF plasma density control method can be implemented independently and / or in combination with a pulsed voltage (PV) waveform biasing method to independently and finely control ion energy, IEDF, ion directionality, ion flux, and activated neutral gas molecular flux on the substrate surface.

[0114]

[0124] While the above description applies to embodiments of the present disclosure, other embodiments and further embodiments of the present disclosure may be devised without departing from the basic scope of the present disclosure, and the scope of the present disclosure is determined by the following claims.

Claims

1. A substrate support assembly, Support base, A first electrode is positioned on the support base and is spaced apart from the support base by a first portion of the dielectric material, A second portion of the dielectric material disposed on the first electrode, the second portion of the dielectric material forming a substrate support surface, and A second electrode is positioned at a distance from the center of the first electrode and is separated from the support base by a third portion of the dielectric material. A substrate support assembly comprising, One or more pulse voltage waveform generators electrically connected to the first electrode and the second electrode, A radio frequency (RF) generator electrically connected to the support base, The RF generator is configured to supply an RF signal to the support base. The RF signal establishes a first RF waveform at the first electrode in an RF generator, An edge tuning circuit electrically connected to the second electrode, wherein the edge tuning circuit is configured to adjust one or more characteristics of the second RF waveform established by the second electrode with respect to one or more characteristics of the first RF waveform established by the first electrode. A plasma processing system equipped with [the following features].

2. The edge tuning circuit described above, (a) The voltage amplitude ratio between the second RF waveform at the second electrode and the first RF waveform at the first electrode, (b) the phase difference between the second RF waveform at the second electrode and the first RF waveform at the first electrode, and (c) The power ratio between the second RF waveform at the second electrode and the first RF waveform at the first electrode. The plasma processing system according to claim 1, configured to adjust one or more characteristics of the second RF waveform with respect to one or more characteristics of the first RF waveform by changing one or a combination of the following.

3. The plasma processing system according to claim 1, wherein the RF signal supplied by the RF generator is configured to ignite and maintain plasma from gas or vapor supplied to the processing area of ​​the processing chamber.

4. The plasma processing system according to claim 3, wherein the RF generator is configured to supply the RF signal at a frequency of approximately 1 MHz or higher.

5. The plasma processing system according to claim 1, wherein the substrate support assembly is configured to establish the second RF waveform on the second electrode by capacitively coupling the second electrode to the support base through a third portion of the dielectric material.

6. The plasma processing system according to claim 5, wherein a conductive edge ring is capacitively coupled to the second electrode.

7. The system further comprises a processing chamber, and the processing chamber is Chamber lids that collectively define the processing space, one or more chamber walls, and chamber bases. Equipped with, The plasma processing system according to claim 6, wherein the processing chamber is configured to ignite and maintain the plasma of a gas or vapor supplied to the processing area by capacitively coupling the plasma to the chamber lid and the substrate support assembly.

8. A chamber lid and one or more chamber walls, wherein the chamber lid faces the substrate support assembly, and the chamber lid, the one or more chamber walls, and the substrate support assembly collectively define a processing area, When executed by the processor, it consists of computer execution instructions stored in memory, configured to perform a method of processing the circuit board. The order further includes, (i) Ignition and maintenance of a plasma from a gas or vapor supplied to the processing area, wherein a first portion of the plasma is formed between the chamber lid and the first electrode, and a second portion of the plasma is formed between the chamber lid and the second electrode, and (ii) Using the edge tuning circuit to change the ratio of the plasma density in the second portion of the plasma to the plasma density in the first portion of the plasma, thereby adjusting one or more characteristics of the second RF waveform with respect to one or more characteristics of the first RF waveform, wherein the respective plasma densities are such that the ratio of the plasma density in the first portion and the second portion of the plasma is 1 cm ３ Adjusting one or more characteristics of the second RF waveform, including the number of free electrons per unit area. A plasma processing system according to claim 1, including the following:

9. Adjusting one or more characteristics of the second RF waveform with respect to one or more characteristics of the first RF waveform increases the plasma density in the second part of the plasma with respect to the plasma density in the first part of the plasma, and the method (iii) Before or after (ii), lift the substrate from the substrate support surface, and (iv) After (iii), extinguish the plasma. The plasma processing system according to claim 8, further comprising:

10. One or more pulse voltage waveform generators are configured to establish a first pulse voltage waveform and a second pulse voltage waveform, respectively, on the first electrode and the second electrode. The first pulse voltage waveform and the second pulse voltage waveform each include a series of repeating cycles, and the waveform within each repeating cycle has a first portion that occurs during a first time interval and a second portion that occurs during a second time interval. The waveform has a voltage peak during the first time interval, and The plasma processing system according to claim 1, wherein the waveform has a substantially positive slope, a substantially negative slope, or is substantially constant for at least a portion of the second time interval.

11. A first transmission line electrically connects a first pulse voltage waveform generator among the one or more pulse voltage waveform generators to the first electrode, and comprises a first blocking capacitor disposed between the first pulse voltage waveform generator and the first electrode. A first clamping network comprising a first direct current (DC) voltage source and a first blocking resistor, wherein the first DC voltage source is electrically connected between a first point on the first transmission line and ground, the first point is located between a first blocking capacitor and a first electrode, and the first blocking resistor is electrically connected between the first point and the first DC voltage source. The plasma processing system according to claim 1, further comprising the following:

12. (i) Using an RF signal from a radio frequency (RF) generator to generate a plasma of gas or vapor supplied to a processing area defined by the chamber lid and the substrate support assembly, wherein the substrate support assembly A support base electrically connected to the RF generator, A first electrode disposed on the support base and spaced apart from the support base by a first portion of a dielectric material, wherein the RF signal establishes a first RF waveform at the first electrode, A second portion of the dielectric material disposed on the first electrode, the second portion of the dielectric material forming a substrate support surface, and A second electrode is positioned at a distance from the center of the first electrode, spaced apart from the support base by a third portion of the dielectric material, and electrically connected to the edge tuning circuit. A device that generates a gas or vapor plasma, (ii) Establishing a second RF waveform at the second electrode by using the RF signal and the tuning circuit, wherein the second RF waveform is such that one or more characteristics of the first RF waveform are different from the characteristics of the second RF waveform. A method for processing a substrate, including the processing of a substrate.

13. The one or more different characteristics between the first RF waveform and the second RF waveform are, (a) The difference in voltage amplitude ratio between the second RF waveform at the second electrode and the first RF waveform at the first electrode, (b) The difference in current amplitude ratio between the second RF waveform and the first RF waveform, (c) The phase difference between the second RF waveform at the second electrode and the first RF waveform at the first electrode, or (d) A combination of (a), (b), or (c) The method according to claim 12, including the method described in claim 12.

14. The first portion of the plasma is formed between the chamber lid and the first electrode. The second portion of the plasma is formed between the chamber lid and the second electrode. The one or more different characteristics between the second RF waveform and the first RF waveform are configured to control the plasma density in the second portion of the plasma with respect to the plasma density in the first portion of the plasma, wherein the plasma density is such that ３ The method according to claim 13, including the number of free electrons per unit.

15. (iii) Adjusting one or more characteristics of the second RF waveform with respect to the first RF waveform in order to increase the plasma density in the second part of the plasma with respect to the plasma density in the first part of the plasma, (iv) Lifting the substrate at least partially from the substrate support surface, and (v) After (iv), extinguish the plasma. The method according to claim 14, further comprising:

16. The method according to claim 15, wherein adjusting the one or more characteristics of the second RF waveform with respect to the one or more characteristics of the first RF waveform includes changing the capacitance of one or more variable capacitors of an edge tuning circuit.

17. The method according to claim 16, wherein generating the plasma includes igniting and maintaining the plasma from the gas or vapor supplied to the processing area by capacitively coupling the plasma to the chamber lid and the substrate support assembly.

18. The plasma is a cleaning plasma formed from one or more cleaning gases. The plasma density in the second portion of the cleaning plasma is greater than the plasma density in the first portion of the cleaning plasma, and The method according to claim 13, further comprising exposing the surface of the substrate support assembly to the cleaning plasma in order to remove processing by-products.

19. The method further includes establishing a first pulse voltage waveform at the first electrode using a first pulse voltage waveform generator. The first pulse voltage waveform includes a series of repeating cycles, The method according to claim 12, wherein the waveform within each cycle has a first portion that occurs during a first time interval and a second portion that occurs during a second time interval.

20. To electrostatically chuck the substrate to the substrate support assembly, a first direct current (DC) voltage source is used to supply a chucking voltage to the first electrode. It further includes, The first pulse voltage waveform generator is electrically connected to the first electrode using a first transmission line, the first transmission line includes a first blocking capacitor, and The method according to claim 19, wherein the first DC voltage source is electrically connected between a first point of the first transmission line and ground, and the first point is located between the first blocking capacitor and the first electrode.

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