Display board and method for manufacturing the same, display device

Abstract

The present invention provides a display panel, a manufacturing method thereof, and a display device. The display substrate includes a base substrate, a first electrode layer provided on one side of the base substrate and including a first electrode pattern, a first flat layer provided on the side of the first electrode layer away from the base substrate, and a second electrode layer, a second flat layer, and a third electrode layer stacked on the side of the first flat layer away from the base substrate, the first flat layer has a through hole, the through hole penetrates the first flat layer so as to expose the first electrode pattern, the second electrode layer is provided close to the base substrate, an orthogonal projection of the second electrode layer on the base substrate covers an orthogonal projection of the through hole on the base substrate, the second electrode layer connects the first electrode pattern and the third electrode layer, and the second flat layer is filled in the through hole so as to flatten the through hole.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and particularly to a display substrate, a manufacturing method thereof, and a display device.

Background Art

[0002] Currently, liquid crystal displays are still the mainstream displays. The display panel in a liquid crystal display generally includes an array substrate, a stacked substrate, and liquid crystal filled between the array substrate and the stacked substrate. However, with the improvement of the pixel density of the display panel, the size of a single pixel unit becomes smaller and smaller, so the pixel aperture ratio becoming lower and lower is a problem that needs to be urgently solved in this field.

Summary of the Invention

[0003] The present invention provides a display substrate, and the display substrate includes a base substrate, a first electrode layer provided on one side of the base substrate and including a first electrode pattern, a first flat layer provided on the side of the first electrode layer away from the base substrate, a second electrode layer, a second flat layer, and a third electrode layer stacked on the side of the first flat layer away from the base substrate, a through hole is provided in the first flat layer, and the through hole penetrates the first flat layer so as to expose the first electrode pattern, the second electrode layer is provided so as to approach the base substrate, the orthographic projection of the second electrode layer on the base substrate covers the orthographic projection of the through hole on the base substrate, the second electrode layer connects the first electrode pattern and the third electrode layer, and the second flat layer is filled in the through hole so as to planarize the through hole.

[0004] In an optional implementation form, the orthographic projection of the through hole on the base substrate is completely within the orthographic projection of the second electrode layer on the base substrate.

[0005] In one selectable mounting configuration, the orthographic projection of the second electrode layer on the base substrate is completely contained within the orthographic projection of the third electrode layer on the base substrate.

[0006] In one selectable mounting configuration, the orthographic projection of the second flat layer on the base substrate is completely contained within the orthographic projection of the third electrode layer on the base substrate.

[0007] In one selectable mounting configuration, the shape of the through-hole and the second electrode layer is rectangular, circular, or elliptical.

[0008] In one selectable mounting configuration, the display board includes a display area and a non-display area, and the display area includes an aperture area and a non-aperture area. The display substrate further includes a first thin-film transistor provided between the base substrate and the first electrode layer, the first thin-film transistor being located in the display region, the first thin-film transistor comprising a stacked first active layer, a first gate insulating layer and a first gate, the first active layer comprising a drain contact region, The first electrode layer further includes a second electrode pattern formed integrally with the first electrode pattern, the second electrode pattern being connected to the drain contact region, and the first electrode pattern being located in the non-opening region.

[0009] In one selectable mounting configuration, the first active layer is provided so as to be close to the base substrate, a first interlayer dielectric layer, a first source, and a first passivation layer are laminated on the side of the first gate away from the base substrate, the first electrode layer is provided on the side of the first passivation layer away from the base substrate, and the second electrode pattern is connected to the drain contact region via via holes provided in the first passivation layer, the first interlayer dielectric layer, and the first gate insulating layer.

[0010] In one selectable mounting configuration, the material of the first electrode layer is a transparent conductive material.

[0011] In one selectable mounting configuration, the drain contact region is located in the non-opening region, and the material of the first electrode layer is a metal.

[0012] In one selectable mounting configuration, the drain contact region is located in the non-opening region, and the orthographic projections of the first gate insulating layer, the first interlayer dielectric layer, and the first passivation layer on the base substrate do not overlap with the opening region.

[0013] In one selectable mounting configuration, the first active layer is provided so as to be close to the base substrate, and a first interlayer dielectric layer and a first source-drain layer are laminated on the side of the first gate away from the base substrate, the first source-drain layer includes a first source and a first drain provided in the same layer, the first drain is connected to the drain contact region via via holes provided in the first interlayer dielectric layer and the first gate insulating layer, the first electrode layer is provided on the side of the first drain away from the base substrate, and the second electrode pattern is connected in contact with the first drain.

[0014] In one selectable mounting configuration, the drain contact region is located in the non-opening region, and the material of the first drain is metal.

[0015] In one selectable mounting configuration, the display board includes a display area and a non-display area, and the display area includes an aperture area and a non-aperture area. The display substrate further includes a first thin-film transistor provided on the side of the base substrate closer to the first electrode layer, the first thin-film transistor located in the display region, the first thin-film transistor comprising a stacked first active layer, a first gate insulating layer, a first gate, a first interlayer dielectric layer, and a first source, the first active layer being provided closer to the base substrate, the first active layer including a drain contact region, the drain contact region being located in the opening region, The orthographic projections of the first gate insulating layer and the first interlayer dielectric layer on the base substrate do not overlap with the aperture region, and the drain contact region is the first electrode pattern.

[0016] In one selectable implementation configuration, the material of the first active layer includes a metal oxide.

[0017] In one selectable implementation, the display area further includes data lines and scan lines, the first source extending along a first direction to constitute the data lines, the first gate extending along a second direction intersecting the first direction to constitute the scan lines, and the orthographic projections of the data lines and scan lines on the base substrate each cover the orthographic projection of the channel area of ​​the first active layer on the base substrate.

[0018] In one selectable implementation configuration, the material of the first active layer includes polycrystalline silicon, and the orthographic projection of the data lines on the base substrate covers the orthographic projection of the first active layer on the base substrate.

[0019] In one selectable mounting configuration, a shielding layer and a second interlayer dielectric layer are further laminated between the first active layer and the base substrate, the shielding layer is positioned close to the base substrate, and the orthographic projection of the shielding layer on the base substrate covers the orthographic projection of the channel region of the first active layer on the base substrate.

[0020] In an optional implementation form, the display area further includes data lines and scanning lines, and the orthographic projection of the shielding layer on the base substrate covers the orthographic projections of the data lines and the scanning lines on the base substrate.

[0021] In an optional implementation form, the shielding layer is connected to a fixed potential input terminal.

[0022] In an optional implementation form, the shielding layer is connected to the first source through via holes provided in the second interlayer dielectric layer, the first gate insulating layer, and the first interlayer dielectric layer.

[0023] In an optional implementation form, the material of the shielding layer includes at least one of molybdenum, aluminum, and silver.

[0024] In an optional implementation form, the display substrate further includes a second thin film transistor, the second thin film transistor is located in the non-display area, and the material of the active layer of the second thin film transistor includes polycrystalline silicon.

[0025] In an optional implementation form, the channel region of the first active layer includes a first channel region, a first resistance region, and a second channel region sequentially arranged along a first direction, the first gate includes a first sub-gate and a second sub-gate provided separately, the orthographic projection of the first sub-gate on the base substrate covers the orthographic projection of the first channel region on the base substrate, and the orthographic projection of the second sub-gate on the base substrate covers the orthographic projection of the second channel region on the base substrate.

[0026] In an optional implementation form, a second passivation layer and a fourth electrode layer are laminated on the side of the first electrode layer away from the base substrate. The fourth electrode layer is transparent and connected to the first fixed potential input terminal. The second passivation layer is provided so as to approach the base substrate. The first electrode layer overlaps with the orthographic projection of the fourth electrode layer on the base substrate. The first flat layer is provided on the side of the fourth electrode layer away from the base substrate. The through hole penetrates the second passivation layer, and the through hole does not overlap with the orthographic projection of the fourth electrode layer on the base substrate.

[0027] In an optional implementation form, the display substrate includes an opening region, and a color resist layer is further provided on the side of the first electrode layer away from the base substrate. The orthographic projection of the color resist layer on the base substrate covers the opening region. The first flat layer is provided on the side of the color resist layer away from the base substrate. The orthographic projection of the through hole on the base substrate does not overlap with the orthographic projection of the color resist layer on the base substrate.

[0028] In an optional implementation form, a third passivation layer and a common electrode layer are laminated on the side of the third electrode layer away from the base substrate. The third passivation layer is provided so as to approach the base substrate. The common electrode layer includes a plurality of strip-shaped electrodes, and the material of the common electrode layer is metal.

[0029] In an optional implementation form, isolation columns are further provided on the side of the first flat layer away from the base substrate. The isolation columns are formed synchronously with the second flat layer.

[0030] The present invention provides a display device including the display substrate described in any embodiment.

[0031] The present invention provides a method for manufacturing a display substrate. The manufacturing method includes: The steps include preparing the base board and The steps include forming a first electrode layer including a first electrode pattern on one side of the base substrate, A first flat layer is sequentially formed on the side of the first electrode layer away from the base substrate, and through holes are provided in the first flat layer, and the through holes penetrate the first flat layer so as to expose the first electrode pattern. The process includes the step of sequentially forming a second electrode layer, a second flat layer, and a third electrode layer on the side of the first flat layer away from the base substrate, The orthographic projection of the second electrode layer on the base substrate covers the orthographic projection of the through hole on the base substrate, the second electrode layer is for connecting the first electrode pattern and the third electrode layer, and the second flat layer is for flattening the through hole.

[0032] The above description is merely an overview of the proposed technical aspects of the present invention, and to further clarify the technical means of the present invention, it can be implemented according to the specifications, and to further clarify the above and other objectives, features and merits of the present invention, embodiments of the present invention are specifically listed below. [Brief explanation of the drawing]

[0033] Below, in order to more clearly explain the technical concepts in the embodiments of the present invention or related technologies, the drawings that need to be used in describing the embodiments or related technologies are briefly introduced. The drawings in the following description represent only some embodiments of the present invention, and it is obvious to those skilled in the art that other drawings can be obtained from these drawings without requiring any creative work. Note that the proportions in the drawings are schematic and do not represent actual proportions.

[0034] [Figure 1] This is a schematic diagram showing the cross-sectional structure of a display substrate provided in an embodiment of the present invention. [Figure 2] This is a schematic diagram showing the cross-sectional structure of a display substrate provided in an embodiment of the present invention. [Figure 3]This is a schematic diagram showing the cross-sectional structure of a display substrate provided in an embodiment of the present invention. [Figure 4] This is a schematic diagram of the planar structure of a display substrate provided in an embodiment of the present invention. [Figure 5] This is a schematic diagram showing the planar structure of the first thin-film transistor provided in an embodiment of the present invention. [Figure 6] This is a schematic diagram showing the cross-sectional structure of the first thin-film transistor provided in an embodiment of the present invention. [Figure 7] This is a schematic diagram showing the planar structure of the shielding layer provided in an embodiment of the present invention. [Figure 8] This is a schematic diagram showing the cross-sectional structure of a display substrate after the manufacturing of the second electrode layer provided in an embodiment of the present invention has been completed. [Figure 9] This is a schematic diagram showing the cross-sectional structure of a display substrate after the fabrication of the second flat material layer provided in an embodiment of the present invention has been completed. [Figure 10] This is a schematic diagram showing the cross-sectional structure of a display substrate after the manufacturing of the second flat layer provided in an embodiment of the present invention has been completed. [Figure 11] This is a schematic diagram showing the cross-sectional structure of a display substrate after the manufacturing of the third electrode layer provided in an embodiment of the present invention has been completed. [Figure 12] This is a schematic diagram showing the cross-sectional structure of a display substrate after the fabrication of the third passivation layer provided in an embodiment of the present invention has been completed. [Figure 13] This is a schematic diagram showing the cross-sectional structure of a display substrate after the common electrode layer provided in an embodiment of the present invention has been manufactured. [Figure 14] This is a schematic diagram showing the planar structure of a display substrate after the first active layer provided in an embodiment of the present invention has been manufactured. [Figure 15] This is a schematic diagram showing the planar structure of a display board after the first gate provided in an embodiment of the present invention has been manufactured. [Figure 16] This is a schematic diagram showing the planar structure of a display substrate after the first interlayer dielectric layer provided in an embodiment of the present invention has been manufactured. [Figure 17]This is a schematic diagram showing the planar structure of a display board after the data lines provided in an embodiment of the present invention have been manufactured. [Figure 18] This is a schematic diagram showing the planar structure of a display substrate after the first electrode layer provided in an embodiment of the present invention has been manufactured. [Figure 19] This is a schematic diagram showing the planar structure of a display substrate after the manufacturing of the color resist layer provided in an embodiment of the present invention has been completed. [Figure 20] This is a schematic diagram showing the planar structure of a display substrate after the first flat layer provided in an embodiment of the present invention has been manufactured. [Figure 21] This is a schematic diagram showing the planar structure of a display substrate after the fabrication of the third electrode layer provided in an embodiment of the present invention has been completed. [Figure 22] This is a schematic diagram showing the planar structure of a display substrate after the common electrode layer provided in an embodiment of the present invention has been manufactured. [Modes for carrying out the invention]

[0035] Hereinafter, in order to further clarify the object, technical proposal, and advantages of the embodiments of the present invention, the technical proposal of the embodiments of the present invention will be described more clearly and completely with reference to the drawings of the embodiments of the present invention. It is clear that the embodiments described are merely some embodiments of the present invention, and not all embodiments. All other embodiments obtained based on the embodiments of the present invention, without requiring any creative work from those skilled in the art, fall within the scope of the protection of the present invention.

[0036] One embodiment of the present invention provides a display substrate. Referring to Figures 1 to 3, this display substrate includes a base substrate 11, a first electrode layer 12 provided on one side of the base substrate 11 and including a first electrode pattern 121, and a first flat layer 13 provided on the side of the first electrode layer 12 away from the base substrate 11, wherein the first flat layer 13 is provided with through holes, and the through holes penetrate the first flat layer 13 so as to expose the first electrode pattern 121.

[0037] On the side of the first flat layer 13 away from the base substrate 11, a second electrode layer 14, a second flat layer 15, and a third electrode layer 16 are laminated. Here, the second electrode layer 14 is positioned close to the base substrate 11, the orthographic projection of the second electrode layer 14 on the base substrate 11 covers the orthographic projection of the through-hole on the base substrate 11, the second electrode layer 14 connects the first electrode pattern 121 and the third electrode layer 16, and the second flat layer 15 fills the through-hole to flatten it.

[0038] On the other hand, the second flat layer 15 provided within the through-holes fills the through-holes in the first flat layer 13, eliminating the deep hole structure in the first flat layer 13 and preventing light leakage caused by the deep hole structure. This eliminates the need to provide a large light-shielding layer to block light leakage, thus improving the aperture ratio of pixels in the display area.

[0039] On the other hand, since the third electrode layer 16 is provided on a flat surface, when the third electrode layer 16 is used as a pixel electrode layer, the distance between the pixel electrode layer and the common electrode layer can be kept constant, the electric field can be made uniform, the liquid crystal can be deflected normally, light leakage due to abnormal liquid crystal deflection can be avoided, and there is no need to provide a larger light-shielding layer to block light leakage, thus improving the aperture ratio of pixels in the display area.

[0040] Furthermore, by providing the second electrode layer 14 and the third electrode layer 16, the problem of high contact resistance that occurs when only the second electrode layer 14 is provided can be solved. Additionally, by further contacting the side of the second flat layer 15 away from the base substrate 11 with the third electrode layer 16, the problem of high contact resistance can be solved.

[0041] In one selectable mounting configuration, the materials of the first electrode layer 12, the second electrode layer 14 and the third electrode layer 16 may be, for example, transparent conductive materials or metallic materials, but this embodiment is not limited thereto. When the materials of the first electrode layer 12, the second electrode layer 14 and the third electrode layer 16 are all transparent conductive materials, the transmittance of the display area can be further improved. When the materials of the first electrode layer 12 and the second electrode layer 14 are the same, one masking process can be omitted by laminating them simultaneously and forming them using the same patterning process.

[0042] Here, the transparent conductive material may include, for example, at least one of transparent metal oxides such as indium tin oxide (ITO), indium zinc oxide (IZO), and graphene oxide.

[0043] In one selectable mounting configuration, the orthographic projection of the through-holes in the first flat layer 13 on the base substrate 11 is entirely contained within the orthographic projection of the second electrode layer 14 on the base substrate 11.

[0044] In one selectable mounting configuration, the orthographic projection of the second electrode layer 14 on the base substrate 11 is completely contained within the orthographic projection of the third electrode layer 16 on the base substrate 11.

[0045] In one selectable mounting configuration, the orthographic projection of the second flat layer 15 on the base substrate 11 is completely contained within the orthographic projection of the third electrode layer 16 on the base substrate 11.

[0046] In one selectable mounting configuration, the shape of the through-holes in the first flat layer 13 and the shape of the second electrode layer 14 in a plane parallel to the base substrate 11 is rectangular, circular, or elliptical, but this embodiment is not limited thereto.

[0047] In one selectable mounting configuration, referring to Figures 1 and 2, the display substrate includes a display area and a non-display area, the display area includes an opening area and a non-opening area, and the display substrate may further include a first thin-film transistor 17 provided between a base substrate 11 and a first electrode layer 12, the first thin-film transistor 17 being located in the display area, and the first thin-film transistor 17 including a stacked first active layer 171, a first gate insulating layer 172 and a first gate 173, the first active layer 171 including a drain contact area 21. The first electrode layer 12 may further include a second electrode pattern 122 formed integrally with the first electrode pattern 121, the second electrode pattern 122 being connected to the drain contact area 21, and the first electrode pattern 121 being located in the non-opening area.

[0048] In this implementation, the first thin-film transistor 17 may have a top-gate structure (as shown in Figures 1 and 2) or a bottom-gate structure, but this embodiment is not limited to either.

[0049] The first gate 173 may be a single-gate structure (as shown in Figure 1), a dual-gate structure (as shown in Figure 2), or a multi-gate structure, but this embodiment is not limited to these.

[0050] The material of the first active layer 171 may include amorphous silicon, polycrystalline silicon, or metal oxides, but this embodiment is not limited thereto.

[0051] The drain contact region 21 may be formed by making the material of the first active layer 171 conductive. Conductivity may be achieved by processes such as ion doping or plasma treatment.

[0052] To achieve connection between the second electrode pattern 122 and the drain contact region 21, in one selectable mounting configuration, referring to Figure 1, the first active layer 171 is provided so as to be close to the base substrate 11, the first interlayer dielectric layer 18, the first source 19 and the first passivation layer 110 are stacked on the side of the first gate 173 away from the base substrate 11, the first electrode layer 12 is provided on the side of the first passivation layer 110 away from the base substrate 11, and the second electrode pattern 122 is connected to the drain contact region 21 via via holes provided in the first passivation layer 110, the first interlayer dielectric layer 18 and the first gate insulating layer 172.

[0053] In this implementation, the material of the first electrode layer 12 may be a transparent conductive material, which can improve the transmittance of the display area. If the material of the first electrode layer 12 is a transparent conductive material, the material of the first active layer 171 may contain a metal oxide, which can reduce the contact resistance between the second electrode pattern 122 and the drain contact area 21.

[0054] In this implementation, the material of the first electrode layer 12 may be a metallic material, and the second electrode pattern 122 and the drain contact region 21 connected to the second electrode pattern 122 may be located in a non-aperture region, thereby further improving the aperture ratio of the pixel. If the material of the first electrode layer 12 is a metallic material, the contact resistance between the second electrode pattern 122 and the drain contact region 21 can be reduced.

[0055] In this implementation, referring to Figure 1, the second electrode pattern 122 in the first electrode layer 12 is multiplexed as the drain of the first thin-film transistor and connected to the drain contact region 21 via a via hole. By providing the source and drain of the first thin-film transistor in a stepped manner, the pitch between them can be reduced, contributing to an improvement in the resolution of the display substrate.

[0056] To further improve the transmittance of the aperture region, the orthographic projections of the first gate insulating layer 172, the first interlayer dielectric layer 18, and the first passivation layer 110 on the base substrate 11 do not need to overlap with the aperture region. By cutting out the first gate insulating layer 172, the first interlayer dielectric layer 18, and the first passivation layer 110 in the aperture region, the film thickness in the aperture region can be reduced, the number of film layer interfaces can be reduced, and thereby the light transmittance of the aperture region can be improved.

[0057] To achieve connection between the second electrode pattern 122 and the drain contact region 21, in other selectable mounting configurations, referring to Figure 2, the first active layer 171 is provided closer to the base substrate 11, and a first interlayer dielectric layer 18 and a first source-drain layer are laminated on the side of the first gate 173 away from the base substrate 11, the first source-drain layer includes a first source 19 and a first drain 111 provided in the same layer, the first drain 111 is connected to the drain contact region 21 via via holes provided in the first interlayer dielectric layer 18 and the first gate insulating layer 172, the first electrode layer 12 is provided on the side of the first drain 111 away from the base substrate 11, and the second electrode pattern 122 is connected in contact with the first drain 111.

[0058] In this implementation, the material of the first drain 111 is metal. A first drain 111 made of metal can reduce the contact resistance between the first drain 111 and the drain contact region 21. To avoid occupying the opening region, the drain contact region 21 and the first drain 111 connected to the drain contact region 21 may be located within a non-opening region.

[0059] In this implementation, the first electrode layer 12 functions as a relay layer, and the material of the first electrode layer 12 may be a transparent conductive material, which can improve the aperture ratio and transmittance.

[0060] When the first active layer 171 is positioned close to the base substrate 11, the first thin-film transistor 17 has a top-gate structure. Compared to a conventional bottom-gate structure, the first gate 173 does not need to shield the backlight, thus allowing for a smaller size. Furthermore, the parasitic capacitance formed between the first gate 173 and other film layers can be reduced, thereby lowering power consumption.

[0061] To further improve the transmittance of the aperture region, the orthographic projections of the first gate insulating layer 172 and the first interlayer dielectric layer 18 on the base substrate 11 do not need to overlap with the aperture region. By cutting out the first gate insulating layer 172 and the first interlayer dielectric layer 18 in the aperture region, the film thickness in the aperture region can be reduced, the number of film layer interfaces can be reduced, and thereby the light transmittance of the aperture region can be improved.

[0062] In one selectable mounting configuration, referring to Figure 3, the display substrate includes a display area and a non-display area, and the display area includes an opening area and a non-opening area. The display substrate further includes a first thin-film transistor 17 provided on the side of the base substrate 11 closer to the first electrode layer 12, the first thin-film transistor 17 located in the display area, and the first thin-film transistor 17 includes a stacked first active layer 171, a first gate insulating layer 172, a first gate 173, a first interlayer dielectric layer 18, and a first source 19, the first active layer 171 provided closer to the base substrate 11, the first active layer 171 includes a drain contact area 21, the drain contact area 21 is located in the opening area, and the drain contact area 21 is a first electrode pattern 121.

[0063] To improve the transmittance of the aperture region, the orthographic projections of the first gate insulating layer 172 and the first interlayer dielectric layer 18 on the base substrate 11 do not necessarily have to overlap with the aperture region.

[0064] Since the drain contact region is located within the opening region, it can contact the first electrode layer located within the opening region, eliminating the need to manufacture an intermediate electrode or drain, thus improving the aperture ratio and transmittance of the display region. Furthermore, since the material of the first active layer 171 is a transparent metal oxide, even if the drain contact region 21 of the first active layer 171 is provided in the opening region, it does not affect the aperture ratio and transmittance of the display region.

[0065] In one selectable implementation configuration, the display area further includes data lines 41 and scan lines 42. Referring to Figure 4, the first source 19 extends along a first direction to constitute the data lines 41, and the first gate 173 extends along a second direction intersecting the first direction to constitute the scan lines 42. The orthographic projections of the data lines 41 and scan lines 42 on the base substrate 11 each cover the orthographic projection of the channel region of the first active layer 171 on the base substrate 11. For example, as shown in Figure 4, the second direction may be perpendicular to the first direction.

[0066] When the material of the first active layer 171 includes polycrystalline silicon, the orthographic projection of the data lines 41 on the base substrate 11 covers the orthographic projection of the first active layer 171 on the base substrate 11. Since the first active layer 171 made of polycrystalline silicon is opaque, the aperture ratio of the pixels can be improved by placing the first active layer 171 within the non-aperture region corresponding to the data lines 41.

[0067] When the first thin-film transistor 17 has a top-gate structure, in order to avoid the backlight hitting the first active layer 171 and affecting the electrical characteristics of the first thin-film transistor 17, in one selectable mounting configuration, referring to Figures 1 to 3, a shielding layer 112 and a second interlayer dielectric layer 113 are further laminated between the first active layer 171 and the base substrate 11, the shielding layer 112 is positioned close to the base substrate 11, and the orthographic projection of the shielding layer 112 on the base substrate 11 covers the orthographic projection of the channel region of the first active layer 171 on the base substrate 11.

[0068] To further improve the transmittance of the aperture region, the orthographic projection of the second interlayer dielectric layer 113 on the base substrate 11 does not need to overlap with the aperture region.

[0069] In one selectable mounting configuration, the orthographic projection of the shielding layer 112 on the base substrate 11 can cover the orthographic projections of the data lines 41 and scan lines 42 on the base substrate 11. That is, the shielding layer 126 has a mesh structure. A shielding layer having a mesh structure can increase the area of ​​the shielding layer without affecting the aperture ratio, thereby reflecting more backlight and improving the backlight transmittance.

[0070] In one selectable mounting configuration, the shielding layer 112 is connected to the fixed potential input terminal. This mounting configuration can prevent display abnormalities caused by drift in the threshold voltage of the first thin-film transistor 17 and improve the uniformity of the display.

[0071] In one selectable implementation configuration, as shown in Figure 3, the shielding layer 112 is connected to the first source 19 via via holes provided in the second interlayer dielectric layer 113, the first gate insulating layer 172, and the first interlayer dielectric layer 18.

[0072] To further improve the utilization rate of the backlight, the material of the shielding layer 126 can be a highly reflective metallic material, which may include at least one of molybdenum, aluminum, silver, and tin. By using a shielding layer made of a highly reflective material, the backlight that hits the shielding layer can be reflected, and the reflected backlight can be reused, thereby improving the transmittance of the backlight.

[0073] The shielding layer material may be, for example, Al / top TIN, Al / top Mo, Al alloy / top TIN, or Al alloy / top Mo, and these materials have excellent high-temperature stability and stable reflectivity before and after high-temperature annealing.

[0074] In one selectable implementation configuration, the material of the first active layer 171 comprises a metal oxide, the display substrate further comprises a second thin-film transistor 114, the second thin-film transistor 114 is located in a non-display region, and the material of the active layer of the second thin-film transistor 114 comprises polycrystalline silicon.

[0075] The second thin-film transistor 114 may be formed by a low-temperature polycrystalline silicon (LTPS) process, improving the circuit driving capability of the non-display area. The first thin-film transistor 17 may be formed by an indium gallium zinc oxide (IGZO) process, which can reduce leakage current, improve voltage retention, and enhance the display effect of the display area.

[0076] In one selectable implementation configuration, referring to Figures 5 and 6, the channel region 22 of the first active layer 171 may include a first channel region 61, a first resistive region 62, and a second channel region 63 arranged sequentially along a first direction, the first gate 173 includes a separately provided first subgate 64 and a second subgate 65, the orthographic projection of the first subgate 64 on the base substrate 11 covers the orthographic projection of the first channel region 61 on the base substrate 11, and the orthographic projection of the second subgate 65 on the base substrate 11 covers the orthographic projection of the second channel region 63 on the base substrate 11.

[0077] Note that, in order to clearly identify the first active layer 171, the first subgate 64 and the second subgate 65 in Figure 5 are not fully shown.

[0078] Referring to Figures 5 and 6, the first channel region 61, the first resistive region 62, and the second channel region 63 are arranged sequentially along the first direction to form an I-type channel. The first channel region 61 and the second channel region 63 may be equivalent to two thin-film transistor switches connected in series, and the first resistive region 62 may be equivalent to a resistor connected in series between the two thin-film transistor switches. Here, the first resistive region 62 may be formed by performing processes such as ion doping or plasma treatment on the material of the first active layer 171.

[0079] In this embodiment, by providing a first resistance region 62 between the first channel region 61 and the second channel region 63, it is equivalent to connecting a resistor in series between the two thin-film transistor switches. The provision of the resistor can suppress the generation of leakage current, thereby reducing the leakage current of the thin-film transistor and improving the stability of the threshold voltage.

[0080] The first subgate 64 is for receiving a signal that controls the on / off state of the first channel region 61. The second subgate 65 is for receiving a signal that controls the on / off state of the second channel region 63. In one selectable implementation, the signals received by the first subgate 64 and the second subgate 65 may be the same, but this embodiment is not limited thereto.

[0081] In this implementation, the first thin-film transistor has a double-gate structure, resulting in high electrical stability and good voltage retention, thus improving the display effect and reliability of the display substrate. Furthermore, since the channel of the first thin-film transistor is an I-type channel, it occupies a small area within the pixel unit of the display substrate, improving the aperture ratio of the display substrate, and significantly improving the aperture ratio of display substrates with high pixel density. This display substrate may be applied to virtual reality (VR) display technology, augmented reality (AR) display technology, and the like.

[0082] Referring to Figures 5 and 6, the source contact region 20 in the first active layer 171 may include a first conductor region 66 and a second resistance region 67, the second resistance region 67 being positioned close to the first channel region 61. The drain contact region 21 may include a second conductor region 69 and a third resistance region 68, the third resistance region 68 being positioned close to the second channel region 63. By providing the second resistance region 67 and the third resistance region 68, leakage current can be further reduced.

[0083] Referring to Figure 2, a second passivation layer 115 and a fourth electrode layer 116 are laminated on the side of the first electrode layer 12 away from the base substrate 11. The fourth electrode layer 116 is transparent and connected to the first fixed potential input terminal. The second passivation layer 115 is positioned close to the base substrate 11. The orthographic projection of the first electrode layer 12 on the base substrate 11 overlaps with the orthographic projection of the fourth electrode layer 116 on the base substrate 11. The first flat layer 13 is positioned on the side of the fourth electrode layer 116 away from the base substrate 11. The through-hole penetrates the second passivation layer 115 and does not overlap with the orthographic projection of the fourth electrode layer 116 on the base substrate 11.

[0084] Here, as shown in Figure 2, the first electrode layer 12 and the fourth electrode layer 116 can extend into the aperture region. Both the first electrode layer 12 and the fourth electrode layer 116 may be made of transparent conductive material, and in this way the transmittance of the aperture region can be improved.

[0085] Since the orthographic projection of the first electrode layer 12 on the base substrate 11 overlaps with the orthographic projection of the fourth electrode layer 116 on the base substrate 11, a storage capacitance is formed, increasing the storage capacitance of the pixels, ensuring sufficient storage capacitance even in small pixel spaces, improving voltage retention, and ensuring normal display. Here, the voltage at the fourth electrode layer 116 may be, for example, a common voltage.

[0086] Referring to Figure 2, an insulating layer 121 is further provided on the side of the fourth electrode layer 116 away from the base substrate 11, and the data lines 41 are provided on the side of the insulating layer 121 away from the base substrate 11. The first flat layer 13 is provided on the side of the data lines 41 away from the base substrate 11, and the through holes penetrate the insulating layer 121, and the through holes do not overlap with the orthographic projection of the data lines 41 on the base substrate 11.

[0087] By providing the fourth electrode layer 116 between the data line 41 and the first electrode layer 12, the formation of coupling capacitance due to the distance between the data line 41 and the first electrode layer 12 being too close can be avoided. Since the fourth electrode layer 116 is connected to a fixed potential, even when the signal on the data line 41 changes at a high frequency, the influence of the signal on the data line 41 on the first electrode layer 12 is shielded, and furthermore, the influence of the data line 41 on the pixel voltage at the pixel electrode layer is shielded, thereby enabling normal display of the pixels.

[0088] Referring to Figure 1, the display substrate includes an aperture region, and a color resist layer 117 is further provided on the side of the first electrode layer 12 away from the base substrate 11, and the orthographic projection of the color resist layer 117 on the base substrate 11 covers the aperture region. The first flat layer 13 is provided on the side of the color resist layer 117 away from the base substrate 11, and the orthographic projection of the through hole on the base substrate 11 does not overlap with the orthographic projection of the color resist layer 117 on the base substrate 11.

[0089] In concrete implementation, first, the first electrode layer 12 and the color resist layer 117 can be sequentially patterned and formed on the side of the first passivation layer 110 away from the base substrate 11, and then the first flat layer 13 can be formed on the side of the color resist layer 117 and the first electrode layer 12 away from the base substrate 11.

[0090] The color resist layer 117 may include a red color resist layer, a green color resist layer, and a blue color resist layer, and each color resist layer is provided on a different subpixel unit to achieve color display.

[0091] In this implementation, by providing a color resist layer on the display substrate, the display substrate can be brought closer to the backlight source in the display device, reducing light crosstalk between adjacent subpixel units and affecting the display effect.

[0092] In one selectable mounting configuration, referring to Figures 1 to 3, a third passivation layer 118 and a common electrode layer 119 are laminated on the side of the third electrode layer 16 away from the base substrate 11, with the third passivation layer 118 positioned closer to the base substrate 11. The material of the common electrode layer 118 may be a transparent conductive material or a metallic material, but this embodiment is not limited thereto.

[0093] Here, the common electrode layer 118 may include a plurality of strip-shaped electrodes, which can form a horizontal electric field with the pixel electrode layer 19. The width and pitch of the strip-shaped electrodes may be designed according to actual requirements, but this embodiment is not limited thereto. To reduce light ray crosstalk between adjacent pixels, the material of the common electrode layer 118 may be metal.

[0094] In one selectable mounting configuration, referring to Figure 1, an isolation column 120 is further provided on the side of the first flat layer 13 away from the base substrate 11, and the isolation column 120 is formed synchronously with the second flat layer 15. The isolation column 120 and the second flat layer 15 are made of the same material and are formed by the same process, which simplifies the process steps and reduces costs.

[0095] Another embodiment of the present invention further provides a display device which may include a display substrate as described in any embodiment.

[0096] In this embodiment, the display device may be any product or component having 2D or 3D display capabilities, such as a display panel, electronic paper, mobile phone, tablet, television, laptop computer, digital camera, or navigator.

[0097] Another embodiment of the present invention further provides a method for manufacturing a display substrate, which includes the following steps.

[0098] Step 11: Prepare the base board.

[0099] Step 12: A first electrode layer including the first electrode pattern is formed on one side of the base substrate.

[0100] Step 13: A first flat layer is sequentially formed on the side of the first electrode layer away from the base substrate, and through holes are provided in the first flat layer, with the through holes penetrating the first flat layer so as to expose the first electrode pattern.

[0101] Step 14: A second electrode layer, a second flat layer, and a third electrode layer are sequentially formed on the side of the first flat layer away from the base substrate, where the orthographic projection of the second electrode layer on the base substrate covers the orthographic projection of the through hole on the base substrate, the second electrode layer is for connecting the first electrode pattern and the third electrode layer, and the second flat layer is for flattening the through hole.

[0102] The manufacturing method provided in this embodiment can be used to manufacture the display board described in any of the above embodiments.

[0103] In one selectable mounting configuration, the method for manufacturing the display board provided in this embodiment may include the following steps.

[0104] Step 21: First, after completing the manufacturing of the first thin-film transistor 17 and the second thin-film transistor 114 on the base substrate 11, the first electrode layer 12, the first flat layer 13, and the second electrode layer 14 are sequentially formed on the side of the first passivation layer 110 away from the base substrate 11. Here, through holes are provided in the first flat layer 13, and the second electrode layer 14 covers these through holes to form a display substrate as shown in Figure 8.

[0105] Step 22: A second flat material layer is manufactured and filled into the through-holes in the first flat layer 13 to form a display substrate as shown in Figure 9.

[0106] Step 23: By patterning the second flat material layer and controlling the exposure energy of different regions, the isolation columns 120 and the second flat layer 15 are formed, respectively, to form a display substrate as shown in Figure 10. Here, the second flat layer 15 is for filling through holes in the first flat layer 13, and the materials of the second flat layer 15 and the first flat layer 13 may be the same or different.

[0107] Step 24: ITO is stacked and patterned to form a third electrode layer, creating a display substrate as shown in Figure 11.

[0108] Step 25: A third passivation layer 118 is stacked and formed to create a display substrate as shown in Figure 12.

[0109] Step 26: Pattern the common electrode layer 119 to form a display substrate as shown in Figure 1.

[0110] In one selectable mounting configuration, the method for manufacturing the display board provided in this embodiment may include the following steps.

[0111] Step 31: A shielding layer is fabricated to shield the channel region of the first thin-film transistor, preventing the backlight from affecting the characteristics of the thin-film transistor. Referring to Figure 13, a schematic diagram of the planar structure of the display substrate after the fabrication of the shielding layer is complete is shown.

[0112] Step 32: The buffer layer and the first active layer of metal oxide material are manufactured. The drain contact area is located in the aperture area, and since the metal oxide is transparent, it does not affect the aperture ratio of the pixels. Referring to Figure 14, a schematic diagram of the planar structure of the display substrate after the manufacturing of the first active layer is completed is shown.

[0113] Step 33: The first gate insulating layer and the first gate are manufactured, ensuring that the first gate is located within the shielding layer region and that the channel region in the first active layer is shielded by the shielding layer. Referring to Figure 15, a schematic diagram of the planar structure of the display substrate after the manufacturing of the first gate is complete is shown.

[0114] Step 34: The first interlayer dielectric layer is fabricated and holes are made in the position corresponding to the source contact region of the first active layer, so that the subsequent film layer comes into contact with the first active layer, as shown at 161 in Figure 16. Referring to Figure 16, a schematic diagram of the planar structure of the display substrate after the fabrication of the first interlayer dielectric layer is complete is shown.

[0115] Step 35: Fabricate data lines that connect to the source contact region via via holes provided in the first interlayer dielectric layer. Referring to Figure 17, a schematic diagram of the planar structure of the display substrate after the fabrication of the data lines is complete.

[0116] Step 36: The first passivation layer and the first electrode layer are fabricated, and holes are made in the first passivation layer at positions corresponding to the drain contact area of ​​the first active layer, so that the first electrode layer is connected to the drain contact area via via holes provided in the first passivation layer, as shown in 181 in Figure 18. Referring to Figure 18, a schematic diagram of the planar structure of the display substrate after the fabrication of the first electrode layer is complete is shown.

[0117] Step 37: By manufacturing the color resist layer and placing the color resist layer on the display substrate, crosstalk between different colored lights can be effectively reduced. Referring to Figure 19, a schematic diagram of the planar structure of the display substrate after the manufacturing of the color resist layer is complete is shown.

[0118] Step 38: The first flat layer is manufactured and through holes are formed, as shown in 201 in Figure 20. Referring to Figure 20, a schematic diagram of the planar structure of the display substrate after the manufacturing of the first flat layer is completed is shown.

[0119] Step 39: The second electrode layer, the second flat layer, and the third electrode layer are formed sequentially. The second flat layer is formed to fill the through-holes in the first flat layer. This structure ensures electrical connection between the third electrode layer and the first electrode layer, as well as overall flatness of the third electrode layer, and ensures the formation of a uniform electric field between it and the common electrode layer. Referring to Figure 21, a schematic diagram of the planar structure of the display substrate after the manufacturing of the third electrode layer is completed is shown.

[0120] Step 310: A third passivation layer and a common electrode layer are manufactured. The common electrode layer, together with the third electrode layer, forms an electric field to drive and deflect the liquid crystal. Referring to Figure 22, a schematic diagram of the planar structure of the display substrate after the manufacturing of the common electrode layer is complete is shown. In this way, the display substrate shown in Figure 1 can be manufactured.

[0121] Each example in this specification is described incrementally, and each example focuses on the differences from the other examples, but identical or similar parts between each example should be referenced to one another.

[0122] Finally, it should be noted that, in this specification, relational terms such as “first” and “second” are used solely to distinguish one entity or operation from another, and do not necessarily require or imply that such an actual relationship or order exists between these entities or operations. Also, the terms “include,” “incorporate,” or any other variation thereof are intended to mean non-exclusive inclusion. Thus, a process, method, product, or equipment that includes a set of elements includes not only those elements, but also other elements not explicitly listed, or elements specific to such a process, method, product, or equipment. Unless otherwise specified, an element limited by the phrase “includes one of…” does not preclude the existence of other identical elements in a process, method, product, or equipment that includes that element.

[0123] The display substrate, its manufacturing method, and display device provided by the present invention have been described in detail above. In this specification, the principles and embodiments of the present invention have been described using specific examples, but the above description of examples is merely to aid in understanding the method and gist of the present invention. Furthermore, those skilled in the art will know that there are changes to the specific embodiments and scope of application based on the concept of the present invention, and therefore, the contents of this specification should not be understood as limitations on the present invention.

[0124] Those skilled in the art will readily acquire other embodiments of the present invention through understanding the specification and practicing the inventions described herein. The present invention includes any modifications, uses, or adaptive variations of the present invention, such modifications, uses, or adaptive variations, in accordance with the general principles of the present invention, and include prior art knowledge or common technical means not disclosed herein. The specification and examples are merely illustrative, and the true scope and spirit of the present invention are indicated by the following claims.

[0125] The present invention is not limited to the specific configurations described above and illustrated in the drawings, and various modifications and changes may be made without departing from its scope. The scope of the present invention is limited only to the appended claims.

[0126] In this specification, “one embodiment,” “an embodiment,” or “one or more embodiments” means that the specific features, structures, or properties described in conjunction with the embodiments are included in at least one embodiment of the present invention. It should also be noted that examples of the term “in one embodiment” do not necessarily refer to the same embodiment.

[0127] Many specific details are described in the description provided herein. However, it can be understood that embodiments of the present invention may be realized without these specific details. In some examples, known methods, structures, and techniques are not illustrated in detail so as not to obscure the understanding of this specification.

[0128] In the claims, no reference numerals placed in parentheses shall be configured to limit the scope of the claims. The word “including” shall not preclude the existence of elements or steps not described in the claims. The word “1” or “one” preceding an element shall not preclude the existence of multiple such elements. The present invention can be realized by hardware comprising several different elements and a appropriately programmed computer. In a claim of a unit listing several devices, some of these devices may be concretely embodied by the same hardware. The use of words such as “first,” “second,” “third,” etc., shall not indicate any order. These words may be interpreted as names.

[0129] Finally, the above embodiments are for illustrative purposes only and are not limiting. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that the inventions described in each of the above embodiments may be modified, or some of the technical features therein may be replaced with equivalents. Such modifications or substitutions will not cause the essence of the corresponding inventions to depart from the spirit and scope of the inventions described in each embodiment.

Claims

1. Base board and A first electrode layer is provided on one side of the base substrate and includes a first electrode pattern, A first flat layer provided on the side of the first electrode layer away from the base substrate, A display substrate comprising a second electrode layer, a second flat layer, and a third electrode layer laminated on the side of the first electrode layer away from the base substrate, The first flat layer is provided with through holes, and the through holes penetrate the first flat layer so as to expose the first electrode pattern. The second electrode layer and the second flat layer are located within the through-hole of the first flat layer, and the third electrode layer is located on the side of the first flat layer away from the base substrate. The second electrode layer is provided so as to be close to the base substrate, the orthographic projection of the second electrode layer on the base substrate covers the orthographic projection of the through hole on the base substrate, the second electrode layer connects the first electrode pattern and the third electrode layer, and the second flat layer is filled into the through hole so as to flatten the through hole. The display substrate includes a display area and a non-display area, and the display area includes an aperture area and a non-aperture area. The display substrate further includes a first thin-film transistor provided on the side of the base substrate closer to the first electrode layer, the first thin-film transistor located in the display region, the first thin-film transistor comprising a stacked first active layer, a first gate insulating layer, a first gate, a first interlayer dielectric layer, and a first source, the first active layer being provided closer to the base substrate, the first active layer including a drain contact region, the drain contact region being located in the opening region, The orthographic projections of the first gate insulating layer and the first interlayer dielectric layer on the base substrate do not overlap with the aperture region, and the drain contact region is the first electrode pattern. Display board.

2. The orthographic projection of the through-hole in the base substrate is completely contained within the orthographic projection of the second electrode layer in the base substrate. The display board according to claim 1.

3. The orthographic projection of the second electrode layer on the base substrate is completely contained within the orthographic projection of the third electrode layer on the base substrate. The display board according to claim 1.

4. The orthographic projection of the second flat layer on the base substrate is completely contained within the orthographic projection of the third electrode layer on the base substrate. The display board according to claim 1.

5. The shape of the through-hole and the second electrode layer is rectangular, circular, or elliptical. The display board according to claim 1.

6. The material of the first electrode layer is a transparent conductive material. The display board according to claim 1.

7. The material of the first electrode layer is a metal. The display board according to claim 1.

8. The material of the first active layer includes a metal oxide. The display board according to claim 1.

9. The display area further includes data lines and scan lines, wherein the first source extends along a first direction to constitute the data lines, and the first gate extends along a second direction intersecting the first direction to constitute the scan lines, and the orthographic projections of the data lines and scan lines on the base substrate each cover the orthographic projection of the channel area of ​​the first active layer on the base substrate. The display board according to claim 1.

10. The material of the first active layer comprises polycrystalline silicon, and the orthographic projection of the data lines on the base substrate covers the orthographic projection of the first active layer on the base substrate. The display board according to claim 9.

11. A shielding layer and a second interlayer dielectric layer are further laminated between the first active layer and the base substrate, the shielding layer being positioned closer to the base substrate, and the orthographic projection of the shielding layer on the base substrate covering the orthographic projection of the channel region of the first active layer on the base substrate. The display board according to claim 1.

12. The display area further includes data lines and scan lines, and the orthographic projection of the shielding layer on the base substrate covers the orthographic projection of the data lines and scan lines on the base substrate. The display board according to claim 11.

13. The shielding layer is connected to the fixed potential input terminal. The display board according to claim 11.

14. The shielding layer is connected to the first source via via holes provided in the second interlayer dielectric layer, the first gate insulating layer, and the first interlayer dielectric layer. The display board according to claim 11.

15. The material of the shielding layer includes at least one of molybdenum, aluminum, and silver. The display board according to claim 11.

16. The display substrate further includes a second thin-film transistor, the second thin-film transistor located in the non-display region, and the material of the active layer of the second thin-film transistor includes polycrystalline silicon. The display board according to claim 1.

17. The channel region of the first active layer includes a first channel region, a first resistive region, and a second channel region arranged sequentially along a first direction, the first gate includes a separately provided first subgate and a second subgate, the orthographic projection of the first subgate on the base substrate covers the orthographic projection of the first channel region on the base substrate, and the orthographic projection of the second subgate on the base substrate covers the orthographic projection of the second channel region on the base substrate. The display board according to claim 1.

18. A third passivation layer and a common electrode layer are laminated on the side of the third electrode layer away from the base substrate, the third passivation layer is positioned closer to the base substrate, the common electrode layer includes a plurality of strip-shaped electrodes, and the material of the common electrode layer is metal. The display board according to claim 1.

19. An isolation column is further provided on the side of the first flat layer away from the base substrate, and the isolation column is formed in synchronization with the second flat layer. The display board according to claim 1.

20. A display device comprising a display board according to any one of claims 1 to 9.

21. A method for manufacturing a display board, The steps include preparing the base board and The steps include forming a first electrode layer including a first electrode pattern on one side of the base substrate, A first flat layer is sequentially formed on the side of the first electrode layer away from the base substrate, and through holes are provided in the first flat layer, and the through holes penetrate the first flat layer so as to expose the first electrode pattern, The process includes the step of sequentially forming a second electrode layer, a second flat layer, and a third electrode layer on the side of the first electrode layer away from the base substrate, The second electrode layer and the second flat layer are located within the through-hole of the first flat layer, and the third electrode layer is located on the side of the first flat layer away from the base substrate. The orthographic projection of the second electrode layer on the base substrate covers the orthographic projection of the through hole on the base substrate, the second electrode layer is for connecting the first electrode pattern and the third electrode layer, and the second flat layer is for flattening the through hole. The display substrate includes a display area and a non-display area, and the display area includes an aperture area and a non-aperture area. The method for manufacturing the display board is as follows: The step further includes forming a first thin-film transistor on the side of the base substrate that is closer to the first electrode layer, The first thin-film transistor is located in the display region, and the first thin-film transistor includes a stacked first active layer, a first gate insulating layer, a first gate, a first interlayer dielectric layer, and a first source, the first active layer is provided so as to be close to the base substrate, the first active layer includes a drain contact region, the drain contact region is located in the opening region, The orthographic projections of the first gate insulating layer and the first interlayer dielectric layer on the base substrate do not overlap with the aperture region, and the drain contact region is the first electrode pattern. A method for manufacturing a display board.

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