Implementation structure

Abstract

To achieve a mounting structure enabling stable fixture at the mounting without affecting the electric characteristics of the other circuits about a chip component.SOLUTION: A mounting structure includes a substrate with a first electrode connection part, a circuit structure element provided on the substrate, and a chip component provided between the substrate and the circuit structure element. The circuit structure element includes a second electrode connection part provided on a surface on the chip component side. The chip component includes a first surface facing the substrate, a second surface provided on the opposite side of the first surface and facing the circuit structure element, a first external electrode provided protruding from the first surface and electrically connected to the first electrode connection part, a second external electrode provided protruding from the second surface and electrically connected to the circuit structure element, and an insulating adhesive provided to a part of the first surface where the first external electrode is not provided and fixing the first surface and the substrate.SELECTED DRAWING: Figure 4

Description

Technical Field

[0001] The present disclosure relates to an implementation structure.

Background Art

[0002] An inductor provided inside a multilayer substrate is known (for example, Patent Document 1). In Patent Document 1, a switching IC (Integrated Circuit) provided on the surface of the substrate and an inductor provided inside the substrate are electrically connected to realize a DCDC converter module. Inside the substrate, an inductor in which wiring is formed in a loop shape is provided.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] The DCDC converter module described in Patent Document 1 includes an inductor formed by a wiring pattern provided in a substrate. Therefore, it is difficult to make the entire implementation structure small. If small components are used, there is a possibility that the entire implementation structure can be made small. However, for small components, it is also conceivable that it is difficult to stably fix them when mounting on a substrate. In addition, it is necessary to consider so that the mounted components do not have an adverse effect (such as malfunction) on other circuits.

[0005] The present disclosure has been made in view of the above, and an object thereof is to provide an implementation structure that can be stably fixed during implementation without affecting the electrical characteristics of other circuits with respect to chip components.

Means for Solving the Problems

[0006] To solve the above-mentioned problems and achieve the objective, a mounting structure according to one aspect of the present disclosure is a mounting structure for mounting a chip component on the mounting surface of a first substrate, wherein the chip component comprises a first surface facing the mounting surface, a second surface provided on the opposite side of the first surface, a first external electrode protruding from the first surface and electrically connected to a first electrode connection portion, a second external electrode protruding from the second surface and electrically connected to other circuit components, and an insulating adhesive provided on the portion of the first surface where the first external electrode is not provided, and which fixes the first surface and the mounting surface together. Furthermore, a protective film is provided on the entire surface of the chip component, excluding the first external electrode, the second external electrode, and the adhesive. This is the implementation structure. [Effects of the Invention]

[0007] According to this disclosure, a mounting structure can be realized for chip components that can be stably fixed during mounting without affecting the electrical characteristics of other circuits. [Brief explanation of the drawing]

[0008] [Figure 1] Figure 1 shows an example of an implementation structure for a comparative example. [Figure 2] Figure 2 is a circuit diagram corresponding to the implementation structure in Figure 1. [Figure 3] Figure 3 shows an example of a chip inductor used in the mounting structure shown in Figure 1. [Figure 4] Figure 4 shows an example of a mounting structure including the chip inductor shown in Figure 3. [Figure 5] Figure 5 shows the implementation structure according to the first embodiment of this disclosure. [Figure 6] Figure 6 shows a cross-section of the chip inductor used in the mounting structure shown in Figure 5. [Figure 7] Figure 7 shows the chip inductor viewed from the direction of the arrow in Figure 6. [Figure 8] Figure 8 shows a chip inductor used in the mounting structure according to the second embodiment of this disclosure. [Figure 9]FIG. 9 is a diagram showing a chip inductor used in the mounting structure according to the third embodiment of the present disclosure. [Figure 10] FIG. 10 is a diagram of the chip inductor viewed from the direction of the arrow in FIG. 9. [Figure 11] FIG. 11 is a diagram showing a chip inductor used in the mounting structure according to the fourth embodiment of the present disclosure. [Figure 12] FIG. 12 is a diagram showing a chip inductor used in the mounting structure according to the fifth embodiment of the present disclosure. [Figure 13] FIG. 13 is a diagram for explaining the first mounting procedure. [Figure 14] FIG. 14 is a diagram for explaining the first mounting procedure. [Figure 15] FIG. 15 is a diagram for explaining the first mounting procedure. [Figure 16] FIG. 16 is a diagram for explaining the first mounting procedure. [Figure 17] FIG. 17 is a diagram for explaining the second mounting procedure. [Figure 18] FIG. 18 is a diagram for explaining the second mounting procedure. [Figure 19] FIG. 19 is a diagram for explaining the second mounting procedure. [Figure 20] FIG. 20 is a diagram for explaining the third mounting procedure. [Figure 21] FIG. 21 is a diagram for explaining the third mounting procedure. [Figure 22] FIG. 22 is a diagram for explaining the third mounting procedure. [Figure 23] FIG. 23 is a diagram for explaining the third mounting procedure. [Figure 24] FIG. 24 is a diagram showing an example of another mounting structure. [Figure 25] FIG. 25 is a partially enlarged view of the mounting structure of FIG. 24. [Figure 26] FIG. 26 is a diagram showing an example of a mounting structure with a shorter conduction path for switching noise. [Figure 27] FIG. 27 is a partially enlarged view of the mounting structure of FIG. 26. [Figure 28]Figure 28 is a diagram illustrating the steps to realize the implementation structure shown in Figure 27. [Figure 29] Figure 29 shows an example of an implementation structure that uses wiring cables to shorten the conduction path of switching noise. [Figure 30] Figure 30 is a magnified view of a portion of the implementation structure shown in Figure 29. [Figure 31] Figure 31 is a diagram illustrating the procedure for realizing the implementation structure shown in Figures 29 and 30. [Figure 32] Figure 32 shows an example of a case where multiple chip inductors are provided. [Figure 33] Figure 33 is a diagram illustrating the procedure for realizing the implementation structure shown in Figure 32. [Figure 34] Figure 34 shows an example of a case where multiple chip inductors are provided on the main surface of a switching IC. [Figure 35] Figure 35 shows an example of a case where multiple chip inductors are provided on the main surface of a switching IC. [Figure 36] Figure 36 shows an example of a case where multiple chip inductors are provided on the main surface of a switching IC. [Figure 37] Figure 37 shows another example of a case where multiple chip inductors are provided on the main surface of a switching IC. [Figure 38] Figure 38 shows another example of a case where multiple chip inductors are provided on the main surface of a switching IC. [Figure 39] Figure 39 shows another example of a case where multiple chip inductors are provided on the main surface of a switching IC. [Modes for carrying out the invention]

[0009] Embodiments of the present invention will be described in detail below with reference to the drawings. In the following descriptions of each embodiment, the same or equivalent components as those in other embodiments will be denoted by the same reference numerals, and their descriptions will be simplified or omitted. The present invention is not limited by each embodiment. Furthermore, the components of each embodiment include those that are easily substituted or substantially identical to those that a person skilled in the art can substitute. The configurations described below can be combined as appropriate. Furthermore, configurations can be omitted, substituted, or modified without departing from the spirit of the invention.

[0010] To facilitate understanding of each embodiment, the implementation structure using comparative examples will be described first.

[0011] (Comparative example) Figure 1 shows an example of a mounting structure according to a comparative example. Figure 2 is a circuit diagram corresponding to the mounting structure in Figure 1. Figure 1 schematically shows a cross-section of the substrate 40. The mounting structure shown in Figure 1 includes a chip inductor 1, a substrate 40, a switching IC 50, and a load 60. The chip inductor 1, the switching IC 50, and the load 60 are provided on one main surface 40M side of the substrate 40. Note that no inductors with wiring formed in a loop are provided within the substrate 40.

[0012] The substrate 40 is composed of multiple layers. The substrate 40 includes a wiring pattern 41 and a ground layer 42. The wiring pattern 41 is provided on one main surface 40M side of the substrate 40. A portion of the wiring pattern 41 may pass through the inner layers of the substrate 40.

[0013] The switching IC 50 functions as a DC-DC converter that converts the input direct current (DC) voltage. The switching IC 50 is electrically connected to the circuit board 40 by solder balls B1, B2, B3, etc.

[0014] The chip inductor 1 and the switching IC 50 are electrically connected by solder balls (not shown). The chip inductor 1 and the electrode connection portion 43 of the substrate 40 are electrically connected by solder balls (not shown). The chip inductor 1 functions as a choke coil.

[0015] In the above configuration, the current flowing through the switching IC 50 as shown by arrow Y1 flows into the substrate 40 through the chip inductor 1 as shown by arrow Y2. The current that has flowed into the substrate 40 flows along the wiring pattern 41 as shown by arrows Y3 and Y4 and is input to the load 60.

[0016] The current output from load 60 flows toward the ground layer as indicated by arrow Y5, and is input to the ground terminal of switching IC 50 through the ground layer as indicated by arrows Y6, Y7, and Y8.

[0017] Next, referring to Figure 2, the circuit corresponding to the mounting structure shown in Figure 1 includes input terminals T1 and T2, a switching integrated circuit (hereinafter referred to as a switching IC) 50, an inductor L1 corresponding to the chip inductor 1 in Figure 1, and capacitors C1 and C2.

[0018] Inductor L1 in Figure 2 corresponds to chip inductor 1 in Figure 1. Inductor L1 functions as a choke coil. Capacitors C1 and C2 in Figure 2 are smoothing capacitors. Capacitors C1 and C2 are not shown in Figure 1.

[0019] The input voltage applied between input terminals T1 and T2 is supplied between input terminal 501 and ground terminal 503 of the switching IC 50. The switching IC 50 outputs a voltage corresponding to the input voltage.

[0020] Arrows Y11 to Y14 in Figure 2 indicate the flow of current. The DC current output from the output terminal 502 of the switching IC 50 is input to the load 60 through the inductor L1, as shown by arrow Y11. The current output from the load 60 flows toward the ground layer, as shown by arrow Y12, and is input to the ground terminal 503 of the switching IC 50 through the ground layer, as shown by arrows Y13 and Y14.

[0021] Figure 3 shows an example of a chip inductor used in the mounting structure of Figure 1. Figure 4 shows an example of a mounting structure including the chip inductor of Figure 3. Figure 4 shows a magnified view of the portion of Figure 1 indicated by the dashed line H1.

[0022] Figure 3 is a schematic diagram showing a cross-section of a chip inductor 1p. In Figure 3, the chip inductor 1p includes a roughly rectangular body 10, a coil 21, and lead-out sections 31 and 32. The coil 21 and lead-out sections 31 and 32 are located inside the body 10.

[0023] Furthermore, the chip inductor 1p includes external electrodes 11 and 12 and a dummy electrode D. The external electrodes 11 and dummy electrode D are provided on the first surface M1 side of the main body 10. The external electrode 12 is provided on the second surface M2 side of the main body 10. The first surface M1 and the second surface M2 are surfaces of the main body 10 that are located on opposite sides of each other.

[0024] The coil 21 consists of internal patterns 21a, 21b, 21c, and 21d that are connected in a helical manner. Referring to the cross-sectional view in Figure 3, each internal pattern 21a, 21b, 21c, and 21d appears to be a separate pattern. In reality, the internal patterns 21a, 21b, 21c, and 21d are electrically connected so that the whole structure forms a helical shape.

[0025] The lead-out portion 31 is electrically connected to the end of the internal pattern 21a, which is one end of the coil 21. One end of the lead-out portion 31 is connected to the internal pattern 21a, and the other end of the lead-out portion 31 is electrically connected to the external electrode 11. The external electrode 11 is electrically connected to an electrode connection portion 43 provided on the substrate 40, as will be described later.

[0026] The lead-out portion 32 is electrically connected to the end of the internal pattern 21d, which is the other end of the coil 21. One end of the lead-out portion 32 is connected to the internal pattern 21d, and the other end of the lead-out portion 32 is electrically connected to the external electrode 12. The external electrode 12 is electrically connected to the external electrode 52 of the switching IC 50, as will be described later.

[0027] Figure 4 is a schematic diagram showing a cross-section of the chip inductor 1p and a portion of the cross-section of the switching IC 50 shown in Figure 3. As shown in Figure 4, the chip inductor 1p is provided between the substrate 40 and the switching IC 50. The first surface M1 of the chip inductor 1p is the surface facing the substrate 40. The second surface M2 of the chip inductor 1p is the surface facing the switching IC 50, which is a circuit component.

[0028] The external electrode 11 is electrically connected to an electrode connection portion 43 provided on the substrate 40. The external electrode 11 and the electrode connection portion 43 are electrically connected by the melting of a solder ball (not shown). In other words, the first external electrode, the external electrode 11, is electrically connected to the electrode connection portion 43 (shown as a dashed line in Figure 3) provided on the substrate 40.

[0029] External electrode 12 is electrically connected to external electrode 52 of switching IC 50. External electrode 12 and external electrode 52 are electrically connected by the melting of solder ball B10. In other words, external electrode 12, which is the second external electrode, is electrically connected to external electrode 52 of switching IC 50 (shown by a dashed line in Figure 3).

[0030] Furthermore, the switching IC 50 and the substrate 40 are electrically connected by the melting of numerous solder balls, including solder balls B1 and B2. Solder ball B2 is electrically connected to the external electrode 51 of the switching IC 50. In Figure 4, the other solder balls are not shown.

[0031] Referring to Figure 4, a dummy electrode D is provided on the first surface M1 facing the main surface 40M, which is the mounting surface of the substrate 40. If the dummy electrode D were not provided, only the lower surface of the external electrode 11 would be the connection point between the chip inductor 1p and the substrate 40. In that case, the chip inductor 1p would be supported by the external electrode 11, resulting in a cantilever structure. A cantilever structure is undesirable because the connection between the chip inductor 1p and the substrate 40 is unstable.

[0032] In contrast, as shown in Figure 4, the presence of a dummy electrode D eliminates the cantilever structure, resulting in a stable mounting structure. The lower surfaces of the dummy electrode D and the external electrode 11 form the connection point between the chip inductor 1p and the substrate 40. This allows the chip inductor 1p to be supported by the dummy electrode D and the external electrode 11. Thus, the instability caused by the cantilever structure is eliminated by providing the dummy electrode D in addition to the external electrode 11.

[0033] However, because a dummy electrode D is provided, a stray capacitance is generated between the dummy electrode D and the coil 21. This stray capacitance is undesirable because it affects the characteristics of the entire circuit.

[0034] (First Embodiment) Figure 5 shows a mounting structure according to the first embodiment of this disclosure. Figure 5 schematically shows a cross-section of a chip inductor 1a and a part of the cross-section of a switching IC 50. The chip inductor 1a is provided between the substrate 40 and the switching IC 50. The substrate 40 corresponds to the first base body, and the chip inductor 1a, which is a chip component, is mounted on one main surface 40M, which is the mounting surface. The external electrode 11, which corresponds to the first external electrode of the chip inductor 1a, is electrically connected to the electrode connection part 43, which corresponds to the first electrode connection part. The external electrode 12, which corresponds to the second external electrode of the chip inductor 1a, is electrically connected to the switching IC 50, which is another circuit component. In the mounting structure shown in Figure 5, unlike the mounting structure shown in Figure 4, the chip inductor 1a has adhesive 13 on its lower surface. The adhesive 13 is provided on the first surface M1 of the chip inductor 1a in the part where the external electrode 11 is not provided. The first surface M1 and the substrate 40 are fixed together by this adhesive 13. The substrate 40 has a ground layer 42 (not shown) as described with reference to Figure 1.

[0035] The adhesive 13 is an insulating adhesive. Therefore, no stray capacitance is generated between the adhesive 13 and the coil 21. The adhesive 13 may be a resin adhesive that melts during the reflow process and solidifies at room temperature. For example, a thermoplastic engineering plastic can be used as the adhesive 13.

[0036] In the above mounting structure, the adhesive 13 and the lower surface of the external electrode 11 form the connection point between the chip inductor 1a and the substrate 40. This allows the chip inductor 1a to be supported by the adhesive 13 and the external electrode 11. Since this is not a cantilever structure, a stable mounting structure can be achieved. The substrate 40 may be a flexible substrate or a substrate with a lead frame.

[0037] (Chip inductor) Figure 6 shows a cross-section of the chip inductor 1a used in the mounting structure of Figure 5. Unlike the chip inductor 1p in Figure 3, the chip inductor 1a has adhesive 13 on its lower surface. Also, the chip inductor 1a does not have a dummy electrode D.

[0038] As shown in Figure 6, the chip inductor 1a has a roughly rectangular body 10. An external electrode 11 is provided near a corner 101 of the roughly rectangular body 10. Corner 101 is the end of the first face M1. An external electrode 12 is provided near another corner 102 of the roughly rectangular body 10. Corner 102 is the end of the second face M2. The first face M1 and the second face M2 are faces on the body 10 that are opposite each other. Therefore, it can be said that the external electrodes 11 and 12 are provided at diagonal positions on the roughly rectangular body 10. The material of the external electrodes 11 and 12 may be a single metal such as Cu, Au, Ni, or Sn, or a composite material of a metal and resin such as Ag. The external electrodes 11 and 12 may be formed by any method, such as plating, frame terminals, or a composite paste of metal and resin.

[0039] Figure 7 is a view of the chip inductor 1a from the direction of arrow Ya in Figure 6, i.e., from above the second surface M2. As shown in Figure 7, a coil 21 is provided inside the chip inductor 1a. In Figure 7, the cross-sectional view of section AA corresponds to Figure 6.

[0040] As shown in Figure 7, when viewing the chip inductor 1a from the second surface M2, the first electrode, the external electrode 11, provided on the first surface M1, and the second electrode, the external electrode 12, provided on the second surface M2, are positioned so as not to overlap with each other.

[0041] Returning to Figure 6, the external electrode 11 protrudes from the first surface M1, which is the lower surface of the chip inductor 1a. The external electrode 12 protrudes from the second surface M2, which is the upper surface of the chip inductor 1a. Here, the amount of protrusion of the external electrode 11, i.e., the thickness of the external electrode 11 (i.e., the height relative to the first surface M1), is denoted as t11. Also, the thickness of the adhesive 13 before mounting to the substrate 4 is denoted as t13. Furthermore, the solder thickness between the electrode connection portion 43 and the external electrode 11 during mounting to the substrate 4 is denoted as ts (not shown). In this case, it is preferable that the relationship between each thickness satisfies equation (1). t13 = t11 + ts …(1)

[0042] However, in order to ensure the adhesive function of the adhesive 13, the thickness t13 may be slightly larger. For example, the thickness t13 may be 10% larger. That is, it is preferable that equation (2) is satisfied. (t11+ts)≦t13≦(t11+ts)×1.1 …(2)

[0043] If the thickness t13 of the adhesive 13 is small, the adhesive function of the adhesive 13 may not be achieved. However, even if the thickness t13 is 10% larger, there is no problem because the adhesive 13 will spread along the first surface M1.

[0044] Furthermore, the thickness of the adhesive 13 after the switching IC 50 and the chip inductor 1a are mounted on the substrate 40 is defined as t13'. In this case, it is preferable that the thickness t13' satisfies, for example, equation (3). (t11+ts)×0.9≦t13'≦(t11+ts)×1.1 …(3)

[0045] Furthermore, the adhesive 13 needs to be applied only to the first surface M1, which is the lower surface of the chip inductor 1a. If the adhesive 13 is applied to other surfaces, for example, the second surface M2, which is the upper surface of the chip inductor 1a, the adhesive 13 may flow between the chip inductor 1a and the switching IC 50, or between the switching IC 50 and the substrate 40. In that case, the adhesive 13 may interfere with the electrical connection, which is undesirable.

[0046] (Second Embodiment) Figure 8 shows a chip inductor 1b used in the mounting structure according to the second embodiment of this disclosure. Figure 8 shows the chip inductor 1b as viewed from the second surface M2 side. The chip inductor 1b has adhesive 13 on its first surface M1, which is its bottom surface. The chip inductor 1a does not have a dummy electrode D. The chip inductor 1b is provided between the substrate 40 and the switching IC 50, as in the case of Figure 5.

[0047] In the chip inductor 1b, a marker M is provided on the second surface M2, i.e., the top surface. The marker M is provided to indicate the orientation when mounting the chip inductor 1b. By providing the marker M, the orientation when mounting the chip inductor 1b can be confirmed. In other words, the chip inductor 1b includes a marker M to identify the second surface M2, which is the top surface, and the marker M is provided on the portion of the second surface M2 where the external electrodes 12 are not provided.

[0048] If the adhesive 13 is transparent or translucent, it is difficult to determine which side of the chip inductor 1b is the second surface M2, i.e., the top surface. For example, an automated mounting device for the chip inductor 1b can be realized by analyzing an image of the chip inductor 1b taken with a camera (not shown). In this case, by analyzing the image of the chip inductor 1b, it can be recognized that the side on which the marker M is placed is the second surface M2. That is, it can be recognized that the side on which the marker M is placed should be the top surface (the side facing the switching IC 50), and the side without the marker M should be the bottom surface (the side facing the substrate 40) when mounting.

[0049] Marker M is provided, for example, by laser engraving. The shape of marker M when viewed from above the second surface M2 is, for example, circular. The shape of marker M may also be triangular or star-shaped.

[0050] In chip inductor 1b, the configuration is the same as that of chip inductor 1a, as described with reference to Figures 5 to 7, except that marker M is provided.

[0051] (Third embodiment) Figure 9 shows a chip inductor 1c used in a mounting structure according to a third embodiment of the present disclosure. Figure 9 is a schematic diagram showing a cross-section of the chip inductor 1c. The chip inductor 1c is provided between the substrate 40 and the switching IC 50, as in the case of Figure 5. The chip inductor 1c has adhesive 13 on its first surface M1, which is its bottom surface. The chip inductor 1c also has adhesive 13a on its second surface M2, which is its top surface. The chip inductor 1a does not have a dummy electrode D.

[0052] Figure 10 shows the chip inductor 1c as viewed from the direction of arrow Ya in Figure 9, i.e., from the second surface M2 side. As shown in Figure 10, the first surface M1 is provided with an external electrode 11 and adhesive 13, while the second surface M2 is provided with an external electrode 12 and adhesive 13a. When viewing the chip inductor 1c from the second surface M2 side, the first electrode, the external electrode 11, provided on the first surface M1, and the second electrode, the external electrode 12, provided on the second surface M2, are positioned so as not to overlap with each other.

[0053] In Figure 10, when the second surface M2 is the top surface and the first surface M1 is the bottom surface, the chip inductor 1c on the substrate 40 is supported by the external electrode 11 and adhesive 13 provided on the first surface M1. Conversely, when the first surface M1 is the top surface and the second surface M2 is the bottom surface, the chip inductor 1c on the substrate 40 is supported by the external electrode 12 and adhesive 13a provided on the second surface M2. Therefore, even if the first surface M1 and the second surface M2 are reversed, it does not become a cantilever structure and can be mounted appropriately. In other words, for the chip inductor 1c, there is no mounting direction for the first surface M1 and the second surface M2. Therefore, it is not necessary to provide the marker M explained with reference to Figure 8 for the chip inductor 1c.

[0054] (Fourth Embodiment) Figure 11 shows a chip inductor 1d used in a mounting structure according to the fourth embodiment of this disclosure. The chip inductor 1d has a configuration in which a protective film 14 is added to the surface of the chip inductor 1a described with reference to Figure 6. The protective film 14 is provided on the entire surface of the chip inductor 1d, excluding the external electrodes 11, 12 and adhesive 13.

[0055] The protective film 14 is composed of an insulating material based on resin or inorganic material. The protective film 14 may be formed using a photosensitive resin such as a photoresist, or a protective film formed on the entire surface by coating or the like may be removed. When manufacturing the chip inductor 1d using a lamination method or a thin-film method, a protective film of a different material from the base material may be formed during manufacturing.

[0056] (Fifth embodiment) Figure 12 shows a chip inductor 1e used in the mounting structure according to the fifth embodiment of this disclosure. The chip inductor 1e has a configuration in which a protective film 14 is added to the surface of the chip inductor 1c described with reference to Figure 9. The protective film 14 is provided on the entire surface of the chip inductor 1e, excluding the external electrodes 11, 12, adhesive 13, and adhesive 13a. The protective film 14 is the same as in the fourth embodiment.

[0057] (Implementation procedure) Next, we will describe the implementation procedures for realizing each of the above implementation structures. The following describes the implementation procedures from the first to the third, assuming the implementation of the chip inductor 1a.

[0058] (First implementation step) Figures 13 to 16 illustrate the first implementation procedure. Figure 14 is a magnified view of the dashed line H2 in Figure 13.

[0059] First, as shown in Figure 13, the chip inductor 1a is placed on one main surface 40M of the substrate 40, and the substrate 40 and the chip inductor 1a are temporarily bonded together with an adhesive. For example, an adhesive that partially cures at 100°C or below is used. For example, an adhesive made of thermosetting resin such as epoxy can be used.

[0060] At this time, as shown in Figure 14, solder balls B11 are pre-placed on the electrode connection portion 43, and as shown in Figure 13, the chip inductor 1a is placed on one main surface 40M of the substrate 40. As a result, as shown in Figure 15, the chip inductor 1a is temporarily fixed on the substrate 40. At this time, since it is before the reflow process, the solder balls B11 have not melted.

[0061] Subsequently, as shown in Figure 15, the switching IC 50, equipped with solder balls B1, B2, B3, etc., is placed on one main surface 40M. In the state shown in Figure 15, a reflow process is performed, causing the solder balls B1, B2, B3, and B11 to melt. As a result, as shown in Figure 16, the switching IC 50 and chip inductor 1a are electrically connected to the substrate 40. At this time, the adhesive 13, which was in a partially cured state, fully hardens, and the chip inductor 1a is fixed to the substrate 40. As shown in Figure 16, a stable mounting structure can be achieved because a cantilever structure is not formed.

[0062] (Second implementation step) Figures 17 to 19 illustrate the second implementation procedure. Figures 17 and 18 are schematic diagrams showing a cross-section of the switching IC 50. Figure 19 is a magnified view of the dashed line H3 portion of Figure 18. Figure 19 is a schematic diagram showing a cross-section of a part of the switching IC 50 and a cross-section of the chip inductor 1a.

[0063] As shown in Figure 17, the switching IC 50 includes a printed circuit board 53, through-holes 54, and an IC chip 55. The IC chip 55 is electrically connected to the printed circuit board 53 by bonding wires 56, 57, etc. In other words, bonding wires 56, 57, etc. are routed inside the switching IC 50.

[0064] The printed circuit board 53 is provided with wiring patterns (not shown) and through-holes 54. Bonding wires 57 electrically connect the IC chip 55 to the through-holes 54.

[0065] Next, as shown in Figure 18, a chip inductor 1a is placed on the underside of the switching IC 50. At this time, the external electrodes 12 of the chip inductor 1a and the through-hole 54 are electrically connected. That is, as shown in Figure 19, the external electrodes 12 provided on the second surface M2 of the chip inductor 1a and the through-hole 54 of the switching IC 50 are electrically connected by solder balls B12. After that, the switching IC 50 and chip inductor 1a in the state shown in Figure 18 are placed on the substrate 40 and a reflow process is performed, which melts the solder balls B21 and so on. As a result, the switching IC 50 and chip inductor 1a are electrically connected to the substrate 40. At this time, since adhesive 13 is provided on the chip inductor 1a, the chip inductor 1a is fixed to one main surface 40M of the substrate 40 without becoming a cantilever structure.

[0066] (Third implementation step) Figures 20 to 23 illustrate the third implementation procedure. Figure 21 is a magnified view of the dashed line H4 in Figure 20.

[0067] As shown in Figure 20, first, the chip inductor 1a is mounted on the underside of the switching IC 50. At this time, as shown in Figure 21, the external electrodes 12 and 52 are electrically connected by solder balls B12. Then, as shown in Figure 22, solder balls B1, B2, and B3 are placed on the underside of the switching IC 50. At this time, solder balls are also placed on the external electrodes 11 of the chip inductor 1a. Finally, as shown in Figure 23, the switching IC 50 and the chip inductor 1a are placed on the substrate 40. In this state, the solder balls B1, B2, and B3 are melted by performing a reflow process. As a result, the switching IC 50 and the chip inductor 1a are electrically connected to the substrate 40. At this time, since adhesive 13 is provided on the chip inductor 1a, the chip inductor 1a is fixed to one main surface 40M of the substrate 40 without becoming a cantilever structure.

[0068] (Examples of other implementation structures) Figure 24 shows an example of another mounting structure. Figure 25 is a partially enlarged view of the mounting structure in Figure 24. As shown in Figures 24 and 25, this example includes substrates 40A and 40B. Substrate 40A has a ground layer 42A. Components are mounted on one main surface 40AM, which is the side of substrate 40A opposite to the ground layer 42A. Substrate 40B has a ground layer 42B. Components are mounted on one main surface 40BM, which is the side of substrate 40B opposite to the ground layer 42B.

[0069] As shown in Figures 24 and 25, a switching IC 50 is mounted on one main surface 40AM of substrate 40A. A chip inductor 1a is connected between the main surface 40AM of substrate 40A and the switching IC 50. As shown in Figure 24, the switching IC 50 is fixed to the main surface 40AM of substrate 40A by solder balls B1, B2, and B3. As shown in Figure 25, the chip inductor 1a is electrically connected to the external electrode 51 of the switching IC 50 by solder ball B12. Also, as shown in Figure 24, a load 60 is mounted on one main surface 40BM of substrate 40B.

[0070] As shown in Figure 24, substrates 40A and 40B can be bonded together. When substrates 40A and 40B are bonded together, a space is formed between them. At this time, the switching IC 50, chip inductor 1a, load 60, etc., are housed in the space between substrates 40A and 40B. This structure, in which a space is formed between substrates 40A and 40B, can be used, for example, in smartphones.

[0071] Arrows Y14 to Y20 in Figure 24 indicate the flow of current. The DC current output from the switching IC 50 passes through the chip inductor 1a, then through wiring patterns 41A and 41B as shown by arrows Y14 to Y16, and is input to the load 60. The current output from the load 60 passes through the ground layer 42B and wiring pattern 42C as shown by arrows Y17 to Y20, and is input to the ground terminal of the switching IC 50.

[0072] In smartphones, components are sometimes mounted at high density. If all components cannot be mounted on a single board, a two-layer board structure using two boards 40A and 40B may be adopted, as shown in Figure 24. In this two-layer board structure, depending on the component layout, the switching IC 50 and the load 60 may be placed on different boards, as shown in Figure 24. In that case, the conduction path of switching noise generated from the switching IC 50 becomes longer, and the loop diameter through which the noise is conducted becomes larger. Generally, if the loop diameter through which the noise is conducted is large, the noise is more likely to spread to surrounding wiring patterns, which can adversely affect other circuits. For example, it may cause malfunctions in other circuits.

[0073] Figure 26 shows an example of an implementation structure with a shorter switching noise conduction path. Figure 27 is a magnified view of a portion of the implementation structure in Figure 26.

[0074] In the mounting structures shown in Figures 26 and 27, the switching IC 70 is mounted on one main surface 40AM of the substrate 40A, similar to the mounting structures shown in Figures 24 and 25. However, unlike the mounting structures shown in Figures 24 and 25, the chip inductor 1a is placed on the upper surface of the switching IC 70. That is, the switching IC 70 corresponds to the first substrate, and the chip component chip inductor 1a is mounted on the main surface 70M, which is the mounting surface. In this case, the first surface M1 of the chip inductor 1a and the main surface 70M of the switching IC 70 face each other. Instead of the chip inductor 1a, any of the chip inductors 1b to 1e described earlier may be used.

[0075] Here, as shown in Figure 27, the switching IC 70 has an electrode pad 71 corresponding to the first electrode connection portion. The external electrode 11 corresponding to the first external electrode of the chip inductor 1a and the electrode pad 71 of the switching IC 70 are electrically connected by a solder ball (not shown). The adhesive 13 is applied to the portion of the chip inductor 1a where the external electrode 11 is not provided. The first surface M1 and the main surface 70M are fixed together by this adhesive 13.

[0076] The external electrode 12, which corresponds to the second external electrode of the chip inductor 1a, is connected to the wiring pattern 41B of the substrate 40B. The wiring pattern 41B corresponds to other circuit components. The external electrode 12 of the chip inductor 1a and the wiring pattern 41B of the substrate 40B are electrically connected by solder balls (not shown).

[0077] Arrows Y21 to Y26 in Figure 26 indicate the flow of current. The DC current output from the switching IC 70 passes through the chip inductor 1a, then through the wiring pattern 41B as shown by arrows Y21 to Y22, and is input to the load 60. The current output from the load 60 passes through the ground layer 42B and the wiring pattern 42C as shown by arrows Y23 to Y26, and is input to the ground terminal of the switching IC 70.

[0078] Figure 28 is a diagram illustrating the procedure for realizing the mounting structure shown in Figure 27. As shown in Figure 28, in a two-layer substrate consisting of substrate 40A and substrate 40B, solder balls B51, B52, B53 and B54 are provided on substrate 40A. In addition, solder ball B4 is provided at the position of the wiring pattern 41B corresponding to the position of the electrodes of the chip inductor 1a.

[0079] Subsequently, substrate 40B is moved in the direction of arrow Y40, and substrates 40A and 40B are bonded together. By performing the reflow process with substrates 40A and 40B bonded together, the solder balls B51, B52, B53 and B54 are melted. As a result, substrates 40A and 40B are connected, as shown in Figures 26 and 27. This results in the switching IC 70, chip inductor 1a, load 60, etc. being housed in the space between substrates 40A and 40B.

[0080] According to the mounting structure described with reference to Figures 26 to 28, the conduction path of switching noise generated from the switching IC 70 is shortened compared to the mounting structures shown in Figures 24 and 25. As a result, the loop diameter through which the noise is conducted is reduced, preventing adverse effects on other circuits. Even when the switching IC 70 and the load 60 are not placed on the same board in a two-layer substrate, the noise conduction path can be made as short as possible. This allows the switching noise generated from the switching IC 70 to return to the switching IC 70 from the load 60 via the shortest distance (minimum loop). Therefore, the noise does not spread to the surrounding circuits of the switching IC 70, preventing adverse effects on other circuits.

[0081] (Use of wiring cables) Figure 29 shows an example of an implementation structure that uses wiring cables to shorten the conduction path of switching noise.

[0082] Figure 30 is a partially enlarged view of the mounting structure shown in Figure 29. In the mounting structures shown in Figures 29 and 30, similar to the mounting structures shown in Figures 26 and 27, the switching IC 70 is mounted on one main surface 40AM of the substrate 40A. The chip inductor 1a is then placed on the main surface 70M of the switching IC 70. In this example, the switching IC 70 is the first substrate, and the main surface 70M of the switching IC 70 is the mounting surface. The chip inductor 1a has an external electrode 11, which is a first external electrode, and an external electrode 12, which is a second external electrode. The external electrode 11 of the chip inductor 1a is electrically connected to an electrode pad 71, which is the first electrode connection part, by a solder ball (not shown). The adhesive 13 is applied to the part of the chip inductor 1a where the external electrode 11 is not provided. The first surface M1 and the main surface 70M are fixed together by this adhesive 13.

[0083] Furthermore, the external electrodes 12 of the chip inductor 1a are electrically connected to the wiring cable 8. In addition, the wiring cable 8 is electrically connected to the wiring pattern 41B of the substrate 40B. In this case, unlike the mounting structures shown in Figures 26 and 27, the external electrodes 12 of the chip inductor 1a and the wiring pattern 41B are electrically connected via the wiring cable 8. In other words, the mounting structures shown in Figures 29 and 30 further include the wiring cable 8 provided in the space formed by the connection of substrates 40A and 40B. Then, via the wiring cable 8, the external electrodes 12 of the chip inductor 1a are electrically connected to the wiring pattern 41B, which is another circuit component.

[0084] In Figures 29 and 30, the wiring cable 8 is, for example, a flexible cable made of FPC (Flexible Printed Circuit). By removing a portion of the insulating film from the surface 8M of the wiring cable 8 in advance and providing solder balls (not shown) on the external electrodes 12, the external electrodes 12 of the chip inductor 1a and the wiring cable 8 can be electrically connected. Then, as shown in Figure 29, one end 81 of the wiring cable 8 can be electrically connected to the wiring pattern 41B of the substrate 40B. The other end 82 of the wiring cable 8 is preferably connected to one main surface 40AM of the substrate 40A, for example. If the end 82 of the wiring cable 8 is fixed to one main surface 40AM of the substrate 40A, the position of the end 81 of the wiring cable 8 is stabilized. This makes it easier to connect the end 81 of the wiring cable 8 to the wiring pattern 41B in the reflow process described later.

[0085] Figure 31 is a diagram illustrating the procedure for realizing the mounting structure shown in Figures 29 and 30. As shown in Figure 31, in a two-layer substrate consisting of substrate 40A and substrate 40B, solder balls B51, B52, B53 and B54 are provided on substrate 40A. In addition, solder ball B4 is provided at the position of the wiring pattern 41B corresponding to the position of the end 81 of the wiring cable 8.

[0086] Subsequently, substrate 40B is moved in the direction of arrow Y40, and substrates 40A and 40B are bonded together. By performing a reflow process with substrates 40A and 40B bonded together, solder balls B51, B52, B53, B54 and B4 are melted. As a result, substrates 40A and 40B are connected, as shown in Figures 29 and 30. This electrically connects the external electrode 12 of the chip inductor 1a and the wiring pattern 41B via the wiring cable 8. The switching IC 70, chip inductor 1a, wiring cable 8, load 60, etc. are then housed in the space between substrates 40A and 40B.

[0087] According to the mounting structure described with reference to Figures 29 to 31, the conduction path of switching noise generated from the switching IC 70 is shortened compared to the mounting structures shown in Figures 24 and 25. As a result, the loop diameter through which the noise is conducted is reduced, preventing adverse effects on other circuits. Even when the switching IC 70 and the load 60 are not placed on the same board in a two-layer substrate, the noise conduction path can be made as short as possible. This allows the switching noise generated from the switching IC 70 to return to the switching IC 70 from the load 60 via the shortest distance (minimum loop). Therefore, the noise does not spread to the surrounding circuits of the switching IC 70, preventing adverse effects on other circuits.

[0088] (Multiple chip components) In each of the embodiments described above, the case in which one chip inductor 1a is provided was explained. The number of chip inductors 1a is not limited to one, and multiple chip inductors 1a may be provided. Figure 32 shows an example in which multiple chip inductors 1a are provided. In this example, the switching IC 70 is the first substrate, and the main surface 70M of the switching IC 70 is the mounting surface. As shown in Figure 32, the switching IC 70 is mounted on one main surface 40AM of the substrate 40A by solder balls B1, B2, B3 and B5. Multiple chip inductors 1a are provided on the main surface of the switching IC 70.

[0089] Each chip inductor 1a has an external electrode 11 (not shown), which is a first external electrode, and an external electrode 12 (not shown), which is a second external electrode, similar to the embodiments described above. The external electrode 11 of the chip inductor 1a is electrically connected to an electrode pad 71 (not shown), which is a first electrode connection part, by a solder ball (not shown), similar to the case in Figure 30. Adhesive 13 (not shown) is provided on the part of the chip inductor 1a where the external electrode 11 is not provided, and the first surface M1 (not shown) and the main surface 70M of each chip inductor 1a are fixed together by this adhesive 13.

[0090] The substrate 40B is provided with another circuit component, an antenna coil ANT. One external electrode 12 (not shown) of one of the multiple chip inductors 1a and the antenna coil ANT are electrically connected by a wiring cable 80. At this time, one end 83 of the wiring cable 80 is connected to the antenna coil ANT, and the other end 84 is connected to one of the chip inductors 1a. The multiple chip inductors 1a operate, for example, as a matching circuit that performs impedance matching. Bonding wire may be used instead of the wiring cable 80.

[0091] Figure 33 is a diagram illustrating the procedure for realizing the mounting structure shown in Figure 32. As shown in Figure 33, in a two-layer substrate consisting of substrate 40A and substrate 40B, solder balls B51, B52, B53, and B54 are provided on substrate 40A. Solder balls B1, B2, B3, and B5 are provided on one main surface 40AM of substrate 40A, and the switching IC 70 is mounted thereon. The end 84 of the wiring cable 80 is connected to one of the multiple chip inductors 1a provided on the main surface of the switching IC 70. In addition, solder ball B6 is provided on the electrode (not shown) of the antenna coil ANT, which corresponds to the end 83 of the wiring cable 80.

[0092] Subsequently, substrate 40B is moved in the direction of arrow Y40, and substrates 40A and 40B are bonded together. By performing the reflow process with substrates 40A and 40B bonded together, the solder balls B51, B52, B53 and B54 are melted. As a result, substrates 40A and 40B are connected, as shown in Figure 32. This results in the switching IC 70, chip inductor 1a, wiring cable 80, etc. being housed in the space between substrates 40A and 40B.

[0093] (Improved implementability) Incidentally, the switching IC 70 is sometimes attracted to the surface by the nozzle of the mounter (hereinafter referred to as the IC mounter), which is a device for mounting the switching IC 70. As shown in Figures 32 and 33, when multiple chip inductors 1a are provided on the top surface of the switching IC 70, attraction can become difficult. In particular, since there are areas between the chip inductors 1a where nothing is mounted, a gap is created between the tip of the nozzle and the top surface of the switching IC 70, which worsens the mountability of the switching IC 70.

[0094] The following describes embodiments for improving the mountability of the switching IC 70. Figures 34 to 36 show an example in which multiple chip inductors 1a are provided on the main surface, i.e., the top surface, of the switching IC 70. First, multiple chip inductors 1a are placed in the direction of arrow Y40 in Figure 34. In this example as well, adhesive 13 (not shown) is provided in the areas where chip inductors 1a and external electrodes 11 (not shown) are not provided, and the first surface M1 (not shown) of each chip inductor 1a is fixed to the main surface 70M by this adhesive 13. After that, each chip inductor 1a is provided on the main surface 70M, which is the mounting surface of the switching IC 70, which is the first substrate, by a reflow process. As a result, as shown in Figure 35, the electrode pad electrode 71 (not shown), which is the first electrode connection part of the main surface 70M of the switching IC 70, and the electrode of each chip inductor 1a are electrically connected.

[0095] In the state shown in Figure 35, there is an area between the chip inductors 1a where nothing is mounted. As shown in Figure 36, filler material J is provided on the upper surface of the switching IC 70 in the area where the chip inductors 1a are not provided. The filler material J is, for example, an insulating resin. In the embodiments of Figures 32 and 33, filler material J is not provided in the area where the end 84 of the wiring cable 80 is connected, so as not to interfere with the electrical connection. A mold (not shown) is provided in advance on the upper surface of the switching IC 70, and by pouring the filler material J into the mold, filler material J can be provided between the chip inductors 1a as shown in Figure 36. If the viscosity of the filler material J is relatively high, the filler material J may be poured without providing a mold. The size of the area where the filler material J is provided should be large enough to secure a surface area for the tip of the nozzle of a mounter (not shown) to make contact.

[0096] After pouring in the filler material J, the surface is flattened and hardened, so that, in the state shown in Figure 36, when the switching IC 70a is picked up by the nozzle (not shown) of the mounter from the direction of arrow Y50, the gap is small, making it easier to pick up. Therefore, the mountability of the switching IC 70 can be improved. Furthermore, by pouring in the filler material J and sealing the top surface of the switching IC 70, the weather resistance of the switching IC 70 can also be improved.

[0097] In the mounting structure described with reference to Figures 34 to 36, multiple chip inductors 1a, which are chip components, are provided on the main surface, i.e., the top surface, of the switching IC 70. Filler material J is provided between the multiple chip inductors 1a. Filler material J is provided on the parts of the main surface of the switching IC 70 where chip inductors 1a are not provided. By adopting such a mounting structure, the mountability of the switching IC 70 can be improved. That is, as described with reference to Figures 32 and 33, when the switching IC 70 is placed on one main surface 40AM of the substrate 40A, the top surface of the switching IC 70 is easily attracted by the nozzle (not shown) of the mounter. Therefore, the mountability can be improved.

[0098] Figures 37 to 39 show other examples of cases where multiple chip inductors 1a are provided on the main surface, i.e., the top surface, of the switching IC 70. As shown in Figure 37, the first base body of this example, the switching IC 70a, has recesses 72. That is, multiple recesses 72 are provided on the main surface 70M, which is the mounting surface of the switching IC 70a in this example. Each chip inductor 1a is mounted in a recess 72. The size of each recess 72 is approximately the same as the size of each chip inductor 1a. Because they are approximately the same size, each chip inductor 1a can be inserted into each recess 72. The depth of each recess 72 is approximately the same as the height of each chip inductor 1a.

[0099] Solder balls are placed on electrodes (not shown) within the recess 72, and the chip inductor 1a is inserted into the recess 72 as shown by arrow Y40 in Figure 38. In this example as well, adhesive 13 (not shown) is applied to the portion of the chip inductor 1a where the external electrodes 11 (not shown) are not provided, and the first surface M1 (not shown) and the main surface 70M of each chip inductor 1a are fixed together by this adhesive 13. Subsequently, a reflow process is performed to electrically connect the chip inductor 1a and the switching IC 70a, as shown in Figure 39.

[0100] In the state shown in Figure 39, the height of the top surface of the chip inductor 1a and the main surface 70M of the switching IC 70a are approximately the same. In the state shown in Figure 39, when the switching IC 70a is picked up by the nozzle of the mounter (not shown) from the direction of arrow Y50, the gap is small, making it easier to pick up. Therefore, the mountability of the switching IC 70a can be improved.

[0101] In the mounting structure described with reference to Figures 37 to 39, the first substrate, the switching IC 70a, includes a plurality of recesses 72 provided on its main surface 70M, and a chip component, the chip inductor 1a, is provided in each of the plurality of recesses 72. By adopting such a mounting structure, the mountability of the switching IC 70a can be improved. That is, as described with reference to Figures 32 and 33, when the switching IC 70a is placed on one main surface 40AM of the substrate 40A, the upper surface of the switching IC 70a is easily attracted by the nozzle (not shown) of the mounter. Therefore, the mountability can be improved.

[0102] (Other chip components) The above explanation described the case where the chip component is an inductor, but by adopting the same mounting structure not only for inductors but also for other chip components such as capacitors, it is possible to prevent the generation of stray capacitance and achieve stable mounting.

[0103] With regard to the description of the claims, this disclosure may take the following forms: (1) A mounting structure for mounting chip components on the mounting surface of a first substrate, The aforementioned chip component is A first surface facing the mounting surface, and a second surface provided on the opposite side of the first surface, A first external electrode is provided protruding from the first surface and electrically connected to the first electrode connection portion, A second external electrode is provided protruding from the second surface and electrically connected to other circuit components, An insulating adhesive is provided on the portion of the first surface where the first external electrode is not provided, and which fixes the first surface and the mounting surface together. An implementation structure having the following characteristics. (2) The chip component further includes a marker for identifying the second surface, The mounting structure according to (1) above, wherein the marker is provided in the portion of the second surface where the second external electrode is not provided. (3) The mounting structure according to (1) or (2) above, wherein, when viewed from the second surface of the chip component, the first external electrode provided on the first surface and the second external electrode provided on the second surface are positioned so as not to overlap each other. (4) The mounting structure according to any one of (1) to (3) above, wherein a protective film is provided on the entire surface of the chip component, excluding the first external electrode, the second external electrode, and the adhesive. (5) The mounting structure according to any one of (1) to (3) above, wherein the adhesive is provided on the entire surface of the chip component, excluding the first external electrode and the second external electrode. (6) The aforementioned chip component is an inductor, and the mounting structure is as described in any one of (1) to (5) above. (7) The first substrate includes a ground layer, The other circuit component is a switching integrated circuit that converts the input DC voltage. The inductor is a choke coil that receives the current output from the switching integrated circuit as input. The current that passes through the inductor flows to the ground layer via the load in the mounting structure described in (6) above. (8) It includes a first substrate and a second substrate having a main surface facing the main surface of the first substrate, The first substrate, which is a circuit component, is provided on the first substrate. The mounting structure according to any one of (1) to (6) above, wherein the circuit components and the chip components are housed in a space formed by connecting the first substrate and the second substrate. (9) The second substrate has other circuit components, The mounting structure according to (8) above, wherein the second external electrode of the chip component and the other circuit components are electrically connected. (10) The present invention further includes wiring cables provided in the space formed by the connection of the first substrate and the second substrate, The mounting structure according to (9) above, wherein the second external electrode of the chip component and the other circuit components are electrically connected via the wiring cable. (11) The chip component is provided on the mounting surface of the first substrate in the mounting structure described in (8) above. (12) Multiple chip components are provided on the mounting surface of the first substrate. The mounting structure according to (11) above, further comprising a filler material provided on the portion of the mounting surface in which the chip component is not provided. (13) The mounting structure described in (11) above further includes a plurality of recesses provided on the mounting surface of the first substrate, wherein the chip component is provided in each of the recesses. [Explanation of Symbols]

[0104] 1, 1a~1e, 1p Chip Inductor 8, 80 Wiring Cable 11, 12 External electrode 13, 13a Adhesive 14 Protective film 21 coils 40, 40A, 40B circuit boards 41 Wiring Patterns 42 Ground Layer 43 Electrode connection section 50, 70, 70a switching ICs ANT antenna coil D Dummy electrode M Marker

Claims

1. A mounting structure for mounting chip components on the mounting surface of a first substrate, The aforementioned chip component is A first surface facing the mounting surface, and a second surface provided on the opposite side of the first surface, A first external electrode is provided protruding from the first surface and electrically connected to the first electrode connection portion, A second external electrode is provided protruding from the second surface and electrically connected to other circuit components, An insulating adhesive is provided on the portion of the first surface where the first external electrode is not provided, and which fixes the first surface and the mounting surface together. It has, A protective film is provided on the entire surface of the chip component, excluding the first external electrode, the second external electrode, and the adhesive. Implementation structure.

2. The chip component further includes a marker for identifying the second surface, The mounting structure according to claim 1, wherein the marker is provided in the portion of the second surface where the second external electrode is not provided.

3. The mounting structure according to claim 1 or claim 2, wherein, when viewed from the second surface of the chip component, the first external electrode provided on the first surface and the second external electrode provided on the second surface are positioned so as not to overlap each other.

4. The mounting structure according to claim 1 or claim 2, wherein the chip component is an inductor.

5. The first substrate includes a ground layer, The other circuit component is a switching integrated circuit that converts the input DC voltage. The inductor is a choke coil that receives the current output from the switching integrated circuit as input. The mounting structure according to claim 4, wherein the current passing through the inductor flows to the ground layer via the load.

6. It includes a first substrate and a second substrate having a main surface facing the main surface of the first substrate, The first substrate, which is a circuit component, is provided on the first substrate. The circuit components and chip components are housed in the space formed by connecting the first substrate and the second substrate. The mounting structure according to claim 1.

7. The second substrate has other circuit components, The second external electrode of the chip component and the other circuit components are electrically connected. The mounting structure according to claim 6.

8. The present invention further includes a wiring cable provided in the space formed by the connection of the first substrate and the second substrate, The second external electrode of the chip component and the other circuit components are electrically connected via the wiring cable. The mounting structure according to claim 7.

9. The chip component is provided on the mounting surface of the first substrate. The mounting structure according to claim 6.

10. Multiple chip components are provided on the mounting surface of the first substrate. The aforementioned mounting surface further includes a filler material provided in the portion where the chip component is not provided. The mounting structure according to claim 9.

11. The first substrate further includes a plurality of recesses provided on the mounting surface, and the chip component is provided in each of the recesses The mounting structure according to claim 9.

Images