Disqueeze method for physical layer interfaces on multichip modules

Abstract

To provide a deskewing method for a physical layer interface on a multi-chip module.SOLUTION: A circuit connected to a plurality of communication lanes is configured to: train each lane to synchronize a local clock of the lane with a corresponding global clock at a beginning of a timing window 1505; in response to determining that all of the lanes have an incorrect symbol alignment 1515 / none, symbol-rotate each lane by a single step 1520; in response to determining that some but not all of the lanes have a correct symbol alignment 1515 / some, symbol-rotate lanes which have an incorrect symbol alignment by a single step 1525; when the end of the timing window has been reached 1530 / yes, symbol-rotate lanes which have a correct symbol alignment and adjust a phase of a corresponding global clock to compensate for wrong symbol rotations 1535.SELECTED DRAWING: Figure 15

Description

Background Art

[0001] Recent semiconductor chips include various circuits and components that facilitate high-speed and efficient computing. When transferring information between functional blocks within a semiconductor chip, electrical signals are typically transmitted over metal traces. A transmitter within a first functional block transmits an electrical signal over the metal trace. A receiver within a second functional block receives the electrical signal. In some cases, the two functional blocks are on the same die. In other cases, the two functional blocks are on separate dies.

[0002] The processing speeds of information processing systems and information processing devices continue to increase as new systems and devices are developed. When data signals and corresponding clock signals are transmitted between functional blocks, the signals can sometimes become misaligned with each other. Re-aligning the signals typically involves a significant amount of latency.

[0003] By referring to the following description in conjunction with the accompanying drawings, the advantages of the methods and mechanisms described herein can be well understood.

Brief Description of the Drawings

[0004] [Figure 1] A block diagram of one embodiment of a general-purpose computer or communication system including a transmitter and a receiver. [Figure 2] A block diagram of one embodiment of a computing system. [Figure 3] A diagram of one embodiment of a physical layer interface connection. [Figure 4] A block diagram of one embodiment of a circuit for adjusting the phase of a local clock to achieve synchronous clock domain crossing. [Figure 5] A block diagram of one embodiment of a circuit implementing an optional FIFO mode to increase the timing margin available for achieving synchronous clock domain crossing. [Figure 6]This is a diagram illustrating one embodiment of the circuit used in a deserializer. [Figure 7] This is a timing diagram of one embodiment in which symbol locking is performed using a barrel shifter in a deserializer. [Figure 8] This is a timing diagram of one embodiment showing the point in time after the barrel shifter has shifted the clock phase by a single step. [Figure 9] This is a timing diagram of one embodiment showing the point in time after the barrel shifter has shifted the clock phase by the second step. [Figure 10] This is a state diagram of one embodiment in which a link-wide deskue is executed with minimum latency. [Figure 11] This is a diagram illustrating one embodiment of the circuit used in a deserializer. [Figure 12] This diagram shows one embodiment of a two-row FIFO circuit that increases the timing margin while taking clock jitter into consideration. [Figure 13] This is a generalized flowchart illustrating one embodiment of a method for performing training to synchronize a local clock with a global clock. [Figure 14] This is a generalized flowchart illustrating one embodiment of a method for achieving synchronous cross-domain crossing across multiple lanes. [Figure 15] This is a generalized flowchart illustrating one embodiment of a method for deskewing across multiple lanes with reduced latency. [Figure 16] This is a block diagram showing one embodiment of a non-temporary computer-readable storage medium for storing circuit representations. [Modes for carrying out the invention]

[0005] The following description includes numerous specific details to provide a full understanding of the methods and mechanisms presented herein. However, those skilled in the art should recognize that various embodiments can be carried out without these specific details. In some examples, well-known structures, components, signals, computer program instructions, and techniques are not shown in detail to avoid obscuring the approach described herein. For simplicity and clarity, it should be understood that the illustrated elements are not necessarily drawn to scale. For example, the dimensions of some elements may be exaggerated relative to others.

[0006] Various systems, apparatus, methods, and computer-readable media are disclosed for a deskew method for a physical layer interface on a multichip module that implements synchronous clock domain crossing with reduced latency. In one embodiment, a circuit connected to multiple communication lanes trains each lane at the beginning of a timing window to synchronize the lane's local clock with the corresponding global clock. The circuit then symbol rotates each lane by a single step depending on whether it determines that all of the multiple lanes have incorrect symbol alignment. Depending on whether it determines that some, but not all, of the multiple lanes have correct symbol alignment, the circuit symbol rotates the lanes with incorrect symbol alignment by a single step. Upon reaching the end of the timing window, the circuit symbol rotates the lanes with correct symbol alignment and adjusts the phase of the corresponding global clock to compensate for the incorrect symbol rotation. Depending on whether it determines that all of the multiple lanes have correct symbol alignment, the circuit samples multiple data signals using multiple local clocks to generate multiple data sequences.

[0007] In various embodiments, techniques for implementing synchronous clock domain crossing with reduced latency are disclosed. In one embodiment, a circuit generates a local clock while receiving a global clock and data signals. The circuit includes a register that samples the local clock with the global clock. The circuit also includes a barrel shifter that generates a phase-shifted version of the local clock with a single unit interval (UI) step size. Furthermore, the circuit includes control logic that uses the barrel shifter to sweep the local clock across all phases until an edge transition is detected. If an edge transition is detected, it indicates that the local clock is aligned with the global clock. The control logic then adjusts the phase of the local clock to satisfy setup and hold requirements for sampling the data signals. The data signals are then sampled with the phase-adjusted local clock to generate a data sequence.

[0008] Referring to Figure 1, a block diagram of one embodiment of a general-purpose computer or communication system 100 including a transmitter 105 and a receiver 110 is shown. In one embodiment, the transmitter 105 transmits data to the receiver 110 via a communication channel 115. Depending on the embodiment, the communication channel 115 is a cable, a backplane, one or more metal traces, or another type of communication channel. For example, in one embodiment, channel 115 is one or more metal traces between two chips of a multichip module. At the physical layer, communication between the transmitter 105 and the receiver device 110 may be unidirectional or bidirectional according to a predetermined transmission protocol. Note that the system 100 may include any number and type of other devices. Also, the system 100 may include any number of transceiver pairs distributed throughout the system.

[0009] The transmitter 105 and receiver 110 may be of any type depending on the embodiment. For example, in one embodiment, the transmitter 105 is a processing unit (e.g., a central processing unit (CPU), a graphics processing unit (GPU)), and the receiver 110 is a memory device. The memory device may be any type of memory, such as dynamic random access memory (DRAM), synchronous DRAM (SDRAM), double data rate (DDR, DDR2, DDR3, etc.), SDRAM (including mobile versions of SDRAM such as mDDR3 and / or low-power versions of SDRAM such as LPDDR2), RAMBUS DRAM (RDRAM), or static RAM (SRAM). One or more memory devices may be coupled to a circuit board to form a memory module such as a single in-line memory module (SIMM) or a dual in-line memory module (DIMM). Alternatively, the memory device may be implemented in a system-on-chip (SoC) or integrated circuit (IC) in a chip-on-chip, package-on-package, or multi-chip module (MCM) configuration.

[0010] In another embodiment, the transmitter 105 is an input / output (I / O) fabric, and the receiver 110 is a peripheral device. The peripheral device may include various types of wireless communication devices such as Wi-Fi®, Bluetooth®, cellular, and global positioning systems. The peripheral device may also include additional storage devices, including RAM storage, solid-state storage, or disk storage. The peripheral device may also include user interface devices such as a display screen, including a touch display screen or a multi-touch display screen, a keyboard or other input devices, a microphone, and a speaker. In another embodiment, the transmitter 105 and receiver 110 are other types of devices. Note that the system 100 may be any type of system, such as an IC, SoC, and MCM.

[0011] Referring to Figure 2, a block diagram of one embodiment of computing system 200 is shown. As shown, system 200 represents a desktop computer 210, a laptop computer 220, a server 230, a mobile device 240, or other chips, circuits, components, etc. Other devices are possible and will be considered. In the illustrated embodiment, system 200 includes any pair of transmitters 202A-N and receivers 203A-N.

[0012] Referring to Figure 3, a diagram of one embodiment of a physical layer interface connection is shown. On the left side of Figure 3 is a master physical coding sublayer (PCS) 305 connected via channel 340 to a slave PCS 380 on the right side of Figure 3. In one embodiment, the master PCS 305 is located on a first integrated circuit (IC) (i.e., chip) of a multi-chip module (MCM), and the slave PCS 380 is located on a second IC of the MCM. For example, in one embodiment, the master PCS 305 is part of an input / output (I / O) semiconductor die, and the slave PCS 380 is part of a core complex semiconductor die. In other embodiments, the master PCS 305 and slave PCS 380 are included together with other types of components or functional units.

[0013] In various embodiments, the master PCS305 includes or is coupled to a phase-locked loop (PLL) 310 that generates a clock, and the PLL310 is coupled to a clock transmit module 325 and other modules within the master PCS305. The master PCS305 includes an array of N receivers 315 and an array of M transmitters 335, where N and M are positive integers, and the values ​​of N and M vary depending on the embodiment. A receive clock gating (RXCG) module 320 is coupled to the receiver array 315, and a transmit clock gating (TXCG) module 330 is coupled to the transmitter array 335. In one embodiment, the clock is transferred from the master PCS305, and the master PCS305 is used as the reference clock for the PLL310. The clock generated by the PLL310 is transferred via channel 340 and used as the reference clock for PLL375 (of the slave PCS380) and the downstream logic. In one embodiment, a half-rate architecture is utilized by a master PCS305 and a slave PCS380, where the clock frequency is half the data rate frequency, and data is sampled on the rising and falling edges of the clock.

[0014] In one embodiment, the transmitter array 335 of the master 305 is connected to corresponding lanes in a channel 340 having a width greater than 1000 microns (i.e., micrometers) between the furthest lanes. Also in one embodiment, the receiver array 315 of the master 305 is connected to corresponding lanes in a package channel 340 having a width greater than 1000 microns between the furthest lanes. This results in drift between the clock edges of different clocks transmitted on the lanes of channel 340.

[0015] In one embodiment, synchronous clock domain crossing is achieved across the transmitter array 335 using one or more of the methods and mechanisms described herein. For example, even when the lanes of the transmitter array 335 are separated by a distance greater than 1000 microns, synchronous clock domain crossing is achieved using the techniques presented herein, adding a relatively small amount of latency to the interface (compared to conventional approaches). In one embodiment, to achieve synchronous clock domain crossing, the local clock of the slave PCS380 is trained to match the transferred controller clock. As used herein, the term “local clock” is defined as a segmented version of a relatively fast PLL clock. Also, as used herein, the term “controller clock” is defined as a system-on-chip (SoC) master clock distributed across the lanes of a channel (e.g., channel 340).

[0016] In one embodiment, a delay is added at a granularity of 1 unit interval (UI) to minimize transmit channel skew between lanes. In one embodiment, an arbitrary first-in, first-out (FIFO) mode is implemented to increase the available timing margin to achieve synchronous crossing. Enabling FIFO mode makes additional delay available at the expense of further latency. However, this provides an additional range of adjustment available to reduce transmit channel skew. In one embodiment, before training, symbol start points are spread across various transmit lanes of channel 340. After training, symbol start points on various transmit lanes of channel 340 are aligned with each other within 1 UI.

[0017] Referring to FIG. 4, a block diagram of an embodiment of a circuit 400 for adjusting the phase of a local clock to achieve synchronous clock domain crossing is shown. In one embodiment, for a physical layer (PHY) interface, the input controller clock is fixed in phase, and the local clock is a divided version (using divider 422) of a high-speed clock generated by PLL 420. The local clock is supplied to clock training unit 425. An example of clock training unit 425 is shown as control logic within block 405. As shown in block 405, the local clock is phase shifted by the use of barrel shifter 415. In one embodiment, a plurality of local clocks are trained to align with the corresponding controller clocks, and then the trained local clocks are coupled to a 10 / 2 serializer as shown in block 430.

[0018] In one embodiment, a two-step training method is executed to train the phase of the local clock to match the corresponding controller clock. In the first step, a training step is executed when the phase relationship between the local clock and the controller clock is unknown, and the phase relationship of the local clock for each lane with respect to the controller clock is established. In the second step of the training method, the phase of each local clock is adjusted with respect to the controller clock to meet the setup requirements and hold requirements.

[0019] In one embodiment, the controller clock is used to sample the local clock in the synchronization register 417, and the output of the synchronization register 417 is provided to the clock training finite state machine (FSM) 410. The barrel shifter 415 is used to sweep the local clock across all phases until it is detected that the sampler output (i.e., the output of the synchronization register 417) changes from 0 to 1. When it is detected that the sampler output changes from 0 to 1, it indicates that the local clock is aligned within the + / - 1 unit interval (UI) of the controller clock. In one embodiment, 1 UI is 1 / 10 of the 1x clock, and 1 UI is the minimum resolution for sweeping the clock. In one embodiment, additional averaging is performed in the clock training FSM 410 to account for the delta value due to the low-frequency phase offset. Once the local clock is aligned with the controller clock, the phase of the local clock is adjusted to meet the setup requirements and the hold timing requirements. This method is repeated for all lanes so that data from different lanes is synchronized to the controller clock with relatively low latency. Also, in one embodiment, a delay is added between lanes to minimize the skew caused by the transmitter and the channel.

[0020] Using the approach shown in FIG. 4, data is passed from the controller clock domain to the local clock domain at the per-flop timing, thereby reducing the latency present in conventional designs. Timing diagram 440 shows an example of the pre-training timing of the local clock with respect to the controller clock. Timing diagram 450 shows an example of the timing achieved between the local clock and the controller clock after training, where the local clock is adjusted with respect to the controller clock to meet the setup requirements and the hold requirements.

[0021] Referring to Figure 5, a block diagram of one embodiment of circuit 500 that implements an optional FIFO mode to increase the available timing margin to achieve synchronous clock domain crossing is shown. In one embodiment, the computing system has a clock domain crossing between a potentially high-jitter controller clock and a lane-generating local clock. The controller clock is used as a parallel data initiation clock from the master PCS, and the lane-generating local clock (i.e., word clock) is used as a parallel data capture in the PHY interface. In one embodiment, the synchronous clock domain crossing from the controller clock to the lane-generating local clock is achieved via a clock training algorithm with an optional FIFO buffer. If the predicted controller clock jitter is sufficiently high that the timing cannot be met even with the trained interface, in one embodiment, a FIFO is used to increase the jitter tolerance. In one embodiment, a 2-entry FIFO is used to double the jitter tolerance.

[0022] In one embodiment, in default mode, the local clock is adjusted with 1UI resolution based on the initial average difference between the controller clock and the local clock to ensure a sufficient timing margin for the expected controller clock jitter. In one embodiment, in optional FIFO mode, a half-rate version of the controller clock acts as the write pointer, while a half-rate version of the local clock is used as the read pointer. The clock training algorithm determines the initial average write / read pointer separation for the programmable placement of the read pointer. In one embodiment, the read pointer placement is adjusted with 1UI resolution to ensure a sufficient timing margin and to minimize latency in the parallel data capture interface based on the expected controller clock jitter scale. In one embodiment, if a sufficient margin exists in the pointer separation, the read pointer is further adjusted after initial clock training with a 1UI step size to reduce lane-by-lane skew. Once data is passed to the local clock domain, the data is serialized and provided to the channel via the transmit lane.

[0023] In one embodiment, input data is supplied via flop 510 in the domain of physical coding sublayer (PCS) 505. The controller clock is supplied to the clock input of flop 510. In one embodiment, the input data is 10 bits wide. However, in other embodiments, the input data may have a different bit width. Similarly, in other embodiments, the bit width of other paths in circuit 500 may vary. The output of flop 510 is supplied in parallel to flops 515 and 520 in the transmit macro domain 507. The half-rate controller clock is supplied as a clock to the clock inputs of flops 515 and 520. The outputs of flops 515 and 520 are supplied to the input of multiplexer 525. The output of multiplexer 525 is coupled to the input of flop 535. The 1x-rate local clock is coupled to the clock input of flop 535. The output of flop 535 is supplied to a serializer (not shown).

[0024] In one embodiment, a high-speed 5x-rate clock is supplied as input to a word clock barrel shifter 540. In one embodiment, the word clock barrel shifter 540 generates 10 unique phases of a local 1x-rate clock. The phase-aligned output of the word clock barrel shifter 540 is inverted and then coupled to the clock port of flop 530. The output of flop 530 is inverted and then coupled again to the input of flop 530 to generate a phase-aligned half-rate local clock. The phase-aligned half-rate local clock is coupled to the select input of multiplexer 525. The 1x controller clock is inverted and coupled to the clock input of flop 545. The output of flop 545 is inverted and then coupled again to the input of flop 545 to generate a half-rate controller clock. Note that the flops shown in circuit 500 (in Figure 5) may be implemented using any type of suitable register (e.g., a D-type flip-flop).

[0025] Referring to Figure 6, a diagram of one embodiment of circuit 600 for use in a deserializer is shown. In one embodiment, circuit 600 is implemented as part of a 2-to-10 deserializer. The 2-to-10 deserializer receives 2 input bits per input clock cycle and produces 10 output bits per output clock cycle. However, in other embodiments, circuit 600 may be modified for use by other types of deserializers that receive a different number of input bits per cycle and / or produce a different number of output bits per cycle. In one embodiment, circuit 600 performs symbol locking as part of a 2-to-10 deserializer having a 1UI granularity with a 2UI clock phase. In one embodiment, symbol locking is performed as part of link training for a link between two separate functional units. By using this technique, the input deserialized (deserialized) data is realigned to the correct symbols with relatively low latency. In one embodiment, there are two aspects of the use of this symbol locking technique. The first aspect deserializes the input serial data using a barrel-shifted clock phase. The second aspect captures the input serial data in a different way to obtain accurate symbols.

[0026] As shown in circuit 600, the input serial data is sampled on both edges of the half-rate clock by flops 615A-B and passed to flop 645 via multiplexers 620,622 to obtain 2 bits of data. In one embodiment, after deserialization, the data is in the local clock domain and is moved again to the controller clock domain. This is achieved by synchronous clock domain crossing, as discussed above in the discussion of Figure 4. In one embodiment, the slave's controller clock is derived from a local PLL having a reference clock transferred from the master.

[0027] Regarding the operation of circuit 600, input data is received from channel 605 and coupled to two pairs of flops 615A and 615B. Clock generation unit 610 generates a first clock with a phase of 0 degrees coupled to the input of flop 615A. Clock generation unit 610 also generates a second clock with a phase of 180 degrees coupled to the input of flop 615B. The second clock with a phase of 180 degrees coupled to the input of flop 615B is 180 degrees out of phase with respect to the first clock with a phase of 0 degrees coupled to the input of flop 615A. The output of flop 615A is labeled Data1 and coupled to the "1" input of multiplexers 620 and 622. The output of flop 615B is labeled Data0 and coupled to the "0" input of multiplexers 620 and 622. The selection signals for multiplexers 620 and 622 are generated by the shift data counter 625, which flips for odd counts.

[0028] Logic 630, which checks whether symbol rotation is required, generates shift data to rotate the clock. The output from logic 630 is coupled to shift data counter 625 and barrel shifter 635. A 5x rate clock is also coupled to barrel shifter 635. Barrel shifter 635 generates multiple 1x rate clocks with different phases based on the 5x rate clock input. The multiple 1x clocks with different phases generated by barrel shifter 635 are fed to different flops between flop 645. The output of flop 645 is coupled to the input of flop 650. Flop 650 is clocked with the local clock, and the output of flop 650 is coupled to flop 655, which is clocked with the controller clock. In the case of odd shifts, an additional flop 640 exists to ensure that samples from "0" flop 645 are delayed and thus the data is not overwritten by the input bits.

[0029] Referring to Figure 7, a timing diagram 700 is shown in which symbol locking is performed using a barrel shifter in the deserializer. The timing diagram 700 is intended to represent an example of the timing at which the input serial data is sampled using circuit 600 (in Figure 6). In one embodiment, the data from the sampler is multiplexed as 2 bits of data to achieve a 0 / 1 UI delay when the multiplexer is selected, as shown in the timing diagram 700. The 2 bits of data are input in series to a 10-bit register with a shifted clock phase. From the 10-bit register, the output is sampled at the local clock. The deserialized data is then analyzed to infer whether the data needs to be rotated to achieve accurate symbol timing. As shown in line 710 for the example in timing diagram 700, the input data is sampled at the original unphase-shifted clock timing as a7: 0 bits and x9: 8 bits, where 'a' is the current symbol and 'x' is the previous symbol. The goal is to sample the input data as a9: 0 bits to have accurate symbols. As shown in line 710, the following symbols are sampled as b7: 0 bits and a9: 8 bits.

[0030] Referring to Figure 8, timing diagram 800 is shown at a point in time after the barrel shifter has performed a single step of symbol rotation. Timing diagram 800 is intended to represent the timing of circuit 600 (in Figure 6) for a certain embodiment after a single symbol rotation step has been performed. The difference between timing diagram 800 and timing diagram 700 (in Figure 7) illustrates the effect of performing symbol rotation. In timing diagram 800, the phase of the clocks of the odd-numbered registers is shifted. Register 9 takes the phase timing from the previous register 0, register 1 takes the phase timing from the previous register 2, register 3 takes the phase timing from the previous register 4, and so on. Thus, half of the registers shift their clocks 2 UI to the right. While the clocks of half of the registers are shifted to the right, the local clocks remain the same. After the 2 UI phase shift, a8:0 and x9 are sampled data as shown in line 810. In the case of an odd shift, samples from flop 0 are delayed, so an additional flop 0_delay exists to prevent the data from being overwritten by the latest input bit a9.

[0031] Referring to Figure 9, timing diagram 900 is shown at the point in time after the barrel shifter has performed a second symbol rotation step. Timing diagram 900 is intended to represent circuit 600 (in Figure 6) after the clock phase has been shifted by a second symbol rotation step for a particular embodiment. The difference between timing diagram 900 and timing diagram 800 (in Figure 8) illustrates the effect of performing the second symbol rotation step. In the first example shown in timing diagram 700 (in Figure 7), two symbol rotation steps are required to sample the exact symbol. Thus, the clock phase of the first stage of half of the register is rotated by a factor of two by the barrel shifter to achieve the exact symbol. Also, an even rotation shifts the local clock by two UI steps. In Figure 900, a substantially two UI shift has occurred, the data becomes a9:0, and the multiplexers 620,622 are shifted again. This technique locks the symbol by shifting the symbol window by a precise number of UI steps without introducing latency. As shown in Figures 800 and 900, the phase is shifted by 1 UI by moving it by 2 UI per clock cycle.

[0032] Referring to Figure 10, a state diagram 1000 of one embodiment for performing link-wide deskue with minimum latency is shown. In one embodiment, the method is implemented according to state diagram 1000 for link training at the receive physical layer (PHY) interface. A method is performed to determine the position of the symbol eye for each lane of multiple lanes to match symbols on the lanes, and at the same time, to desk them to achieve synchronous data transfer. "Symbol eye" refers to the data valid period of a symbol based on bit transitions on the data lane of the link. In conventional approaches, the source synchronous clock scheme for deskue uses an additional stage that simplifies the timing for capturing accurate symbols, and this additional stage results in relatively high latency. However, using the method associated with state diagram 1000, latency is significantly reduced compared to conventional approaches. In one embodiment, the approach associated with state diagram 1000 uses a symbol locking scheme with a 2to10 deserializer with 1UI granularity and 2UI clock phase, along with the synchronous clock domain crossing scheme described above.

[0033] Prior to link training, a synchronous clock domain crossing scheme is used to train each lane so that the local clock timing to the controller clock is at the beginning of the timing window (i.e., to satisfy the maximum hold time and minimum setup time). This step is repeated until the link is established. As used herein, the term “timing window” is defined as the period during which the corresponding data is valid. The timing window is defined by the leading and trailing edges of the data signal. After the link is established, each lane is checked and one of the following options is used: If all lanes do not have the correct symbols, the state diagram 1000 moves from the reset state 1005 to the out-eye state 1015. In the out-eye state 1015, each lane is symbol-rotated by one step using a barrel shifter, and the controller clock is also rotated by one step to maintain the established timing relationship. All lanes are then checked. If some lanes are symbol-locked, the state diagram moves to state 1010. In state 1010, the local clock for the unsymbol-locked lanes is shifted by 1 UI. In one embodiment, lanes that are not symbol-locked are shifted by 1 UI using a barrel shifter. Because the controller clock is static, the timing relationship between the controller clock and the local clock increases by 1 UI for setup time and 1 UI for hold time. This continues until all lanes are symbol-locked up to the timing margin window. If some lanes are still not symbol-locked by the time the timing margin window is reached, state diagram 1000 returns to reset state 1005. Otherwise, if all lanes are symbol-locked, state diagram 1000 returns to locked state 1030.

[0034] In reset state 1005, if several lanes are symbol-locked, state diagram 1000 moves to state 1010. State diagram 1000 moves from state 1010 to analysis state 1025. Then, state diagram 1000 moves to the begin_end_eye state 1020, in which the local clock is shifted for symbol-matched lanes. This method is used until the end of the timing window (i.e., minimum hold time, maximum setup time) is reached. At the end of the timing window, all locked lanes and controller clocks are rotated to compensate for the incorrect rotation. If a newly locked lane is locked for a deskewed symbol, existing locked lanes, except for the most recently locked lane and controller clock, are rotated to compensate for the incorrect rotation.

[0035] Referring to Figure 11, Figure 1100 shows one embodiment of a symbol eye starting point spanning four communication lanes 1105A–D. Lanes 1105A–D represent any number of lanes included as part of a communication channel. While four lanes are shown in Figure 11, it should be understood that this number is intended to serve as an example for illustrative purposes. Other embodiments may have other numbers of lanes, and the techniques described herein can be used to align the symbol eye across multiple lanes. The symbol eye for lanes 1105A–D is shown as a shaded rectangle within lanes 1105A–D.

[0036] Due to mismatched trace lengths connected to lanes 1105A-D and / or other factors, the symbol eyes of each lane are typically different in different lanes 1105A-D before training. The IN_EYE starting point for resetting is shown at the top of Figure 1100 to represent an example of one embodiment of the control logic that performs the method related to state diagram 1000 (in Figure 10). The control logic attempts to track the symbol eyes for each lane 1105A-D by rotating the local clock for the misaligned lanes. If the control logic reaches the END_EYE point of a lane before tracking the symbol eyes for all lanes, the control logic resets and restarts when the next symbol is received on lanes 1105A-D. The purpose of training is to adjust the phase of the local clocks of lanes 1105A-D so that the symbol eyes of each lane are aligned with the symbol eyes of the other lanes.

[0037] Referring to Figure 12, a diagram of one embodiment of a two-entry FIFO circuit 1200 is shown, which increases the timing margin to account for clock jitter. In one embodiment, data is received from a channel and provided to a sampler, and the sampler clock is a high-speed PLL clock (compared to a word clock). Various algorithms are executed, starting with clock data recovery (CDR) to establish a lock between the input serial bitstream and the high-speed PLL clock to ensure that the data is sampled accurately. In one embodiment, after the lock is established, the input bitstream is deserialized into parallel data. In one embodiment, the input serial bitstream is deserialized into 10-bit parallel data. However, in other embodiments, parallel data of a different number of bits is generated.

[0038] In one embodiment, after deserialization, the data resides in the local clock domain and needs to be moved to the controller clock domain. In one embodiment, this is achieved by using the synchronous clock domain crossing technique described above and by using circuit 1200. In one embodiment, clock domain crossing between the local clock (i.e., word clock) and the potentially high-jitter controller clock is achieved by a two-entry FIFO circuit 1200. The half-rate local clock is used as the write pointer, and the half-rate version of the controller clock acts as the read pointer. Both the write pointer and the local clock are generated from a common high-speed clock. In one embodiment, the write pointer placement is adjusted with a 1UI resolution.

[0039] In one embodiment, input serial data is coupled to the inputs of flops 1205A-N. In one embodiment, the input data includes 10 input lanes. However, in other embodiments, other numbers of input lanes may be supported by circuit 1200 by adjusting the number of flops 1205A-N and the bit width of other components of circuit 1200. In one embodiment, word clock barrel shifter 1207 receives a high-speed 5x rate clock that the word clock barrel shifter 1207 uses to generate a 1x rate clock output having five intrinsic phases and 2UI resolution. These 1x rate clocks with different phases are coupled to the clock ports of flops 1205A-N. The data inputs to flops 1205A-N are sampled using the phase-shifted clocks.

[0040] In one embodiment, the outputs from flops 1205A-N are coupled to the input ports of flop 1210. A word clock barrel shifter 1207 generates a local 1x rate clock that is coupled to the clock port of flop 1210. The output of flop 1210 is coupled to the input ports of flops 1215 and 1220. A high-speed 5x rate clock is coupled to the write pointer generator 1240. The write pointer generator 1240 generates a half-rate local clock that is coupled to the clock port of flop 1215. The half-rate local clock of the write pointer generator 1240 is negated and coupled to the clock port of flop 1220. The output of flop 1215 is coupled to the "0" input of multiplexer 1225, and the output of flop 1220 is coupled to the "1" input of multiplexer 1225. The half-rate controller clock generated by flop 1245 is coupled to the select port of multiplexer 1225. The output lane of the multiplexer 1225 is coupled to the input port of the flop 1235. A 1x rate controller clock is coupled to the clock port of the flop 1235. The parallel data output from the flop 1235 is supplied to a controller (not shown) or other components for further processing.

[0041] Referring to Figure 13, one embodiment of method 1300 for training a local clock to align with a global clock is shown. For illustrative purposes, the steps in this embodiment and the steps in Figure 14 are shown in order. However, it should be noted that in various embodiments of the method described, one or more of the elements described are performed simultaneously, in a different order than illustrated, or are omitted entirely. Other additional elements are also performed as needed. Any of the various systems or devices described herein are configured to carry out method 1300.

[0042] The circuit receives a global clock signal and data signals (block 1305). Note that the global clock may also be referred to herein as the “controller clock”. In some embodiments, the circuit receives multiple global clocks and multiple data signals. In one embodiment, the global clock and data signals are generated in a functional unit separate from the receiving functional unit. The circuit also generates a local clock signal (block 1310). For example, in one embodiment, the circuit generates the local clock signal using a local PLL.

[0043] The circuit sweeps the local clock across phases in 1UI steps using a barrel shifter and samples the local clock with a register clocked by the global clock to detect edge transitions (block 1315). In one embodiment, the output of the register is coupled to control logic that detects edge transitions. In one embodiment, the control logic includes a finite state machine (FSM). In one embodiment, the edge transition is a rising edge transition (i.e., from low voltage to high voltage). The control logic then determines that the local clock is aligned with the global clock in response to detecting an edge transition (block 1320). The phase of the local clock is then adjusted relative to the global clock to satisfy setup and hold timing requirements (block 1325). The data signal is then sampled using the phase-adjusted local clock (block 1330). The sampled data is then provided to subsequent stages for additional processing and / or storage (block 1335). In one embodiment, the sampled data is provided to a deserializer. After block 1335, method 1300 ends.

[0044] Referring to Figure 14, one embodiment of a method for achieving synchronous cross-domain crossing for multiple lanes is shown. The circuit receives multiple data signals and multiple corresponding global clock signals (block 1405). The circuit also generates multiple local clock signals (block 1410). For example, in one embodiment, the circuit generates each local clock signal using different local PLLs. The circuit sweeps each local clock over the phase in one UI step using a barrel shifter and samples the local clocks with a register clocked by the corresponding global clock to detect edge transitions (block 1415). In one embodiment, the output of the register is coupled to control logic that detects edge transitions. In one embodiment, the control logic includes a finite state machine (FSM). In one embodiment, the edge transition is a rising edge transition (i.e., from logic "0" to logic "1").

[0045] Next, the control logic, upon detecting an edge transition, determines that each local clock is aligned with the corresponding global clock (block 1420). Then, the phase of each local clock is adjusted relative to the corresponding global clock to satisfy the setup and hold timing requirements (block 1425). Next, each data signal is sampled using the corresponding phase-adjusted local clock (block 1430). The sampled data is then provided to subsequent stages for additional processing and / or storage (block 1435). In one embodiment, the sampled data is provided to a deserializer. After block 1435, method 1400 ends.

[0046] Referring to Figure 15, one embodiment of method 1500 for deskewing across multiple lanes with reduced latency is shown. Each of the multiple lanes is trained to synchronize its local clock with the global clock at the beginning of the timing window (i.e., maximum hold time, minimum setup time) (block 1505). In one embodiment, method 1400 (in Figure 14) is performed to carry out block 1505. Next, the symbol timing of each lane is checked (block 1510). If no lane has accurate symbol alignment (condition block 1515: "no lane"), each lane is symbol rotated by a single step (block 1520). In one embodiment, symbol rotating each lane by a single step involves shifting every other clock (a clock generated by a barrel shifter for a lane with a phase shift) by a single unit interval. The clocks generated by the barrel shifter with a phase shift are provided to a first column of flops that deserialize the data samples captured from the lanes. After block 1520, method 1500 returns to block 1510.

[0047] If some of the lanes have accurate symbol alignment (condition block 1515: "some lanes"), the unlocked lanes are symbol-rotated by a single step (block 1525). In one embodiment, blocks 1520 and 1525 are performed using circuit 600 (Figure 6). After block 1525, if the end of the timing window is reached (condition block 1530: "yes"), all locked lanes and the global clock are rotated to compensate for any incorrect rotation (block 1535). After block 1535, method 1500 returns to block 1510. If the end of the timing window is not reached (condition block 1530: "no"), method 1500 returns to block 1525. If all lanes have accurate symbol alignment (condition block 1515: "all lanes"), method 1500 terminates.

[0048] Referring to Figure 16, a block diagram is shown illustrating one embodiment of a non-temporary computer-readable storage medium 1600 that stores circuit representations 1605. In one embodiment, a circuit manufacturing system 1610 processes the circuit representations 1605 stored in the non-temporary computer-readable storage medium 1600 and manufactures any number of integrated circuits 1615A to N based on the circuit representations 1605.

[0049] The non-temporary computer-readable storage medium 1600 may include any of various suitable types of memory devices or storage devices. The medium 1600 may be an installation medium (e.g., a thumb drive, a CD-ROM), computer system memory or random access memory (e.g., DRAM, DDR RAM, SRAM, EDO RAM, Rambus RAM), non-volatile memory (e.g., flash memory, magnetic media, hard drives, optical storage devices), registers, or other types of memory elements. The medium 1600 may include any combination of these, along with other types of non-temporary memory. The medium 1600 may include two or more memory media located in different locations (e.g., in different computer systems connected via a network).

[0050] In various embodiments, the circuit representation 1605 is specified using any of a variety of suitable computer languages, including, but not limited to, hardware description languages ​​such as VHDL, Verilog, SystemC, System Verilog, and RHDL. The circuit representation 1605 is available to the circuit manufacturing system 1610 for manufacturing at least one or more parts of the integrated circuits 1615A-N. The format of the circuit representation 1605 is recognizable by at least one circuit manufacturing system 1610. In some embodiments, the circuit representation 1605 includes one or more cell libraries that specify the synthesis and / or layout of the integrated circuits 1615A-N.

[0051] The circuit manufacturing system 1610 includes any of various suitable elements configured to manufacture integrated circuits. These may include, for example, elements for depositing semiconductor material (e.g., on a wafer, which may include masking), elements for removing material, elements for changing the shape of deposited material, and elements for modifying material (e.g., by doping the material or by changing the dielectric constant using ultraviolet processing). The circuit manufacturing system 1610 may also perform tests on the manufactured circuits for accurate operation.

[0052] In various embodiments, integrated circuits 1615A-N operate according to a circuit design specified by circuit representation 1605, which may include performing any of the functions described herein. For example, integrated circuits 1615A-N may include any of the various elements shown in the circuit shown herein and / or any of multiple instances of the circuit shown herein. Furthermore, integrated circuits 1615A-N may perform various functions described herein together with other components. For example, integrated circuits 1615A-N may be coupled to a voltage supply circuit configured to provide a supply voltage (e.g., instead of including the voltage supply device itself). Furthermore, the functions described herein may be performed by multiple connected integrated circuits.

[0053] As used herein, the phrase "a circuit representation specifying the design of the circuit..." does not imply that the circuit in question must be manufactured to fulfill its elements. Rather, the phrase indicates that the circuit representation, when manufactured, is configured to perform a specified operation or contains a specified component.

[0054] In various embodiments, program instructions are used to implement the methods and / or mechanisms described herein. For example, program instructions describing the operation or design of hardware are written. In one embodiment, such program instructions are represented in a hardware design language (HDL), such as Verilog. In various embodiments, program instructions are stored in any of various non-temporary computer-readable storage media. The storage media are accessible by a computing system during use and supply the program instructions to the computing system for circuit manufacturing, program execution, or other purposes. Generally, such a computing system includes at least one memory and one or more processors configured to execute program instructions.

[0055] It should be emphasized that the embodiments described above are merely non-limiting examples of embodiments. A number of variations and modifications will become apparent to those skilled in the art once the above disclosure is fully understood. The following claims are intended to be construed as encompassing all such variations and modifications.

Claims

1. A first circuit configured to synchronize the local clock of each of the multiple communication lanes with the global clock, A second circuit is provided, The second circuit described above is In response to determining that one or more of the aforementioned communication lanes have inaccurate symbol alignment, each of the communication lanes having inaccurate symbol alignment is rotated by the same amount. Upon detecting the end of the timing window, the symbol timing of each of the one or more communication lanes is checked to determine whether symbol rotation is necessary. It is configured to do the following: circuit.

2. The second circuit is configured to rotate the symbols of each of the communication lanes having inaccurate symbol alignment by a single step, in response to detecting the end of the timing window. The circuit according to claim 1.

3. The first circuit is configured to sweep the local clocks across multiple phases while sampling them with the global clock, in order to synchronize the local clocks of each of the multiple communication lanes with the global clock. The circuit according to claim 1.

4. The first circuit is configured to sweep the local clock and, in response to the detection of an edge transition during the sweep, determine that the local clock is synchronized with the global clock. The circuit according to claim 1.

5. After the local clock synchronizes with the global clock, the phase of the local clock is adjusted. The circuit according to claim 4.

6. The second circuit is configured such that, after the local clock has synchronized with the global clock, it samples data on one of the communication lanes among the plurality of communication lanes using the local clock. The circuit according to claim 1.

7. The data on the communication lane sampled by the local clock is transmitted to the deserializer. The circuit according to claim 1.

8. Synchronizing the local clock of each of the multiple communication lanes with the global clock, In response to determining that none of the aforementioned communication lanes have accurate symbol alignment, each of the aforementioned communication lanes is rotated by the same amount of symbol alignment. The process includes, upon detecting the end of a timing window, checking the symbol timing of one or more of the multiple communication lanes to determine whether symbol rotation is necessary, method.

9. In response to detecting the end of the timing window, the system includes rotating the symbols of each of the communication lanes having inaccurate symbol alignment by a single step. The method of claim 8.

10. To synchronize the local clock of each of the multiple communication lanes with the global clock, the method includes sweeping the local clock across multiple phases while sampling the local clock with the global clock. The method of claim 8.

11. This includes sweeping the local clock and determining, in response to the detection of an edge transition during the sweep, that the local clock is synchronized with the global clock. The method of claim 8.

12. This includes adjusting the phase of the local clock after the local clock has synchronized with the global clock. The method according to claim 11.

13. The local clock is synchronized with the global clock, and the local clock then samples data on one of the communication lanes among the multiple communication lanes. The method of claim 8.

14. This includes transmitting the data on the communication lane sampled by the local clock to the deserializer, The method of claim 8.

15. The first functional unit, A channel having multiple communication lanes, A second functional unit coupled to the first functional unit via the channel, the second functional unit configured to transmit a first global clock and a first data signal to the first functional unit via the channel, The first functional unit is, Synchronizing the local clock of each of the multiple communication lanes with the global clock, In response to determining that one or more of the aforementioned communication lanes have inaccurate symbol alignment, each of the communication lanes having inaccurate symbol alignment is rotated by the same amount. Upon detecting the end of the timing window, the symbol timing of one or more of the multiple communication lanes is checked to determine whether symbol rotation is necessary. It is configured to do the following: system.

16. The first functional unit is configured to, upon detecting the end of the timing window, rotate the symbols of each of the communication lanes among the plurality of communication lanes that have inaccurate symbol alignment by a single step. The system according to claim 15.

17. The first functional unit is configured to sweep the local clocks across multiple phases while sampling them with the global clock, in order to synchronize the local clocks of each of the multiple communication lanes with the global clock. The system according to claim 15.

18. The first functional unit is configured to sweep the local clock and, in response to the detection of an edge transition during the sweep, determine that the local clock is synchronized with the global clock. The system according to claim 15.

19. After the local clock synchronizes with the global clock, the phase of the local clock is adjusted. The system according to claim 18.

20. The first functional unit is configured such that, after the local clock has synchronized with the global clock, it samples data on one of the communication lanes among the plurality of communication lanes using the local clock. The system according to claim 15.

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