Modular configuration for integrated Group III nitride devices

Abstract

To provide electronic modules and half-bridge circuits allowing higher circuit stability, improved performance, and lower production costs.SOLUTION: An electronic module 500 for a half-bridge circuit includes a base substrate 510 with an insulating layer between a first metal layer and a second metal layer. A trench 514 formed through the first metal layer electrically isolates a first portion 511, a second portion 512 and a third portion 513 from one another. A high-side switch 582 includes an enhancement (E)-mode transistor and a depletion (D)-mode transistor. The D-mode transistor includes a III-N material structure on an electrically conductive substrate. A drain electrode 636 is connected to the first portion. A source electrode 651 of the E-mode transistor is connected to the second portion. A drain electrode of the E-mode transistor is connected to a source electrode 634 of the D-mode transistor. A gate electrode of the D-mode transistor is connected to the electrically conductive substrate. The electrically conductive substrate is connected to the second portion.SELECTED DRAWING: Figure 5A

Description

[Technical Field]

[0001] This disclosed technology relates to a semiconductor electronic module designed to achieve improved performance and reliability. [Background technology]

[0002] [background] Currently, typical power semiconductors (including devices such as transistors, diodes, power MOSFETs, and insulated-gate bipolar transistors (IGBTs)) are fabricated from silicon (Si) semiconductor materials. More recently, wide-bandgap materials (SiC, III-N, III-O, diamond) have been considered for power devices due to their superior properties. Group III nitride or III-N semiconductor devices (such as gallium nitride (GaN) devices) are emerging as attractive candidates for carrying large currents, supporting high voltages, and providing ultra-low on-resistance with fast switching times.

[0003] Figure 1A shows a schematic diagram 100 of a half-bridge circuit including a high-potential switching transistor 102 and a low-potential switching transistor 103. The half-bridge circuit has a high-potential node 111 and a low-potential or ground node 113. The output node 112 of the half-bridge (between the source of the high-potential transistor 102 and the drain of the low-potential transistor 103) is connected to a load motor (inductive component 104). To ensure proper operation of the circuit in Figure 1A, the DC high-potential node 111 must be maintained as an AC ground. That is, node 111 can be capacitively coupled to the DC ground 113 by connecting one terminal of a capacitor 106 to the high-potential node 111 and the other terminal of the capacitor to ground 113. Thus, when either transistor 102 or 103 is switched on or off, the capacitor 106 can be charged or discharged as appropriate to provide the current necessary to maintain a substantially constant voltage on the high-potential and low-potential sides of the circuit.

[0004] Figure 1B shows a schematic circuit of a three-phase full-bridge circuit 120 configured to drive a three-phase motor. The three half-bridges 122, 124, and 126 in circuit 120 each contain two transistors (141-146) (e.g., the half-bridges in Figure 1A). The three half-bridges each have output nodes 137, 138, and 139. Each transistor in this circuit can block voltage in a first direction and conduct current in a first direction (or bidirectionally, at the option of choice).

[0005] One type of transistor that offers promising advantages when used in the circuits of Figures 1A and 1B is the III-N high electron mobility transistor (HEMT). This can be used as transistor 102 and / or transistor 103 in the half-bridge in Figure 1A, or any transistor in the bridge circuit in Figure 1B, etc. The most common III-N HEMTs and related transistors are normally-on (i.e., have a negative threshold voltage), which means they conduct current at zero gate voltage. These devices with negative threshold voltages are known as depletion-mode (D-mode) devices. In power electronics, it is preferable to have normally-off devices (i.e., devices with a positive threshold voltage) that are off when zero volts are applied to the gate relative to the source, in order to prevent accidental turn-on of a device (which could lead to damage to that device or other circuit components). Normally-off devices are generally called enhancement-mode (E-mode) devices.

[0006] To date, the reliable manufacturing and operation of high-voltage III-N E-mode transistors has been known to be extremely difficult. One alternative to a single high-voltage E-mode transistor is to combine a high-voltage D-mode III-N transistor and a low-voltage silicon E-mode FET in a cascode configuration. As shown in Figure 2, the cascode configuration 200 includes a high-voltage D-mode transistor 223 and a low-voltage E-mode transistor 222, both housed in a package 205. The source electrode 234 of transistor 223 is connected to the drain electrode 213 of transistor 222. The gate electrode 235 of transistor 223 and the source electrode 211 of transistor 222 are connected to each other and to the source lead 207 of package 205. The gate electrode 212 of transistor 222 is connected to the gate lead 208 of package 205. The drain electrode 236 of transistor 223 is connected to the drain lead 209 of package 205. The E-mode FET transistor 222 includes an integrated body diode 237 formed between the source 211 and the drain 213. Each device in the cascode configuration 200 in Figure 2 can operate in the same way as a single high-voltage E-mode transistor, with leads 207, 208, and 209 acting as the source, gate, and drain of the device, respectively, and in many cases achieving the same or similar output characteristics as a single high-voltage E-mode transistor.

[0007] A common method of operation for the circuits in Figures 1A and 1B involves hard switching of switches (i.e., transistors or cascode switches). In a hard-switching circuit configuration, a high current (e.g., greater than 10A) flows through each switch as soon as it is switched on, and a high voltage is generated through them as soon as they are switched off. Switches that operate under these conditions are said to be "hard-switched." Alternative circuit configurations utilize additional passive and / or active components (alternatively signal timing techniques) to allow the switches to be "soft-switched." In a soft-switching circuit configuration, the switches switch on during zero-current (or near-zero-current) conditions and off during zero-voltage (or near-zero-voltage) conditions. Soft-switching methods and configurations have evolved to address the high levels of electromagnetic interface (EMI) and associated ringing observed in hard-switched circuits (particularly in high-current and / or high-voltage applications). While soft switching can often circumvent these problems, the circuits required for soft switching typically involve many additional components, resulting in increased overall cost and complexity. Soft switching also typically requires the circuit to be configured to switch only at specific times when zero current or zero voltage conditions are met, which often limits the applicable control signals and degrades circuit performance. Therefore, alternative configurations and methods are desirable for hard-switched power switch circuits to maintain sufficiently low levels of EMI, reduce circuit inductance, and improve switching speed stability.

[0008] [Summary] This specification describes a modular configuration for integrated III-N devices. In this modular configuration, low-voltage enhancement-mode devices and high-voltage depletion-mode III-N devices are integrated into a single electronic component module to form half-bridge and full-bridge power switching circuits. The term “device” is generally used for any transistor, switch, or diode unless there is a need to distinguish between them.

[0009] In a first embodiment, an electronic module is described. The electronic module includes a base substrate having an insulating layer between a first metal layer and a second metal layer, the first metal layer comprising a first portion, a second portion and a third portion, and grooves formed through the first metal layer electrically insulating the first, second portion and third portion of the first metal layer from each other. The electronic module further includes a high-side switch comprising an enhancement-mode transistor and a depletion-mode transistor, the depletion-mode transistor comprising a III-N material structure on a conductive substrate. The electronic module further includes a low-side switch. The drain electrode of the depletion-mode transistor is electrically connected to a first portion of the first metal layer, the source electrode of the enhancement-mode transistor is electrically connected to a second portion of the first metal layer, the drain electrode of the enhancement-mode transistor is electrically connected to the source electrode of the depletion-mode transistor, the gate electrode of the depletion-mode transistor is electrically connected to a conductive substrate, and the conductive substrate is electrically connected to a second portion of the first metal layer.

[0010] In a second embodiment, a half-bridge circuit is described. The half-bridge circuit comprises a high-side switch and a low-side switch, each housed in a single electronic package, the package comprising a high-voltage terminal, an output terminal, and a ground terminal. The high-side switch comprises a first enhancement-mode transistor and a first depletion-mode transistor arranged in a cascode configuration. The low-side switch comprises a second enhancement-mode transistor and a second depletion-mode transistor arranged in a cascode configuration. The drain electrode of the first III-N transistor is electrically connected to the high-voltage terminal, the conductive substrate of the first depletion-mode III-N transistor is electrically connected to the output terminal, the drain electrode of the second III-N transistor is electrically connected to the output terminal, and the conductive substrate of the second depletion-mode III-N transistor is electrically connected to the ground terminal.

[0011] In a third aspect, a half-bridge circuit is described. The half-bridge circuit comprises a high-side switch and a low-side switch, each housed in a single electronic package. The high-side switch is connected to a high-voltage node, the low-side switch is connected to a ground node, and an inductor is connected to the output terminal of the package formed between the high-side switch and the low-side switch. The low-side switch comprises a low-voltage enhancement-mode transistor and a high-voltage III-N depletion-mode transistor arranged in a cascode configuration. The half-bridge circuit is configured such that, in a first operating mode, current flows through the high-side switch in a first direction and through the inductor while the high-side switch is biased to ON and the low-side switch is biased to OFF. In a second operating mode, current flows through the low-side switch in a second direction and through the inductor while the high-side switch is biased to OFF and the low-side switch is biased to OFF. In the third operating mode, while the high-side switch is biased to off and the low-side switch is biased to on, current flows through the low-side switch in the second direction and through the inductor. During the second operating mode, the low-side switch is configured to conduct a reverse DC current greater than 50A, and during the third operating mode, the increase in the on-resistance of the III-N depletion mode transistor compared to the first mode is less than 5%.

[0012] Each of the electronic modules and / or transistors described herein may include one or more of the following features: A high-side switch and a low-side switch may constitute a half-bridge circuit. A depletion-mode transistor may be configured to block at least 600V when the high-side switch is biased to off and to conduct a current greater than 30A when the high-side switch is biased to on. An electronic module may include a capacitor, the first terminal of which is electrically connected to a first portion of a first metal layer, and the second terminal of which is electrically connected to a third portion of the first metal layer. The capacitor may be formed perpendicularly above a groove. The capacitor may be a hybrid capacitor having resistive and capacitive components connected in series. The resistive component may be greater than 0.1 ohms, and the capacitive component may be greater than 0.1 nF. The gate electrode, source electrode, and drain electrode may be on the opposite side of the III-N material structure from the conductive substrate. The III-N material structure may include via holes formed through the substrate, and the gate electrode of the depletion-mode transistor is electrically connected to the substrate through these via holes. The electronic module may include a package, in which the substrate, high-side switch, and low-side switch are placed. The electronic module may also include a gate driver placed within the package, the first terminal of which is connected to the gate electrode of the high-side switch, and the second terminal of which is connected to the gate electrode of the low-side switch. The gate driver may be integrated with the low-side switch and each E-mode transistor of the low-side switch. A second high-side switch may be connected in parallel with the high-side switch, and a second low-side switch may be connected in parallel with the low-side switch. A second portion of the first metal layer is connected to the output node of the electronic module. The module is configured such that during operation, a first portion of the first metal layer is connected to a DC voltage source, and a third portion of the first metal layer is connected to DC ground. A ferrite bead having a first terminal and a second terminal, the first terminal of which is connected to a second portion of the first metal layer, and the second terminal is connected to the output terminal.Each substrate of the first and / or second depletion mode III-N transistor is a silicon-doped p-type substrate having a hole concentration of 1×10. 19 holes / cm 3 or greater. During the second operating mode, an inverse DC current flows through the parasitic body diode of the enhancement mode transistor and through the device channel of the III-N depletion mode transistor. During the third operating mode, an inverse DC current flows through the channel of the enhancement mode transistor and through the device channel of the III-N depletion mode transistor.

[0013] In this specification, “hybrid enhancement mode electronic device or component” (or simply “hybrid device or component”) is an electronic device or component formed from a depletion mode transistor and an enhancement mode transistor, wherein the depletion mode transistor is capable of a higher operating voltage and / or breakdown voltage compared to the enhancement mode transistor, and the hybrid device or component is configured to operate similarly to a single enhancement mode transistor having a breakdown voltage and / or operating voltage that is approximately as high as the breakdown voltage and / or operating voltage of the depletion mode transistor. That is, the hybrid enhancement mode device or component includes at least three nodes having the following characteristics: When the first node (source node) and the second node (gate node) are maintained at the same voltage, the hybrid enhancement mode device or component can block a high positive voltage applied to the third node (drain node) relative to the source node (i.e., a voltage greater than the maximum voltage that the enhancement mode transistor can block). If the gate node is maintained at a sufficiently positive voltage relative to the source node (i.e., a voltage greater than the threshold voltage of the enhancement-mode transistor), current flows from the source node to the drain node, or if a sufficiently positive voltage relative to the source node is applied to the drain node, current flows from the drain node to the source node. If the enhancement-mode transistor is a low-voltage device and the depletion-mode transistor is a high-voltage device, the hybrid component can operate similarly to a single high-voltage enhancement-mode transistor. The depletion-mode transistor may have a breakdown voltage and / or maximum operating voltage that is at least 2 times, at least 3 times, at least 5 times, at least 10 times, or at least 20 times the breakdown voltage and / or maximum operating voltage of the enhancement-mode transistor.

[0014] As used herein, the terms III-nitride or III-N material, layer, device, etc. refer to a material or device composed of a semiconductor composite material that follows the stoichiometric formula B w Al x In y Ga z N, where w + x + y + z is approximately 1, and 0 ≤ w ≤ 1, 0 ≤ x ≤ 1, 0 ≤ y ≤ 1, and 0 ≤ z ≤ 1. The III-N material, layer, or device can be formed or prepared by directly growing it on a suitable substrate (e.g., by metalorganic chemical vapor deposition), or by growing it on a suitable substrate, separating it from the original substrate, and bonding it to another substrate.

[0015] As used herein, when two or more contacts or other elements (such as conductive channels or components) are "electrically connected," it means that they are connected by a sufficiently conductive material to ensure that, under any bias conditions, the potentials of the respective contacts or elements are always the same (e.g., substantially the same).

[0016] As used herein, "blocking a voltage" refers to the ability of a transistor, device, or component to prevent a substantial current (e.g., a current greater than 0.001 times the operating current during normal conduction) from flowing through the transistor, device, or component when a voltage is applied to it. In other words, while the transistor, device, or component is blocking the voltage applied to it, the total current passing through the transistor, device, or component does not exceed 0.001 times the operating current during normal conduction. Devices with an off-state current greater than this value exhibit high losses and low efficiency and are typically not suitable for many applications (especially power switching applications).

[0017] As used herein, a "high voltage device" (e.g., a high voltage switching transistor, HEMT, bidirectional switch, or four quadrant switch (FQS)) is an electronic device optimized for high voltage applications. That is, when the device is off, it can block a high voltage (e.g., about 300V or more, about 600V or more, or about 1200V or more), and when the device is on, it has a sufficiently low on-resistance (R ON ) (e.g., the conduction loss experienced when a substantial current passes through the device is sufficiently low). A high voltage device can at least block a voltage equal to the high voltage supply or the maximum voltage in the circuit in which it is used. A high voltage device may be able to block 300V, 600V, 1200V, 1700V, 2500V, or other suitable blocking voltages required by the application. In other words, a high voltage device can block all voltages from 0V to V max provided that V max is the maximum voltage that can be supplied by the circuit or power supply, and V max may be, for example, 300V, 600V, 1200V, 1700V, 2500V, or other suitable blocking voltages required by the application. For a bidirectional switch or four quadrant switch, when the switch is off, the blocked voltage may be of any polarity less than a specific maximum value (±300V or ±600V, ±1200V, etc., ±V max ), and when the switch is on, the current may be in any direction.

[0018] In this specification, “III-N device” is a device having a conductive channel formed within a III-N material. A III-N device can be designed to operate as a transistor or a switch (where the state of the device is controlled by a gate terminal) or a two-terminal device (where there is no gate terminal and current is blocked in one direction and conduction in the other). A III-N device may also be a high-voltage device suitable for high-voltage applications. In such a high-voltage device, when the device is biased off (for example, when the gate voltage relative to the source is below the device threshold voltage), the device can at least support all source-drain voltages below the high voltage of the application in which the device is used (e.g., 100V, 300V, 600V, 1200V, 1700V, 2500V, or higher). When the high-voltage device is biased on (for example, when the gate voltage relative to the source or associated power terminal is greater than the device threshold voltage), the device can conduct substantial current at low on-voltages (i.e., low voltages between source and drain or between both power terminals). The maximum permissible voltage is the highest on-state voltage that can be maintained in the application in which the device is used.

[0019] In this specification, the terms “over,” “under,” “between,” and “on” refer to the relative position of one layer to another. Therefore, for example, a layer positioned above or below another layer may be in direct contact with that other layer, or one or more layers may be interposed between them. Furthermore, a layer positioned between two layers may be in direct contact with those two layers, or one or more layers may be interposed between them. In contrast, the first layer “on” the second layer is in contact with the second layer. Moreover, the relative positions of each layer are provided assuming that operations are performed on the substrate, without considering the absolute orientation of the substrate.

[0020] In typical power switching applications using high-voltage switching transistors, the transistor is in one of two states for most of the time. In the first state (commonly called the "on state"), the voltage of the gate electrode relative to the source electrode is higher than the transistor threshold voltage, and substantial current flows through the transistor. In this state, the source-drain voltage difference is typically low, usually a few volts or less (e.g., about 0.1 to 5 volts). In the second state (commonly called the "off state"), the voltage of the gate electrode relative to the source electrode is lower than the transistor threshold voltage, and substantial current does not flow through the transistor (except for off-state leakage current). In this second state, the source-drain voltage difference can vary arbitrarily from about 0V to the value of the circuit's high-voltage supply (in some cases 100V, 300V, 600V, 1200V, 1700V or higher, but can be lower than the transistor's breakdown voltage). In some applications, inductive elements in the circuit may cause the source-drain voltage to be even higher than the circuit's high-voltage supply. In addition, immediately after the gate is switched on or off, there is a short period of time during which the transistor is in a transition mode between the two states described above. When a transistor is in the off state, it is said to be “blocking the voltage” between its source and drain. In this specification, “blocking the voltage” means the ability of a transistor, device, or component to prevent substantial current (for example, a current greater than 0.001 times the average operating current during normal on-state conduction) from flowing through the transistor, device, or component when a voltage is applied to the transistor, device, or component. In other words, while a transistor, device, or component is blocking the voltage applied to it, the total current flowing through the transistor, device, or component will not be greater than 0.001 times the average operating current during normal on-state conduction.

[0021] The accompanying drawings and the following description reveal details of one or more disclosed implementations of the subject matter described herein. Additional features and variations may also be included in the implementations. Other features, embodiments, and advantages will be evident from the description, drawings, and claims. [Brief explanation of the drawing]

[0022] [Figure 1A] A schematic diagram of a half-bridge circuit. [Figure 1B] Schematic diagram of a three-phase bridge circuit. [Figure 2] A schematic diagram of a hybrid normally-off device arranged in a cascode configuration. [Figure 3A] Plan view of an electronic module featuring a half-bridge. [Figure 3B] A cross-sectional view along a portion of the electronic module in Figure 3A. [Figure 4A] Plan view of a low-voltage enhancement-mode transistor coupled to a high-voltage depletion-mode III-N transistor to form a cascode switch. [Figure 4B] A cross-sectional view along a portion of the cascode switch in Figure 4A. [Figure 5A] Plan view of an electronic module featuring a half-bridge. [Figure 5B] A cross-sectional view of a portion of the electronic module shown in Figure 5A. [Figure 6] Plan view of a low-voltage enhancement-mode transistor coupled to a high-voltage depletion-mode III-N transistor to form a cascode switch. [Figure 7A] Circuit diagram of the half-bridge operating mode. [Figure 7B] Circuit diagram of the half-bridge operating mode. [Figure 7C] Circuit diagram of the half-bridge operating mode. [Figure 7D] Circuit diagram of the half-bridge operating mode. [Figure 7E] Circuit diagram of the half-bridge operating mode. [Figure 8] Plan view of an electronic module featuring a half-bridge. [Figure 9] Plan view of an electronic module featuring a half-bridge in an SMPT type package. [Figure 10] Plan view of an electronic module featuring a half-bridge in an SMPT type package. [Figure 11] Plan view of an electronic module featuring a half-bridge in an SMPT type package. [Figure 12] Plan view of an electronic module featuring a half-bridge in an SMPT type package. [Figure 13A] Side view of an encapsulated SMPD-type package. [Figure 13B] Top view of an encapsulated SMPD-type package. [Figure 14] A plan view of an electronic module featuring two half-bridges configured in parallel. [Figure 15] Plan view of an electronic module featuring a three-phase bridge circuit. [Figure 16] Plan view of an electronic module featuring a half-bridge with integrated gate drivers. [Figure 17] Plan view of an electronic module featuring a half-bridge with integrated gate drivers.

[0023] In various drawings, the same reference numerals indicate the same elements. [Modes for carrying out the invention]

[0024] This specification describes an electronic module and its operating method suitable for maintaining low levels of EMI, thereby enabling high circuit stability and improved performance. The module design (combined with the design of the switches used within the module) can reduce inductance and other parasitic elements, which leads to the aforementioned performance improvements. The electronic module can also have a reduced size and be easier to assemble than conventional modules, thereby enabling lower manufacturing costs.

[0025] Figures 3A and 3B show a plan view and a cross-sectional view of the electronic module 300, respectively. Module 300 includes cascode switches 382 and 383 connected to the half-bridge configuration shown in Figure 1. Plan views and cross-sectional views of cascode switches 400 that can be used for switches 382 and 383 are shown in Figures 4A and 4B, respectively (other cascode configurations may be used instead of cascode switches 400).

[0026] Referring to Figures 4A and 4B, the cascode switch 400 includes a low-voltage E-mode transistor 422 directly attached to the source pad 434 of a high-voltage D-mode transistor 423, the drain pad 453 of the E-mode transistor 422 being directly bonded to the source electrode 434 of the D-mode transistor 423. The E-mode transistor 422 may be, for example, a silicon FET, and the D-mode transistor may be, for example, a III-N HEMT. The cascode switch 400 can operate in the same way as a single high-voltage E-mode III-N transistor and, in many cases, achieves the same or similar output characteristics as a single high-voltage E-mode III-N transistor. The D-mode transistor 423 has a greater breakdown voltage than the E-mode transistor 422 (for example, at least three times greater). The maximum voltage that can block while the cascode switch 400 is biased to the off state is at least the same magnitude as the maximum blocking voltage or breakdown voltage of the D-mode transistor 423.

[0027] The E-mode transistor 422 includes a semiconductor body layer 455. The transistor 422 further includes an FET source electrode 451 and an FET gate electrode 452 on the first side of the semiconductor body layer 455, and an FET drain electrode 453 on the second side of the semiconductor body layer 455 (opposite the FET source electrode 451).

[0028] The D-mode transistor 423 comprises a III-N material structure 418 (e.g., a combination of GaN and AlGaN) grown on a suitable substrate 411, which may be a conductive semiconductor (e.g., silicon (e.g., p-type or n-type Si), GaN (e.g., p-type or n-type GaN)), or any other sufficiently conductive substrate, or an insulating (e.g., sapphire) substrate, or a semi-insulating substrate (e.g., semi-insulating silicon carbide).

[0029] The III-N material structure 418 may include a III-N buffer layer 412 (e.g., GaN or AlGaN) grown on the substrate 411. The buffer layer 412 can be rendered to be insulating or substantially free of unintended n-type carriers. The buffer layer 412 may have a substantially uniform composition overall, or its composition may vary. The thickness and composition of the buffer layer 412 may be optimized for high-voltage applications. That is, the buffer layer can block voltages equal to the maximum voltage or high-voltage supply in the circuit in which it is used. For example, the buffer layer 412 may be able to block voltages greater than 600V or greater than 900V. The thickness of the buffer layer 412 can be greater than 2 μm. For example, the III-N buffer layer may have a thickness between 5 μm and 10 μm.

[0030] The III-N material structure may further include a III-N channel layer 413 (e.g., GaN) above the III-N buffer layer 412, and a III-N barrier layer 414 (e.g., AlGaN, AlInN, or AlGaInN) above the III-N channel layer 413. The band gap of the III-N barrier layer 414 is greater than the band gap of the III-N channel layer 413. The III-N channel layer 413 has a different composition from the III-N barrier layer 414, and the thickness and composition of the III-N barrier layer 414 are selected so that a two-dimensional electron gas (2DEG) channel 419 (shown by a dashed line in Figure 4B) is induced in the III-N channel layer 413 adjacent to the interface between layers 414 and 413.

[0031] Typically, III-N high electron-mobility transistors (HEMTs) are formed from epitaxial (i.e., epi) III-N material structures grown in a reactor by metal-organic chemical vapor deposition (MOCVD) or molecular beam epitaxy (MBE). As shown in Figure 4B, the III-N material structure may be grown in a Group III polar (e.g., Ga polar) orientation (e.g., [0 0 0 1] (C-plane) orientation). Alternatively, III-N HEMTs may be formed on a III-N material structure grown in an N polar (i.e., N-plane) orientation (e.g., [0 0 0 -1] orientation (not shown)). In N-polar devices, the III-N barrier layer may be above the III-N buffer layer, and the III-N channel layer may be above the III-N barrier layer. N-polar III-N materials have a polarization field in the opposite direction to that of Group III polar III-N materials and therefore enable the implementation of III-N device structures that cannot be formed using Group III polar structures.

[0032] An insulating layer 415 (e.g., a dielectric layer) is grown or deposited on top of the upper surface of the III-N material structure 418. The insulating layer 415 is made of, for example, aluminum oxide (Al2O3), silicon dioxide (SiO2), Si x N y , Al 1-x Si x N, Al 1-x Si x O, Al1-x Si x It may be formed from or include ON or any other wide-bandgap insulator. Although the insulator 115 is illustrated as a single layer, it may alternatively be formed from several layers and / or materials deposited between various processing steps to form a single composite insulating layer.

[0033] The source electrode 434 and drain electrode 436 are formed on the side opposite the substrate of the D-mode transistor 423, so that the device 423 is characterized as a lateral III-N device (i.e., the source and drain are on the same side of the device, and current flows laterally through the device between the source 434 and the drain 436). The source electrode 434 and drain electrode 436 make ohmic contact and are electrically connected to the device 2DEG channel 419 formed within layer 413. The source and drain electrodes 434,436 may each be formed from a stack of multiple metal layers. Each metal stack may be, for example, Ti / Al / Ni / Au, Ti / Al, or a stack of other suitable metal layers.

[0034] The D-mode transistor 423 further includes a gate electrode 435. The gate electrode 435 can be formed such that an insulating layer 415 extends between the gate electrode 435 and the III-N material structure 418 to separate them, as shown in Figure 4B. Alternatively, the gate electrode 435 may be formed to contact the III-N material structure 418 (not shown). The gate electrode 435 may be formed from a suitable conductive material such as a metal stack (e.g., titanium / aluminum (Ti / Al) or nickel / gold (Ni / Au)). Alternatively, the gate electrode 435 may be another conductive material or material stack containing one or more materials with a large work function, such as a semiconductor material with a large work function (e.g., p-type polysilicon, indium tin oxide, tungsten nitride, indium nitride, or titanium nitride).

[0035] The low-voltage E-mode device 422 is electrically connected to the high-voltage D-mode III-N device 423 to form a cascode switch 400. This may be a hybrid III-N device. Here, the drain electrode 453 of the E-mode transistor 422 is electrically connected by direct contact (e.g., mounting) with the source electrode 434 of the III-N transistor 423. The drain electrode 453 of the E-mode transistor 422 may also be connected to the source electrode 434 of the D-mode transistor 423 (e.g., by solder, solder paste, conductive epoxy, conductive tape, or other suitable mounting method that allows for high-quality mechanical, thermal, and electrical connections between the FET drain electrode 453 and the source electrode 434 of the D-mode transistor). The E-mode transistor 422 may be mounted above the 2DEG channel 419 as shown in Figure 4B, or the device 422 may be mounted in a region outside the active region of the device, partially or entirely, so that the FET 422 does not come above the 2DEG channel layer. The gate node of the cascode switch 400 may be connected to the gate electrode 452 of the E-mode device 422. Conventional cascode switches typically pack the D-mode and E-mode transistors side-by-side on a ceramic insulating substrate (such as an AlN shim), requiring an external wire connector to make the FET drain-to-HEMT source connection necessary for the cascode configuration. However, as shown in Figures 4A and 4B, mounting the E-mode device 422 directly on the D-mode device 423 eliminates the need for an external wire connector and ceramic substrate. This dramatically reduces the parasitic inductance of the circuit, enabling higher current ratings and faster switching speeds.

[0036] The gate electrode 435 of the D-mode transistor 423, although not shown in Figure 4A or 4B, should be connected to the source electrode 451 of the E-mode transistor 422 (necessary for the cascode switch to function properly), and these two electrodes are indeed electrically connected when the cascode switch 400 is mounted on module 300 in Figures 3A and 3B (because these electrodes are bonded to a common metal layer). This is evident from Figures 3A and 3B and will be explained in more detail below.

[0037] Returning to Figures 3A and 3B, the module 300 includes a directly bonded copper (DBC) substrate 310 (best shown in Figure 3B) which can serve as the base substrate of the module. The DBC substrate is formed by direct bonding of pure copper to a ceramic insulator (such as AlN or Al2O3) in a high-temperature melt diffusion process. The DBC substrate 310 includes an insulating (e.g., ceramic or AlN) substrate 315 on which an upper metal layer (e.g., copper or nickel) is patterned into at least a first portion 311 that functions as a high-voltage plate, a second portion 312 that functions as an output plate, and a third portion 313 that functions as a ground plate. Each portion 311, 312, and 313 is electrically insulated from one another by grooves 314 formed through the metal layer. As shown in Figure 3B, the DBC substrate may include a back metal layer 316 (e.g., copper or nickel) on the opposite side of the insulating substrate 315 from the upper metal layer (311 / 312 / 313). Optionally, the ground plate 313 may be electrically connected to the back metal layer 316 by forming metal via holes 317 through the insulating substrate 315. The high-position switch 382 and the low-position switch 383 are cascode switches as shown in Figures 4A and 4B, respectively. The high-position switch 382 is mounted directly on the output plate 312, and the low-position switch 383 is mounted directly on the ground plate 313.

[0038] For the high-side switch 382, ​​the drain electrode 436 of the D-mode transistor is electrically connected to the high-voltage plate 311 via connector 341, and the gate electrode 435 of the D-mode transistor and the source electrode 451 of the E-mode transistor are electrically connected to the output plate 312 via wire connectors 340 and 342, respectively. For the low-side switch 383, the drain electrode 436' of the D-mode transistor is electrically connected to the output plate 312 via connector 343, and the gate electrode 435' of the D-mode transistor and the source electrode 451' of the E-mode transistor are electrically connected to the ground plate 313 via wire connectors 346 and 348, respectively.

[0039] Optionally, the electronic module 300 includes a package containing electronic components, the package including a first input lead 372, a second input lead 373, a high-voltage lead 391, a ground lead 383, and an output lead 392. The first input lead 372 is connected to the gate electrode 452 of the E-mode transistor of the high-side switch 382, ​​the second input lead 373 is connected to the gate electrode 452' of the E-mode transistor of the low-side switch 383, the high-voltage lead 391 is connected to the high-voltage plate 311, the ground lead 393 is connected to the ground plate 313, and the output lead 392 is connected to the output plate 312.

[0040] To ensure proper operation of the half-bridge circuit formed by the electronic module 300 in Figures 3A and 3B, the high-voltage node 391 should be maintained on AC ground. That is, node 391 can be capacitively coupled to the DC ground node 393 by connecting the first terminal of capacitor 375 to the high-voltage plate 311 and the second terminal of capacitor 375 to the ground plate 393. As shown in Figure 3A, capacitor 375 can be directly positioned above a portion of via 314. When either switch 382 or 383 is switched on or off, capacitor 375 can be charged and discharged as needed to provide the current necessary to maintain substantially constant voltages on the high and low sides of the circuit. Furthermore, capacitor 375 may be a hybrid capacitor including capacitive and resistive components. For example, capacitor 375 may be configured as a series-connected capacitor and resistor. Due to the large di / dt required for high-current operation, ringing and voltage spikes may occur during the turn-off of the high-side switch or the low-side switch. Typically, ringing frequencies are observable within the range of 100 mHz. This ringing is effectively attenuated by a series-connected resistor and capacitor rather than a simple decoupling capacitor. For operating currents around 30 A, capacitance values ​​can range from 0.01 nF to 100 nF, and resistance values ​​can range from 0.1 ohms to 100 ohms. Designers may choose higher resistance and capacitance values ​​to bias towards conditions with weaker attenuation.

[0041] Figures 5A and 5B show plan and cross-sectional views of another electronic module 500, which offers improved performance and reliability and reduced complexity compared to module 300. Module 500 utilizes cascode switches 600, shown in Figure 6, for its high-position and / or low-position switches (582 and 583), respectively. As will be described in more detail below, the design of the cascode switches 600 used for switches 582 and 583 allows for the omission of certain external connectors in module 500, resulting in both reduced complexity and improved performance and reliability for module 500.

[0042] As shown in Figure 6, the cascode switch 600 used in module 500 is similar to the cascode switch 400 used in module 300, but with added new features. First, the substrate 611 on which the III-N material structure 618 is formed is a conductive substrate (for example, formed from p-type silicon, n-type silicon, p-type GaN, n-type GaN, or n-type SiC), and the substrate is electrically connected (i.e., short-circuited) to the upper metal layer of module 500 to which the substrate is attached.

[0043] In addition, the gate electrode 635 of the high-voltage D-mode transistor 623 is electrically connected to the conductive substrate 611 by a via hole 638 (e.g., a through-epivia or TEV) formed through a portion of the III-N material structure 618. The via hole 638 can be formed through the entire thickness of the III-N material structure 618 and extend all the way to the substrate 611, as shown by the dashed region 638 in Figure 6. The metal of the gate electrode 635 is formed at least partially within the via hole 638 and makes ohmic contact with the conductive substrate 611, thereby electrically connecting the gate electrode 635 of the III-N transistor 623 to the conductive substrate 611. The dashed region in Figure 6 shows a via hole 638 passing through a 2DEG channel 619, but the via hole 638 is formed in such a way that the 2DEG channel 619 is continuous with the source and drain electrodes 634 and 636 of the D-mode device (for example, the via hole may be formed within a portion of the III-N material that is outside the active region of the III-N transistor).

[0044] Finally, a back metal layer 617 (e.g., Ti / Ni / Ag) may optionally be formed on the back side of the conductive substrate 611, opposite to the III-N material structure 618. The back metal layer 617 may be used as an adhesive layer to allow the substrate 611 to be attached to the underlying metal plate in the module 500 by solder, solder paste, conductive epoxy, conductive tape, or other suitable mounting method that enables high-quality mechanical, thermal, and electrical connections to the metal layer of the device substrate 611.

[0045] Returning to Figures 5A and 5B, in order to form the half-bridge module 500, a first cascode switch (switch 600, etc.) is directly attached to the output plate 512 to form the high-side switch 582, and a second cascode switch (switch 600, etc.) is directly attached to the ground plate 513 to form the low-side switch 583. For the high-side switch 582, the gate electrode 635 of the D-mode transistor is electrically connected to the conductive substrate 611 by a via hole 638, and the conductive substrate is directly attached to the output plate 512, so the gate electrode 635 is electrically attached to the output plate 512 without the need for an external connector (connector 340, etc. in Figures 3A and 3B). Similarly, for the low-side switch 583, the gate electrode 635' of the D-mode transistor is electrically connected to the conductive substrate by a via hole, and the conductive substrate is directly attached to the ground plate 513, so the gate electrode 635' is electrically attached to the ground plate 513 without the need for an external connector (connector 346, etc. in Figures 3A and 3B). As a result, the assembly of Module 500 is simplified, circuit inductance is reduced, and switching noise and EMI are lowered.

[0046] For completeness, other aspects and features of module 500 and the cascode switch 600 used in module 500 are as follows. Referring to Figure 6, the cascode switch 600 includes a low-voltage E-mode transistor 622 mounted directly on the source pad 634 of a high-voltage D-mode transistor 623, the drain pad 653 of the E-mode transistor 622 being directly bonded to the source electrode 634 of the D-mode transistor 623. The E-mode transistor 622 is, for example, a silicon FET, and the D-mode transistor is, for example, a III-N HEMT. The cascode switch 600 can operate similarly to a single high-voltage E-mode III-N transistor and, in many cases, achieves the same or similar output characteristics as a single high-voltage E-mode III-N transistor. The D-mode transistor 623 has a greater breakdown voltage than the E-mode transistor 622 (for example, at least three times greater). The maximum voltage that can be blocked while the cascode switch 600 is biased to the off state can be at least as large as the maximum blocking voltage or breakdown voltage of the D-mode transistor 623.

[0047] The E-mode transistor 622 includes a semiconductor body layer 655. The transistor 622 further includes an FET source electrode 651 and an FET gate electrode 652 on the first side of the semiconductor body layer 655, and an FET drain electrode 653 on the second side of the semiconductor body layer 655 (opposite the FET source electrode 651).

[0048] The D-mode transistor 623 includes a III-N material structure 618 (e.g., a combination of GaN and AlGaN) grown on a conductive substrate 611, which may be, for example, silicon (e.g., p-type or n-type Si), GaN (e.g., p-type or n-type GaN), n-type SiC, or any other sufficiently conductive substrate.

[0049] The III-N material structure 618 may include a III-N buffer layer 612 (e.g., GaN or AlGaN) grown on the substrate 611. The buffer layer 612 can be rendered to be insulating or substantially free of unintended n-type carriers. The buffer layer 612 may have a substantially uniform composition overall, or its composition may vary. The thickness and composition of the buffer layer 612 may be optimized for high-voltage applications. That is, the buffer layer can block voltages equal to the maximum voltage or high-voltage supply in the circuit in which it is used. For example, the buffer layer 612 may be able to block voltages greater than 600V or greater than 900V. The thickness of the buffer layer 612 can be greater than 2 μm. For example, the III-N buffer layer may have a thickness between 5 μm and 10 μm.

[0050] The III-N material structure may further include a III-N channel layer 613 (e.g., GaN) above the III-N buffer layer 612, and a III-N barrier layer 614 (e.g., AlGaN, AlInN, or AlGaInN) above the III-N channel layer 613. The band gap of the III-N barrier layer 614 is greater than the band gap of the III-N channel layer 613. The III-N channel layer 613 has a different composition from the III-N barrier layer 614, and the thickness and composition of the III-N barrier layer 614 are selected so that a two-dimensional electron gas (2DEG) channel 619 (shown by a dashed line in Figure 6) is induced in the III-N channel layer 613 adjacent to the interface between layers 614 and 613.

[0051] Typically, III-N high electron mobility transistors (HEMTs) are formed from epitaxial (i.e., epi) III-N material structures grown in a reactor by metal-organic chemical vapor deposition (MOCVD) or molecular beam epitaxy (MBE). As shown in the device in Figure 6, the III-N material structure may be grown in a Group III polar (e.g., Ga polar) orientation (e.g., [0 0 0 1] (C-plane) orientation). Alternatively, III-N HEMTs may be formed on a III-N material structure grown in an N polar (i.e., N-plane) orientation (e.g., [0 0 0 -1] orientation (not shown)). In N-polar devices, the III-N barrier layer may be above the III-N buffer layer, and the III-N channel layer may be above the III-N barrier layer. N-polar III-N materials have a polarization field in the opposite direction to that of Group III polar III-N materials and therefore enable the implementation of III-N device structures that cannot be formed using Group III polar structures.

[0052] An insulating layer 615 (e.g., a dielectric layer) is grown or deposited on top of the upper surface of the III-N material structure 618. The insulating layer 615 is made of, for example, aluminum oxide (Al2O3), silicon dioxide (SiO2), Si x N y , Al 1-x Si x N, Al 1-x Si x O, Al 1-x Si x It may be formed from or include ON or any other wide-bandgap insulator. Although the insulating layer 115 is illustrated as a single layer, it may alternatively be formed from several layers and / or materials deposited between various processing steps to form a single composite insulating layer. The insulating layer 18 may be entirely constant or formed from insulating materials of varying types.

[0053] The source electrode 634 and drain electrode 636 are formed on the side of the D-mode transistor 623 opposite the substrate, so that the device 623 is characterized as a lateral III-N device (i.e., the source and drain are on the same side of the device, and current flows laterally through the device between the source 634 and the drain 636). The source and drain electrodes 634 and 636 may each be formed from a stack of multiple metal layers. Each metal stack may be, for example, Ti / Al / Ni / Au, Ti / Al, or a stack of other suitable metal layers.

[0054] The D-mode transistor 623 further includes a gate electrode 635. As shown in Figure 6, the gate electrode 635 may be formed such that an insulating layer 615 is at least partially between the gate electrode and the III-N material structure 618. The gate electrode 435 may be formed from a suitable conductive material such as a metal stack (e.g., titanium / aluminum (Ti / Al) or nickel / gold (Ni / Au)).

[0055] The low-voltage E-mode device 622 is electrically connected to the high-voltage D-mode III-N device 623 to form a cascode switch 600. Here, the drain electrode 653 of the E-mode transistor 622 is electrically connected by direct contact (e.g., mounting) with the source electrode 634 of the III-N transistor 623. The drain electrode 653 of the E-mode transistor 622 may also be connected to the source electrode 634 of the D-mode transistor 623 (e.g., by solder, solder paste, conductive epoxy, conductive tape, or other suitable mounting method that allows for high-quality mechanical, thermal, and electrical connections between the FET drain electrode 653 and the source electrode 634 of the D-mode transistor). The E-mode transistor 622 may be mounted above the 2DEG channel 619 as shown in Figure 6, or the device 622 may be mounted in a region outside the active region of the device, partially or entirely, so that the FET 622 does not come above the 2DEG channel layer.

[0056] Returning to Figures 5A and 5B, the module 500 includes a directly bonded copper (DBC) substrate 510 (best shown in Figure 5B) which can serve as the base substrate of the module. The DBC substrate 510 includes an insulating (e.g., ceramic) substrate 515 on which an upper metal layer (e.g., copper) is patterned into at least a first portion 511 that functions as a high-voltage plate, a second portion 512 that functions as an output plate, and a third portion 513 that functions as a ground plate. Each portion 511, 512, and 513 is electrically insulated from one another by grooves 514 formed through the upper metal layer. The DBC substrate 510 may optionally include a back metal layer 516 on the opposite side of the insulating substrate 515 from the upper metal layers (511 / 512 / 513). Optionally, the ground plate 513 may be electrically connected to the back metal layer 516 by forming metal via holes 517 through the insulating substrate 515. The high-position switch 582 and the low-position switch 583 are cascode switches, as shown in Figure 6. The high-position switch 582 is mounted directly on the output plate 512, and the low-position switch 583 is mounted directly on the ground plate 513.

[0057] For the high-side switch 582, the drain electrode 636 of the D-mode transistor is electrically connected to the high-voltage plate 511 via connector 541, and the source electrode 651 of the E-mode transistor is electrically connected to the output plate 512 via wire connector 542. For the low-side switch 583, the drain electrode 636' of the D-mode transistor is electrically connected to the output plate 512 via connector 543, and the source electrode 651' of the E-mode transistor is electrically connected to the ground plate 513 via wire connector 544. Connectors 541-544 may comprise a single wire bond (illustrated), multiple parallel wire bonds, ribbons, conductive metal clips, or other connectors comprising a conductive material (e.g., aluminum (Al), gold (Au), copper (Cu), or other suitable material).

[0058] Optionally, the electronic module 500 includes a package containing electronic components, the package including a first input lead 572, a second input lead 573, a high-voltage lead 591, a ground lead 593, and an output lead 592. The first input lead 572 is connected to the gate electrode 652 of the E-mode transistor of the high-side switch 582, the second input lead 573 is connected to the gate electrode 652' of the E-mode transistor of the low-side switch 583, the high-voltage lead 591 is connected to the high-voltage plate 511, the ground lead 593 is connected to the ground plate 513, and the output lead 592 is connected to the output plate 512.

[0059] To ensure proper operation of the half-bridge circuit formed by the electronic module 500 in Figures 5A and 5B, the high-voltage node 591 should be maintained to AC ground. That is, node 591 can be capacitively coupled to the DC ground node 593 by connecting the first terminal of capacitor 575 to the high-voltage plate 511 and the second terminal of capacitor 575 to the ground plate 593. As shown in Figure 5A, capacitor 575 can be directly positioned above a portion of via 514. When either switch 582 or 583 is switched on or off, capacitor 575 can be charged and discharged as needed to provide the current necessary to maintain substantially constant voltages on the high and low sides of the circuit. Furthermore, capacitor 575 may be a hybrid capacitor including capacitive and resistive components. For example, capacitor 575 may be configured as a single component including a series-connected capacitor and resistor. Due to the large di / dt required for high-current operation, ringing and voltage spikes may occur during the turn-off of the high-side or low-side switch. Typically, ringing frequencies are observable within the range of 100 mHz. This ringing is effectively attenuated by a series-connected resistor and capacitor rather than a simple decoupling capacitor. For operating currents around 30 A, the capacitance value can be greater than 0.1 nF, for example, in the range of 0.1 nF to 100 nF, and the resistance value can be greater than 0.1 ohms, for example, in the range of 0.1 ohms to 100 ohms. Designers may choose higher resistance and capacitance values ​​to bias toward conditions with weaker attenuation.

[0060] Figures 7A, 7B, and 7C show three different modes for operating a half-bridge buck converter circuit similar to the half-bridge in Figure 1A. The half-bridge circuit includes a high-side switch 102 connected to a high-voltage node 111 and a low-side switch 103 connected to a ground node 113. An inductor 104 is connected to node 112 (between the low-side switch 103 and the high-side switch 102) and the output node V of the circuit.OUT It is connected between the two. The first capacitor 106 is connected between the high-voltage node 111 and the DC ground 113. The second capacitor 107 is connected between the output node V of the circuit. OUT It is connected between this and the DC ground 113. The low-side switch 103 and the high-side switch 102 are selected to have characteristics that improve the efficiency of the step-down converter circuit. Specifically, switches 102 and 103 have low on-resistance (R DS(ON) ) and should have low switching losses. Switches 102 and / or 103 may be formed in conjunction with, for example, the cascode switch 200 in Figure 2. Alternatively, switches 102 and / or 103 may be implemented as the cascode switch 600 in Figure 6 assembled within the half-bridge module 500 in Figure 5A.

[0061] The step-down converter half-bridges shown in Figures 7A-7C can operate as follows. Referring to Figure 7A, in the first operating mode, the gate of the high-side switch 102 is biased to ON (i.e., V GS 102>V TH ), the gate of the low-side switch 103 is biased to off (i.e., V GS 103 <V TH The current 97 flows forward from the high-voltage node 111 through the high-side switch 102 to node 112. This current is blocked by the low-side switch 103 and flows through the inductor 104 as indicated by the current path 97. While the device is operating in the first operating mode, the gate-source voltage of the high-side switch 102 is switched to low or off (i.e., V GS 102 <V TH ), when both gates of switches 102 and 103 are biased to the off position, the half-bridge switches to the second operating mode shown in Figure 7B. Current must continue to flow through inductor 104.

[0062] Figures 7D and 7E show the schematic circuit of a cascode switch (such as the cascode switch 200 in Figure 2), and also show the various parasitic inductances and capacitances inherent in the cascode configuration. Parasitic gate-drain capacitance (C) of D-mode III-N transistor 223. GD The ) is shown as capacitor 57. The built-in body diode of the E-mode FET 222 is shown by diode 237. The parasitic inductance of the source connection of the E-mode FET 222 is shown as inductor 54, and the parasitic inductance of the gate connection of the D-mode III-N transistor 223 is shown as inductor 53. When the circuits of Figures 7D and 7E are implemented as a low-side switch 383 in a half-bridge module (similar to module 300 in Figure 3A), inductor 54 represents the inductance of the wire (for example, wire 348 in Figure 3A) connecting the source 451' of the E-mode transistor to the ground plate 313. An external gate wire connector 346 is used to connect the gate electrode 435' of the D-mode transistor of switch 383 to the source electrode 451' of the E-mode transistor of switch 383, and to connect the gate electrode 435' of the D-mode transistor to the ground plate 313. As a result of this gate wire connector 346, a substantial inductance (represented by inductor 53 in Figure 7D) is created between the gate electrode 435 of the D-mode transistor and the ground plate 313. Parasitic inductances 53 and 54 can reduce the module's turn-on and turn-off times, increase switching losses, and thereby degrade the circuit's performance.

[0063] Figure 7D shows the detailed current path through the cascode configuration of the low-side switch 103 during the transition time T1 between the first and second operating modes shown in Figures 7A and 7B. During the transition time T1, the voltage at node 112 (shown in Figures 7A and 7B) drops to a negative value, and the current path I in Figure 7D ACAs shown, the displacement current flows through the parasitic gate-drain capacitor 57 of the D-mode III-N transistor 223. When the voltage at node 112 becomes sufficiently negative, the gate of the low-side switch 102 is biased to off (i.e., V GS <V TH ), the built-in body diode 237 of the E-mode FET transistor 222 switches on, and switch 103 changes from off to reverse conduction. This is called reverse conduction mode (i.e., freewheel diode mode). At the end of transition time T1, switch 103 transitions from off to reverse conduction, and the current changes from the displacement current through the gate-drain capacitor 57 of the D-mode transistor 223 (shown in Figure 7D) to the reverse DC current flowing through the built-in body diode 237 of the E-mode transistor 222 and the channel of the D-mode transistor 223 (current path I in Figure 7E). DC It transitions abruptly to (as shown by).

[0064] When the operating current through inductor 104 is high, current path transitions may cause voltage spikes and ringing across the gate of D-mode transistor 223. These voltage spikes inject charge into the gate dielectric of the D-mode transistor (e.g., insulating layer 415 or 615), reducing the channel-on resistance (R) of the D-mode transistor. ON This leads to an increase in the on-resistance of the cascode switch 383. Since the current in the inductor 104 must be continuous, reverse conduction of switch 103 occurs in the circuit of Figure 7B even when the gate of switch 103 is biased to off.

[0065] Returning to Figure 7C, as shown in Figure 7B, after the gate of the high-side 102 switches off, the low-side switch 103 switches on (i.e., V GS >V TH), the step-down converter is operated in the third operating mode, and the current 98 continues to flow through the low-side switch 103 in the same direction (reverse direction) as in the second mode, except that the low-side switch 103 is biased to ON. By biasing the low-side switch to ON during the third operating mode, the reverse voltage drop across the E-mode transistor 222 is reduced compared to the second operating mode, enabling higher efficiency compared to the second operating mode. To prevent the high-voltage node 111 from accidentally short-circuiting to the ground node 113, a sufficient dead time is used between the time the high-side switch 102 is turned OFF and the time the low-side switch 103 is turned ON.

[0066] The design of the cascode switch and associated modules can be a critical factor in determining the performance of the low-side switch 103 in reverse conduction mode. By implementing device 600 as the low-side device 103 within the half-bridge module 500, and thereby eliminating the need for an external gate wire connection (e.g., wire 346 in Figure 3A) between the D-mode transistor of switch 583 and the ground plate 513 within module 500 (since the gate of the D-mode transistor is connected to the ground plate 513 through via hole 638), the parasitic inductance within the half-bridge module (shown by inductor 53 in Figure 7D) is reduced. This reduces the voltage spikes and ringing experienced by the gate of the D-mode transistor of switch 583 during the current path transition between the first and second operating modes. Surprisingly, it was shown that the degradation (i.e., increase) of the switch's channel-on resistance is substantially reduced compared to conventional modules with external gate wires, even when operating with very high reverse DC currents. This result was unexpected. The contribution of gate wire inductance from the depletion-mode transistor to the module switching performance was considered negligible to the inventors because there is no DC current flowing through this path and the gate voltage of the depletion-mode transistor of the low-side switch is typically pinned to ground. This degradation in on-resistance is commonly referred to as current collapse or dispersion and is a major concern for the implementation of III-N devices in half-bridge circuits. When the cascode switch 600 is implemented as the low-side switch 583 in the half-bridge module 500, the switch 583 can operate with reverse DC currents greater than 50A (even 70A) between the second and third operating modes while showing little increase in on-resistance. For example, the increase in on-resistance may be less than 5% compared to the first operating mode. Conventional modules with external gate wire connections can typically show an increase in on-resistance of 30% or more even when operating with reverse DC currents of 30A or less. The low-side switch 583 can block voltages greater than 600V during the first operating mode.

[0067] In addition, the high-side switch 582 can operate in reverse conduction mode during certain switching procedures. Here, the gate connection between the D-mode III-N transistor of the cascode switch 582 and the output plate 512 is connected through via hole 638, further reducing the parasitic inductance of the electronic module. This further reduces the voltage spikes and ringing experienced by the cascode switch 582 during the current path transition when switching to reverse conduction mode.

[0068] Figure 8 is a top view of an integrated electronic module 800 that forms a half-bridge circuit similar to the integrated electronic half-bridge module 500 of Figure 5A, having an alternative DBC810 layout that allows for a more compact arrangement of the high-voltage plate 811, output plate 812, and ground plate 813 compared to module 500 of Figure 5A. This reduces the size and footprint of the electronic module and lowers the cost. Module 800 also includes a high-side source sensing node 896 and a low-side source sensing node 897. Although not shown in Figure 5A, module 500 may also include sensing nodes 896 and 897. The high-side source sensing node 896 is connected to the output plate 812, and the low-side source sensing node 897 is connected to the ground plate 813. The first input lead 872, the high-side source sensing node 896, the second input lead 873, and the low-side source sensing node 897 (collectively, the gate nodes) extend from the first side of module 800, and all gate nodes are configured to extend from the same side of the module and connect to an external gate driver. In some examples, the high-side gate nodes may be connected to a high-side gate driver, and the low-side gate nodes may be connected to a low-side gate driver. The high-voltage node 891, the ground node 893, and the output node 892 extend from the second side of module 800, opposite to the first side, with the high-voltage node 891 configured to connect to a circuit high-voltage supply, the ground node 893 configured to connect to a circuit ground, and the output node 892 configured to connect to an inductive element or circuit load. The high-position switch 882 is positioned with a 90° rotation compared to the low-position switch 883 of module 800, enabling a more compact arrangement of module components and shorter wire bond connections to DBC810. In particular, in the high-position switch 882, the source electrode 634 and drain electrode 634 are positioned along a first axis, while in the low-position switch 883, the source electrode 634' and drain electrode 634' are positioned along a second axis perpendicular to the first axis.

[0069] Figure 9 is a top view of an integrated electronic module 900 that forms a half-bridge circuit integrated into a surface-mount power device (i.e., SMPD) type package. The half-bridge circuit configured within the electronic module 900 is similar to module 500 in Figure 5A, but includes an additional metal routing layer on the DBC 910 and connector leads that house source-sensing pins and gate-connecting ferrite beads. The electronic module 900 includes a high-side switch 582 and a low-side switch 583, which may be identical to those of module 500 in Figure 5A. Module 900 includes a DBC 910 which includes a high-voltage plate 911, an output plate 912, and a ground plate 913, each plate separated by grooves 914 formed in the upper metal layer of the DBC 910. The DBC 910 can be constructed in a similar manner to the DBC 510 in Figures 5A and 5B, but an alternative upper metal layer configuration may result from the separation pattern from the grooves 914. The electronic module 900 further includes a high-voltage lead 991 connected to a high-voltage plate 911, an output lead 992 connected to an output plate 912, and a ground lead 993 connected to a ground plate 913. The electronic module 900 further includes a first input lead 961 (which may be multiple leads), a high-side source sensing lead 962, a second input lead 963 (which may be multiple leads), and a low-side source sensing lead 964. Module 900, like module 500 in Figure 5A, includes a hybrid capacitor 575 connected between the high-voltage plate 911 and the ground plate 913.

[0070] Figure 9 further includes an optional high-side ferrite bead 68 and an optional low-side ferrite bead 69. The high-side ferrite bead 68 includes a first terminal electrically coupled to a first input lead 961 and a second terminal electrically coupled to a first side of a high-side gate connector 65. The high-side gate connector 65 includes a second side connected to the gate electrode of the E-mode transistor of the cascode switch 582. The low-side ferrite bead 69 includes a first terminal electrically coupled to a second input lead 963 and a second terminal electrically coupled to a first side of a low-side gate connector 67. The low-side gate connector 67 includes a second side connected to the gate electrode of the E-mode transistor of the cascode switch 583. The electronic module 900 further includes a source detection connector 66 having a first side electrically connected to a high-side source detection node 962 and a second side electrically connected to an output plate 912. Connector 66 is used to bridge the ground plate 913 and ensure that the high-side source sensing node 962 is at the same potential as the source of the high-side switch 582. Connectors 65, 66, and 67 may also include other connectors comprising a single wire bond (illustrated), multiple parallel wire bonds, ribbons, conductive metal clips, or conductive material (e.g., aluminum (Al), gold (Au), copper (Cu), or other suitable material).

[0071] As shown in Figure 9, the high-position switch 582 is directly mounted to the output plate 912, and as a result, the gate of the D-mode III-N transistor of the cascode switch 582 is electrically connected directly to the output plate 912 via the substrate of the cascode switch 582 without the use of an external wire connector. Similarly, the low-position switch 583 is directly mounted to the ground plate 913, and as a result, the gate of the D-mode III-N transistor of the cascode switch 583 is electrically connected to the ground plate 912 via the substrate of the switch 583 without the use of an external wire connector. A hybrid capacitor 575 is connected to the input side of the module 900 between the first input lead 931 and the high-position switch 582. Integrating the cascode switches 582 and 583 into an SMPD-type package enables simplified and efficient integration of the half-bridge circuit into an industrial-standard power device package.

[0072] Figure 10 is a top view of the integrated electronic module 1000, which is similar to the electronic module 900 in Figure 9, but compared to the input side of the module shown in Figure 9, module 1000 connects a hybrid capacitor 1075 between the ground plate 1013 and the high-voltage plate 1011 on the output side of module 1000. Module 1000 includes a DBC 1010 which includes a high-voltage plate 1011, an output plate 1012, and a ground plate 1013, with each plate separated by grooves 1014 formed in the upper metal layer of the DBC 1010. The DBC 1010 can be constructed in a similar manner to the DBC 510 in Figures 5A and 5B, but the separation pattern from the grooves 1014 results in an alternative upper metal layer configuration. Here, both the high-side switch 582 and the source sensing lead 962 are directly connected to the first output plate 1012, and the connector 66 in Figure 6 is omitted. The connector 66' of module 1000 has a first side connected to output plate 1012 and a second side connected to output plate 1012'. Output node 992 is in direct contact with the second output plate 1012', thereby bringing output node 992 and the source of cascode switch 582 to the same potential.

[0073] Figure 11 is a top view of the integrated electronic module 1100, which is similar to the electronic module 1000 in Figure 10, but module 1100 includes a capacitor 1174 and a resistor 1175 as two separate components connected in series to connect to the high-voltage plate 1111 and the ground plate 1113 (unlike module 1000 which uses a single hybrid component 1075), thereby maintaining the high-voltage plate 1111 to the AC ground of DBC 1110. The use of two separate components allows for the selection of additional components used by the circuit designer to change the package performance. In addition, the relative order of the capacitor 1174 and the resistor 1175 is interchangeable.

[0074] Figure 12 is a top view of the integrated electronic module 1200, which is similar to the electronic module 1000 in Figure 10, but module 1200 is implemented using a source ferrite bead 1266 (having a first terminal electrically coupled to the source voltage of the high-side switch 582 and a second terminal electrically coupled to the output lead 992). The source ferrite bead 1266 can be implemented so that the ferrite bead bridges the high-voltage plate 1011, similar to the connector 66' in Figure 10. Implementing module 1200 with the source ferrite bead 1266 instead of the connector 66' helps to suppress voltage ringing and other noise at the output node, thereby further improving the operation of the half-bridge module.

[0075] Figures 13A and 13B show external renderings of fully encapsulated SMPD-type packages available for modules 900–1200, with side and top views, respectively. The encapsulated package contains mold compound 1311 (or other suitable material for hermetically sealing and electrically encapsulating the components of the integrated electronic module, such as plastic, epoxy, metal, or other suitable material).

[0076] While integrated electronic modules 900, 1000, 1100, and 1200 exhibit surface-mount power device (SMPD) package types, alternative module packages are also available, such as quad flat no-lead (QFN) or loss-free package (LFPAK), or other suitable module packages capable of appropriately accommodating the high-side 582 and low-side switch 583 to form a half-bridge circuit. Each component of modules 900-1200 can be arranged or configured in a manner that best suits the designer's and package type's needs.

[0077] Figure 14 is a top view of the integrated electronic module 1400, which is similar to the electronic module 500 in Figure 5A, but module 1400 is implemented using two high-voltage switches (582 and 582a) connected in parallel and two low-voltage switches (583 and 583a) connected in parallel. Connector 41a connects the high-voltage plate 11 to the drain electrodes 36a of each D-mode transistor of the high-voltage switch 582a. Connector 42a connects the source electrode 51a of the E-mode transistor of the high-voltage switch 582a to the output plate 12. Connector 43a connects the output plate 12 to the drain electrode 36a' of the D-mode transistor of the low-voltage switch 583a, and connector 44a connects the source electrode 51a' of the E-mode transistor of the low-voltage switch 583a to the ground plate 13. The first input lead 572 is connected to the gate electrodes of the E-mode transistors of the high-side switches 582 and 582a, respectively, and the second input lead 573 is connected to the gate electrodes of the E-mode transistors of the low-side switches 583 and 583a, respectively. Here, the substrates of the first high-side switch 582 and the second high-side switch 582a are both electrically connected by contacting the same portion of the upper metal layer of the DBC1410 that forms the output plate 12. Similarly, the substrates of the first low-side switch 583 and the second low-side switch 583a are both electrically connected by contacting the same portion of the upper metal layer of the DBC1410 that forms the ground plate 13. By mounting multiple switches connected in parallel to the same portion of the upper metal layer to form module 1400, the operating performance of the module is improved, and the overall rated power can be significantly increased.

[0078] During the operation of module 1400, when the first input lead 572 is switched on or off, both switches 582 and 582a are switched on or off simultaneously. Similarly, when the second input lead 573 is switched on or off, both switches 583 and 583a are switched on or off simultaneously. Typically, parallelizing a half-bridge circuit using multiple distributed components involves external routing wires that can cause circuit matching problems when switched at high speeds. Integrating these switching transistors into the same electronic module can mitigate switching mismatch problems and improve overall circuit performance. Figure 14 shows two high-side switches and two low-side switches, but for example, three or four high-side and low-side switches may be connected in parallel. Theoretically, there is no limit to the number of switches that can be parallelized in this way.

[0079] Returning to Figure 1B, a schematic diagram of the three-phase full-bridge circuit 120 is shown. The three half-bridges 122, 124, and 126 within the circuit 120 can each be implemented using integrated electronic modules (for example, electronic modules 300 to 1400 as described herein).

[0080] Figure 15 is a top view of an electronic module 1500 that includes an integrated three-phase full-bridge circuit (e.g., circuit 120 in Figure 1B) in a single package. The first phase half-bridge circuit includes a high-side switch 82 and a low-side switch 83. The second phase half-bridge circuit includes a high-side switch 82' and a low-side switch 83'. The third phase half-bridge circuit includes a high-side switch 82'' and a low-side switch 83''. All high-side and low-side switches can be implemented using the cascode switch 600 in Figure 6. Module 1500 includes a DBC layer 1510, the upper metal layer of DBC 1510 is patterned into at least five parts separated by grooves 1514 formed through the upper metal layer of DBC 1510. The first part functions as a high-voltage plate 14, which is configured to be connected to a DC high voltage via a high-voltage lead 91. The second part functions as an output plate 15, which is connected to the output node 92 of the first phase. The third section functions as output plate 16, which is connected to the second phase output node 92'. The fourth section functions as output plate 17, which is connected to the third phase output node 92''. The fifth section functions as ground plate 18, which is configured to be connected to DC ground via ground lead 93.

[0081] The substrates of the high-side switches 82, 82', and 82'' are electrically connected by contact with the output plates 15, 16, and 17, respectively. The substrates of the low-side switches 83, 83', and 83'' are electrically connected by contact with the ground plate 18, and all low-side switches are electrically connected by contact with the same metal part of the DBC1510. The substrates of the high-side switches 82, 82', and 82'' are electrically isolated from each other. The drain electrode 36 of the D-mode transistor node of high-side switch 82 is connected to the high-voltage plate 14 at connector 41, the drain electrode 36' of the D-mode transistor of high-side switch 82' is connected to the high-voltage plate 14 at connector 41', and the drain electrode 36'' of the D-mode transistor of high-side switch 82'' is connected to the high-voltage plate 14 at connector 41''. The source electrode 34 of the E-mode transistor node of the high-side switch 82 is connected to the output plate 15 via connector 42, the source electrode 34' of the E-mode transistor of the high-side switch 82' is connected to the output plate 16 via connector 42', and the source electrode 34'' of the E-mode transistor of the high-side switch 82'' is connected to the output plate 17 via connector 42''. The drain electrode 56 of the D-mode transistor of the low-side switch 83 is connected to the first-phase output plate 15 via connector 43, the drain electrode 56' of the D-mode transistor of the low-side switch 83' is connected to the second-phase output plate 16 via connector 43', and the drain electrode 56'' of the D-mode transistor of the low-side switch 83'' is connected to the third-phase output plate 17 via connector 43''. The source electrode 54 of the E-mode transistor node of the low-side switch 83 is connected to the ground plate 18 via connector 44, the source electrode 54' of the E-mode transistor of the low-side switch 83' is connected to the ground plate 18 via connector 44', and the source electrode 54'' of the E-mode transistor of the low-side switch 83'' is connected to the ground plate 18 via connector 44''.

[0082] The gate driver operates module 1500 using three independent gate signals to operate each high-side switch and three independent gate signals to operate each low-side switch. Each independent high-side gate signal from the gate driver can be connected to gate input nodes 94, 94', and 94'', and each low-side gate signal from the gate driver can be connected to gate input nodes 95, 95', and 95''. By integrating the three-phase full-bridge circuit 120 of Figure 1B into a single integrated electronic device module 1500, switching efficiency can be greatly improved while simultaneously reducing circuit complexity. Although not shown for simplicity, module 1500 may include an integrated gate driver placed in the same package as a component of module 1500. The gate driver can be configured in a manner similar to that described below with respect to Figure 16.

[0083] Figure 16 is a top view of an integrated electronic module 1600 that forms a half-bridge circuit similar to the integrated electronic half-bridge module 500 of Figure 5A. However, module 1600 also includes a gate driver 1620 integrated within the same module package as the high-side switch 582 and the low-side switch 583. Components with similar numbering have the same or similar characteristics as those in module 500. Module 1600 includes a DBC 1610. The DBC 1610 includes a high-voltage plate 511, an output plate 512 and a ground plate 513, and optionally a driver plate 515, all separated by grooves 516. The gate driver 1620 may be mounted on the driver plate 515, or alternatively, the gate driver 1620 may be mounted directly to the module's constituent package base (e.g., a copper or Ni lead frame (not shown)). The driver plate 515 may be configured in multiple parts to accommodate and mount multiple leads extending from or connected to the gate driver 1620. The gate driver 1620 has at least a first terminal 1622 (V) connected to the gate electrode 652 of the E-mode transistor of the high-side switch 582. INThe gate driver 1620 includes a second terminal 1623, which is a high-side source current sensing node, connected to the output plate 512, or optionally, directly connected to the source electrode 651 of the E-mode transistor of the high-side switch 582 (not shown). The gate driver 1620 also includes a third terminal 1624 (V) connected to the gate electrode 652' of the E-mode transistor of the low-side switch 583. IN The gate driver 1620 includes a fourth terminal 1626, which is a low-side source current sensing node, connected to the ground plate 513, or optionally, directly connected to the source electrode 651' of the E-mode transistor of the high-side switch 583 (not shown). Integrating the gate driver 1620 into module 1600 increases cost and complexity compared to module 500, but the overall performance of module 1600 may be better than module 500 operating with an external gate driver. In addition, the overall size of the electronic circuit components into which module 1600 can be incorporated can be reduced, resulting in cost savings and other benefits. Although not shown, the gate driver 1620 may also consist of two separate gate drivers, where the first gate driver is connected to the high-side switch and the second gate driver is connected to the low-side switch.

[0084] Figure 17 is a top view of an integrated electronic module 1700 that forms a half-bridge circuit similar to the integrated electronic half-bridge module 1600 of Figure 16. However, module 1700 includes a gate driver 1720 in which the E-mode transistors of the high-side switch 582 and the E-mode transistors of the low-side switch 583 are integrated within the gate driver 1720. The high-side D-mode III-N transistor 1782 is mounted on the output plate 512, and the low-side D-mode III-N transistor 1783 is mounted on the ground plate 513. The gate driver 1720 includes at least a first terminal 1721 that connects the source of the integrated E-mode transistor of the high-side switch to the output plate 512. This connection couples the source of the E-mode transistor to the output terminal 592 and to the conductive substrate of the high-side D-mode III-N transistor 1782. The gate driver 1722 includes a second terminal 1722 that connects the drain of the integrated E-mode transistor of the high-side switch to the source electrode 634 of the high-side D-mode III-N transistor 1782. The gate driver 1720 includes a third terminal 1724 that connects the source of the integrated E-mode transistor of the low-side switch to the ground plate 513. This connection couples the source of the E-mode transistor to the ground terminal 593 and the conductive substrate of the low-side D-mode III-N transistor 1783. The gate driver 1722 also includes a fourth terminal 1725 that connects the drain of the integrated E-mode transistor of the low-side switch to the source electrode 634' of the low-side D-mode III-N transistor 1783. By integrating the E-mode transistors of the high-side and low-side switches into the gate driver 1720, the complexity of module 1700 can be reduced compared to module 1600, and the overall assembly cost can be reduced. Although not shown in the diagram, the gate driver 1720 may alternatively consist of two separate gate drivers, the first of which is connected to the high-position switch and the second of which is connected to the low-position switch.

[0085] Several embodiments have been described. However, it will be understood that various modifications can be made without departing from the spirit and scope of the technology and devices described herein. Therefore, other implementations are also within the scope of the appended claims.

Claims

1. It is an electronic module, A package and a conductive lead frame, wherein the conductive lead frame comprises a first portion configured to be connected to a high-voltage node, a second portion configured to be connected to an output node, and a third portion configured to be connected to a ground node, and each of the first, second, and third portions is electrically insulated from one another; A high-side switch comprising a cascode-configured enhancement-mode transistor and a III-N depletion-mode transistor, wherein the III-N depletion-mode transistor has a III-N material structure on a conductive substrate; Low-side switch; Equipped with, The drain electrode of the III-N depletion mode transistor is electrically connected to the first portion of the lead frame, the source electrode of the enhancement mode transistor is electrically connected to the second portion of the lead frame, the gate electrode of the III-N depletion mode transistor is electrically connected to the conductive substrate of the III-N depletion mode transistor, and the substrate of the III-N depletion mode transistor is electrically connected to the second portion of the lead frame. Electronic module.

2. The low-side switch comprises a second enhancement mode transistor and a second III-N depletion mode transistor, and the second III-N depletion mode transistor comprises a second III-N material structure on a second conductive substrate. The drain electrode of the second III-N depletion mode transistor is electrically connected to the second portion of the lead frame, the source electrode of the second enhancement mode transistor is connected to the third portion of the lead frame, the gate electrode of the second III-N depletion mode transistor is electrically connected to the second conductive substrate, and the second conductive substrate is electrically connected to the third portion of the lead frame. The electronic module according to claim 1.

3. The electronic module according to claim 2, wherein the high-side switch and the low-side switch form a half-bridge circuit.

4. The electronic module according to claim 3, wherein the III-N depletion mode transistor is configured to interrupt at least 600V while the high-side switch is biased to the off position and to conduct a current greater than 30A while the high-side switch is biased to the on position.

5. The electronic module according to claim 3, further comprising a capacitor, wherein a first terminal of the capacitor is electrically connected to the first portion of the lead frame, and a second terminal of the capacitor is electrically connected to the third portion of the lead frame.

6. The electronic module according to claim 1, further comprising a second high-side switch and a second low-side switch, wherein the high-side switch and the second high-side switch are electrically connected in parallel, and the low-side switch and the second low-side switch are electrically connected in parallel.

7. The electronic module according to claim 5, characterized in that the capacitor is a hybrid capacitor comprising a resistive element and a capacitive element in series.

8. The gate, source, and drain electrodes of the III-N depletion mode transistor are located on the opposite side of the conductive substrate of the III-N material structure, The aforementioned III-N material structure includes via holes formed therein, The metal layer forming the gate electrode is electrically connected to the conductive substrate via the via hole. The electronic module according to claim 1.

9. The electronic module according to claim 2, further comprising a gate driver housed in the package, wherein a first terminal of the gate driver is connected to the gate electrode of the enhancement mode transistor, and a second terminal of the gate driver is connected to the gate electrode of the second enhancement mode transistor.

10. The electronic module according to claim 9, wherein the enhancement mode transistor or the second enhancement mode transistor is internally integrated within the gate driver.

11. It is a half-bridge circuit, It comprises a high-side switch and a low-side switch, each housed within a single electronic package, the package comprising a high-voltage terminal, an output terminal, and a ground terminal. The high-side switch comprises a first enhancement-mode transistor and a first depletion-mode III-N transistor arranged in a cascode configuration. The low-side switch comprises a second enhancement-mode transistor and a second depletion-mode III-N transistor arranged in a cascode configuration. The first drain electrode of the first depletion mode III-N transistor is electrically connected to the high-voltage terminal, the first gate electrode of the first depletion mode III-N transistor is electrically connected to the output terminal, the second drain electrode of the second depletion mode III-N transistor is electrically connected to the output terminal, and the second gate electrode of the second depletion mode III-N transistor is electrically connected to the ground terminal. Half-bridge circuit.

12. The circuit according to claim 11, wherein the first gate electrode of the first depletion mode III-N transistor is electrically connected to the substrate of the first depletion mode III-N transistor, and the substrate of the first depletion mode III-N transistor is electrically connected to the output terminal.

13. The circuit according to claim 12, wherein the second gate electrode of the second depletion mode III-N transistor is electrically connected to the substrate of the second depletion mode III-N transistor, and the substrate of the second depletion mode III-N transistor is electrically connected to the ground terminal.

14. The circuit according to claim 13, wherein the half-bridge circuit further comprises a capacitor having a first terminal and a second terminal, the first terminal of the capacitor being connected to the high-voltage terminal and the second terminal being connected to the ground terminal.

15. The circuit according to claim 14, wherein the half-bridge circuit further comprises a gate driver housed in the package, the first terminal of the gate driver being connected to the gate electrode of the first enhancement mode transistor, and the second terminal of the gate driver being connected to the gate electrode of the second enhancement mode transistor.

16. The circuit according to claim 15, wherein the first enhancement mode transistor and the second enhancement mode transistor are integrated within the gate driver.

17. The circuit according to claim 14, wherein the half-bridge circuit further comprises a second high-side switch and a second low-side switch, the high-side switch and the second high-side switch are electrically connected in parallel, and the low-side switch and the second low-side switch are electrically connected in parallel.

18. The circuit according to claim 11, wherein the circuit includes η high-side switches connected in parallel and η low-side switches connected in parallel.

19. It is an electronic module, First, second, and third high-side switches; First, second, and third low-side switches; A single common electronic package housing the first, second, and third high-side switches, and the first, second, and third low-side switches, comprising a first metal layer electrically connected to a high-voltage terminal and a second metal layer electrically connected to a ground terminal; Equipped with, Each of the first, second, and third low-side switches comprises an enhancement-mode transistor and a depletion-mode III-N transistor arranged in a cascode configuration, each depletion-mode III-N transistor comprises a III-N material structure formed on its respective conductive substrate, each conductive substrate of the first, second, and third low-side switches is electrically connected to the second metal layer of the electronic package, and each gate electrode of each depletion-mode III-N transistor is electrically connected to its respective conductive substrate. The first, second, and third high-side switches and the first, second, and third low-side switches form a three-phase bridge circuit. Electronic module.

20. The electronic module according to claim 19, wherein the package further comprises third, fourth, and fifth metal layers, the substrate of the first high-side switch is connected to the third metal layer, the substrate of the second high-side switch is connected to the fourth metal layer, the substrate of the third high-side switch is connected to the fifth metal layer, and the first, second, third, fourth, and fifth metal layers are all electrically insulated from one another.

21. The electronic module according to claim 20, further comprising a first output terminal, a second output terminal, and a third output terminal, wherein the first output terminal is electrically connected to the third metal layer, the second output terminal is electrically connected to the fourth metal layer, and the third output terminal is electrically connected to the fifth metal layer.

22. The electronic module according to claim 21, wherein in the first low-side switch, the gate electrode of the III-N depletion mode transistor is on the opposite side of the III-N material structure from the conductive substrate, the III-N material structure includes via holes formed therein, and the metal layer forming the gate electrode is electrically connected to the conductive substrate via the via holes.

23. The electronic module according to claim 19, further comprising a capacitor, wherein a first terminal of the capacitor is electrically connected to the first metal layer, and a second terminal of the capacitor is electrically connected to the second metal layer.

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