Integration of display drivers and spread spectral image transport

Abstract

The video display includes a display panel having gate drivers and source drivers, each of the source drivers arranged to receive a discrete-time continuous amplitude signal representing a video stream on a transmission medium, and to decode the signal using demodulation to generate a plurality of samples for output on an output of the source driver, and at least one of the source drivers arranged to extract a gate driver timing control signal from the signal, and to output a gate driver control signal to the gate driver for synchronizing an output of the gate driver and the source driver, such that the video stream is displayed on a display panel of a display unit.

Description

[Technical Field]

[0001] (Cross-reference of related applications) This application claims priority to U.S. Provisional Patent Application No. 63 / 240,630 (Docket No. HYFYP009P1), filed 3 September 2021, U.S. Provisional Patent Application No. 63 / 280,017 (Docket No. HYFYP009P2), filed 16 November 2021, U.S. Provisional Patent Application No. 63 / 317,336 (Docket No. HYFYP014P), filed 7 March 2022, and U.S. Provisional Patent Application No. 63 / 346,064 (Docket No. HYFYP014P2), filed 26 March 2022, which are incorporated herein by reference in their entirety.

[0002] This application also references, for reference, U.S. Patent Application No. 15 / 925,123 (Docket No. HYFYP001) filed on 19 March 2018, U.S. Patent Application No. 16 / 494,901 (Docket No. HYFYP002) filed on 17 September 2019, U.S. Patent Application No. 17 / 879,499 (Docket No. HYFYP003) filed on 2 August 2022, U.S. Patent Application No. 17 / 686,790 (Docket No. HYFYP004AX1) filed on 4 March 2022, U.S. Patent Application No. 17 / 887,849 (Docket No. HYFYP006) filed on 15 August 2022, and U.S. Patent Application No. 17 / 851,821 (Docket No. HYFYP004AX1) filed on 28 June 2022. We refer to U.S. Patent Application No. HYFYP007, U.S. Patent Application No. 63 / 398,460 (Docket No. HYFYP008P) filed on 16 August 2022, and U.S. Patent Application No. 63 / 391,226 (Docket No. HYFYP013P3) filed on 21 July 2022.

[0003] The present invention generally relates to displaying images on the display panel of a display unit. Specifically, the present invention relates to a source driver for decoding analog signals for display. [Background technology]

[0004] Image sensors, display panels, and video processors are constantly competing to achieve larger formats, greater color depth, higher frame rates, and higher resolution. Local site video transport involves performance scaling bottlenecks that limit throughput, leading to performance compromises while consuming more cost and power. Eliminating these bottlenecks can offer significant advantages.

[0005] For example, as display resolution increases, the data speed of video information transferred from the video source to the display screen has increased exponentially, from 3Gbps for Full HD 10 years ago to 160Gbps for the new 8K screen. Typically, a display with 4K resolution requires approximately 18Gbps of bandwidth at 60Hz, while it requires 36Gbps at 120Hz. An 8K display requires 72Gbps at 60Hz and 144Gbps at 120Hz.

[0006] Until now, data has been transferred digitally using a variation of low-voltage differential signaling (LVDS) data transfer, with a bit rate of 16 Gbps per signal pair, by paralleling the pairs to achieve the required total bit rate. With a wiring delay of 5 ns / m, the wavelength of every bit on the digital connection is 12 mm, which is close to the limit of this type of connection and therefore requires extensive data synchronization to obtain usable data. Next, this digital information needs to be converted to analog pixel information on the fly using ultrafast digital-to-analog (D / A) conversion in the display's source driver.

[0007] Today, D / A converters use 8 bits, but soon D / A conversion may require 10 bits or even 12 bits, and then accurately converting at sufficiently high data rates will become extremely difficult. Consequently, displays must perform D / A conversion within a very short time, and the time available for conversion is also becoming shorter, resulting in D / A conversion stabilization becoming an issue again.

[0008] Therefore, it is desirable that new devices and technologies eliminate the need for D / A conversion in the display source driver, increase bandwidth, and utilize analog video signals generated outside or within the display unit. [Overview of the project]

[0009] To achieve the above, according to the object of the present invention, a source driver for a display panel within a display unit is disclosed, which decodes an analog signal into a voltage expected by the display panel.

[0010] A video signal is a series of luminance values. It is understood that precisely maintaining fixed-bit width (i.e., digital) luminance values ​​is inefficient with respect to video transmission, and since there is no requirement for bit-precise reproduction of these luminance values, analog voltages offer a much larger dynamic range. Therefore, this invention proposes transmitting display panel video signals as analog signals rather than digital signals.

[0011] The advantages include reduced power consumption. In conventional technology, power consumption significantly limits system performance; however, using the present invention, up to 60% less power is consumed. Furthermore, some embodiments provide noise immunity and EM stealth in such a way that the EMI / RFI emissions of the display panel remain well below mandated limits. Moreover, the transmission range of the novel analog signal is much greater than that of conventional Ethernet or HDBaseT signals. Conventional transmission uses expensive mixed-signal processing for high-speed digital circuits, but embodiments of the present invention utilize low-cost analog processing for greater flexibility and lower manufacturing costs.

[0012] Furthermore, the use of a novel analog spread-spectrum video transport (SSVT) signal for data transfer between the display controller and source driver of a display panel dramatically reduces the cost of silicon chips and their complexity. For example, comparing the traditional transport between the signal source and the source driver receiver (with a D / A converter) (via an LVDS or Vx1 transmitter) with the equivalent functionality implemented using transport between a novel SSVT transmitter and a novel SSVT receiver for 4K / 60Hz and 8K / 120Hz panels, the chip area savings are 3:1 and 10:1, respectively.

[0013] This invention relates to a circuit for decoding analog video data transmitted between a video source and a video sink, using a technique that borrows modulation-based code division multiple access (CDMA) channel sharing from direct spread spectrum (SSDS). As will be described in more detail below, the number and content of input video samples received from the video source depend on the operating color space in the video source. Regardless of the color space used, each video sample represents an amount of light perceived or measured within the specified color space.

[0014] When a stream of input digital video samples is received by the encoder, the input digital video samples are (1) repeatedly distributed by assigning the input video samples into the encoder input vector according to a predetermined sequence, and (2) encoded by applying SSDS-based modulation to each of the multiple encoder input vectors (applying an orthogonal code) in order to generate multiple composite EM signals with pseudo-noise characteristics. (3) The analog EM signals are transmitted over the transmission medium. At the receiving end, (4) the input analog EM signals are decoded by applying SSDS-based demodulation using the same orthogonal code to reconstruct the samples into an output vector, and then (5) the output vector is presented as a voltage to the display. As a result, the original stream of time-series video samples, including color and pixel-related information, is transmitted from the video source to the video sink.

[0015] Once captured and converted at the video source, the digital video data can be encoded and transmitted to a video display for near-real-time display. The captured video data can also be stored for later viewing in time-shift mode. In either case, an analog SSVT signal is used to transmit the digital video data received from the video source (or storage device) to the video sink of the display (or storage). The SSVT signal may originate from a computer or other processor and be delivered to the display unit (video sink), thus occurring outside the display unit, or the SSVT signal may be generated within the display unit or display panel itself.

[0016] The present invention, along with its further advantages, is best understood by referring to the following description incorporated in conjunction with the accompanying drawings. [Brief explanation of the drawing]

[0017] [Figure 1] This illustrates conventional technology for delivering digital signals to the display panel within a display unit. [Figure 2]Shows the conventional display driver architecture of a display such as a display panel. [Figure 3] Shows the delivery of an analog video signal to a display panel by using a conversion near the SoC of a display unit. [Figure 4] Shows the delivery of an analog video signal to a display unit by using a conversion near the digital video processor of a local site video system. [Figure 5] Shows the delivery of an SSVT analog video signal to a display panel by using conversion and encoding within a display unit. [Figure 6] Shows an example of a display source driver. [Figure 7] Shows a more detailed diagram of a decoder unit and its output. [Figure 8] Shows a source driver that buffers samples and then amplifies them. [Figure 9] Is a block diagram of one of the decoders of the decoder 656 from FIG. 8. [Figure 10] Is a block diagram of the collector from FIG. 8. [Figure 11] Shows a GPU-to-the-glass platform, a custom printed circuit board that includes not only a current generation GPU but also an SSVT transmitter. [Figure 12] Shows a GPU-to-the-glass system on module (SoM) in which a system on module includes not only a current generation GPU but also an SSVT transmitter. [Figure 13] Shows a enhanced GPU-to-the-glass system in which an enhanced GPU includes a fully integrated SSVT transmitter. [Figure 14] Is an example showing how signal samples (in this case analog values) are encoded in an encoder and then transmitted over an electromagnetic path. [Figure 15] Shows a new encoding technique applicable to signal samples that are digital values. [Figure 16] The decoding of the analog input level encoded using the encoder in Figure 14 is shown. [Figure 17A] This demonstrates the use of an analog encoder and a corresponding analog decoder. [Figure 17B] This demonstrates the use of a digital encoder and a corresponding analog decoder. [Figure 17C] This demonstrates the use of a digital decoder to decode an encoded analog signal that has arrived via an electromagnetic path. [Figure 18] This shows a simulation of the SSVT waveform transmitted via an electromagnetic path. [Figure 19] This is a logic diagram of one of the four decoders. [Figure 20] The diagram shown is a typical decoder track circuit. [Modes for carrying out the invention]

[0018] In a video display system, the conversion of incident light into a signal is typically performed by a source assembly, and a predetermined conversion determines the format of the payload that is transported from the source assembly over one or more electromagnetic paths to a sink assembly (which may be a display or video processor) that receives the payload in a predetermined format and converts the received payload into a signal that is used with a suitable output device to generate synchrotron radiation suitable for human viewing.

[0019] The digitization of the video signal occurs at the signal source of this system (often in the GPU), and the digital signal is then transferred to the display source driver, typically using a combination of high-performance wiring systems, where the digital signal is converted back to an analog signal to be loaded onto the display pixels. Therefore, the sole purpose of digitization is data transfer from the video source to the display pixels. Consequently, we understand that it is far more beneficial to avoid digitization (to the extent possible) and to transfer the analog data directly from the video source to the display driver. This can be done using our novel SSVT coding, which yields an accurate analog voltage that is then decoded again in the source driver. Since the analog data has high precision, there is no need for high bit depth. This means that the sample rate can be at least 10 times lower than in the case of digital transfer, leaving more bandwidth for expansion.

[0020] Furthermore, it is recognized that D / A conversion is far easier because it requires less power than the power needed at the endpoints where the display panel actually needs to be driven. Therefore, instead of transporting the digital signal all the way from the video source to where the analog signal needs to be generated, the analog signal is transported to the display at a sample rate much lower than what would normally be achieved through digitization. This means that instead of needing to transmit gigabits per second over many lines, only a few megasamples per second are needed for analog signals, thus reducing the bandwidth of the channels that need to be used. Moreover, while conventional digital transport occupies only about 1.25 cm (considering that propagation in a cable is about 0.2 m / ns, 16 Gbps means 1 / 16 ns / bit, so 1 bit is 0.2 / 16 meters), transporting analog data results in a tenfold increase in the amount of available space, meaning additional available bandwidth.

[0021] Furthermore, the bits within the digital data must be well-defined. This definition must be quite sensitive to errors and noise, and highs and lows must be detectable with great precision. On the other hand, the proposed analog transmission is far less sensitive. This means that the quality of the cable (for example, extending from one side to the other in a display) does not need to be high.

[0022] The present invention is particularly applicable to high-resolution, high-dynamic-range displays used in computer systems, televisions, monitors, machine vision, automotive displays, virtual or augmented reality displays, and the like.

[0023] (Conventional (digital) transmission of video information to display panels) Figure 1 illustrates the conventional delivery of digital signals to the display panel within the display unit 100 (so-called "display connectivity"). For the purposes of this disclosure, "display panel" refers to the internal part of the display that implements pixels that generate light for viewing, while "display unit" refers to the entire (usually) rectangular housing, including the display panel, panel assembly, frame, drivers, cable routing, and associated electronics for generating the image. Generally, each is updated O(N) times per display interval (reciprocal of the frame rate). 2 A mass-producible display panel containing pixels is controlled by an O(N) voltage.

[0024] HDMI to the system-on-a-chip (SoC) 110 of the display unit (登録商標)This indicates the input of a digital video signal 112 into the display unit via a connector (such as an RJ45 connector). The SoC 110 transports the digital signal to the timing controller 120 (TCON) via the V-by-OneHS standard 116. The timing controller 120 then uses bit serial transport 121 (e.g., SerDes, LVDS, or CEDS) to any number of DACs (digital-to-analog converters) 122 in the source driver of the display panel 118 to convert the digital signal to analog for input into the pixels of the display panel. Digital transport may also use MLVDS, DDI, etc. Control signals 114 provide video framing flags (Vsync, Hsync, etc.), configuration parameters, gate driver control signals, FRC grayscale, driver parameter settings, backlight control, contrast control, etc.

[0025] In addition to the drawbacks mentioned above, this display-connected digital transport presents higher EMI / RFI concerns due to its reliance on high-speed digital circuits, requires high power, is difficult to synchronize, and must be implemented using relatively expensive integrated circuit processes. Furthermore, 8K V-by-One HS, for example, requires 48 wiring pairs at 3.5 Gbps.

[0026] Furthermore, these shortcomings of display connectivity also exist in local site video connectivity. For example, the computer's GPU generates a video signal that is transmitted digitally to the display unit (via V-by-One HS, MLVDS, DDI, etc.), where, again, the DAC in the source driver converts the signal to analog. Typically, the GPU chip is placed on the system / microprocessor board as close as possible to the microprocessor.

[0027] Therefore, it will be recognized that performing the digital-to-analog conversion of digital video signals as close as possible to the SoC, GPU, or digital video processor not only eliminates the need for a DAC in the display panel's source driver, but also achieves the aforementioned advantages when transporting analog signals instead of digital signals within or to the display unit.

[0028] Figure 2 shows a conventional display source driver architecture for a display such as a display panel 118. A source driver 200 (typically having 900 to 1,000 or more outputs) is shown. Multiple instances of this source driver exist in any display that are cascaded together through the top row, such that DIO1 and DIO2 connect any two of the sequences (via a shift register 220). Thus the drivers extend horizontally, and a typical display unit contains 1 to 20 of these drivers. The data input 210 is serial digital data coming from the timing controller of the SoC. Each source driver typically has a digital section 202 and an analog section 204 including a DAC 230. Outputs 240-244 are output into the display row (i.e., directly into the display glass) to drive the source of each pixel, as is well known in this art.

[0029] The source driver 200 requires that a large portion of its driver area be used by digital electronics that require a data rate 10x higher than the associated signals supplied to the display's column lines. This is disadvantageous because the total power consumed by any (digital or analog) circuit depends linearly on the switching frequency (typically the clock frequency).

[0030] (Display connectivity) Figure 3 illustrates the delivery of an analog video signal to a display panel 318 using conversion in or near the SoC 110 of the display unit 300. In this embodiment, the conversion and encoding of the digital video signal to an analog SSVT signal occurs within the display unit itself (and even within the panel assembly), thus improving display connectivity. Shown is the input of a digital video signal 312 to the system-on-chip 310 via an HDMI connector (or, since the invention works with content streamed over the Internet, an RJ45 connector, etc.). The digital signal is transmitted via V-by-One (or other bit-serial transmission) to an SSVT transmitter 315 (which may be implemented within an integrated circuit (e.g., a chip)), which converts the digital video signal, to be transported to the display panel 318 by a novel SSVT source driver 320, into a spread spectral video transport (SSVT) signal 316. Not shown is a timing controller (TCON) located between the SoC 310 and the SSVT transmitter 315. In one embodiment, the SSVT transmitter 315 is implemented within its own integrated circuit, and the SoC and TCON are separate; in another embodiment, both the SSVT transmitter 315 and TCON are combined within a single integrated circuit; and in yet another embodiment, the transmitter 315, TCON, and SoC are all combined within a single integrated circuit. Although not shown in this figure, if the TCON is separate, it would be placed between the SoC 310 and the SSVT transmitter 315.

[0031] The control signals 314 may also provide gate driver control signals, FRC grayscale, driver parameter settings, backlight control, contrast control, etc., as described above, but this is not mandatory. The display panel 318 associates any number of SSVT source drivers 320 (implemented as any number of chips). The SSVT source drivers 320 then decode the analog SSVT signals 316 into the analog voltages expected by the display panel, as will be described in more detail below. The display panel driver chipset is intended to include integrated circuits 315 and 320.

[0032] It should be noted that no DAC (digital-to-analog converter) is required in the display panel, nor in the new source driver described below. Advantageously, the display unit 300 can be implemented using a mature IC process, with EMI / RFI emissions well below the mandated limits, requiring only half the power, and being easy to synchronize. The 8K display would require only eight wiring pairs at 1.6 GHz or 18 wiring pairs at 680 MHz. In contrast, conventional transport of digital video signals from a system-on-a-chip (SoC) into the display unit must be implemented using a relatively expensive IC process, raising concerns about EMI / RFI emissions due to reliance on high-speed digital circuitry. The 8K / 60Hz display would require eight wiring pairs at 16 Gbps or 36 wiring pairs at 3.5 Gbps.

[0033] (Local site video connectivity) Figure 4 illustrates the delivery of an analog video signal to a display panel 400, using a conversion near the digital video processor of the local site video system. In this embodiment, the conversion and encoding of the digital video signal to an analog SSVT signal occurs outside the display unit 401 or the display panel. Thus, the input to the display unit 401 is an analog SSVT signal. A core AI / ML GPU 410 is shown generating the digital video signal; an SSVT transmitter 414 encodes the digital signal, which is to be transported to the display unit and therefore to the display panel 418, into an analog spread spectral video transport (SSVT) signal 416. The display unit includes an arbitrary number of SSVT source drivers 420, which then decode the SSVT signal to the analog voltage expected by the display panel, as will be described in more detail below. Note that no DAC (digital-to-analog converter) is required within the display unit, in the display panel, or in the drivers.

[0034] The GPU 410, on which the video data is processed, may be located within a computer. After being converted and encoded by the SSVT transmitter 414, the analog signal 416 is transported to the display unit 401. The display unit may be located nearby, 10 meters away, or even further away. Thus, the information path from the graphics or video processor (which may effectively be a computer) goes directly to the display unit through numerous transmission connections, never being digital at any point in the data path. Originally, the video signal may originate in a camera or similar device, as shown in Figure 4, which is then transported to the GPU 410. The video signal may also originate from a camera, video processor, or internet modem, where it can be converted into an SSVT signal using the transmitter 414.

[0035] Advantageously, further upstream of the display unit, where D / A conversion and encoding to the SSVT signal are performed (i.e., conversion and encoding are not performed within the display unit itself), there is no need to compress the compressed digital video signal to transmit it over the entire HDMI cable, thus providing further advantages. In this particular embodiment, the full resolution display information is handled within the GPU, then the conversion and encoding to the chip are performed within the GPU, and then all transmission is via a relatively low-frequency SSVT signal until the signal reaches the display unit. In this case, we handled the full display resolution from the GPU source to the display unit endpoint at full frame rate without any internal compression.

[0036] (Display connectivity details) Figure 5 illustrates the delivery of an SSVT analog video signal from a display unit 500 to a display panel 550, using conversion and encoding within the display unit. In this embodiment, the conversion and encoding of the digital video signal to an analog SSVT signal occurs within the display unit 500 itself, thus improving display connectivity. The SoC and TCON of the display unit are not shown. As described above, three or more commercial embodiments may exist: a discrete implementation where the SSVT transmitter is embedded in a mixed-signal integrated circuit and the TCON and SoC are discrete components (an SSVT transmitter "adapter chip" is inserted between the legacy TCON and the novel source driver described herein: the SSVT transmitter translates the TCON output signal into an SSVT signal); a mixed implementation where the SSVT transmitter is integrated with the TCON in a single IC and the SoC is discrete; and a fully integrated implementation where as many functions as possible are integrated within a custom mixed-signal integrated circuit (the SSVT transmitter is integrated with the TCON and SoC).

[0037] In the demonstration system (not shown), the SoC digital functions are implemented within the GPU, communicating with the FPGA carrier board via HDMI 2.0, while the FPGA carrier board implements the TCON digital functions, communicating with a custom mixed-signal PCB that implements SSVT transmitters within the analog subsystem. The SoC functions (such as decompressing compressed digital video signals) are performed in software within the GPU, while the TCON functions (such as generating gate and source driver timing signals) are performed in software within the software circuitry on the FPGA.

[0038] In this example in Figure 5, the display panel 550 is located within the shown panel frame 551, which is inside a 55” HDR 4K60 display unit. As shown, the SSVT transmitter 540 and the panel frame 551 are both located inside the display unit 500. The display panel 550 can be a display panel of any size, a display or array of displays within a VR headset, or a head-up display (HUD) on which the display is projected onto a screen such as a windshield or sun visor.

[0039] Even if the input signal is not SSVT, there are significant advantages to using an internal SSVT signal (i.e., a digital video signal) within the display unit. In conventional display units, we have to decompress the HDMI signal and then transfer the full-fledged, full-bitrate digital data from the receiving end of the display unit to every location within the unit. These connections can be extremely long for a 64 or 80-inch display; that is, the digital data must be transferred from one side of the unit with the input to the other side where the final display source driver is located. Therefore, there are advantages to internally converting the digital signal to SSVT and then transmitting that SSVT signal to every location within the display unit where the source driver is located. Specifically, these advantages include the ability to use lower frequencies, lower EMI signals, and benefit from embedded synchronization / low-latency initialization.

[0040] Figure 5 also shows an SSVT transmitter 540 that generates the SSVT code 592 for the source driver 586 and the power and control signals 590 for the gate driver 560. It includes a rigid PCB 582 and individual flexible PCBs 584, each holding a source driver 586, which generates the source voltage for the display panel. As will be described in more detail below, signal 608 optionally provides information about the display panel to the transmitter 540 to assist in encoding the SSVT signals. The generation of the gate driver control signals 590 may be performed by a timing controller (or other specific hardware) based on synchronization information from the source drivers.

[0041] Typically, the SSVT transmitter and SSVT receiver (in this case, source driver 586) are connected by a transmission medium. In various embodiments, the transmission medium may be a cable (such as HDMI, flat cable, fiber optic cable, metal cable, or non-metallic carbon track flex cable) or wireless. There may be countless EM paths (one path per encoder) on the transmission medium. The SSVT transmitter includes a distributor and multiple encoders. The SSVT receiver will include multiple decoders, the same number as the encoders. The number of paths on the transmission medium is in the range of 1 to 2 or more, any number. In this example, the medium may be a combination of cable, traces on a PCB, IC internal connections, and other mediums used by those skilled in the art.

[0042] During operation, a stream of time-series video samples containing color values ​​and pixel-related information is received from the video source by the display unit 500 and delivered to the SSVT transmitter 540 via the SoC and TCON (processing by the SoC may be performed as is known in the art domain). The number and content of input video samples received from the video source depend on the operating color space in the source (samples may be black and white). Regardless of the color space used, each video sample represents a perceived or measured amount of light within the specified color space.

[0043] When a stream of input digital video samples is received in the SSVT transmitter, the input digital video samples are (1) repeatedly distributed by assigning the video samples into the encoder input vectors according to a predetermined sequence (one vector per encoder), and (2) encoded by applying SSDS-based modulation to each of the encoder input vectors of the multiple encoder input vectors using orthogonal codes to generate multiple composite EM signals (one analog signal from each encoder) with pseudo-noise characteristics. Then, (3) the analog EM signals (one signal per path) are transmitted over the transmission medium.

[0044] For the purpose of explanation, one possible array performed by the distributor to construct the four vectors V0, V1, V2, and V3 is an array in which each contains N samples of color information. In this example, the exposed color information of several sets of samples is "RGB". The exposed RGB samples of several sets of samples in this example are assigned from left to right to vectors V0, V1, V2, and V3. In other words, the "R", "G", and "B" values ​​of the leftmost sample and the "R" signal of the next set of samples are assigned to vector V0, while the next (left to right) "G", "B", "R", and "G" values ​​of the next sample are assigned to vector V1, the next (left to right) "G", "B", "R", and "G" values ​​are assigned to vector V2, and the next (left to right) "R", "G", "R", and "R" values ​​are assigned to vector V3. Once the fourth vector V3 is assigned to the signal, the above process is repeated until each of the four vectors V0, V1, V2, and V3 has N samples. In various embodiments, the number of N samples can vary widely.

[0045] As an example, consider an embodiment with N=60. In this case, the total number of N samples contained in the four vectors V0, V1, V2, and V3 is 240 (60 × 4 = 240). The four encoder input vectors V0, V1, V2, and V3, when fully constructed, contain 80 (240 / 3 = 80) distinct sets of samples (where S=3). In other words: ●Vector V0 is sample P0, N0~P0, N N-1 Includes; ●Vector V1 is sample P1, N0~P1, N N-1 Includes; ●Vector V2 is sample P2, N0~P2, N N-1 including; and ●Vector V3 is sample P3, N0~P3, N N-1 Includes.

[0046] It should be understood that the above examples are merely illustrative and should therefore not be interpreted as limitations. The number of samples N can be approximately 60. It should also be understood that the exposed color information of each set of samples can be any color information (e.g., Y, C, Cr, Cb, etc.) and is not limited to RGB. The number of EM paths on the transmission medium can also vary widely. Therefore, the number of vectors V and the number of encoders can also vary widely from 1 to any number greater than or equal to 2. It should also be understood that the array scheme used to construct the vectors is arbitrary, regardless of the number. Any array scheme can be used and is limited only by which array scheme used on the transmitting side is also used on the receiving side.

[0047] Next, each of the N sample vectors is encoded by its corresponding encoder, generating parallel L output levels using the encoding scheme described herein and specifically shown in Figures 14-17. Preferably, L ≥ N ≥ 2. As described, the encoding may be analog (a DAC is placed before the encoder) or digital (L levels are converted to analog by a DAC before transmission). The L analog output levels are then transmitted as part of the SSVT signal to the SSVT receiver (in this case, the source driver 586) on its EM path. Advantageously, the SSVT signal is an analog signal and no DAC is required in the source driver.

[0048] Although not shown in Figure 5, the SSVT transmitter 540 may also be located outside the display unit.

[0049] (Display panel source driver) Figure 6 shows a display source driver 586. Multiple source drivers are shown in the art and cascaded as known; that is, they then drive the display panel. As shown, source driver 586 does not require a DAC (in the signal path for converting digital samples to analog samples for display) as required in source drivers of prior art. The input of each source driver to the decoding unit 610 is an analog SSVT signal 592 encoded either upstream within the display unit itself or outside the display unit, as described herein. As shown, the SSVT signals 592 are daisy-chained among the source drivers. In alternative embodiments, each source driver would have its own SSVT signal, and the TCON would provide timing information to each source driver chip.

[0050] The decoding unit 610 may have any number (P) decoders, but may also have only a single decoder. Unit 610 decodes the SSVT signal or signal set (as will be described in more detail below) and outputs a number of reconstructed analog sample streams 612 (i.e., analog voltages (a number of samples corresponding to the number of outputs of the source driver)). These analog outputs 612 may not be within the voltage range required by the display panel and may require scaling and may be input to a level shifter 620, which shifts the voltage to a voltage within the voltage range for driving the display panel using analog conversion. Any suitable level shifter known in the art (such as a latching or inverter type) may be used. A level shifter may also be called an amplifier.

[0051] For example, the voltage range coming from the decoding unit may be 0 to 1V, and the voltage range coming from the level shifter may be -8 to 8V (using inverting signal 622 to inform the level shifter to flip the voltage every other frame (i.e., the range is -8 to 0V for one frame and 0V to +8V for the next frame)). In this way, the SSVT signal does not need to flip its voltage every frame; the decoding unit provides (for example) a positive voltage range, and the level shifter flips the voltage every other frame as expected by the display panel. The decoding unit may also perform line inversion and dot inversion. The inverting signal tells the level shifter which voltage should be switched. Some display panels, such as OLEDs, do not need this voltage to flip every other frame. In this case, the inverting signal is not needed, and therefore the level shifter will not flip the voltage every other frame. Display panels, such as LCDs, require this voltage flip. The inverting signal 622 is recovered from the decoding unit as described below.

[0052] Furthermore, the input to the level shifter 620 can be a gain and a gamma value; the gain determines how much amplification is applied, and the gamma curve relates the luminous flux to the perceived luminance, which linearizes the human perception of the luminous flux. Typically, in conventional source drivers, both gain and gamma are set values ​​determined by the manufacturing characteristics of the display panel. In the analog level shifter 620, the gain and gamma can be realized as follows: In one embodiment, the gamma is realized in the digital section of the system, and the level shift and gain are realized in the driver by setting the output stage amplification. In the case of gamma, this realization is also possible in the output driver by realizing a nonlinear amplification characteristic. Once shifted, the samples are output into the output 634, which is used to drive the source electrodes in their corresponding rows of the display panel, as is known in the art.

[0053] In order to properly encode the SSVT code for the final display on a particular display panel (whether encoded within the display unit itself or further upstream outside the display unit), various physical characteristics or properties of the display panel are required by the GPU (or other display controller) (i.e., regardless of which entity performs the SSVT encoding). These physical characteristics are labeled 608 and include, among others, resolution, mosaicization, backlight layout, color profile, aspect ratio, and gamma curve. Resolution is a constant with respect to a particular display panel; mosaicization refers to the way the surface of the panel is fractured into several regions in a regular, predetermined manner, and is a unit of pixels; backlight layout refers to the resolution and diffusion characteristics of the backlight panel; color profiles are all accurate luminance responses of primary colors, providing accurate colors for the image; and the aspect ratio of the display panel will have discrete known values.

[0054] These physical characteristics of a particular display panel can be delivered, hardwired, or provided to a particular display controller in a wide variety of ways. In the example shown in Figure 5, signal 608 delivers the values ​​of these physical characteristics directly from the display panel (or another location within the display unit) to the SSVT transmitter 540. Alternatively, the SSVT transmitter 540 embedded within the particular display unit carries these values ​​hard-encoded within the transmitter. Or, a particular display controller is intended to be used only with a specific type of display panel, and its characteristic values ​​are hard-encoded within that display controller.

[0055] The input to the display panel may also be a backlight signal 604 that instructs the backlight LEDs (i.e., when and at what level they should be switched on). In other words, the input to the display panel is typically a low-resolution representation of the image, which means that the backlight LEDs light up where the display needs to be bright and dim where the display needs to be dim. The backlight signal may also be a monochrome signal embedded within the SSVT signal (i.e., another parallel and independent video signal running alongside other parallel video signals, (e.g.) R, G, and B), and may be low-resolution or high-resolution.

[0056] The output from the decoding unit 610 is a gate driver control signal 606, which shares timing control information with the gate driver 560 at the left edge of the display panel to synchronize the gate driver and the source driver. Typically, each decoding unit includes a timing acquisition circuit that acquires the same timing control information for the gate drivers, and one or more source driver flexfoils (usually the leftmost and / or rightmost source drivers) lead this timing control information to the gate drivers. The gate driver timing control information is embedded in the SSVT signal and is therefore recovered from the signal using established spread spectrum techniques.

[0057] Conventional display drivers typically use "COF" (Chip-on-Flex or Chip-on-Foil) IC packages and are directly connected to the glass; conventional COG (Chip-on-Glass) is also possible, but is not common for large displays. These drivers can be replaced with the new source drivers shown in Figures 6 and 7 (thus converting existing display panels into SSVT-compatible panels). The inputs of these ICs are typically connected collectively via a PCBA, providing input signals from the video source and timing controller. The inputs of these ICs may be close to or far from the display panel, transferring video and control signals across the entire low-cost wiring.

[0058] (Details of SSVT decoding and integration with source drivers) On the receiving end, each source driver's decoder is responsible for decoding the stream of differential EM level signals received on the transmission medium and returning it to a format suitable for display. In this suitable format, the video content contained within the sample can be presented frame by frame on the video display. As a result, video capture by any video source can be regenerated by video sync. Alternatively, the decoded video information can be stored in time-shift mode for later display.

[0059] Figure 7 shows a more detailed diagram of the source driver's decoding unit 610. P represents the number of input electromagnetic pairs known to have been generated in a dense manner by the encoder at the transmitter, with each pair carrying an SSVT signal independent of the others (except that it is an isochronous signal). The source driver includes P decoders 780 and collectors (blocks 782, 786). The decoders 780 perform the inverse transform of the encoders of their pairs at the transmitter, reconstructing their input differential EM level signals into an output vector of N reconstructed samples (although single-ended inputs may be used rather than differential inputs). The collectors assign the decoder output vector samples (or "reconstructed samples") to their designated positions in the source driver input 612. The source driver input 612 contains S reconstructed samples corresponding to groups of driven columns in the display panel. A re-timer function is included within the collector.

[0060] P decoders 780 (labeled 0 to P-1) are arranged to receive differential EM level signals Level0 to LevelP-1 (702 to 704), respectively. In response, each decoder 780 generates N differential pairs of reconstructed samples (samples 0 to N-1). In the case of four decoders 780 (P=4), four vectors V0, V1, V2, and V3 are constructed, respectively. The number of samples N is exactly equal to the number of orthogonal codes used for early coding; that is, there are N orthogonal codes used (meaning N codes from the codebook). Preferably, the code set is an identity matrix.

[0061] Reconstruction bank 782 contains N reconstructed samples (samples 0 to 782) of each of the four decoder output vectors V0, V1, V2, and V3 at the end of each decoding interval. N-1 Each of the differential pairs is sampled and held. Then, the voltage signals of these received differential pairs are sampled (sampled) for each of the four vectors V0, V1, V2 and V3. N-1~are each output as a sample 0). Essentially, each reconstruction bank reconstructs from a differential pair voltage to a single voltage. Relay bank 786 receives all the reconstructed samples (N n-1 ~N0) of each of the four decoder output vectors V0, V1, V2, and V3 and acts as an analog output buffer. Once moved into relay bank 786, the samples are triggered by a latch signal 632 derived from the decoded SSVT signal. The latch signals can be daisy-chained between source drivers. Once released from the relay bank, the samples are sent to level shifter 620.

[0062] Decoder unit 610 also includes a channel aligner 787 and a relay controller 789 that receives framing information and aperture information from each decoder 780. In response, relay controller 789 coordinates the timing of relay bank 786 to ensure that all samples come from a common time interval (when the level signal was transmitted by the SSVT transmitter). As a result, the individual channels of the transmission medium do not necessarily all have the same length as channel aligner 787 and relay controller 789 compensate for any timing differences. Gate driver control signal 606 provides timing information to the gate driver (or to an intermediate circuit configuration), and the gate driver in turn provides the correct timing and control signals to the gate driver, and gate driver control signal 606 can originate from channel aligner 787.

[0063] Note that FIG. 7 discloses a decoder that buffers samples in relay bank 786 and then shifts (amplifies) the levels; it is also possible to shift the levels and then buffer the output samples.

[0064] (Display panel source driver array) Figure 8 shows an alternative embodiment for implementing an array of source drivers. Array 650 is suitable for use with a display panel having 8K resolution and a 144Hz refresh rate (i.e., an "8K144" panel). Figure 8 shows that in this embodiment, each source driver includes a single decoder (i.e., a decoding unit of one decoder) followed by an collector and an amplifier, while Figures 6 and 7 show that each source driver may have many decoders within the decoding unit of the source driver. Either method can be used.

[0065] Shown are 24 720MHz SSVT signals 652-654, each a stranded pair from SSVT transmitter 540: that is, each stranded pair originates from the transmitter's encoder. Each pair is input to one of decoders 656-658, each decoder outputs 64 analog samples at a frequency of 11.25MHz. Each of these samples is input to one of 24 collectors 662-664, each collector collecting 15 sets of these samples before updating its output once every 15 decoding intervals, as will be shown in more detail below. As mentioned above, each collector consists of a relay bank + reconstruction bank (not explicitly shown in this diagram). Next, these 960 analog samples from each collector are input to one of amplifiers 666-668 at a frequency of 750 kHz (11.25 MHz × 64 / 960) for amplification before being output as an amplified analog level 670 on the display row of the display panel at a frequency of 750 kHz. For clarity, signals 604, 606, 608, 622, and 632 shown in Figures 6 and 7 are not shown.

[0066] Theoretically, an amplifier or level shifter can be omitted if the encoded SSVT signal is at a higher voltage, and the decoded signal produces the sample voltage required by the display. However, since SSVT signals are typically at a low voltage (a higher voltage output is required for the display), amplification is necessary.

[0067] Note that Figure 8 discloses a decoder that buffers the sample in the collector 664 and then amplifies it; that is, it is also possible to amplify the sample for output and then collect (buffer) it. Any embodiment may be used.

[0068] Figure 9 is a block diagram of one of the decoders 656 from Figure 8. Shown is one of the SSVT signals 652 input to the decoder. The decoder includes a chip counter 680, a codebook 682 which is normally stored in RAM containing orthogonal codes used for encoding and decoding, and a block diagram 684 of the decoding circuit for each of the 64 output analog samples 688. Each group of the 64 analog samples is output as "enabled" for every cycle from the L cycle at 11.25 MHz. Decoding is described in more detail below with specific circuit diagrams.

[0069] Figure 10 is a block diagram of the collectors from Figure 8, showing more detail of the relay bank 786 from Figure 7. Essentially, each collector performs a series / parallel conversion into partitioned row buffers. The inputs shown to each of the collectors 662-664 are a set of 64 analog samples 690-692 from each decoder at a frequency of 11.25 MHz (the reconstruction bank 782 is not shown). As shown, during each decoding interval, a new set of 64 reconstructed samples to be input is stored in the collector, and each collector is filled once per decoding interval. After each 15 decoding interval, the 960 stored samples 698 from each collector are output into their corresponding amplifiers 666-668 before being delivered to the corresponding columns on the display panel, as shown.

[0070] In one particular embodiment, each of the source drivers in Figure 8 (e.g., decoder 658, collector 664, and amplifier 668) is implemented within an integrated circuit, and each such integrated circuit may be mounted on a flexible PCB 584 as shown in Figure 5.

[0071] (Specific display panel embodiment) In a first specific embodiment, the present invention may be implemented within a large-area display panel (LDP), such as a TFT LCD panel frame assembly having characteristics (8K144 resolution / frame rate; at least 10 bits of sub-pixel color depth), and is suitable for use in displays of 65 inches or larger. In this embodiment, the SSVT transmitter 540 is implemented within a single integrated circuit, and there are 24 source drivers 586, each implemented within a single integrated circuit. Each transmitter 540 has a maximum frequency of 780 Msps. SSVT It outputs 24 wire pairs 592 (SSVT signals) with each input of each source driver up to 780 Msps f SSVT This is a single SSVT signal wiring pair having [specific characteristics]. The optical characteristics of this embodiment (e.g., color reproduction, brightness, contrast, response time) are equivalent to those of conventional LDPs.

[0072] In a second specific embodiment, the present invention may be implemented within a large-area display panel (LDP), such as an LCD panel frame assembly having 8K240 resolution / frame rate and at least 10 bits of sub-pixel color depth; and is suitable for use in displays of 65 inches or larger. In this embodiment, the SSVT transmitter 540 is implemented within a single integrated circuit, and there are 24 source drivers 586, each implemented within a single integrated circuit. Input to the transmitter 540 is via CEDS (clock-embedded differential signaling), and the transmitter 540 each has a maximum frequency of 1,300 Msps. SSVT It outputs 24 wire pairs 592 (SSVT signals) with each source driver; each input of each source driver has a maximum of 1,300 Msps f SSVT This is a single SSVT signal wiring pair with each source driver outputting 960 columns. The optical characteristics of this embodiment (e.g., color reproduction, brightness, contrast, response time) are equivalent to those of conventional LDPs.

[0073] (SSVT transmitter integration embodiment) The following are various embodiments describing different levels of integration for SSVT transmitters with GPUs. These embodiments offer the advantages discussed above for various use cases such as gameplay, home theaters, retail signage, outdoor signage, public displays, and televisions. In each of these embodiments below, the SSVT signal is generated outside the display unit and then delivered to the source driver of the display unit for displaying the video data on the display panel within the display unit. Compared to conventional digital video transmission technologies, these embodiments offer up to 10 times the range, 100 times the noise immunity, and use less power (depending on the level of integration).

[0074] Figure 11 shows a GPU-to-the-glass platform embodiment 800, where the GPU-to-the-glass platform is a custom printed circuit board 802 that includes not only the current-generation (or "legacy") GPU IC 804 but also the SSVT transmitter IC 806. In this embodiment, the SSVT transmitter is not integrated within the GPU. Video data is received from storage, cameras, the internet, etc. 808 and processed by the GPU 804 before being converted into an SSVT signal 810 by the SSVT transmitter 806 and encoded. This signal is then carried to a display unit 819 via any preferred EM path (physical wiring, radio frequency, or fiber optic cable), where the signal is delivered to each of the source drivers 812-818, which are then decoded as described above and displayed on the display panel. The display unit may include any large format, high dynamic range, high frame rate, and high resolution display as described above. This PCB-level integration embodiment uses 20% less power compared to conventional technology.

[0075] Figure 12 shows a GPU-to-the-glass system-on-module (SoM) embodiment 820, where the SoM 822 includes not only the current-generation GPU IC 824 but also the SSVT transmitter IC 826; these ICs may be known-good-die (KGD). In this embodiment, the SSVT transmitter is not integrated within the GPU. Video data is received from storage, cameras, the internet, etc. (828) and processed by the GPU 824 before being converted and encoded into an SSVT signal 830 by the SSVT transmitter 826. This signal is then carried to a display unit 839 via any preferred EM path (physical wiring, radio frequency, or fiber optic cable), where the signal is delivered to each of the source drivers 832-838, which are then decoded as described above and displayed on the display panel. The display unit may include any large format, high dynamic range, high frame rate, and high resolution display as described above. This highly integrated embodiment uses 50% less power compared to conventional technology.

[0076] Figure 13 shows an enhanced GPU-to-glass embodiment 840, in which the enhanced GPU 844 includes a fully integrated SSVT transmitter 846 within the GPU die. Video data is received from storage, cameras, the internet, etc. 848 and processed by the GPU 844 before being converted and encoded into an SSVT signal 850 by the SSVT transmitter 846. This signal is then carried to a display unit 859 via any preferred EM path (physical wiring, radio frequency, or fiber optic cable), where the signal is delivered to each of the source drivers 852-858, then decoded as described above and displayed on a display panel. The display unit may include any large format, high dynamic range, high frame rate, and high resolution display as described above. This highest level of integration embodiment uses 60% less power compared to conventional technology. Furthermore, the GPU has an SSVT transmitter integrated within the same silicon. Thus, high data rates on a single chip are not so critical, as all digital transmission occurs over very short distances.

[0077] (SSVT signal, encoding, and decoding) As previously stated, various embodiments of the present invention disclose, among other advantages, that "an analog SSVT signal is used to transport video information into (or to) a display unit in order to eliminate the need for a DAC in the source driver." The techniques for encoding and decoding such signals are described below.

[0078] For the purposes of this disclosure, an electromagnetic signal (EM signal) is a variable represented as electromagnetic energy whose amplitude changes over time. EM signals propagate from transmitter terminals to receiver terminals via EM paths such as wiring pairs (or cables), free space (or radio), and optical or waveguide (fiber). EM signals can be characterized as being independently continuous or discrete in one of two dimensions (time and amplitude). A “pure analog” signal is a continuous-time and continuous-amplitude EM signal; a “digital” signal is a discrete-time and discrete-amplitude EM signal; and a “sampled analog” signal is a discrete-time and continuous-amplitude EM signal. This disclosure discloses a novel discrete-time, continuous-amplitude EM signal called “spread-spectrum video transport” (SSVT) signal, which is an improvement over existing SSDS-CDMA signals. SSVT refers to the transmission of electromagnetic signals on or along an EM path using improved spread-spectrum direct sequence (SSDS) based modulation.

[0079] Code Division Multiple Access (CDMA) is a well-known channel access protocol commonly used for wireless communication technologies, including cell phone communications. CDMA is an example of multiple access where several different transmitters can transmit information simultaneously over a single channel. In telecommunications applications, CDMA allows multiple users to share a particular frequency band without interference from other users. CDMA employs Direct Spread Spectrum (SSDS) coding, which relies on a unique code to encode each user's data. Using the unique code, transmissions from multiple users can be combined and transmitted without interference between users. At the receiving end, the same unique code is used to demodulate each user's transmission and recover each user's data, respectively.

[0080] SSVT signals differ from CDMA. When a stream of input video (e.g.) samples is received by an encoder, these are encoded by applying SSDS-based modulation to each of the multiple encoder input vectors to generate an SSVT signal. The SSVT signal is then transmitted over the transmission medium. At the receiving end, the input SSVT signal is decoded by applying corresponding SSDS-based demodulation to reconstruct the encoded samples. As a result, the original stream of time-series video samples, including color and pixel-related information, is carried from a single video source to a single video sink, unlike CDMA which distributes data from multiple users to multiple receivers.

[0081] Figure 14 shows a simple example illustrating how signal samples (in this case, analog values) are encoded within an encoder and then transmitted over an electromagnetic path. Shown is an input vector of N analog values ​​902–908, each representing the voltage of an individual pixel in a video frame. These voltages may represent the luminance of a grayscale image or the intensity of a specific color value within a pixel (e.g., the R, G, or B color value of the pixel) (i.e., each value represents a perceived or measured amount of light in a given color space). While pixel voltages are used in this example, this encoding technique can be used with voltages representing any of the wide variety of signals from a sensor (e.g., LIDAR values, audio values, tactile values, aerosol values, etc.), and the analog values ​​may represent other samples such as current. Signal samples that are digital values ​​can also be encoded, and this digital encoding is described below. Furthermore, even if only one encoder and one EM path are shown, one embodiment of the present invention works well with multiple encoders, each transmitting over an EM path.

[0082] Preferably, the start signal sample voltage is typically higher than the encoded voltage in the SSVT signal. After encoding, the voltage range is typically 0-1V in terms of efficiency, but different ranges are possible. Lower voltages mean less power is consumed and may be used in the future.

[0083] These voltages are typically taken from pixels in a row of a frame in a specific order, but other conventions may be used to select and order these pixels. Regardless of which convention is used to select these pixels and order them for encoding, the same convention will be used by the decoder at the receiving end to place these voltages in the resulting frame to which they belong, in order to decode them. Similarly, if the frame is in color and uses RGB, the convention in this encoder may be that all R pixel voltages are encoded first, followed by the G and B voltages or conventions, where voltages 902-906 are the RGB values ​​of the pixels in that row, and the next three voltages 908-912 represent the RGB values ​​of the next pixels. Again, the same convention used by this encoder to order and encode the voltages is used by the decoder at the receiving end. Any specific convention for ordering the analog values ​​902-908 (whether by color value, by row, etc.) may be used, as long as the decoder uses the same convention. As shown, any number of N analog values ​​902–908 can be presented for encoding at one time using codebook 920, limited only by the number of entries in the codebook.

[0084] As previously stated, the codebook 920 has an arbitrary number of N codes 932-938; that is, in this simple example, the codebook has four codes, which means that four analog values ​​902-908 are encoded at once. Many codes, such as 127 codes or 255 codes, may be used, but due to practical considerations such as circuit complexity, it is preferable to use fewer codes. As is known in the art, the codebook 920 contains N mutually orthogonal codes, each of length L; in this example, L=4. Typically, each code is an SSDS code, but it does not necessarily have to be a spreading code as discussed herein. As shown, each code is divided into L time intervals (also called "chips"), and each time interval contains the binary value of the code. As shown in code representation 942, the code 934 may be represented in the traditional binary form "1100", but the code may also be represented as "11-1-1" as shown in code representation 944 for ease of use when modulating values, as described below. Codes 932 and 936-938 may also be represented by code 942 or 944. Note that each code of length L is not associated with a different computing device (such as a telephone), a different person, or a different transmitter, as is done in CDMA.

[0085] Therefore, the following technique is used to transmit the four analog values ​​902-908 to a receiver (having a corresponding decoder) over the transmission medium 34. Each analog value is modulated by each chip in the representation 944 of its corresponding code; for example, the value 902 (i.e., .3) is sequentially modulated (948) by each chip in the representation 944 of code 932. Modulation 948 can be a multiplication operator. Thus, modulating .3 by code 932 produces the sequence ".3,3,3,3". Modulating .7 by code 934 produces ".7,7,-.7,-.7"; the value "0" becomes "0,0,0,0"; and the value "1" becomes "1,-1,1,-1". Typically, the first chip of each code modulates its corresponding analog value, then the next chip of each code modulates its analog value, but one implementation may also modulate a particular analog value by all chips of that code before moving to the next analog value.

[0086] For each time interval, the modulated analog values ​​are summed at 951 (perceived vertically in this figure) to obtain analog output levels 952-958; for example, the sum of the modulated values ​​for these time intervals results in output levels of 2, 0, 6, -1.4. These analog output levels 952-958 can be further normalized or amplified to match the voltage constraints of the transmission line, and then transmitted sequentially as they are generated in that order over the electromagnetic path (such as a differential twisted pair) of the transmission medium 34. The receiver then receives their output levels 952-958 in that order and then decodes them using the same codebook 920 using the inverse of the encoding scheme shown here. The resulting pixel voltages 902-908 can then be displayed within the frame of a display at the receiving end according to the convention used. Thus, the analog values ​​902-908 are effectively encoded synchronously and transmitted over a single electromagnetic path in a series of L analog output levels 952-958. Numerous encoders and electromagnetic paths can also be used as shown and described herein. Furthermore, the number of N samples that can be encoded in this manner depends on the number of orthogonal codes used in the codebook.

[0087] Advantageously, even if the use of robust SSDS technology (such as spreading codes) results in a significant reduction in bandwidth, the use of mutual orthogonal codes, the modulation and summing of each sample by the corresponding code chip, and the transmission of N samples in parallel using L output levels result in a significant bandwidth gain. In contrast to traditional CDMA technology where binary numbers are sequentially encoded and then summed, the present invention first modulates all samples (i.e., all analog or digital values, not single bits) by each chip in the corresponding code, and then sums those modulations at each time interval of the code to obtain the resulting analog voltage level for each specific time interval, thus utilizing the amplitude of the resulting waveform. It is these analog output levels, not binary representations, that are transmitted over the transmission medium. Furthermore, unlike CDMA technology which allows multiple access by various people, various devices, or various sources and transmits to multiple sinks, the present invention facilitates the transmission of analog voltage from one video source to another video sink, i.e., endpoint to endpoint. Moreover, compression for the transport of sample values ​​is not required.

[0088] Figure 15 illustrates this novel encoding technique, applicable to signal samples that are digital values. Here, the digital values ​​902'-908' are digital representations of voltages. Using various examples of voltages, value 902' is "1101", value 904' is "0011", value 906' is "0001", and value 908' is "1000". Each digital value is modulated (digitally multiplied) by the representation 944 of each code (i.e., by "1" or "-1", depending on the chip of the code corresponding to the modulated digital value). Considering only the first time interval of each code, 940, and adding the most significant bit (MSB), which is the sign bit, the modulation of "1101" produces "01101" (MSB "0" means a positive value), the modulation of "0011" produces "00011", the modulation of "0001" produces "00001", and the modulation of "1000" produces "01000". These modulation values ​​are shown and annotated on the first time interval. (Although not shown, modulation with a -1 chip produces a negative value that can be represented in binary using a suitable binary representation of a negative value).

[0089] By digitally summing these modulation values ​​within the first time interval, we get the digital value 952'"011001" (again, the MSB is the sign bit); the other digital values ​​954'-958' are not shown in this example but are calculated in the same way. Considering this sum within base 10, we can verify that the modulation values ​​13, 3, 1 and 8 sum to 25. Although not shown in this example, an additional MSB is usually available for the resulting level 952'-958', in that the sum may require 6 bits or more. For example, if the values ​​902'-908' are represented using 4 bits, then the level 952'-958' may be represented using up to 10 bits in the case of 64 codes (adding 64 bits log2). Or, if 32 modulation values ​​are summed, an additional 5 bits are added. The number of bits required for the output level depends on the number of codes.

[0090] The output level 950' may first be normalized to suit the input requirements of the DAC, and then sequentially fed to the DAC959 to convert each digital value to its corresponding analog value for transmission on the EM path. The DAC959 may be a MAX5857 RF DAC (including a clock multiplier PLL / VCO and a 14-bit RF DAC core, with the complex path being bypassed for direct access to the RF DAC core), followed by a bandfilter (not shown), and then a variable gain amplifier (VGA). In some situations, the number of bits used in level 950' is greater than the number allowed by the DAC959; for example, level 952' is represented by 10 bits, but the DAC959 is an 8-bit DAC. In these situations, an appropriate number of LSBs are discarded, and the remaining MSBs are processed by the DAC, with no loss of visual quality of the resulting image on the display.

[0091] Advantageously, all digital values ​​are modulated, and then these modulated digital values ​​are digitally summed to generate a digital output level for conversion and transmission. This technique differs from CDMA, which modulates each binary of a digital value and then sums the modulated bits to generate the output. For example, assuming there are B bits in each digital value, CDMA would have a total B × L output level to transmit, whereas this new digital (or analog) coding technique would only have a total L output level to transmit, thus having an advantage.

[0092] Figure 16 shows the decoding of analog input levels encoded using the encoder of Figure 14. As shown, L input levels 950 were received on a single electromagnetic path of the transmission medium 34. As described herein and noted earlier, the codebook 920 includes N orthogonal codes 932-938 used to decode the input levels 950 to produce N analog values ​​902-908, i.e., output vectors of the same analog values ​​902-908 encoded as described above. To perform the decoding, each input level 952-958 is modulated by each chip of each code corresponding to a specific index in the output vector 902-908 (961), as indicated by the vertical arrows. Considering the modulation of levels 952-958 by the first code 932, such modulation produces the sequence of modulated values ​​"2,0,6,-1,4". Modulation at levels 952-958 using the second code 934 generates the sequence of modulation values ​​"2,0,-.6,1.4". Modulation using the third code 936 generates "2,0,-.6,-1.4", and modulation using the fourth code 938 generates "2,0,6,1.4".

[0093] Next, as indicated by the horizontal arrows, the modulation values ​​of each sequence are summed to produce one of the analog values ​​902-908. For example, the first sequence is summed to produce the analog value "1.2" (which becomes "3" after being normalized using a scaling factor of "4"). In a similar manner, the modulation values ​​of the other three sequences are summed to produce the analog values ​​"2.8", "0", and "4", and after normalization, produce an output vector of analog values ​​902-908. Each code can modulate the input level, and then the sequence can be summed, or all codes can modulate the input level before each sequence is summed. Thus, the output vectors of N analog values ​​902-908 were transported in parallel using L output levels.

[0094] Although examples of decoded digital input levels are not shown in these examples, those skilled in the art will see that performing such decoding is simple and straightforward by reading the encoding of digital values ​​in the above description.

[0095] Figures 17A, 17B, and 17C illustrate that encoders and decoders can act on either analog or digital samples. Various analog and digital encoders and decoders have already been described above. As described above, depending on the case, there may be two or more EM paths, and therefore two or more encoder / decoder pairs, and a corresponding number of DACs or ADCs.

[0096] Figure 17A illustrates the use of an analog encoder and a corresponding analog decoder. The input to the analog encoder 900 is either an analog sample 970 or a digital sample 971, which has been converted to analog by a DAC 972 located in the analog encoder. In this way, either the analog or digital sample arriving at the analog encoder can be encoded for transmission over the electromagnetic path on the transmission medium 34. The analog decoder 900' decodes the encoded analog sample to produce an analog sample 970 for output. The analog sample 970 may be used as is, or it may be converted to a digital sample using an ADC (not shown).

[0097] Figure 17B illustrates the use of a digital encoder and a corresponding analog decoder. The input to the digital encoder 901 is either a digital sample 971 or an analog sample 970, which has been converted to digital by an ADC 973 located in the digital encoder. Since the encoder is digital, a DAC 959 located in the encoder converts the encoded sample to analog before transmission over the electromagnetic path. In this way, either an analog or digital sample arriving at the digital encoder can be encoded for transmission over the electromagnetic path on the transmission medium 34. The analog decoder 900' decodes the encoded analog sample to produce an analog sample 970 for output. The analog sample 970 may be used as is, or it may be converted to a digital sample using an ADC (not shown).

[0098] Figure 17C illustrates the use of a digital decoder to decode an encoded analog signal that has arrived over the electromagnetic path on the transmission medium 34. The encoded analog signal is transmitted using either the analog encoder or the digital encoder described above. The ADC 974 located in the digital decoder 976 receives the encoded analog sample transmitted over the electromagnetic path and converts this sample to digital. These encoded digital samples are then decoded into digital samples 978 by the digital decoder 976 (corresponding to the values ​​of the input vectors of the samples originally encoded before transmission over the electromagnetic path). The digital samples 978 may be used as is or converted to analog samples using a DAC.

[0099] Figure 18 shows a simulation (similar to an idealized oscilloscope trace) of the SSVT waveform 602 transmitted via the electromagnetic path after output from the analog encoder (or after being digitally encoded and then converted by the DAC). The vertical axis is voltage, and the horizontal axis is a 100 ps oscilloscope measurement time interval. Note that the SSVT signal 602 is an analog waveform rather than a digital signal (i.e., the signal does not represent a binary number), and in this embodiment, it can carry a voltage range of approximately -15V to approximately +15V. The voltage values ​​of an analog waveform are sufficiently analog (or at least can be). Also, the voltage is not limited to a certain maximum value, but high values ​​are impractical.

[0100] As previously explained, analog voltage levels are transmitted sequentially over an electromagnetic path, and each level (the analog output levels 952-958 or digital output levels 952'-958' after passing through the DAC) is the sum of modulated samples over a time interval. When transmitted, these output levels appear as waveforms such as waveform 602. In particular, voltage level 980 represents the sum of modulated samples over a specific time interval (i.e., the output level). Using a simple example, a series of voltage levels 980-986 represents the transmission of four output levels. In this example, 32 codes are used, which means that 32 samples can be transmitted in parallel; therefore, voltage levels 980-986 (followed by many subsequent voltage levels depending on the number of chips in code L) form a parallel transmission of 32 encoded samples (such as pixel voltages from a video source). After such transmission, the next set of L voltage levels in waveform 602 represents the transmission of the next 32 samples. Generally, waveform 602 represents the encoding of analog or digital values ​​to analog output levels to form a composite analog waveform, as well as the transmission of those levels within a discrete time interval.

[0101] Due to phenomena such as attenuation, reflections resulting from impedance mismatch, and infringing aggressor signals, any electromagnetic path degrades the electromagnetic signals propagating through it, and therefore, the measured results of the input level at the receiving terminal are always subject to errors regarding the corresponding output level made available at the transmitting terminal. Thus, scaling of the input level at the receiver (or normalization or amplification of the output level at the transmitter) may be performed to compensate, as is known in the art. Furthermore, due to process gain (i.e., due to an increase in L which also increases the electroelastic energy), the decoded input level at the decoder is normalized by a scaling factor using the code length to recover the transmitted output level, as is known in the art.

[0102] (Detailed Decoder Embodiment) Figure 19 is a logic diagram of one of the four decoders 780. Decoder 780 includes a differential amplifier 1092 and a sample-and-hold circuit 1094 arranged to receive and sample-and-hold one of the four differential EM level signals received on the transmission medium. Other types of circuits (receivers) arranged to receive and sample-and-hold input EM level signals can also be used. The sampled EM level signal is then passed to N decoder track circuits 1096(N n-1 The sequencer controller 1098 provides the same SSDS chip applied on the transmitting side to each of the N decoder track circuits 1096. As a result, the sample output (N) n-1 ~N0) is provided to reconstruction bank 782. Since the same SSDS chip used on the transmitting side is used by each of the decoder track circuits 1096, the demodulated sample N n-1 ~N0 is the same as the one before modulation on the transmitting side.

[0103] The controller 1098 for each decoder in decoder 780 also generates several control signals, including strobe signals, end-of-bank (EOB) signals, aperture signals, and framing signals. The EOB signal is provided to reconstruction bank 782 and represents the timing when relay bank 786 is completely filled with samples. When this occurs, the EOB signal is asserted, and the next set of reconstructed samples (N) n-1 Based on the expected value (~N0), both the decoder track 1096 and the relay bank 786 are cleared. The aperture control signal is provided to the sample-and-hold circuit 1094, and the framing signal is provided to the channel aligner 787 and the relay controller 789.

[0104] Referring to Figure 20, a diagram of a typical encoder track circuit 1096 is shown. The decoder track circuit 1096 includes a multiplier section and an accumulator section. The multiplier section includes a first pair of switches S1-S1, a second pair of switches S2-S2, a third pair of switches S3-S3, and a pair of capacitors C1-C1 on the first (positive) and second (negative) power rails. The accumulator section includes an additional pair of transistors S4-S4, S5-S5, S6-S6, and S7-S7, an operational amplifier, and a pair of capacitors CF-CF on the first (positive) and second (negative) power rails, respectively.

[0105] During each demodulation cycle, a differential EM level signal pair is received at the first level input (level +) terminal and the second level input (level -) terminal. The differential EM level signal pair is demodulated in the multiplier section by conditional inversion, which is achieved by multiplying it by either positive (1) or negative (-1) depending on the value of the received SSDS chip.

[0106] If the SSDS chip has a value of (+1), then when clk1 is active, transistor pairs S1-S1 and S3-S3 are closed, while S2-S2 remains open. As a result, the voltage values ​​at the first level input (level +) terminal and the second level input (level -) terminal are passed and stored by the two capacitors C1 and C1 on the positive and negative rails, respectively. In other words, the input values ​​are multiplied by (+1), and no inversion occurs.

[0107] If the SSDS chip has a value of -1, both S1-S1 switches are off, while switches S2-S2 and S3-S3 are all turned on when clk1 is activated. As a result, the voltage values ​​received at the positive or first (+) terminal and the negative or second (-) terminal are swapped. In other words, the input voltage value provided at the first or positive terminal is led to capacitor C1 on the lower negative rail and stored there, while the voltage value provided at the second or (-) terminal is switched to capacitor C1 on the upper positive rail and stored there. Thus, the received voltage values ​​at the input terminals are inverted, i.e., multiplied by (-1).

[0108] When clk1 transitions to the inactive state, C1 and the accumulated charge on C1 remain. When clk2 transitions to the active state, transistor pairs S4-S4 open while transistor pairs S5-S5 and S6-S6 close. Next, the accumulated charge on capacitor C1 on the lower or negative rail and on C1 on the upper or positive rail is supplied to the differential input of the operational amplifier. The output of the operational amplifier is the original + / - sample pairs prior to encoding on the transmitting side.

[0109] The charge stored on the two capacitors C1 and C1 is also transferred to the capacitor CF on the upper or positive rail and the capacitor CF on the lower or negative rail when Clk2 is active. With each demodulation cycle, the charge on the upper and lower rail capacitors C1 is stored on the two capacitors CF on the upper and lower rails, respectively. When both clk1 and the EOB signal are active, both transistor pairs S7-S7 are closed, short-circuiting the plates of each capacitor CF. As a result, the stored charge is removed, and the two capacitors CF are reset and ready for the next demodulation cycle.

[0110] Each decoder 780 has N decoder track circuits 1096, so N decoded or original + / - sample pairs are regenerated with each demodulation cycle. These N + / - sample pairs are then provided to the reconstruction bank 782, and then to the relay bank 786. As a result, the samples of the original pair are regenerated with their original color content information (e.g., S=3 for RGB).

[0111] Decoder track 1096 reconstructs input level samples over a series of L cycles, and each successive input level is demodulated by the successive SSDS chip of the track's code. The result of each of the L demodulations is stored on a feedback capacitor CF. When EOB is asserted during clk1, which corresponds to the first demodulation cycle of the decoding cycle, CF is cleared after EOB so that it can begin to store again from zero volts or some other reset voltage. In various non-exclusive embodiments, the value of L is a predetermined parameter. Generally, the higher the parameter L, the greater the SSDS process gain, which is better than the electrical elasticity of transmitting the SSVT signal on the transmission medium. On the other hand, the higher the parameter L, the higher the required frequency for applying SSVT modulation, which can degrade signal quality due to insertion loss caused by the transmission medium.

[0112] The above demodulation cycle is repeated over and over again by each decoder. The final result is the recovery of the original time-series samples (i.e., a set of S-samples), each containing their original color content information.

[0113] Although the invention described herein has been explained in considerable detail for the purpose of clarity of understanding, it will become apparent that several variations and modifications may be implemented within the scope of the appended claims. Accordingly, the embodiments described should be considered illustrative but not restrictive, and the invention should not be limited to the details described herein, but should be defined by the full scope of the following claims and their equivalents.

Claims

1. A display panel including multiple gate drivers and multiple source drivers, A video display unit comprising: a video signal transmitter that receives a video stream of digitally represented video samples, distributes the digitally represented video samples into a plurality of input vectors according to a predetermined arrangement, and converts each of the input vectors of the digitally represented video samples into an analog level of a sequence of sequences for delivery to one of the source drivers via an electromagnetic path, wherein there is one sequence of sequences per electromagnetic path; Each of the source drivers is arranged to receive one of the sequential analog levels representing the video stream through the electromagnetic path in order to generate a plurality of samples for output on the output of each source driver according to the predetermined arrangement. As a result, the video stream is displayed on the display panel of the video display unit.

2. The video display unit according to claim 1, further comprising each decoder of the source driver, which decodes the analog levels of the sequenced sequence with reference to a predetermined code set of mutual orthogonal codes to generate the plurality of samples, wherein the code set is an identity matrix.

3. The video display unit according to claim 1, further comprising each decoder of the source driver, which decodes the analog levels of the sequential sequence with reference to a predetermined set of orthogonal codes to generate the plurality of samples.

4. The video display unit according to claim 1, further comprising an input port for receiving the sequential analog levels from an external display controller.

5. The video display unit according to claim 1, wherein each of the source drivers does not include a D / A converter for the purpose of converting digital pixel data to analog pixel data.

6. A receiver arranged to receive multiple sequential sequences of analog input values ​​from a transmitter in a display unit including a display panel via an electromagnetic path, wherein each of the sequential sequences of analog input values ​​uses a predetermined sequence; A buffer arranged to collect analog input values ​​of each sequential sequence into an output vector of an analog sample according to the predetermined arrangement, and a buffer arranged to output the output vector of the analog sample in parallel from the buffer, A plurality of amplifiers arranged to amplify the analog samples of the output vector and to output each of the analog samples to a row of display panels. Source drivers that include this.

7. A decoder that decodes L analog input values ​​of each sequence into output vectors of N analog samples by referring to a predetermined code set of N mutually orthogonal codes, each of which has length L, wherein each of the N codes is associated with one of the samples, and L = N ≥ 2, and the code set is an identity matrix, according to claim 6.

8. A source driver according to claim 6, further comprising a decoder that decodes each of the L analog input values ​​in the sequence into output vectors of N analog samples by referring to a predetermined set of codes of N mutual orthogonal codes, each of which has length L, wherein each of the N codes is associated with one of the samples, and L ≥ N ≥ 2.

9. The source driver according to claim 6, wherein the plurality of sequential analog input values ​​are received from a transmitter outside the display unit, including the display panel.

10. The source driver according to claim 6, wherein the source driver does not include a digital-to-analog converter (DAC) for the purpose of converting digital pixel data to analog pixel data.

11. A display panel including multiple gate drivers and multiple source drivers, A video display unit comprising: a video signal transmitter that receives a video stream of digitally represented video samples, distributes the digitally represented video samples into a plurality of input vectors according to a predetermined arrangement, and converts each of the input vectors of the digitally represented video samples into an analog level of a sequence of sequences for delivery to one of the source drivers via an electromagnetic path, wherein there is one sequence of sequences per electromagnetic path; Each of the source drivers is arranged to receive one of the sequential analog levels representing the video stream through the electromagnetic path, and to decode the analog level using demodulation to generate a plurality of samples for output on the output of each source driver according to a predetermined arrangement. As a result, the video stream is displayed on the display panel of the video display unit.

12. A video signal transmitter that receives the video stream in digital representation and encodes the video stream using modulation of the sequence to analog levels for delivery to each of the source drivers. The video display unit according to claim 11, further comprising:

13. Input port for receiving the analog level of the sequence from an external display controller. The video display unit according to claim 11, further comprising:

14. The video display unit according to claim 11, wherein each of the source drivers does not include a D / A converter for the purpose of converting digital pixel data to analog pixel data.

15. The video display unit according to claim 11, wherein each of the source drivers includes a plurality of decoders, and a number of decoders equal to the number of electromagnetic paths are used to transmit the analog level to each of the source drivers over the electromagnetic paths.

16. The video display unit according to claim 11, wherein the video signal transmitter is implemented in an integrated circuit separate from the video processor.

17. The video display unit according to claim 11, wherein the video signal transmitter is implemented as a system-on-module together with the video processor.

18. The video display unit according to claim 11, wherein the video signal transmitter is integrated within the video processor.

19. The video display unit according to claim 11, wherein at least one of the source drivers is arranged to extract a gate driver control signal from the decoded analog level and to output the gate driver control signal to the plurality of gate drivers in order to synchronize the gate driver and the output of each of the source drivers.

20. Each of the aforementioned source drivers A decoder that decodes each of the aforementioned analog levels into output vectors of N analog samples by referring to a predetermined set of N mutual orthogonal codes, each of which has length L, wherein each of the N codes is associated with one of the samples, each of the aforementioned sequences has L analog levels, and L ≥ N ≥ 2. A buffer is provided to collect the output vectors of N analog samples from the decoder and to output the output vectors of N analog samples in parallel. The video display unit according to claim 11, comprising a plurality of amplifiers arranged to amplify the analog samples of the output vector and to output each of the analog samples to a row of display panels.

21. A receiver arranged to receive L sequential analog input values ​​from an electromagnetic path, A decoder that decodes each of the L analog input values ​​in the sequence into output vectors of N analog samples by referring to a predetermined set of N mutual orthogonal codes, each of which has length L, wherein each of the N codes is associated with one of the samples, and L ≥ N ≥ 2. A buffer is provided to collect the output vectors of N analog samples from the decoder and to output the output vectors of N analog samples in parallel. A plurality of amplifiers arranged to amplify the analog samples of the output vector and to output each of the analog samples to a row of display panels. Source drivers that include this.

22. The source driver according to claim 21, wherein the predetermined code set is the same as the code set used to encode the L analog input values ​​of the sequence.

23. The source driver according to claim 21, wherein L analog input values ​​of the plurality of sequential sequences are received from a transmitter in a display unit including the display panel.

24. The source driver according to claim 21, wherein L analog input values ​​of the plurality of sequential sequences are received from a transmitter outside the display unit including the display panel.

25. The source driver according to claim 21, wherein the source driver does not include a digital-to-analog converter (DAC) for the purpose of converting digital pixel data to analog pixel data.

26. The source driver according to claim 21, wherein the display panel includes C columns, L analog input values ​​of the sequence are received sequentially at frequency freq(SSVT), each of the output vectors of N analog samples is output from the decoder at frequency freq(sample) = freq(SSVT) / N, and the buffer outputs the output vectors of N analog samples in parallel at frequency freq(line) = freq(sample) × N / C.

27. Each of the N codes is indexed, and the source driver further, A set of N two-input correlators, each correlator associated with one of the N locations of the output vector, each correlator having a value in the L input values ​​of the ordered sequence as one input, and a corresponding value in the code associated with one of the N locations as the other input, A set of N two-input adders, each adder associated with one of N locations, each two-input adder having the output of a corresponding two-input correlator as one input and the content of the location of the corresponding output vector as the other input. The source driver according to claim 21, including the following:

28. The source driver according to claim 21, wherein L analog input values ​​of the sequence are received sequentially by the receiver, and the output vectors of N analog samples are output in parallel from the decoder.

29. The source driver according to claim 21, wherein the receiver receives L analog input values ​​of a plurality of sequential sequences from a transmitter in a display unit including the display panel via an electromagnetic path, each of the L analog input values ​​of the sequential sequence using a predetermined array, and the buffer collects the output vectors of N analog samples according to the predetermined array.

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