Pixel circuit for light-emitting element

Abstract

The pixel drive circuit includes a first transistor, a second transistor, and a first capacitor. The first transistor is configured to receive a data signal and drive the light-emitting element based on the data signal. The first transistor includes a first gate terminal, a first source terminal, and a first drain terminal. The second transistor includes a second gate terminal that receives a first bias signal from a first bias source, a second source terminal coupled to the first transistor, and a second drain terminal coupled to the light-emitting element. The first capacitor is disposed between the first gate terminal and the second gate terminal. The first transistor and the second transistor are different types of transistors.

Description

Background Art

[0001] The present disclosure generally relates to display technologies, and more specifically, to pixel circuits.

[0002] Some display devices may have requirements for driving tandem or triple OLEDs with a high cross voltage. In a general-purpose complementary metal oxide semiconductor (CMOS) transistor process, the breakdown voltage of a transistor that drives an OLED using a threshold voltage (Vth) compensation function architecture may be from 6 volts to 8 volts. When these transistors are used in a pixel driving circuit to drive tandem or triple OLEDs, the gate-drain voltage (VGD) or the body-drain voltage (VBD) may exceed the breakdown voltage of the device.

[0003] Therefore, the display device may cause a hot carrier injection (HCI) effect or current leakage, resulting in some detection or abnormal situation.

Summary of the Invention

[0004] In one aspect, a pixel driving circuit is disclosed. The pixel driving circuit includes a first transistor, a second transistor, and a first capacitor. The first transistor is configured to receive a data signal and drive a light-emitting element based on the data signal. The first transistor includes a first gate terminal, a first source terminal, and a first drain terminal. The second transistor includes a second gate terminal that receives a first bias signal from a first bias source, a second source terminal coupled to the first transistor, and a second drain terminal coupled to the light-emitting element. The first capacitor is disposed between the first gate terminal and a second bias source. The first transistor and the second transistor are different types of transistors.

[0005] In some implementations, the pixel driver circuit further includes a driver subcircuit and a data writing subcircuit. The driver subcircuit is coupled to the first gate terminal and the first source terminal to selectively provide the first transistor with a second bias signal from a third bias source. The data writing subcircuit is coupled to the driver subcircuit to selectively provide the first transistor with the data signal.

[0006] In some implementations, the pixel driving circuit further includes a second capacitor located between the driving subcircuit and the data writing subcircuit.

[0007] In some implementations, the scanning period of each display frame includes a reset period and an illumination period, and the drive subcircuit provides the second bias signal to the first transistor during the illumination period in order to drive the light-emitting element.

[0008] In some implementations, the reset period includes an initialization period, a compensation period, and a data writing period, and the drive subcircuit provides a first initialization bias signal to the first capacitor during the initialization period.

[0009] In some implementations, the data writing subcircuit provides a second initialization bias signal to the second capacitor during the initialization period and the compensation period.

[0010] In some implementations, the data writing subcircuit provides the data signal to the first transistor during the data writing period.

[0011] In some implementations, the drive subcircuit includes a first switching element positioned between the first source terminal and the first terminal of the second capacitor; a second switching element positioned between the first terminal of the second capacitor and the third bias source; and a third switching element positioned between the first terminal of the second capacitor and the first gate terminal.

[0012] In some implementations, the drive subcircuit includes a fourth switching element positioned between the third bias source and the first terminal of the second capacitor; and a fifth switching element positioned between the first terminal of the second capacitor and the first gate terminal.

[0013] In some implementations, the drive subcircuit includes a sixth switch element positioned between the first source terminal and the third bias source; a seventh switch element positioned between the first source terminal and the first terminal of the second capacitor; and an eighth switch element positioned between the first terminal of the second capacitor and the first initialization bias source.

[0014] In some implementations, the drive subcircuit includes a ninth switch element positioned between the first source terminal and the third bias source; a tenth switch element positioned between the first source terminal and the first terminal of the second capacitor; and an eleventh switch element positioned between the first terminal of the second capacitor and the first gate terminal.

[0015] In some implementations, the data writing subcircuit includes a 12th switching element positioned between the second terminal of the second capacitor and a data signal source; and a 13th switching element positioned between the second terminal of the second capacitor and a second initialization bias source.

[0016] In some implementations, the data writing subcircuit has a 14th switching element positioned between the second terminal of the second capacitor and the data signal source.

[0017] In some implementations, the data writing subcircuit and the second capacitor are shared by more than one drive subcircuit.

[0018] In some implementations, the first bias source and the second bias source are provided by different voltage sources. In some implementations, the first bias source and the second bias source are provided by the same voltage source.

[0019] In another embodiment, a light-emitting device is disclosed. The light-emitting device includes a light-emitting element and a drive circuit for driving the light-emitting element. The drive circuit includes: a first type transistor having a first gate terminal, a first source terminal, and a first drain terminal for receiving a data signal; a second type transistor having a second gate terminal for receiving a first bias signal from a first bias source, a second source terminal coupled to the first drain terminal, and a second drain terminal coupled to the light-emitting element; a first capacitor positioned between the first gate terminal and the second bias source; a drive subcircuit coupled to the first gate terminal and the first source terminal for providing the data signal and a second bias signal from a third bias source; a data write subcircuit coupled to the drive subcircuit for providing the data signal to the drive subcircuit; and a second capacitor positioned between the drive subcircuit and the data write subcircuit.

[0020] In some implementations, the first type of transistor is a p-type transistor, and the second type of transistor is an n-type transistor.

[0021] In some implementations, the drive sub - circuit includes a first switch element disposed between the first source terminal and the first terminal of the second capacitor; a second switch element disposed between the first terminal of the second capacitor and the third bias source; and a third switch element disposed between the first terminal of the second capacitor and the first gate terminal.

[0022] In some implementations, the drive sub - circuit includes a fourth switch element disposed between the third bias source and the first terminal of the second capacitor; and a fifth switch element disposed between the first terminal of the second capacitor and the first gate terminal.

[0023] In some implementations, the drive sub - circuit includes a sixth switch element disposed between the first source terminal and the third bias source; a seventh switch element disposed between the first source terminal and the first terminal of the second capacitor; and an eighth switch element disposed between the first terminal of the second capacitor and the first initialization bias source.

[0024] In some implementations, the drive sub - circuit includes a ninth switch element disposed between the first source terminal and the third bias source; a tenth switch element disposed between the first source terminal and the first terminal of the second capacitor; and an eleventh switch element disposed between the first terminal of the second capacitor and the first gate terminal.

[0025] In some implementations, the data writing sub - circuit includes a twelfth switch element disposed between the second terminal of the second capacitor and the data signal source; and a thirteenth switch element disposed between the second terminal of the second capacitor and the second initialization bias source.

[0026] In some implementations, the data writing sub-circuit has a fourteenth switching element disposed between the second terminal of the second capacitor and the data signal source.

[0027] In some implementations, the drive circuit further includes a reset signal coupled to the second drain terminal.

[0028] In some implementations, the first bias source and the second bias source are provided by different voltage sources. In some implementations, the first bias source and the second bias source are provided by the same voltage source.

[0029] In a further aspect, a method of driving a light emitting element by a pixel circuit is disclosed. The pixel circuit includes a first transistor, a second transistor disposed between the first transistor and the light emitting element, a first capacitor disposed between the first gate terminal of the first transistor and the second gate terminal of the second transistor, and a second capacitor disposed between the first transistor and the data signal source. During an initialization period, a first end of the first capacitor is initialized to a first initialization bias, and a first end of the second capacitor is initialized to a second initialization bias. During a compensation period, the first end of the first capacitor is compensated to a compensation bias. During a data writing period, a data signal is provided to the first end of the second capacitor. During a light emitting period, the light emitting element is driven to emit light based on the data signal.

[0030] In some implementations, the pixel circuit may further include a reset bias source coupled to the second transistor and the light emitting element. During the initialization period, the compensation period, and the data writing period, a reset bias is provided to the pixel circuit by the reset bias source.

[0031] In some implementations, the sum of the initialization period, the compensation period, the data writing period, and the light emission period is the frame period.

[0032] In some implementations, the first initialization bias is supplied to the first end of the first capacitor; the first bias is supplied to the second end of the first capacitor; the second initialization bias is supplied to the first end of the second capacitor; and the first end of the first capacitor and the second end of the second capacitor are coupled.

[0033] In some implementations, the first initialization bias at the first end of the first capacitor is discharged to the reset bias through the first transistor and the second transistor.

[0034] In some implementations, the voltage difference between the first and second ends of the first capacitor is at least the sum of the first threshold voltage of the first transistor and the second threshold voltage of the second transistor.

[0035] In some implementations, the compensation bias is at least the sum of the first threshold voltage of the first transistor and the second threshold voltage of the second transistor. [Brief explanation of the drawing]

[0036] The accompanying drawings incorporated herein and forming part of herein illustrate the disclosure and, together with herein, further illustrate the principles of the disclosure and enable those skilled in the art to create and use the disclosure.

[0037] [Figure 1] This disclosure shows devices including displays and control logic according to several aspects of this disclosure.

[0038] [Figure 2]This disclosure shows a block diagram of the display shown in Figure 1 in several embodiments.

[0039] [Figure 3] The following are schematic diagrams of pixel driving circuits for light-emitting elements according to some aspects of this disclosure.

[0040] [Figure 4] The following are schematic diagrams of pixel driving circuits for light-emitting elements according to some aspects of this disclosure.

[0041] [Figure 5] The following are schematic diagrams of pixel driving circuits for light-emitting elements according to some aspects of this disclosure.

[0042] [Figure 6A] The following are schematic diagrams of pixel driving circuits for light-emitting elements according to some aspects of this disclosure. [Figure 6B] The following are schematic diagrams of pixel driving circuits for light-emitting elements according to some aspects of this disclosure.

[0043] [Figure 7] The following are schematic diagrams of pixel driving circuits for light-emitting elements according to some aspects of this disclosure.

[0044] [Figure 8] The timing diagrams shown in Figure 7 illustrate the operation of the pixel driving circuit according to several aspects of this disclosure.

[0045] [Figure 9] The following are schematic diagrams of pixel driving circuits for light-emitting elements according to some aspects of this disclosure.

[0046] [Figure 10] The timing diagrams shown in Figure 9 illustrate the operation of the pixel driving circuit according to several aspects of this disclosure.

[0047] [Figure 11] The following are schematic diagrams of pixel driving circuits for light-emitting elements according to some aspects of this disclosure.

[0048] [Figure 12] The timing diagrams shown in Figure 11 illustrate the operation of the pixel driving circuit according to several aspects of this disclosure.

[0049] [Figure 13] The following are schematic diagrams of pixel driving circuits for light-emitting elements according to some aspects of this disclosure.

[0050] [Figure 14] The timing diagrams shown in Figure 13 illustrate the operation of the pixel driving circuit according to several aspects of this disclosure.

[0051] [Figure 15] The following are schematic diagrams of pixel driving circuits for light-emitting elements according to some aspects of this disclosure.

[0052] [Figure 16] The timing diagrams shown in Figure 15 illustrate the operation of the pixel driving circuit according to several aspects of this disclosure.

[0053] [Figure 17] The following are schematic diagrams of pixel driving circuits for light-emitting elements according to some aspects of this disclosure.

[0054] [Figure 18] The timing diagrams shown in Figure 17 illustrate the operation of the pixel driving circuit according to several aspects of this disclosure.

[0055] [Figure 19] The following are schematic diagrams of pixel driving circuits for light-emitting elements according to some aspects of this disclosure.

[0056] [Figure 20]The timing diagrams shown in Figure 19 illustrate the operation of the pixel driving circuit according to several aspects of this disclosure.

[0057] [Figure 21] The following are schematic diagrams of pixel driving circuits for light-emitting elements according to some aspects of this disclosure.

[0058] [Figure 22] The timing diagrams shown in Figure 21 illustrate the operation of the pixel driving circuit according to several aspects of this disclosure.

[0059] [Figure 23] The present disclosure illustrates several applications of the pixel driving circuit 700.

[0060] [Figure 24] The present disclosure illustrates several applications of the pixel driving circuit 900.

[0061] [Figure 25] The present disclosure illustrates several applications of the pixel driving circuit 1100.

[0062] [Figure 26] The present disclosure illustrates several applications of the pixel driving circuit 1300.

[0063] [Figure 27] The present disclosure illustrates several applications of the pixel driving circuit 1300.

[0064] [Figure 28] The present disclosure illustrates several applications of the pixel driving circuit 1100.

[0065] [Figure 29] A flowchart illustrating a method by which a pixel circuit drives a light-emitting element, according to several aspects of this disclosure, is shown.

[0066] This disclosure will be explained with reference to the attached drawings. [Modes for carrying out the invention]

[0067] While specific configurations and arrangements are discussed, it should be understood that this is for illustrative purposes only. Other configurations and arrangements may be used without departing from the intent and scope of this disclosure. Furthermore, it is anticipated that this disclosure may be used in a variety of other applications.

[0068] References in this specification to "one embodiment," "one example," "exemplary embodiment," "several embodiments," etc., should be noted to indicate that the embodiments described may include certain features, structures, or characteristics, but not all embodiments may necessarily include such features, structures, or characteristics. Furthermore, such phases do not necessarily refer to the same embodiment. Moreover, if certain features, structures, or characteristics are described in relation to one embodiment, it is assumed that such features, structures, or characteristics may also be used in relation to other embodiments, whether explicitly described or not.

[0069] In general, technical terms can be understood, at least partially, from their contextual use. For example, as used herein, the term “one or more” may be used, at least partially contextually, to describe any singular feature, structure, or characteristic, or to describe a combination of plural features, structures, or characteristics. Similarly, terms such as "a," "an," or "the" can also be understood, at least partially depending on the context, to indicate whether they are used in the singular or plural form. Furthermore, the term "based on" does not necessarily have to be understood as intended to convey an exclusive set of elements, but rather may allow for the presence of additional elements that are not necessarily explicitly mentioned, at least in part depending on the context.

[0070] As will be disclosed in detail below, among other novel features, the pixel circuits of the light-emitting elements disclosed herein, such as organic light-emitting elements (OLEDs) and micro-LEDs, can improve various display specifications. It should be understood that the light-emitting elements described herein are for illustrative purposes only, and other types of light-emitting elements may also be applicable.

[0071] Figure 1 shows an apparatus 100 including a display 102 and control logic 104, according to several aspects of the present disclosure. Apparatus 100 may be any suitable device, e.g., a VR, AR, or MR device (e.g., a VR headset), a handheld device (e.g., a dam or smartphone, tablet, etc.), a wearable device (e.g., eyeglasses, wristwatch, etc.), a car control station, a gaming console, a television set, a laptop computer, a desktop computer, a notebook computer, a media center, a set-top box, a Global Positioning System (GPS), an electronic billboard, an electronic sign, a printer, or any other suitable device. In some implementations, the display 102 is operably coupled to the control logic 104 and is part of apparatus 100, but is not limited to, an HMD, a handheld device screen, a computer monitor, a television screen, a dashboard, an electronic billboard, or an electronic sign. The display 102 may be an OLED display, a microLED display, a liquid crystal display (LCD), an electronic ink display, an electron light-emitting display (ELD), an LED or incandescent light-equipped billboard display, or any other suitable type of display.

[0072] The control logic 104 may be any suitable hardware, software, firmware, or combination thereof configured to receive display data 106 (e.g., pixel data) and generate control signals 108 for driving subpixels on the display 102. The control signals 108 are used to control the writing of the display data 106 to the subpixels and to direct the operation of the display 102. For example, a subpixel rendering (SPR) algorithm for various subpixel arrangements may be part of the control logic 104 or implemented by the control logic 104. The control logic 104 can be implemented as a standalone integrated circuit (IC) chip, such as an application-specific integrated circuit (ASIC) or a field-programmable gate array (FPGA). The device 100 may also include, but is not limited to, any other suitable components, such as a tracking device 110 (e.g., an inertial sensor, camera, eye tracker, GPS receiver, or any other suitable device for tracking eye movements, facial expressions, head movements, body movements and hand gestures), an input device 112 (e.g., a mouse, keyboard, remote controller, handwriting input device, microphone, scanner, etc.) and a speaker (not shown).

[0073] In some implementations, the device 100 may be a handheld or VR / AR / MR device, such as a smartphone, tablet, or VR headset. The device 100 may also include a processor 114 and memory 116. The processor 114 may be, for example, a graphics processor (e.g., a graphics processing unit (GPU)), an application processor (AP), a general-purpose processor (e.g., an APU, accelerated processing unit; GPGPU, general-purpose computing on a GPU) or any other suitable processor. The memory 116 may be, for example, a discrete frame buffer or integrated memory. The processor 114 is configured to generate display data 106 within a display frame, and may temporarily store the display data 106 in memory 116 before sending it to the control logic 104. The processor 114 may also generate other data, such as control instructions 118 or test signals, and may provide them to the control logic 104 directly or through memory 116. Next, the control logic 104 receives the display data 106 from the memory 116 or directly from the processor 114.

[0074] Figure 2 shows a block diagram of the display 102 shown in Figure 1, including the drive circuitry, according to some aspects of the present disclosure. In some implementations, the display 102 may include a display panel having an active area 200 containing a plurality of subpixels. The display panel may also include on-panel drive circuitry, such as a gate drive circuit 202 and a source drive circuit 204. In some implementations, the gate drive circuit 202 and the source drive circuit 204 do not have to be on-panel drive circuitry, i.e., they do not have to be part of the display panel, but instead are operably coupled to the display panel.

[0075] Each subpixel may be any of the units that make up a pixel (i.e., a subdivision of a pixel). For example, a subpixel may be a monochromatic display element that can be treated individually. In some implementations where the display 102 is a light-emitting element display (e.g., an OLED display or a microLED display), each subpixel may include a light-emitting element (e.g., an OLED or microLED) and a pixel circuit for driving the light-emitting element. Multiple subpixels (and their light-emitting elements) may be arranged in an array having multiple rows and columns according to any suitable subpixel arrangement. Each light-emitting element may emit light at a predetermined brightness and in a predetermined color, but is not limited to, red, green, blue, yellow, cyan, magenta, or white. Each pixel circuit includes a thin-film transistor (TFT) and a capacitor and is configured to drive the corresponding subpixel by controlling the light emission from each light-emitting element according to a control signal 108 from the control logic 104. The pixel circuit may be a 2T1C configuration (i.e., including a switching transistor, a drive transistor, and a storage capacitor), or, in configurations such as 7T1C, 5T1C, 5T2C, or 6T1C, it may include a compensation circuit with more transistors and / or capacitors for brightness uniformity.

[0076] In some implementations, the gate drive circuit 202 is operably coupled to the active region 200 via multiple gate lines G1-Gm (also known as scan lines) and configured to scan multiple subpixels. For example, the gate drive circuit 202 applies multiple scan signals, generated based on control signals 108 from the control logic 104, to multiple gate lines G1-Gm for scanning multiple subpixels in a gate scan sequence. During the scan period, the scan signals are applied to the gate electrodes of the switching transistors of each pixel circuit, turning on the switching transistors so that the data signals of the corresponding subpixels can be written by the source drive circuit 204. Although one gate drive circuit 202 is shown in Figure 2, it should be understood that in some embodiments, multiple gate drive circuits can work together to scan these subpixels.

[0077] In some implementations, the source drive circuit 204 is operably coupled to the active region 200 via multiple source lines S1-Sn (also known as data lines) and is configured to write display data 106 within a frame to multiple subpixels. For example, the source drive circuit 204 may simultaneously apply multiple data signals to multiple source lines S1-Sn of these subpixels. That is, the source drive circuit 204 may include one or more shift registers, a digital-to-analog converter (DAC), a multiplexer (MUX), and arithmetic circuits for controlling the timing of voltage application to the source electrodes of the switching transistors of each pixel circuit (i.e., during the scanning period in each frame) and the magnitude of the voltage applied according to the gradient of the display data 106. Figure 2 shows one source drive circuit 204, but it should be understood that in some implementations, multiple source drive circuits can work together to apply data signals to the source lines of these subpixels.

[0078] Additionally, a light-emitting driver circuit 206 may be included on the display panel. The light-emitting driver circuit 206 may be operably coupled to the active region 200 and may be configured to cause each subpixel to emit light for a specific period in each frame by applying multiple light-emitting signals to multiple light-emitting lines E1-Ek. Although one light-emitting driver circuit 206 is shown in Figure 2, it should be understood that in some implementations, multiple light-emitting driver circuits may work in conjunction with each other.

[0079] Figure 3 shows a schematic diagram of a pixel driver circuit 300 for a light-emitting element 302 according to several embodiments of the present disclosure. The light-emitting element 302 may be an OLED or microOLED driven by the pixel driver circuit 300. The pixel driver circuit 300 includes a p-type driver transistor 304 and a capacitor 306 (e.g., a storage capacitor). In some implementations, the pixel driver circuit 300 may further include a switch (e.g., a switching transistor or a discharge control switch) or other elements. As shown in Figure 3, the maximum gate-drain voltage (VGD) of the p-type driver transistor 304 may be (VDD-VSS), the maximum body-drain voltage (VBD) of the p-type driver transistor 304 may be (VDD-VSS-VOLED_Min), and the minimum voltage at the anode of the light-emitting element 302 may be (VSS+VOLED_Min). In some implementations, the gate-drain voltage (VGD) or body-drain voltage (VBD) of the p-type drive transistor 304 may exceed the breakdown voltage of the p-type drive transistor 304.

[0080] Figure 4 shows a schematic diagram of another pixel driver circuit 400 for a light-emitting element 402 according to some aspects of the present disclosure. The light-emitting element 402 may be an OLED or microOLED driven by the pixel driver circuit 400. The pixel driver circuit 400 includes an n-type driver transistor 404 and a capacitor 406 (e.g., a storage capacitor). In some implementations, the pixel driver circuit 400 may further include a switch (e.g., a switching transistor or a discharge control switch) or other elements. As shown in Figure 4, the maximum value of the drain-gate voltage (VDG) of the n-type driver transistor 404 may be (VDD-VSS), the maximum value of the drain-body voltage (VDB) of the n-type driver transistor 404 may be (VDD-VSS), and the minimum voltage at the anode of the light-emitting element 402 may be (VSS+VOLED_Min). In some implementations, the drain-gate voltage (VDG) or drain-body voltage (VDB) of the n-type drive transistor 404 may exceed the breakdown voltage of the n-type drive transistor 404.

[0081] Figure 5 shows a schematic diagram of a pixel driver circuit 500 for a light-emitting element 502 according to some aspects of the present disclosure. As shown in Figure 5, an n-type transistor 506 is connected to a p-type transistor 508 to drive the light-emitting element 502. In some implementations, the n-type transistor 506 and the p-type transistor 508 are collectively referred to as a pixel core 504. A capacitor 510 (C1) is coupled between the gate of the n-type transistor 506 and the gate of the p-type transistor 508, and a bias V3 is provided to the gate of the p-type transistor 508. In some implementations, a bias V4 may be further provided to the body of the n-type transistor 506, and a bias V5 may be further provided to the body of the p-type transistor 508. As shown in Figure 5, the maximum value of the drain-gate voltage (VDG) of the n-type transistor 506 may be (VDD-V3), which is smaller than (VDD-VSS), and the maximum value of the drain-body voltage (VDB) of the n-type transistor 506 may be (VDD-V4), which is smaller than (VDD-VSS). In addition, as shown in Figure 5, the maximum value of the gate-drain voltage (VGD) of the p-type transistor 508 may be (V3-VSS-VOLED_Min), which is smaller than (VDD-VSS), and the maximum value of the body-drain voltage (VBD) of the p-type transistor 508 may be (V5-VSS-VOLED_Min), which is smaller than (VDD-VSS-VOLED-Min). The minimum voltage at the anode of the light-emitting element 502 may be (VSS+VOLED_Min). In this circuit configuration, when the light-emitting element 502 is driven using high (VDD-VSS), the drain-gate voltage (VDG) of the n-type transistor 506, the gate-drain voltage (VGD) of the p-type transistor 508, the drain-body voltage (VDB) of the n-type transistor 506, or the body-drain voltage (VBD) of the p-type transistor 508 are operated within a safe bias range.

[0082] Figure 6A shows a schematic diagram of a pixel driver circuit 600 for a light-emitting element 602 according to several embodiments of the present disclosure. As shown in Figure 6A, the pixel driver circuit 600 includes a first transistor 606, a second transistor 608, and a first capacitor 610. In some implementations, the first transistor 606 and the second transistor 608 are different types of transistors. In some implementations, the first transistor 606 is an n-type transistor, and the second transistor 608 is a p-type transistor. In some implementations, the first transistor 606 and the second transistor 608 are collectively referred to as a pixel core 604. The first transistor 606 is configured to receive a data signal VDATA and to drive the light-emitting element 602 based on the data signal. The first transistor 606 includes a first gate terminal, a first source terminal, and a first drain terminal. The second transistor 608 includes a second gate terminal for receiving a bias signal from a bias source V3, a second source terminal coupled to the source terminal of the first transistor 606, and a second drain terminal coupled to the light-emitting element 602. The first capacitor 610(C1) is positioned between the first gate terminal of the first transistor 606 and the second gate terminal of the second transistor 608.

[0083] As shown in Figure 6A, the pixel driving circuit 600 further includes a driving sub-circuit 620 and a data writing sub-circuit 630. The driving sub-circuit 620 is coupled to the first gate terminal and first drain terminal of the first transistor 606 to selectively provide a bias signal from the bias source VDD to the first transistor 606, the second transistor 608, and the light-emitting element 602. The data writing sub-circuit 630 is coupled to the driving sub-circuit 620 to selectively provide data signals to the first transistor 606 and the second transistor 608. A second capacitor 612 (C2) is located between the driving sub-circuit 620 and the data writing sub-circuit 630.

[0084] It is understood that the drive subcircuit 620 may be an initialization / compensation / drive subcircuit depending on the different operating periods. For example, in some implementations, the function of the drive subcircuit 620 may be that of an initialization circuit during the initialization period P1. In another example, in some implementations, the function of the drive subcircuit 620 may be that of a compensation circuit during the compensation period P2. In yet another example, in some implementations, the function of the drive subcircuit 620 may be that of a light-emitting drive circuit during the light-emitting period P4. The detailed operation of the initialization period P1, compensation period P2, and light-emitting period P4 will be discussed below.

[0085] In some implementations, when a drive circuit is used to drive the display panel, the source drive circuit may provide display data, such as a data signal VDATA, to multiple subpixels, such as light-emitting elements 602, via multiple source lines within the frame. In some implementations, the switching operation of the data signal VDATA can be controlled by providing switching signals S2-1, S2-2… to a data writing subcircuit 630. Additionally, the drive subcircuit 620 may be operably coupled to the light-emitting elements 602 via the pixel core 604 to cause each subpixel (light-emitting element 602) to emit light for a specific period of time in each frame by providing switching signals EM, S1-1, S1-2… to the drive subcircuit 620. In some implementations, multiple drive subcircuits 620 may operate in conjunction with each other.

[0086] In some implementations, the scanning period of each display frame may include a reset period and an illumination period, and the drive subcircuit 620 drives the light-emitting element 602 by providing a bias signal VDD to the pixel core 604 during the illumination period. In some implementations, the reset period may include an initialization period, a compensation period and a data writing period.

[0087] Figure 6B shows another schematic of a pixel driver circuit 600 for a light-emitting element 602 according to some aspects of the present disclosure. The schematic in Figure 6B is similar to the schematic in Figure 6A, except that the gate terminals of the first capacitor 610 and the second transistor 608 are not coupled to the same voltage source. As shown in Figure 6B, the gate terminal of the second transistor is connected to bias source V3a, and the terminal of the first capacitor 610 is connected to bias source V3b. In some implementations, bias sources V3a and V3b may have different voltage levels. In some implementations, bias sources V3a and V3b may have the same voltage level.

[0088] Figure 7 shows a schematic diagram of a pixel driver circuit 700 for a light-emitting element 702 according to several embodiments of this disclosure. Figure 8 shows a timing diagram illustrating the operation of the pixel driver circuit 700 in Figure 7 according to several embodiments of this disclosure. For the purpose of better illustrating this disclosure, the pixel driver circuit 700 in the timing diagrams of Figures 7 and 8 will be discussed together.

[0089] As shown in Figure 7, the pixel driver circuit 700 may include a first transistor 706, a second transistor 708, a first capacitor 710, and a second capacitor 712. In some implementations, the first transistor 706 and the second transistor 708 are different types of transistors. In some implementations, the first transistor 706 is an n-type transistor, and the second transistor 708 is a p-type transistor. In some implementations, the first transistor 706 and the second transistor 708 are collectively referred to as the pixel core 704. The first transistor 706 includes a first gate terminal, a first source terminal, and a first drain terminal. The second transistor 708 includes a second gate terminal that receives a bias signal from a bias source V3, a second source terminal coupled to the source terminal of the first transistor 706, and a second drain terminal coupled to the light-emitting element 702. The first capacitor 710(C1) is located between the first gate terminal of the first transistor 706 and the second gate terminal of the second transistor 708.

[0090] In addition, switch element S1 is located between the first drain terminal of the first transistor 706 and the first terminal of the second capacitor 712 (C2). Switch element S2 is located between the first terminal of the second capacitor 712 and the bias source VDD / V2. Switch element S3 is located between the first terminal of the second capacitor 712 and the first gate terminal of the first transistor 706. In some implementations, the drive subcircuit 620 in Figures 6A and 6B collectively includes switch elements S1, S2, and S3 in Figure 7. In some implementations, switch elements S1, S2, and S3 can be realized using switching transistors or other suitable elements.

[0091] As shown in Figure 7, the switch element S12 is positioned between the second terminal of the second capacitor 712 and the data signal source providing data signal VDATA, and the switch element S13 is positioned between the second end of the second capacitor 712 and the bias source V1. In some implementations, the data writing subcircuit 630 in Figures 6A and 6B may collectively include the switch elements S12 and S13. In some implementations, the switch elements S12 and S13 may be realized using switching transistors or other suitable elements.

[0092] As shown in Figure 8, during the initialization period P1, a reset signal RS may initiate the reset period by connecting the reset bias VR to the anode of the light-emitting element 702; a control signal S1-1 may turn on the switch element S2 and connect the first end of the second capacitor 712 to the gate terminal of the first transistor 706; a control signal EM may turn on the switch element S2 and connect the bias source G to the first end of the second capacitor 712; and a control signal S2-1 may turn on the switch element S13 and connect the bias source V1 to the second end of the second capacitor 712. In some implementations, the bias source G may collectively provide the bias voltage V2 and the light-emitting voltage VDD for different periods. In some implementations, during the initialization period P1, the first end of the first capacitor 710 is initialized to the first initialization bias V2, and the first end of the second capacitor 712 is initialized to the second initialization bias V1.

[0093] In some implementations, during the initialization period P1, the gate terminal of the first transistor 706 may have an initial voltage. In some implementations, the initial voltage is the first initialization bias V2. In other words, (VG_N1 = V2 = initial voltage). In some implementations, during the initialization period P1, the voltage between the two ends of the first capacitor 710 may be (V2 - V3). In other words, (VCAP_C1 = V2 - V3). In some implementations, if the gate terminals of the first capacitor 610 and the second transistor 608 are not coupled to the same voltage source, the voltage between the two ends of the first capacitor 710 may be (V2 - V3b), as shown in Figure 6B. In other words, (VCAP_C1 = V2 - V3b).

[0094] During the compensation period P2, the control signal EM may turn off the switch element S2, and the control signals S1-2 may turn on the switch element S1. In some implementations, during the compensation period P2, the gate terminal of the first transistor 706 is coupled to the first end of the first capacitor 710, and the first end of the second capacitor 712 is coupled to the drain terminal of the first transistor 706. In some implementations, the initialization bias V2 at the gate terminal of the first transistor 706, the first end of the first capacitor 710, and the first end of the second capacitor 712 is compensated using the drain terminal of the first transistor 706.

[0095] In some implementations, during compensation period P2, the voltage level at the gate terminal of the first transistor 706 may be equal to the sum of the threshold voltage of the first transistor 706, the threshold voltage of the second transistor 708, and voltage V3. In other words, (VG_N1 = VTH_N1 + VTH_P1 + V3). In some implementations, if the gate terminals of the first capacitor 610 and the second transistor 608 are not coupled to the same voltage source, then (VG_N1 = VTH_N1 + VTH_P1 + V3a) is true, as shown in Figure 6B. In some implementations, during compensation period P2, the voltage difference between the two ends of the first capacitor 710 may be the sum of the threshold voltage of the first transistor 706 and the threshold voltage of the second transistor 708. In other words, (VCAP_C1 = VTH_N1 + VTH_P1). In some implementations, if the gate terminals of the first capacitor 610 and the second transistor 608 are not coupled to the same voltage source, the voltage difference between the two ends of the first capacitor 710 is (VCAP_C1=VTH_N1+VTH_P1+(V3a-V3b)), as shown in Figure 6B.

[0096] During the data writing period P3, control signals S1-2 may turn off switch element S1, control signal S2-1 may turn off switch element S13, and control signal S2-2 may turn on switch element S12. In some implementations, during the data writing period P3, the data signal VDATA is provided to the second terminal of the second capacitor 712.

[0097] In some implementations, during the write period P3, the voltage difference between the two ends of the first capacitor 710 may be the sum of the threshold voltage of the first transistor 706, the threshold voltage of the second transistor 708, and the partial voltage at the second end of the second capacitor 712, which is divided by the first capacitor 710 and the second capacitor 712. In other words, the voltage difference between the two ends of the first capacitor 710 is (VCAP_C1=VTH_N1+VTH_P1+ΔV_2 ndend_C2*C2 / (C1+C2)). In some implementations, if the gate terminals of the first capacitor 610 and the second transistor 608 are not coupled to the same voltage source, the voltage difference between the two ends of the first capacitor 710 is (VCAP_C1=VTH_N1+VTH_P1+(V3a-V3b)+ΔV_2, as shown in Figure 6B. nd The result is end_C2*C2 / (C1+C2)).

[0098] During the light emission period P4, the reset signal RS may initiate the light emission period by disconnecting the reset bias VR from the anode of the light-emitting element 702, the control signal EM may turn the switch element S2 on again to provide the light emission voltage VDD, the control signal S1-1 may turn the switch element S2 off, and the control signal S2-2 may turn the switch element S12 off. In some implementations, during the light emission period P4, the light emission voltage VDD may be generated by driving the light-emitting element 702 to emit light based on the data signal VDATA.

[0099] In some implementations, the current I required to cause the light-emitting element 702 to emit light during the light-emitting period P4 is used. EM is (1 / 2*μn*Cox*W_N1 / L_N1*(VGS_N1VTH_N1) 2 ) or (1 / 2*μp*Cox*W_P1 / L_P1*(VSG_P1-VTH_P1]) 2 ) where W / L is the aspect ratio of the first transistor 606 or the second transistor 608, μ is the channel carrier mobility, and Cox is the capacitance of the channel insulating layer of the first transistor 606 or the second transistor 608. In some implementations, the gate-source voltage (VGS) of the first transistor 606 is given by VGS_N1 = [α*ΔV_2 nd end_C2*C2 / (C1+C2)]+VTH_N1, and the gate-source voltage (VGS) of the second transistor 608 is VGS_P1=[β*ΔV_2 nd end_C2*C2 / (C1+C2)]+VTH_P1, where α+β=1.

[0100] In this circuit configuration, when the light-emitting element 702 is driven using high (VDD-VSS), the drain-gate voltage (VDG) of the first transistor 706, the gate-drain voltage (VGD) of the second transistor 708, the drain-body voltage (VDB) of the first transistor 706, or the body-drain voltage (VBD) of the second transistor 708 are operated within a safe bias range.

[0101] Figure 9 shows a schematic diagram of another pixel driver circuit 900 for the light-emitting element 702 according to some aspects of the present disclosure. Figure 10 shows a timing diagram illustrating the operation of the pixel driver circuit 900 in Figure 9 according to some aspects of the present disclosure. For the purpose of better illustrating the present disclosure, the pixel driver circuit 900 in the timing diagrams of Figures 9 and 10 will be discussed together.

[0102] As shown in Figure 9, the drive subcircuit 620 in Figures 6A and 6B collectively includes the switch elements S1, S2, and S3 in Figure 9, and is similar in circuit structure to that in Figure 7. The data writing subcircuit 630 in Figures 6A and 6B may include the switch element S14 in Figure 9. The switch element S14 is located between the second end of the second capacitor 712 and the bias source D. In some implementations, the bias source D may provide a bias voltage V1 and a data signal VDATA for different periods.

[0103] As shown in Figure 10, during the initialization period P1, a reset signal RS may initiate the reset period by connecting the reset bias VR to the anode of the light-emitting element 702; a control signal S1-1 may turn on the switch element S2 and connect the first end of the second capacitor 712 to the gate terminal of the first transistor 706; a control signal EM may turn on the switch element S2 and connect the bias source G to the first end of the second capacitor 712; and a control signal S2-1 may turn on the switch element S14 and connect the bias source V1 to the second end of the second capacitor 712. In some implementations, the bias source G may collectively provide the bias voltage V2 and the light-emitting voltage VDD during different periods. In some implementations, during the initialization period P1, the first end of the first capacitor 710 is initialized to the first initialization bias V2, and the first end of the second capacitor 712 is initialized to the second initialization bias V1.

[0104] During the compensation period P2, the control signal EM may turn off the switch element S2, and the control signals S1-2 may turn on the switch element S1. In some implementations, during the compensation period P2, the gate terminal of the first transistor 706 is coupled to the first end of the first capacitor 710, and the first end of the second capacitor 712 is coupled to the drain terminal of the first transistor 706. In some implementations, the initialization bias V2 at the gate terminal of the first transistor 706, the first end of the first capacitor 710, and the first end of the second capacitor 712 is compensated using the drain terminal of the first transistor 706.

[0105] During the data writing period P3, control signals S1-2 may turn off switch element S1. Control signal S2-1 may keep switch element S14 on, and bias source D may be modified to provide data signal VDATA instead of bias voltage V1.

[0106] During the light emission period P4, the reset signal RS may initiate the light emission period by disconnecting the reset bias VR from the anode of the light-emitting element 702, the control signal EM may turn the switch element S2 on again to provide the light emission voltage VDD, the control signal S1-1 may turn the switch element S2 off, and the control signal S2-1 may turn the switch element S14 off. In some implementations, during the light emission period P4, the light emission voltage VDD may be driven to emit light by the light-emitting element 702 based on the data signal VDATA.

[0107] In this circuit configuration, when the light-emitting element 702 is driven using high (VDD-VSS), the drain-gate voltage (VDG) of the first transistor 706, the gate-drain voltage (VGD) of the second transistor 708, the drain-body voltage (VDB) of the first transistor 706, or the body-drain voltage (VBD) of the second transistor 708 are operated within a safe bias range.

[0108] Figure 11 shows a schematic diagram of another pixel driver circuit 1100 for the light-emitting element 702 according to some aspects of the present disclosure. Figure 12 shows a timing diagram illustrating the operation of the pixel driver circuit 1100 in Figure 11 according to some aspects of the present disclosure. For the purpose of better illustrating the present disclosure, the pixel driver circuit 1100 in the timing diagrams of Figures 11 and 12 will be discussed together.

[0109] As shown in Figure 11, the switch element S4 is positioned between the bias source G and the first end of the second capacitor 712, and the switch element S5 is positioned between the first end of the second capacitor 712 and the gate of the first transistor 706. In some implementations, the drive subcircuit 620 in Figures 6A and 6B collectively includes the switch elements S4 and S5 in Figure 1. In some implementations, the switch elements S4 and S5 can be realized using switching transistors or other suitable elements.

[0110] As shown in Figure 11, the switch element S12 is positioned between the second end of the second capacitor 712 and the data signal source providing data signal VDATA, and the switch element S13 is positioned between the second end of the second capacitor 712 and the bias source V1. In some implementations, the data writing subcircuit 630 in Figures 6A and 6B may collectively include the switch elements S12 and S13. In some implementations, the switch elements S12 and S13 can be realized using switching transistors or other suitable elements. In some implementations, the structure and operation of the switch elements S12 and S13 in Figure 11 may be the same as those of the switch elements S12 and S13 in Figure 7.

[0111] As shown in Figure 12, during the initialization period P1, a reset signal RS may initiate the reset period by connecting the reset bias VR to the anode of the light-emitting element 702, a control signal S1-1 may turn on the switch element S5 to connect the first end of the second capacitor 712 and the gate terminal of the first transistor 706, and a control signal EM may turn on the switch element S4 to connect the bias source G and the first end of the second capacitor 712. In some implementations, the bias source G may collectively provide the bias voltage V2 and the light-emitting voltage VDD for different periods. In some implementations, during the initialization period P1, the first end of the first capacitor 710 is initialized to the first initialization bias V2, and the second end of the second capacitor 712 is initialized to the second initialization bias V1.

[0112] During the compensation period P2, the control signal EM can turn off the switching element S4. In some implementations, during the compensation period P2, the gate terminal of the first transistor 706 is coupled to the first end of the first capacitor 710, and the first end of the second capacitor 712 is coupled to the drain terminal of the first transistor 706. In some implementations, the initialization bias V2 at the gate terminal of the first transistor 706, the first end of the first capacitor 710, and the first end of the second capacitor 712 is compensated using the drain terminal of the first transistor 706.

[0113] During the data writing period P3, control signal S2-1 may turn off switch element S13, and control signal S2-2 may turn on switch element S12. In some implementations, during the data writing period P3, the data signal VDATA is provided to the second terminal of the second capacitor 712.

[0114] During the light emission period P4, the reset signal RS may initiate the light emission period by disconnecting the reset bias VR from the anode of the light-emitting element 702, the control signal EM may turn on the switch element S4 again to provide the light emission voltage VDD, the control signal S1-1 may turn off the switch element S5, and the control signal S2-2 may turn off the switch element S12. In some implementations, during the light emission period P4, the light emission voltage VDD may be generated by driving the light-emitting element 702 to emit light based on the data signal VDATA.

[0115] In this circuit configuration, when the light-emitting element 702 is driven using high (VDD-VSS), the drain-gate voltage (VDG) of the first transistor 706, the gate-drain voltage (VGD) of the second transistor 708, the drain-body voltage (VDB) of the first transistor 706, or the body-drain voltage (VBD) of the second transistor 708 are operated within a safe bias range.

[0116] Figure 13 shows a schematic diagram of another pixel driver circuit 1300 for the light-emitting element 702 according to some aspects of this disclosure. Figure 14 shows a timing diagram illustrating the operation of the pixel driver circuit 1300 in Figure 13 according to some aspects of this disclosure. For the purpose of better illustrating this disclosure, the pixel driver circuit 1300 in the timing diagrams of Figures 13 and 14 will be discussed together.

[0117] As shown in Figure 13, the drive subcircuit 620 in Figures 6A and 6B collectively includes the switch elements S4 and S5 in Figure 13, and is similar to the circuit structure in Figure 11. The data writing subcircuit 630 in Figures 6A and 6B may include the switch element S14 in Figure 13, and is similar to the switch element S14 in Figure 9.

[0118] As shown in Figure 14, during the initialization period P1, a reset signal RS may initiate the reset period by connecting the reset bias VR to the anode of the light-emitting element 702, a control signal S1-1 may turn on the switch element S5 to connect the first end of the second capacitor 712 and the gate terminal of the first transistor 706, and a control signal EM may turn on the switch element S4 to connect the bias source G and the first end of the second capacitor 712. In some implementations, the bias source G may collectively provide the bias voltage V2 and the light-emitting voltage VDD for different periods. In some implementations, during the initialization period P1, the first end of the first capacitor 710 is initialized to the first initialization bias V2, and the second end of the second capacitor 712 is initialized to the second initialization bias V1.

[0119] During the compensation period P2, the control signal EM can turn off the switching element S4. In some implementations, during the compensation period P2, the gate terminal of the first transistor 706 is coupled to the first end of the first capacitor 710, and the first end of the second capacitor 712 is coupled to the drain terminal of the first transistor 706. In some implementations, the initialization bias V2 at the gate terminal of the first transistor 706, the first end of the first capacitor 710, and the first end of the second capacitor 712 is compensated using the drain terminal of the first transistor 706.

[0120] During the data writing period P3, the control signal S2-1 may keep the switch element S14 ON, and the bias source D may be modified to provide the data signal VDATA instead of the bias voltage V1.

[0121] During the light emission period P4, the reset signal RS may initiate the light emission period by disconnecting the reset bias VR from the anode of the light-emitting element 702, the control signal EM may turn on the switch element S4 again to provide the light emission voltage VDD, the control signal S1-1 may turn off the switch element S5, and the control signal S2-1 may turn off the switch element S14. In some implementations, during the light emission period P4, the light emission voltage VDD may be driven to emit light based on the data signal VDATA.

[0122] In this circuit configuration, when the light-emitting element 702 is driven using high (VDD-VSS), the drain-gate voltage (VDG) of the first transistor 706, the gate-drain voltage (VGD) of the second transistor 708, the drain-body voltage (VDB) of the first transistor 706, or the body-drain voltage (VBD) of the second transistor 708 are operated within a safe bias range.

[0123] Figure 15 shows a schematic diagram of another pixel driver circuit 1500 for the light-emitting element 702 according to some aspects of the present disclosure. Figure 16 shows a timing diagram illustrating the operation of the pixel driver circuit 1500 in Figure 15 according to some aspects of the present disclosure. For the purpose of better illustrating the present disclosure, the pixel driver circuit 1500 in the timing diagrams of Figures 15 and 16 will be discussed together.

[0124] As shown in Figure 15, switch element S6 is positioned between the bias source VDD and the first drain terminal of the first transistor 706, switch element S7 is positioned between the first drain terminal of the first transistor 706 and the first end of the second capacitor 712, and switch element S8 is positioned between the first end of the second capacitor 712 and the bias source V2. In some implementations, the drive subcircuit 620 in Figures 6A and 6B collectively includes switch elements S6, S7, and S8 in Figure 15. In some implementations, switch elements S6, S7, and S8 can be realized using switching transistors or other suitable elements.

[0125] As shown in Figure 15, the switch element S12 is positioned between the second end of the second capacitor 712 and the data signal source providing data signal VDATA, and the switch element S13 is positioned between the second end of the second capacitor 712 and the bias source V1. In some implementations, the data writing subcircuit 630 in Figures 6A and 6B may collectively include the switch elements S12 and S13. In some implementations, the switch elements S12 and S13 may be realized using switching transistors or other suitable elements.

[0126] As shown in Figure 16, during the initialization period P1, a reset signal RS may start the reset period by connecting the reset bias VR to the anode of the light-emitting element 702, and a control signal S1-1 may turn on the switch element S8 and connect the bias source V2 to the first end of the second capacitor 712 and the gate terminal of the first transistor 706. A control signal S2-1 may turn on the switch element S13 and connect the bias source V1 and the second end of the second capacitor 712. In some implementations, during the initialization period P1, the first end of the first capacitor 710 is initialized to the first initialization bias V2, and the first end of the second capacitor 712 is initialized to the second initialization bias V1.

[0127] During the compensation period P2, control signal S1-1 may turn off the switch element S8, and control signal S1-2 may turn on the switch element S7. In some implementations, during the compensation period P2, the gate terminal of the first transistor 706 is coupled to the first end of the first capacitor 710, and the first end of the second capacitor 712 is coupled to the drain terminal of the first transistor 706. In some implementations, the initialization bias V2 at the gate terminal of the first transistor 706, the first end of the first capacitor 710, and the first end of the second capacitor 712 is compensated using the drain terminal of the first transistor 706.

[0128] During the data writing period P3, control signals S1-2 may turn off switch element S7, control signal S2-1 may turn off switch element S13 and disconnect bias source V1 and the second end of second capacitor 712, and control signal S2-2 may turn on switch element S12. In some implementations, during the data writing period P3, the data signal VDATA is supplied to the second end of second capacitor 712.

[0129] During the light emission period P4, the reset signal RS may initiate the light emission period by disconnecting the reset bias VR from the anode of the light-emitting element 702, the control signal EM may turn on the switch element S6 to provide the light emission voltage VDD, and the control signal S2-2 may turn off the switch element S12. In some implementations, during the light emission period P4, the light emission voltage VDD may be generated by driving the light-emitting element 702 based on the data signal VDATA.

[0130] In this circuit configuration, when the light-emitting element 702 is driven using high (VDD-VSS), the drain-gate voltage (VDG) of the first transistor 706, the gate-drain voltage (VGD) of the second transistor 708, the drain-body voltage (VDB) of the first transistor 706, or the body-drain voltage (VBD) of the second transistor 708 are operated within a safe bias range.

[0131] Figure 17 shows a schematic diagram of another pixel driver circuit 1700 for the light-emitting element 702 according to some aspects of the present disclosure. Figure 18 shows a timing diagram illustrating the operation of the pixel driver circuit 1700 in Figure 17 according to some aspects of the present disclosure. For the purpose of better illustrating the present disclosure, the pixel driver circuit 1700 in the timing diagrams of Figures 17 and 18 will be discussed together.

[0132] As shown in Figure 17, the drive subcircuit 620 in Figures 6A and 6B collectively includes the switch elements S6, S7, and S8 in Figure 17, and has the same circuit structure as in Figure 15. The data writing subcircuit 630 in Figures 6A and 6B may include the switch element S14 in Figure 17, and is the same as the switch element S14 in Figure 9.

[0133] As shown in Figure 18, during the initialization period P1, a reset signal RS may start the reset period by connecting the reset bias VR to the anode of the light-emitting element 702, and a control signal S1-1 may turn on the switch element S8 and connect the bias source V2 to the first end of the second capacitor 712 and the gate terminal of the first transistor 706. A control signal S2-1 may turn on the switch element S14 and connect the bias source D and the second end of the second capacitor 712. In some implementations, during the initialization period P1, the first end of the first capacitor 710 is initialized to the first initialization bias V2, and the first end of the second capacitor 712 is initialized to the second initialization bias V1.

[0134] During the compensation period P2, control signal S1-1 may turn off the switch element S8, and control signal S1-2 may turn on the switch element S7. In some implementations, during the compensation period P2, the gate terminal of the first transistor 706 is coupled to the first end of the first capacitor 710, and the first end of the second capacitor 712 is coupled to the drain terminal of the first transistor 706. In some implementations, the initialization bias V2 at the gate terminal of the first transistor 706, the first end of the first capacitor 710, and the first end of the second capacitor 712 is compensated using the drain terminal of the first transistor 706.

[0135] During the data writing period P3, control signals S1-2 may turn off switch element S7, and control signal S2-1 may keep switch element S14 ON. The bias source D is changed from providing bias V1 to providing data signal VDATA.

[0136] During the light emission period P4, the reset signal RS may initiate the light emission period by disconnecting the reset bias VR from the anode of the light-emitting element 702, the control signal EM may turn on the switch element S6 to provide the light emission voltage VDD, and the control signal S2-1 may turn off the switch element S14. In some implementations, during the light emission period P4, the light emission voltage VDD may be generated by driving the light-emitting element 702 based on the data signal VDATA.

[0137] In this circuit configuration, when the light-emitting element 702 is driven using high (VDD-VSS), the drain-gate voltage (VDG) of the first transistor 706, the gate-drain voltage (VGD) of the second transistor 708, the drain-body voltage (VDB) of the first transistor 706, or the body-drain voltage (VBD) of the second transistor 708 are operated within a safe bias range.

[0138] Figure 19 shows a schematic diagram of another pixel driver circuit 1900 for the light-emitting element 702 according to some aspects of the present disclosure. Figure 20 shows a timing diagram illustrating the operation of the pixel driver circuit 1900 in Figure 19 according to some aspects of the present disclosure. For the purpose of better illustrating the present disclosure, the pixel driver circuit 1900 in the timing diagrams of Figures 19 and 20 will be discussed together.

[0139] As shown in Figure 19, switch element S9 is positioned between the bias source G and the first drain terminal of the first transistor 706, switch element S10 is positioned between the first drain terminal of the first transistor 706 and the first end of the second capacitor 712, and switch element S11 is positioned between the first end of the second capacitor 712 and the gate terminal of the first transistor 706. In some implementations, the drive subcircuit 620 in Figures 6A and 6B collectively includes switch elements S9, S10, and S11 in Figure 19. In some implementations, switch elements S9, S10, and S11 can be realized using switching transistors or other suitable elements.

[0140] As shown in Figure 19, the switch element S12 is positioned between the second end of the second capacitor 712 and the data signal source providing data signal VDATA, and the switch element S13 is positioned between the second end of the second capacitor 712 and the bias source V1. In some implementations, the data writing subcircuit 630 in Figures 6A and 6B may collectively include the switch elements S12 and S13. In some implementations, the switch elements S12 and S13 may be realized using switching transistors or other suitable elements.

[0141] As shown in Figure 20, during the initialization period P1, a reset signal RS may initiate the reset period by connecting the reset bias VR to the anode of the light-emitting element 702, and a control signal S1-1 may turn on the switch element S11 to connect the gate terminal of the first transistor 706 to the first end of the second capacitor 712. A control signal EM may turn on the switch element S9 to provide the bias signal V2 to the drain terminal of the first transistor 706. A control signal S1-2 may turn on the switch element S10 to connect the first end of the second capacitor 712 and the drain terminal of the first transistor 706. A control signal S2-1 may turn on the switch element S13 to connect the bias source V1 and the second end of the second capacitor 712. In some implementations, during the initialization period P1, the first end of the first capacitor 710 is initialized to the first initialization bias V2, and the first end of the second capacitor 712 is initialized to the second initialization bias V1.

[0142] During the compensation period P2, the control signal EM can turn off the switch element S9. In some implementations, during the compensation period P2, the gate terminal of the first transistor 706 is coupled to the first end of the first capacitor 710, and the first end of the second capacitor 712 is coupled to the drain terminal of the first transistor 706. In some implementations, the initialization bias V2 at the gate terminal of the first transistor 706, the first end of the first capacitor 710, and the first end of the second capacitor 712 is compensated using the drain terminal of the first transistor 706.

[0143] During the data writing period P3, control signals S1-2 may turn off the switch element S10, control signal S2-1 may turn off the switch element S13 and disconnect the bias source V1 and the second end of the second capacitor 712, and control signal S2-2 may turn on the switch element S12. In some implementations, during the data writing period P3, the data signal VDATA is supplied to the second end of the second capacitor 712.

[0144] During the light emission period P4, the reset signal RS may initiate the light emission period by disconnecting the reset bias VR from the anode of the light-emitting element 702, the control signal EM may turn on the switch element S9 again to provide the light emission voltage VDD, and the control signal S2-2 may turn off the switch element S12. In some implementations, during the light emission period P4, the light emission voltage VDD may be driven to emit light based on the data signal VDATA.

[0145] In this circuit configuration, when the light-emitting element 702 is driven using high (VDD-VSS), the drain-gate voltage (VDG) of the first transistor 706, the gate-drain voltage (VGD) of the second transistor 708, the drain-body voltage (VDB) of the first transistor 706, or the body-drain voltage (VBD) of the second transistor 708 are operated within a safe bias range.

[0146] Figure 21 shows a schematic diagram of another pixel driver circuit 2100 for the light-emitting element 702 according to several embodiments of this disclosure. Figure 22 shows a timing diagram illustrating the operation of the pixel driver circuit 2100 in Figure 21 according to several embodiments of this disclosure. For the purpose of better illustrating this disclosure, the pixel driver circuit 2100 in the timing diagrams of Figures 21 and 22 will be discussed together.

[0147] As shown in Figure 21, the drive subcircuit 620 in Figures 6A and 6B collectively includes the switch elements S9, S10, and S11 in Figure 21, and is similar to the circuit structure in Figure 19. The data writing subcircuit 630 in Figures 6A and 6B may include the switch element S14 in Figure 21, and is similar to the switch element S14 in Figure 9.

[0148] As shown in Figure 22, during the initialization period P1, a reset signal RS may initiate the reset period by connecting the reset bias VR to the anode of the light-emitting element 702, and a control signal S1-1 may turn on the switch element S11 to connect the gate terminal of the first transistor 706 to the first end of the second capacitor 712. A control signal EM may turn on the switch element S9 to provide a bias signal V2 to the drain terminal of the first transistor 706. A control signal S1-2 may turn on the switch element S10 to connect the first end of the second capacitor 712 and the drain terminal of the first transistor 706. A control signal S2-1 may turn on the switch element S14 to connect the bias source D and the second end of the second capacitor 712. In some implementations, during the initialization period P1, the first end of the first capacitor 710 is initialized to the first initialization bias V2, and the first end of the second capacitor 712 is initialized to the second initialization bias V1.

[0149] During the compensation period P2, the control signal EM can turn off the switch element S9. In some implementations, during the compensation period P2, the gate terminal of the first transistor 706 is coupled to the first end of the first capacitor 710, and the first end of the second capacitor 712 is coupled to the drain terminal of the first transistor 706. In some implementations, the initialization bias V2 at the gate terminal of the first transistor 706, the first end of the first capacitor 710, and the first end of the second capacitor 712 is compensated using the drain terminal of the first transistor 706.

[0150] During the data writing period P3, control signals S1-2 may turn off switch element S10. Control signal S2-1 may keep switch element S14 ON. The bias source D changes from providing bias V1 to providing data signal VDATA.

[0151] During the light emission period P4, the reset signal RS may initiate the light emission period by disconnecting the reset bias VR from the anode of the light-emitting element 702, the control signal EM may turn on the switch element S9 again to provide the light emission voltage VDD, and the control signal S2-1 may turn off the switch element S14. In some implementations, during the light emission period P4, the light emission voltage VDD may be generated by driving the light-emitting element 702 based on the data signal VDATA.

[0152] In this circuit configuration, when the light-emitting element 702 is driven using high (VDD-VSS), the drain-gate voltage (VDG) of the first transistor 706, the gate-drain voltage (VGD) of the second transistor 708, the drain-body voltage (VDB) of the first transistor 706, or the body-drain voltage (VBD) of the second transistor 708 are operated within a safe bias range.

[0153] Figures 23 to 26 illustrate applications of pixel driving circuits 700, 900, 1100, and 1300 according to several embodiments of the present disclosure. As shown in Figures 23 to 26, one data writing subcircuit 630 may be coupled to multiple driving subcircuits 620. In some implementations, as shown in Figures 23 and 25, a set of second capacitors 712, switch elements S12, and switch elements S13 may be shared by multiple driving subcircuits 620 to drive multiple light-emitting elements 702.

[0154] Similarly, as shown in Figures 24 and 26, a set of second capacitors 712 and switch elements S14 may be shared by multiple drive subcircuits 620 to drive multiple light-emitting elements 702. In addition, as shown in Figures 23 to 26, a switch element S2 or switch element S4 coupled to a bias source G may also be shared by multiple drive subcircuits 620.

[0155] Figures 27 and 28 illustrate another application of the pixel driving circuit 1100 or 1300 according to some aspects of the present disclosure. As shown in Figures 27 and 28, one second capacitor 712 may be shared by multiple driving subcircuits 620 and / or multiple data writing subcircuits 630.

[0156] Figure 29 shows a flowchart of a method 2900 in which a pixel circuit drives a light-emitting element, according to several aspects of the present disclosure. The pixel circuit may include a first transistor 706, a second transistor 708 positioned between the first transistor 706 and the light-emitting element 702. A first capacitor 710 is positioned between the first gate terminal of the first transistor 706 and the second gate terminal of the second transistor, and a second capacitor 712 is positioned between the first transistor 706 and a data signal source VDATA.

[0157] As shown in operation 2902 in Figure 29, during the initialization period, the first end of the first capacitor 710 is initialized to the first initialization bias V2, and the first end of the second capacitor 712 is initialized to the second initialization bias V1. Next, as shown in operation 2904 in Figure 29, during the compensation period, the first end of the first capacitor 710 is compensated to the compensation bias. As shown in operation 2906 in Figure 29, during the data writing period, a data signal is supplied to the first end of the second capacitor 712. As shown in operation 2908 in Figure 29, during the light emission period, the pixel driving circuit drives the light-emitting element 702 to emit light based on the data signal.

[0158] In some implementations, the pixel circuit may further include a reset bias source VR coupled to a second transistor 708 and a light-emitting element 702. During the initialization period, compensation period, and data writing period, the reset bias VR is supplied to the pixel circuit by the reset bias source.

[0159] In some implementations, the sum of the initialization period, compensation period, data writing period, and illumination period is the frame period. In some implementations, a first initialization bias V2 is provided to the first end of the first capacitor 710, and a first bias V3 is provided to the second end of the first capacitor 710. A second initialization bias V1 is provided to the first end of the second capacitor 712. The first end of the first capacitor 710 and the second end of the second capacitor are coupled together.

[0160] In some implementations, the first initialization bias V2 at the first end of the first capacitor 710 is discharged to a reset bias through the first transistor 706 and the second transistor 708. The compensation bias is at least the sum of the first threshold voltage of the first transistor and the second threshold voltage of the second transistor.

[0161] The foregoing description of a particular implementation can be readily modified and / or adapted for various applications. Such adaptations and modifications are therefore intended to be within the meaning and scope of the equivalents of the disclosed implementations, based on the teachings and guidance presented herein.

[0162] The breadth and scope of this disclosure should not be limited by any of the exemplary implementations described above, but should be defined solely by the following claims and their equivalents.

Claims

1. A first transistor configured to receive a data signal and drive a light-emitting element based on the data signal, the first transistor having a first gate terminal, a first source terminal, and a first drain terminal; A second transistor having a second gate terminal for receiving a first bias signal from a first bias source, a second source terminal coupled to the first transistor, and a second drain terminal coupled to the light-emitting element; A first capacitor positioned between the first gate terminal and the second bias source; A drive subcircuit coupled to the first gate terminal and the first drain terminal to selectively provide the first transistor with a second bias signal from a third bias source; A data writing subcircuit coupled to the drive subcircuit for selectively providing the data signal to the first transistor; and A second capacitor located between the drive subcircuit and the data writing subcircuit. Equipped with, The first transistor and the second transistor are different types of transistors. The aforementioned drive sub-circuit is A first switching element positioned between the first drain terminal and the first terminal of the second capacitor; A second switching element positioned between the first terminal of the second capacitor and the third bias source; and A third switching element is positioned between the first terminal and the first gate terminal of the second capacitor. It has, The aforementioned data writing sub-circuit is A twelfth switching element positioned between the second terminal of the second capacitor and the data signal source; and A thirteenth switching element is positioned between the second terminal of the second capacitor and the second initialization bias source. Having, Pixel driving circuit.

2. A first transistor configured to receive a data signal and drive a light-emitting element based on the data signal, the first transistor having a first gate terminal, a first source terminal, and a first drain terminal; A second transistor having a second gate terminal for receiving a first bias signal from a first bias source, a second source terminal coupled to the first transistor, and a second drain terminal coupled to the light-emitting element; A first capacitor positioned between the first gate terminal and the second bias source; A drive subcircuit coupled to the first gate terminal and the first drain terminal to selectively provide the first transistor with a second bias signal from a third bias source; A data writing subcircuit coupled to the drive subcircuit for selectively providing the data signal to the first transistor; and A second capacitor located between the drive subcircuit and the data writing subcircuit. Equipped with, The first transistor and the second transistor are different types of transistors. The aforementioned drive sub-circuit is A first switching element positioned between the first drain terminal and the first terminal of the second capacitor; A second switching element positioned between the first terminal of the second capacitor and the third bias source; and A third switching element is positioned between the first terminal and the first gate terminal of the second capacitor. It has, The aforementioned data writing sub-circuit is A 14th switching element is positioned between the second terminal of the second capacitor and the data signal source. Having, Pixel driving circuit.

3. A first transistor configured to receive a data signal and drive a light-emitting element based on the data signal, the first transistor having a first gate terminal, a first source terminal, and a first drain terminal; A second transistor having a second gate terminal for receiving a first bias signal from a first bias source, a second source terminal coupled to the first transistor, and a second drain terminal coupled to the light-emitting element; A first capacitor positioned between the first gate terminal and the second bias source; A drive subcircuit coupled to the first gate terminal and the first drain terminal to selectively provide the first transistor with a second bias signal from a third bias source; A data writing subcircuit coupled to the drive subcircuit for selectively providing the data signal to the first transistor; and A second capacitor located between the drive subcircuit and the data writing subcircuit. Equipped with, The first transistor and the second transistor are different types of transistors. The aforementioned drive sub-circuit is A fourth switching element positioned between the third bias source and the first terminal of the second capacitor; and A fifth switching element is positioned between the first terminal and the first gate terminal of the second capacitor. It has, The aforementioned data writing sub-circuit is A twelfth switching element positioned between the second terminal of the second capacitor and the data signal source; and A thirteenth switching element is positioned between the second terminal of the second capacitor and the second initialization bias source. Having, Pixel driving circuit.

4. A first transistor configured to receive a data signal and drive a light-emitting element based on the data signal, the first transistor having a first gate terminal, a first source terminal, and a first drain terminal; A second transistor having a second gate terminal for receiving a first bias signal from a first bias source, a second source terminal coupled to the first transistor, and a second drain terminal coupled to the light-emitting element; A first capacitor positioned between the first gate terminal and the second bias source; A drive subcircuit coupled to the first gate terminal and the first drain terminal to selectively provide the first transistor with a second bias signal from a third bias source; A data writing subcircuit coupled to the drive subcircuit for selectively providing the data signal to the first transistor; and A second capacitor located between the drive subcircuit and the data writing subcircuit. Equipped with, The first transistor and the second transistor are different types of transistors. The aforementioned drive sub-circuit is A fourth switching element positioned between the third bias source and the first terminal of the second capacitor; and A fifth switching element is positioned between the first terminal and the first gate terminal of the second capacitor. It has, The aforementioned data writing sub-circuit is A 14th switching element is positioned between the second terminal of the second capacitor and the data signal source. Having, Pixel driving circuit.

5. A first transistor configured to receive a data signal and drive a light-emitting element based on the data signal, the first transistor having a first gate terminal, a first source terminal, and a first drain terminal; A second transistor having a second gate terminal for receiving a first bias signal from a first bias source, a second source terminal coupled to the first transistor, and a second drain terminal coupled to the light-emitting element; A first capacitor positioned between the first gate terminal and the second bias source; A drive subcircuit coupled to the first gate terminal and the first drain terminal to selectively provide the first transistor with a second bias signal from a third bias source; A data writing subcircuit coupled to the drive subcircuit for selectively providing the data signal to the first transistor; and A second capacitor located between the drive subcircuit and the data writing subcircuit. Equipped with, The first transistor and the second transistor are different types of transistors. The aforementioned drive sub-circuit is A sixth switching element positioned between the first source terminal and the third bias source; A seventh switching element positioned between the first source terminal and the first terminal of the second capacitor; and An eighth switching element positioned between the first terminal of the second capacitor and the first initialization bias source. It has, The aforementioned data writing sub-circuit is A twelfth switching element positioned between the second terminal of the second capacitor and the data signal source; and A thirteenth switching element is positioned between the second terminal of the second capacitor and the second initialization bias source. Having, Pixel driving circuit.

6. A first transistor configured to receive a data signal and drive a light-emitting element based on the data signal, the first transistor having a first gate terminal, a first source terminal, and a first drain terminal; A second transistor having a second gate terminal for receiving a first bias signal from a first bias source, a second source terminal coupled to the first transistor, and a second drain terminal coupled to the light-emitting element; A first capacitor positioned between the first gate terminal and the second bias source; A drive subcircuit coupled to the first gate terminal and the first drain terminal to selectively provide the first transistor with a second bias signal from a third bias source; A data writing subcircuit coupled to the drive subcircuit for selectively providing the data signal to the first transistor; and A second capacitor located between the drive subcircuit and the data writing subcircuit. Equipped with, The first transistor and the second transistor are different types of transistors. The aforementioned drive sub-circuit is A sixth switching element positioned between the first source terminal and the third bias source; A seventh switching element positioned between the first source terminal and the first terminal of the second capacitor; and An eighth switching element positioned between the first terminal of the second capacitor and the first initialization bias source. It has, The aforementioned data writing sub-circuit is A 14th switching element is positioned between the second terminal of the second capacitor and the data signal source. Having, Pixel driving circuit.

7. A first transistor configured to receive a data signal and drive a light-emitting element based on the data signal, the first transistor having a first gate terminal, a first source terminal, and a first drain terminal; A second transistor having a second gate terminal for receiving a first bias signal from a first bias source, a second source terminal coupled to the first transistor, and a second drain terminal coupled to the light-emitting element; A first capacitor positioned between the first gate terminal and the second bias source; A drive subcircuit coupled to the first gate terminal and the first drain terminal to selectively provide the first transistor with a second bias signal from a third bias source; A data writing subcircuit coupled to the drive subcircuit for selectively providing the data signal to the first transistor; and A second capacitor located between the drive subcircuit and the data writing subcircuit. Equipped with, The first transistor and the second transistor are different types of transistors. The aforementioned drive sub-circuit is A ninth switching element positioned between the first source terminal and the third bias source; A tenth switching element positioned between the first source terminal and the first terminal of the second capacitor; and An eleventh switching element is positioned between the first terminal and the first gate terminal of the second capacitor. It has, The aforementioned data writing sub-circuit is A twelfth switching element positioned between the second terminal of the second capacitor and the data signal source; and A thirteenth switching element is positioned between the second terminal of the second capacitor and the second initialization bias source. Having, Pixel driving circuit.

8. A first transistor configured to receive a data signal and drive a light-emitting element based on the data signal, the first transistor having a first gate terminal, a first source terminal, and a first drain terminal; A second transistor having a second gate terminal for receiving a first bias signal from a first bias source, a second source terminal coupled to the first transistor, and a second drain terminal coupled to the light-emitting element; A first capacitor positioned between the first gate terminal and the second bias source; A drive subcircuit coupled to the first gate terminal and the first drain terminal to selectively provide the first transistor with a second bias signal from a third bias source; A data writing subcircuit coupled to the drive subcircuit for selectively providing the data signal to the first transistor; and A second capacitor located between the drive subcircuit and the data writing subcircuit. Equipped with, The first transistor and the second transistor are different types of transistors. The aforementioned drive sub-circuit is A ninth switching element positioned between the first source terminal and the third bias source; A tenth switching element positioned between the first source terminal and the first terminal of the second capacitor; and An eleventh switching element is positioned between the first terminal and the first gate terminal of the second capacitor. It has, The aforementioned data writing sub-circuit is A 14th switching element is positioned between the second terminal of the second capacitor and the data signal source. Having, Pixel driving circuit.

9. The first capacitor is positioned between the first gate terminal of the first transistor and the second gate terminal of the second transistor. A pixel driving circuit according to any one of claims 1 to 8.

10. The pixel driving circuit according to any one of claims 1 to 8, wherein the scanning period of each display frame includes a reset period and an illumination period, and the driving subcircuit provides the second bias signal to the first transistor during the illumination period in order to drive the light-emitting element.

11. The pixel driving circuit according to claim 10, wherein the reset period includes an initialization period, a compensation period, and a data writing period, and the driving subcircuit provides a first initialization bias signal to the first capacitor during the initialization period.

12. The pixel driving circuit according to claim 11, wherein the data writing subcircuit provides a second initialization bias signal to the second capacitor during the initialization period and the compensation period.

13. The pixel driving circuit according to claim 11, wherein the data writing subcircuit provides the data signal to the first transistor during the data writing period.

14. The pixel driving circuit according to any one of claims 1 to 8, wherein the data writing subcircuit and the second capacitor are shared by more than one driving subcircuit.

15. The pixel driving circuit according to any one of claims 1 to 8, wherein the first bias source and the second bias source are provided by different voltage sources.

16. The pixel driving circuit according to any one of claims 1 to 8, wherein the first bias source and the second bias source are provided by the same voltage source.

17. Light-emitting element; and Drive circuit for driving the light-emitting element Equipped with, The aforementioned drive circuit is A first type of transistor that receives a data signal and includes a first gate terminal, a first source terminal, and a first drain terminal; A second type of transistor comprising a second gate terminal for receiving a first bias signal from a first bias source, a second source terminal coupled to the first drain terminal, and a second drain terminal coupled to the light-emitting element; A first capacitor positioned between the first gate terminal and the second bias source; A drive subcircuit coupled to the first gate terminal and the first source terminal to provide the data signal and a third bias signal from a third bias source; A data writing subcircuit coupled to the drive subcircuit to provide the data signal to the drive subcircuit; and A second capacitor located between the drive subcircuit and the data writing subcircuit. It has, The aforementioned drive sub-circuit is A first switching element positioned between the first source terminal and the first terminal of the second capacitor; A second switching element positioned between the first terminal of the second capacitor and the third bias source; and A third switching element is positioned between the first terminal and the first gate terminal of the second capacitor. It has, The aforementioned data writing sub-circuit is A twelfth switching element positioned between the second terminal of the second capacitor and the data signal source; and A thirteenth switching element is positioned between the second terminal of the second capacitor and the second initialization bias source. Having, Light-emitting device.

18. Light-emitting element; and Drive circuit for driving the light-emitting element Equipped with, The aforementioned drive circuit is A first type of transistor that receives a data signal and includes a first gate terminal, a first source terminal, and a first drain terminal; A second type of transistor comprising a second gate terminal for receiving a first bias signal from a first bias source, a second source terminal coupled to the first drain terminal, and a second drain terminal coupled to the light-emitting element; A first capacitor positioned between the first gate terminal and the second bias source; A drive subcircuit coupled to the first gate terminal and the first source terminal to provide the data signal and a third bias signal from a third bias source; A data writing subcircuit coupled to the drive subcircuit to provide the data signal to the drive subcircuit; and A second capacitor located between the drive subcircuit and the data writing subcircuit. It has, The aforementioned drive sub-circuit is A first switching element positioned between the first source terminal and the first terminal of the second capacitor; A second switching element positioned between the first terminal of the second capacitor and the third bias source; and A third switching element is positioned between the first terminal and the first gate terminal of the second capacitor. It has, The aforementioned data writing sub-circuit is A 14th switching element is positioned between the second terminal of the second capacitor and the data signal source. Having, Light-emitting device.

19. Light-emitting element; and Drive circuit for driving the light-emitting element Equipped with, The aforementioned drive circuit is A first type of transistor that receives a data signal and includes a first gate terminal, a first source terminal, and a first drain terminal; A second type of transistor comprising a second gate terminal for receiving a first bias signal from a first bias source, a second source terminal coupled to the first drain terminal, and a second drain terminal coupled to the light-emitting element; A first capacitor positioned between the first gate terminal and the second bias source; A drive subcircuit coupled to the first gate terminal and the first source terminal to provide the data signal and a third bias signal from a third bias source; A data writing subcircuit coupled to the drive subcircuit to provide the data signal to the drive subcircuit; and A second capacitor located between the drive subcircuit and the data writing subcircuit. It has, The aforementioned drive sub-circuit is A fourth switching element positioned between the third bias source and the first terminal of the second capacitor; and A fifth switching element is positioned between the first terminal and the first gate terminal of the second capacitor. It has, The aforementioned data writing sub-circuit is A twelfth switching element positioned between the second terminal of the second capacitor and the data signal source; and A thirteenth switching element is positioned between the second terminal of the second capacitor and the second initialization bias source. Having, Light-emitting device.

20. Light-emitting element; and Drive circuit for driving the light-emitting element Equipped with, The aforementioned drive circuit is A first type of transistor that receives a data signal and includes a first gate terminal, a first source terminal, and a first drain terminal; A second type of transistor comprising a second gate terminal for receiving a first bias signal from a first bias source, a second source terminal coupled to the first drain terminal, and a second drain terminal coupled to the light-emitting element; A first capacitor positioned between the first gate terminal and the second bias source; A drive subcircuit coupled to the first gate terminal and the first source terminal to provide the data signal and a third bias signal from a third bias source; A data writing subcircuit coupled to the drive subcircuit to provide the data signal to the drive subcircuit; and A second capacitor located between the drive subcircuit and the data writing subcircuit. It has, The aforementioned drive sub-circuit is A fourth switching element positioned between the third bias source and the first terminal of the second capacitor; and A fifth switching element is positioned between the first terminal and the first gate terminal of the second capacitor. It has, The aforementioned data writing sub-circuit is A 14th switching element is positioned between the second terminal of the second capacitor and the data signal source. Having, Light-emitting device.

21. Light-emitting element; and Drive circuit for driving the light-emitting element Equipped with, The aforementioned drive circuit is A first type of transistor that receives a data signal and includes a first gate terminal, a first source terminal, and a first drain terminal; A second type of transistor comprising a second gate terminal for receiving a first bias signal from a first bias source, a second source terminal coupled to the first drain terminal, and a second drain terminal coupled to the light-emitting element; A first capacitor positioned between the first gate terminal and the second bias source; A drive subcircuit coupled to the first gate terminal and the first source terminal to provide the data signal and a third bias signal from a third bias source; A data writing subcircuit coupled to the drive subcircuit to provide the data signal to the drive subcircuit; and A second capacitor located between the drive subcircuit and the data writing subcircuit. It has, The aforementioned drive sub-circuit is A sixth switching element positioned between the first source terminal and the third bias source; A seventh switching element positioned between the first source terminal and the first terminal of the second capacitor; and An eighth switching element positioned between the first terminal of the second capacitor and the first initialization bias source. It has, The aforementioned data writing sub-circuit is A twelfth switching element positioned between the second terminal of the second capacitor and the data signal source; and A thirteenth switching element is positioned between the second terminal of the second capacitor and the second initialization bias source. Having, Light-emitting device.

22. Light-emitting element; and Drive circuit for driving the light-emitting element Equipped with, The aforementioned drive circuit is A first type of transistor that receives a data signal and includes a first gate terminal, a first source terminal, and a first drain terminal; A second type of transistor comprising a second gate terminal for receiving a first bias signal from a first bias source, a second source terminal coupled to the first drain terminal, and a second drain terminal coupled to the light-emitting element; A first capacitor positioned between the first gate terminal and the second bias source; A drive subcircuit coupled to the first gate terminal and the first source terminal to provide the data signal and a third bias signal from a third bias source; A data writing subcircuit coupled to the drive subcircuit to provide the data signal to the drive subcircuit; and A second capacitor located between the drive subcircuit and the data writing subcircuit. It has, The aforementioned drive sub-circuit is A sixth switching element positioned between the first source terminal and the third bias source; A seventh switching element positioned between the first source terminal and the first terminal of the second capacitor; and An eighth switching element positioned between the first terminal of the second capacitor and the first initialization bias source. It has, The aforementioned data writing sub-circuit is A 14th switching element is positioned between the second terminal of the second capacitor and the data signal source. Having, Light-emitting device.

23. Light-emitting element; and Drive circuit for driving the light-emitting element Equipped with, The aforementioned drive circuit is A first type of transistor that receives a data signal and includes a first gate terminal, a first source terminal, and a first drain terminal; A second type of transistor comprising a second gate terminal for receiving a first bias signal from a first bias source, a second source terminal coupled to the first drain terminal, and a second drain terminal coupled to the light-emitting element; A first capacitor positioned between the first gate terminal and the second bias source; A drive subcircuit coupled to the first gate terminal and the first source terminal to provide the data signal and a third bias signal from a third bias source; A data writing subcircuit coupled to the drive subcircuit to provide the data signal to the drive subcircuit; and A second capacitor located between the drive subcircuit and the data writing subcircuit. It has, The aforementioned drive sub-circuit is A ninth switching element positioned between the first source terminal and the third bias source; A tenth switching element positioned between the first source terminal and the first terminal of the second capacitor; and An eleventh switching element is positioned between the first terminal and the first gate terminal of the second capacitor. It has, The aforementioned data writing sub-circuit is A twelfth switching element positioned between the second terminal of the second capacitor and the data signal source; and A thirteenth switching element is positioned between the second terminal of the second capacitor and the second initialization bias source. Having, Light-emitting device.

24. Light-emitting element; and Drive circuit for driving the light-emitting element Equipped with, The aforementioned drive circuit is A first type of transistor that receives a data signal and includes a first gate terminal, a first source terminal, and a first drain terminal; A second type of transistor comprising a second gate terminal for receiving a first bias signal from a first bias source, a second source terminal coupled to the first drain terminal, and a second drain terminal coupled to the light-emitting element; A first capacitor positioned between the first gate terminal and the second bias source; A drive subcircuit coupled to the first gate terminal and the first source terminal to provide the data signal and a third bias signal from a third bias source; A data writing subcircuit coupled to the drive subcircuit to provide the data signal to the drive subcircuit; and A second capacitor located between the drive subcircuit and the data writing subcircuit. It has, The aforementioned drive sub-circuit is A ninth switching element positioned between the first source terminal and the third bias source; A tenth switching element positioned between the first source terminal and the first terminal of the second capacitor; and An eleventh switching element is positioned between the first terminal and the first gate terminal of the second capacitor. It has, The aforementioned data writing sub-circuit is A 14th switching element is positioned between the second terminal of the second capacitor and the data signal source. Having, Light-emitting device.

25. The light-emitting device according to any one of claims 17 to 24, wherein the first type of transistor is a p-type transistor and the second type of transistor is an n-type transistor.

26. The light-emitting device according to any one of claims 17 to 24, further comprising a reset signal coupled to the second drain terminal.

27. The light-emitting device according to any one of claims 17 to 24, wherein the first bias source and the second bias source are provided by different voltage sources.

28. The light-emitting device according to any one of claims 17 to 24, wherein the first bias source and the second bias source are provided by the same voltage source.

29. A method for driving a light-emitting element using a pixel driving circuit according to any one of claims 1 to 8, wherein the method is: During the initialization period, the first terminal of the first capacitor is initialized to a first initialization bias, and the first terminal of the second capacitor is initialized to a second initialization bias; During the compensation period, the first end of the first capacitor is compensated to the compensation bias; During the data writing period, the step of providing a data signal to the first end of the second capacitor; and During the light emission period, the light-emitting element is driven to emit light based on the data signal. A method that includes [a certain feature].

30. The pixel driving circuit further comprises the second transistor and a reset bias source coupled to the light-emitting element, and the method is During the initialization period, the compensation period, and the data writing period, the reset bias is provided to the pixel drive circuit by the reset bias source. The method according to claim 29, further comprising:

31. The method according to claim 29, wherein the sum of the initialization period, the compensation period, the data writing period, and the light emission period is the frame period.

32. The steps of initializing the first end of the first capacitor to the first initialization bias and initializing the first end of the second capacitor to the second initialization bias are as follows: Steps include providing the first initialization bias to the first end of the first capacitor; Steps include providing a first bias to the second end of the first capacitor; The step of providing the second initialization bias to the first end of the second capacitor; and The step of connecting the first end of the first capacitor and the second end of the second capacitor. Having, The method according to claim 30.

33. The step of compensating the first end of the first capacitor to the compensation bias is: Steps to discharge the first initialization bias at the first end of the first capacitor to the reset bias through the first transistor and the second transistor. Having, The method according to claim 32.

34. The method according to claim 33, wherein the voltage difference between the first end and the second end of the first capacitor is based on the sum of the first threshold voltage of the first transistor and the second threshold voltage of the second transistor.

35. The method according to claim 33, wherein the compensation bias is based on the sum of the first threshold voltage of the first transistor and the second threshold voltage of the second transistor.

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