Indication device

Abstract

To control a pixel circuit with less control signals.SOLUTION: A drive circuit controls a pixel circuit with control signal pulses. In a threshold compensation period, a threshold compensation transistor is held ON to write a threshold compensation voltage. In a data write period after the threshold compensation period, a data signal is written. A pulse width of control signal pulses is at least twice as long as the data write period. The drive circuit turns a first transistor ON with a starting edge of a first control pulse before the data write period starts, holds the first transistor ON and turns a second transistor ON with a starting edge of a second control signal pulse after the threshold compensation period ends so as to start the data write period, and turns the first transistor OFF with an ending edge of the first control signal pulse to end the data write period.SELECTED DRAWING: Figure 3

Description

Technical Field

[0001] The present disclosure relates to a display device.

Background Art

[0002] Since an OLED (Organic Light-Emitting Diode) element is a current-driven self-emitting element, it does not require a backlight and has advantages such as low power consumption, a wide viewing angle, and a high contrast ratio, and is expected in the development of flat panel displays.

[0003] An active matrix (AM) type OLED display device includes a transistor for selecting a pixel and a driving transistor for supplying current to the pixel. The transistor in the OLED display device is a TFT (Thin Film Transistor), and generally, an LTPS (Low Temperature Poly-silicon) TFT is used.

[0004] TFTs have variations in threshold voltage and charge mobility. Since the driving transistor determines the light emission intensity of the OLED display device, such variations in electrical characteristics pose a problem. Therefore, a correction circuit for correcting variations and fluctuations in the threshold voltage of the driving transistor is implemented in the pixel circuit of a general OLED display device.

[0005] For example, in an OLED display device, image retention may occur, and this phenomenon is called image retention. For example, after displaying a black-and-white checkerboard pattern for a specific time and then attempting to display intermediate gradations across the entire screen, afterimages of checkerboards with different gradations are displayed for a while.

[0006] This is due to the history effect of the driving transistor. The history effect refers to a phenomenon in a field-effect transistor where the drain current when the voltage between the gate and source changes from a high voltage to a low voltage and the drain current when the voltage changes from a low voltage to a high voltage are different.

[0007] In other words, the drain current when switching from black to an intermediate grayscale is different from the drain current when switching from white to an intermediate grayscale, resulting in a difference in the light emission intensity of the OLED display device. Furthermore, because this difference in drain current continues for several frames or more, it is perceived as an afterimage. [Prior art documents] [Patent Documents]

[0008] [Patent Document 1] U.S. Patent Application Publication No. 2019 / 0156751 [Patent Document 2] U.S. Patent Application Publication No. 2005 / 0200618 [Overview of the Initiative] [Problems that the invention aims to solve]

[0009] Image retention is due to the current transient response characteristics caused by the hysteresis effect of the driving TFT and the threshold voltage compensation characteristics of the driving TFT by the pixel circuit. In addition, if the threshold voltage compensation of the driving TFT is insufficient, image quality may deteriorate. Furthermore, in order to achieve higher resolution and narrower bezels in display devices, it is desirable to be able to control the pixel circuit with fewer control signals. [Means for solving the problem]

[0010] A display device according to one aspect of the present disclosure includes a display area including a plurality of pixel circuit rows and a drive circuit. Each of the plurality of pixel circuit rows includes a plurality of pixel circuits. Each of the plurality of pixel circuits includes a drive transistor for controlling the amount of current to a light-emitting element, a holding capacitor for holding the control voltage of the drive transistor, a first transistor and a second transistor connected in series for transmitting a data signal to the holding capacitor, and a threshold compensation transistor for writing the threshold compensation voltage of the drive transistor to the holding capacitor. The drive circuit shifts a control signal pulse from the preceding stage to the succeeding stage in the plurality of pixel circuit rows at regular intervals. The pulse width of the control signal pulse is at least twice the regular interval. During the threshold compensation period, the drive circuit writes the threshold compensation voltage to the holding capacitor while keeping the threshold compensation transistor ON. During the data writing period after the threshold compensation period, the drive circuit writes a data signal to the holding capacitor while keeping the threshold compensation transistor OFF and the first and second transistors ON. The pulse width of the control signal pulse is at least twice the data writing period. The drive circuit controls the first transistor with a first control signal pulse. The drive circuit controls the second transistor with a second control signal pulse that is different from the first control signal pulse. The drive circuit turns the first transistor ON by the start edge of the first control signal pulse before the start of the data writing period. After the end of the threshold compensation period, the drive circuit keeps the first transistor ON and turns the second transistor ON by the start edge of the second control signal pulse to start the data writing period. The drive circuit turns the first transistor OFF by the end edge of the first control signal pulse to end the data writing period. [Effects of the Invention]

[0011] According to one aspect of this disclosure, the image quality of a display device can be improved. [Brief explanation of the drawing]

[0012] [Figure 1]A configuration example of an OLED display device is schematically shown. [Figure 2] A configuration example of a pixel circuit and control signals according to an embodiment of the present specification is shown. [Figure 3] An example of a timing chart of signals for controlling the pixel circuit shown in FIG. 2 is shown. [Figure 4] Another example of a timing chart of signals for controlling the pixel circuit shown in FIG. 2 is shown. [Figure 5] The layout of control signal lines for transmitting control signals to the pixel circuit shown in FIG. 2 is schematically shown. [Figure 6] Different examples of pixel circuits and control signals are shown. [Figure 7] Different examples of pixel circuits and control signals are shown. [Figure 8] Different examples of pixel circuits and control signals are shown. [Figure 9] Different examples of pixel circuits and control signals are shown. [Figure 10] An example of a timing chart of signals for controlling the pixel circuit shown in FIG. 9 is shown. [Figure 11] The layout of control signal lines for transmitting control signals to the pixel circuit shown in FIG. 9 is schematically shown. [Figure 12] Other configuration examples of pixel circuits and control signals are shown. [Figure 13] An example of a timing chart of signals for controlling the pixel circuit shown in FIG. 12 is shown. [Figure 14] The layout of control signal lines for transmitting control signals to the pixel circuit shown in FIG. 12 is schematically shown. [Figure 15] Other configuration examples of pixel circuits and control signals are shown. [Figure 16] An example of a timing chart of signals for controlling the pixel circuit shown in FIG. 15 is shown. [Figure 17] Other configuration examples of pixel circuits and control signals are shown. [Figure 18] A plurality of consecutive pixel circuit row regions are schematically shown. [Figure 19] Other configuration examples of pixel circuits and control signals are shown. [Figure 20]Shows another configuration example of a pixel circuit and control signals. [Figure 21] Schematically shows a plurality of consecutive pixel circuit row regions. [Figure 22] Shows another configuration example of a pixel circuit and control signals.

Mode for Carrying Out the Invention

[0013] Hereinafter, embodiments will be described with reference to the drawings. The same reference numerals are assigned to common configurations in each figure. For ease of explanation, the dimensions and shapes of the illustrated objects may be exaggerated in some cases.

[0014] Hereinafter, a technique for improving drive current control in a light-emitting display device using a light-emitting element that emits light by a drive current, such as an OLED (Organic Light-Emitting Diode) display device, will be disclosed. More specifically, a technique for appropriately compensating the threshold value of a drive transistor by a small number of control signals of a pixel circuit and improving display quality will be disclosed.

[0015] For example, image retention is caused by the current transient response characteristics due to the history effect of the drive transistor and the characteristics of the threshold voltage compensation of the drive transistor by the pixel circuit. Not limited to image retention, when the threshold voltage compensation of the drive transistor is insufficient, the image quality may deteriorate.

[0016] The display device according to an embodiment of the present specification writes a voltage for compensating the threshold value of the drive transistor into the holding capacitor of the pixel circuit, and then writes a data signal into the holding capacitor. The pixel circuit includes switch transistors connected in series that transmit the data signal to the holding capacitor. The display device controls these switch transistors by different control signal pulses. The pulse widths of these control signal pulses are twice or more the data writing period, and the phases (edge times) are different. By controlling the switch transistors connected in series with control signal pulses having different phases for a predetermined period, it is possible to effectively perform threshold compensation of the drive transistor with a small number of control signals.

[0017] [Display device configuration] Embodiments of this specification will be described in more detail below. Figure 1 schematically shows an example of the configuration of an OLED display device 1. The OLED display device 1 is composed of a TFT (Thin Film Transistor) substrate 10 on which OLED elements and pixel circuits are formed, and a thin film encapsulation structure (TFE: Thin Film Encapsulation) 20 that encapsulates organic light-emitting elements. The thin film encapsulation structure 20 is one of the encapsulation structure parts, and as another example, the encapsulation structure part may include an encapsulation substrate that encapsulates organic light-emitting elements and a joint part (glass frit seal part) that joins the TFT substrate 10 and the encapsulation substrate. For example, dry air or nitrogen is sealed between the TFT substrate 10 and the encapsulation substrate.

[0018] A scanning driver 31, an emission driver 32, a protection circuit 33, a driver IC 34, and a demultiplexer 36 are arranged around the cathode electrode formation region 14 outside the display area 25 of the TFT substrate 10. The driver IC 34 is connected to an external device via an FPC (Flexible Printed Circuit) 35. These circuits are included in the control circuit that controls the OLED display device 1. Some of these circuits may be omitted.

[0019] The scanning driver 31 drives the scan lines of the TFT substrate 10. The emission driver 32 drives the light emission control lines to control the light emission period of each pixel. As will be described later, in addition to the light emission control lines, the emission driver 32 may also drive scan lines for threshold compensation of the drive transistor or for data writing. For this reason, the scanning driver 31 is sometimes called the first scanning driver and the emission driver 32 is sometimes called the second scanning driver. The light emission control lines are also scan lines because they sequentially select pixel circuit rows. The scan lines and light emission control lines are control lines for controlling the pixel circuit.

[0020] The scanning driver 31 and the emission driver 32 are included in the drive circuit that drives the pixel circuit. A circuit that outputs control signals similar to those of the scanning driver 31 and the emission driver 32 may be located on only one side of the display area 25.

[0021] The scanning driver 31 and the emission driver 32 are located on opposite sides of the display area 25. The scanning lines and light emission control lines extend in the left-right direction and are arranged vertically, for example, in Figure 1. The driver IC 34 is mounted using, for example, an anisotropic conductive film (ACF).

[0022] The protection circuit 33 prevents electrostatic discharge damage to elements within the pixel circuit. The driver IC 34 supplies power and timing signals (control signals) to the scanning driver 31 and the emission driver 32. Furthermore, the driver IC 34 supplies power and data signals to the demultiplexer 36.

[0023] The demultiplexer 36 sequentially outputs the output of one pin of the driver IC 34 to d data lines (where d is an integer greater than or equal to 2). The data lines extend vertically and are arranged horizontally, for example, in Figure 1. The demultiplexer 36 drives d times the number of output pins of the driver IC 34 by switching the data line to which the data signal from the driver IC 34 is output d times within the scanning period.

[0024] As described later, each pixel circuit includes a drive TFT (drive transistor) and a holding capacitor that holds the signal voltage that determines the drive current of the drive TFT. The data signal transmitted by the data line is corrected according to the threshold of the drive TFT and stored in the holding capacitor. The voltage of the holding capacitor determines the gate voltage (Vgs) of the drive TFT. The corrected data signal changes the conductance of the drive TFT analogously, supplying a forward bias current corresponding to the light emission gradation to the OLED element.

[0025] [Pixel circuit configuration] Figure 2 shows an example configuration of a pixel circuit 200 and a control signal according to one embodiment of this specification. The pixel circuit 200 is contained in the Nth (N is an integer) row of pixel circuits. The pixel circuit 200 includes seven transistors (TFTs) M11 to M17, each having a gate, source, and drain. In this example, all transistors M11 to M17 are P-type TFTs (the polarity of the transistors is P-type).

[0026] Transistor M11 is a drive transistor that controls the amount of current supplied to the OLED element E1. The source of drive transistor M11 is connected to power line 241, which transmits the power supply potential PVDD. Drive transistor M11 controls the amount of current supplied to the OLED element E1 from power line 241 according to the voltage held by the retaining capacitor C10. The retaining capacitor C10 holds the written voltage throughout one frame period. The cathode of the OLED element E1 is connected to power line 204, which transmits the power supply potential PVEE from the cathode power supply.

[0027] In the configuration example shown in Figure 2, the retaining capacitor C10 is composed of capacitors C11 and C12 connected in series. One end of the retaining capacitor C10 is supplied with the anode power supply potential PVDD, and the other end is connected to the source / drain of switch transistors M13 and M14. The other end of the retaining capacitor C10 is connected to the gate of drive transistor M11.

[0028] More specifically, one end of capacitor C12 is connected to power line 241. One end of capacitor C11 is connected to the source / drain of switch transistors M13 and M14. The intermediate nodes of capacitors C11 and C12 are connected to the gate of drive transistor M11.

[0029] The voltage across the retaining capacitor C10 is the voltage between the gate of the drive transistor M11 and the anode power supply line 241. The source of the drive transistor M11 is connected to the anode power supply line 241, and the source potential is the anode power supply potential PVDD. Therefore, the retaining capacitor C10 retains the gate-source voltage of the drive transistor M11. In the configuration example in Figure 2, capacitor C12 retains the gate-source voltage of the drive transistor M11.

[0030] Transistor M15 is a light emission control switch transistor that controls the supply of drive current to the OLED element E1 and the resulting ON / OFF of light emission. The source of transistor M15 is connected to the drain of drive transistor M11. Transistor M15 switches the current supply to the OLED element E1 connected to its drain ON / OFF. The gate of transistor M15 is connected to control signal line 232A, and transistor M15 is controlled by the light emission control signal Em_N input to the gate from emission driver 32. The light emission control signal is a selection signal that controls the light emission of the OLED element E1.

[0031] Transistor M16 operates to supply the reset potential Vrst to the anode of the OLED element E1. One end of the source / drain of transistor M16 is connected to the power line 242 that transmits the reset potential Vrst, and the other end is connected to the anode of the OLED element E1.

[0032] The gate of transistor M16 is connected to the control signal line 231A, and transistor M16 is controlled by the selection signal S_N. When transistor M16 is turned ON by the selection signal S_N from the scanning driver 31, it supplies the reset potential Vrst transmitted by the power line 242 to the anode of the OLED element E1. In addition, transistors M15 and M16 supply the reset potential Vrst to the gate of the drive transistor M11 via transistor M12.

[0033] Transistor M12 is a switch transistor (threshold compensation transistor) that writes a voltage for threshold correction (threshold compensation) of the drive transistor M11 to the retaining capacitor C10, and is a transistor that resets the gate potential of the drive transistor M11. The source and drain of transistor M12 are connected to the gate and drain of the drive transistor M11. Therefore, when transistor M12 is ON, the drive transistor M11 is in a diode connection state.

[0034] Transistor M14 is a switch transistor (threshold compensation transistor) that writes a voltage to the holding capacitor C10 for threshold compensation of the drive transistor M11. Transistor M14 controls whether or not a reference potential Vref is supplied to the holding capacitor C10. One source / drain end of transistor M14 is connected to the power line 202 that transmits the reference potential Vref, and the other end is connected to one end of capacitor C11. The gate of transistor M14 is connected to the control signal line 231A, and transistor M14 is controlled by a selection signal S_N input to the gate from the scan driver 31.

[0035] Transistors M12, M16, and M14 are controlled by the selection signal S_N. Therefore, these transistors M12, M16, and M14 are switched ON / OFF simultaneously. While they are ON, the gate potential of the drive transistor M11 is reset when transistor M15 is ON. Subsequently, transistor M15 is turned OFF. When transistors M12 and M14 are ON, transistor M11 constitutes a diode-connected transistor. A threshold compensation voltage is written to the retaining capacitor C10 between the power supply potential PVDD and the reference potential Vrst.

[0036] Transistors M13 and M17, connected in series, are switch transistors that select the pixel circuit to supply the data signal and write the data signal (data signal voltage) Vdata to the retaining capacitor C10.

[0037] One source / drain end of transistor M13 is connected to the retaining capacitor C10, and the other end is connected to one source / drain end of transistor M17. More specifically, one source / drain end of transistor M13 is connected to one end of capacitor C11. The other source / drain end of transistor M17 is connected to the data line 237, which transmits the data signal Vdata.

[0038] The gate of transistor M13 is connected to control signal line 232B, which transmits the light emission control signal Em_N-1 from the emission driver 32. Transistor M13 is controlled by the light emission control signal Em_N-1. The light emission control signal Em_N-1 is a signal that controls the light emission of the (N-1)th row of pixel circuitry, but transistor M13 is not a transistor that controls the light emission of the OLED element E1, but rather a switch transistor that controls the supply of the data signal Vdata to the holding capacitor C10.

[0039] The gate of transistor M17 is connected to control signal line 231B, which transmits the selection signal S_N+1 from the scanning driver 31. Transistor M17 is controlled by the selection signal S_N+1, which is the signal that selects the (N+1)th pixel circuit row. Transistor M17 controls the supply of the data signal Vdata to the holding capacitor C10.

[0040] When transistors M13 and M17 are ON simultaneously, they supply the data signal Vdata, provided by the driver IC 34 via the data line 237, to the holding capacitor C10. As described above, since transistors M13 and M17 are controlled by control signals from different pixel circuit rows, they can only supply the data signal Vdata to the holding capacitor C10 during the period when the two control signals S_N+1 and Em_N-1 are simultaneously at a low level.

[0041] Figure 3 is an example of a timing chart for the signals that control the pixel circuit 200 shown in Figure 2, illustrating the operation of writing the threshold compensation voltage of the drive transistor M11 and the data signal Vdata to the pixel circuit of the Nth row of pixel circuits.

[0042] Specifically, Figure 3 shows the time variation of the signal potential levels in one frame for the selection signal S_N of the Nth pixel circuit row to which the data signal Vdata is written, the selection signal S_N+1 of the (N+1)th pixel circuit row, the light emission control signal Em_N-1 of the (N-1)th pixel circuit row, and the light emission control signal Em_N of the Nth pixel circuit row. The selection signal is one of the control signals and is also called the scanning signal.

[0043] In the timing chart of Figure 3, the 1H period is the period during which the data signal Vdata is written to the pixel circuit, and is the period during which transistors M13 and M17 are ON. The threshold compensation period is 1H or longer, and is 2H in the example of Figure 3.

[0044] At time T1, the selection signal S_N+1 is High, and transistor M17 is OFF. Also, the light emission control signal Em_N is Low, and transistor M15 is ON.

[0045] At time T1, the selection signal S_N changes from High to Low, and the light emission control signal Em_N-1 changes from Low to High. In response to the change in the selection signal S_N, transistors M12, M14, and M16 change from OFF to ON. In response to the change in the light emission control signal Em_N-1, transistor M13 changes from ON to OFF.

[0046] Transistor M16 turns ON, and the supply of reset potential Vrst to the anode of OLED element E1 begins. Transistors M12, M15, and M16 are ON, and the supply of reset potential Vrst to the gate of drive transistor M11 begins. This state continues from time T1 to time T2. Time T1 to T2 is the reset period for the anode potential of OLED element E1 and the gate potential of drive transistor M11. The length of the period from time T1 to time T2 is 1H. During the reset period, transistors M13 and M17 are OFF.

[0047] At time T2, the selection signal S_N+1 changes from High to Low. Also at time T2, the light emission control signal Em_N changes from Low to High. In response to the change in the selection signal S_N+1, transistor M17 changes from OFF to ON. In response to the change in the light emission control signal Em_N, transistor M15 changes from ON to OFF. As transistor M15 changes to OFF, the supply of the reset potential Vrst to the gate of drive transistor M11 stops.

[0048] At time T2, transistors M12, M14, M16, and M17 are ON. Transistors M13 and M15 are OFF. Since transistors M13 and M15 are OFF and transistors M12 and M14 are ON, the threshold compensation voltage is written to the retaining capacitor C10. At time T2, the writing of the threshold compensation voltage to the retaining capacitor C10 begins. As described above, with the start of the threshold compensation period, transistor M17 is turned ON from OFF by the start edge of the selection signal S_N+1.

[0049] From time T2 to time T3, the potential levels of signals S_N, S_N+1, Em_N-1, and Em_N are maintained. At time T3, the selection signal S_N changes from Low to High. Furthermore, the light emission control signal Em_N-1 changes from High to Low.

[0050] In response to the change in the selection signal S_N, transistors M12, M14, and M16 change from ON to OFF. As a result, the writing of the threshold compensation voltage to the holding capacitor C10 is completed at time T3. The period from time T2 to T3 is the writing period to the holding capacitor C10 of the threshold compensation voltage, and in the example in Figure 3, its length is 2H.

[0051] In response to the change in the light emission control signal Em_N-1 at time T3, transistor M13 changes from OFF to ON. With transistors M13 and M17 ON, the data signal Vdata is written to the retaining capacitor C10 via transistors M13 and M17. At time T3, the writing of the data signal Vdata to the retaining capacitor C10 begins. From time T3 to time T4, the potential levels of signals S_N, S_N+1, Em_N-1, and Em_N are maintained.

[0052] At time T4, the selection signal S_N+1 changes from Low to High. This causes transistor M17 to turn from ON to OFF, completing the data writing process to the Nth pixel circuit row. The period from time T3 to T4 is the data writing period to the Nth pixel circuit row, and its length is 1H. After time T4, the selection signal S_N+1 remains High.

[0053] At time T4, the light emission control signal Em_N changes from High to Low. This causes transistor M15 to change from OFF to ON. This provides a drive current to the OLED element E1, causing the OLED element to start emitting light.

[0054] Figure 4 is another example of a timing chart for the signals controlling the pixel circuit 200 shown in Figure 2, illustrating the operation for writing the threshold compensation voltage of the drive transistor M11 and the data signal Vdata to the pixel circuit of the Nth row of pixel circuit. Specifically, Figure 4 shows the time variation of the signal potential levels of the selection signal S_N, selection signal S_N+1, light emission control signal Em_N-1, and light emission control signal Em_N in one frame.

[0055] In the timing chart of Figure 4, the 1H period is the period during which the data signal Vdata is written to the pixel circuit, and is the period during which transistors M13 and M17 are ON. The threshold compensation period is 1H or longer, and is 1H in the example of Figure 4.

[0056] At time T11, the selection signal S_N+1 is High, and transistor M17 is OFF. Also, the light emission control signal Em_N is Low, and transistor M15 is ON.

[0057] At time T11, the selection signal S_N changes from High to Low, and the light emission control signal Em_N-1 changes from Low to High. In response to the change in the selection signal S_N, transistors M12, M14, and M16 change from OFF to ON. In response to the change in the light emission control signal Em_N-1, transistor M13 changes from ON to OFF.

[0058] Transistor M16 turns ON, and the supply of reset potential Vrst to the anode of OLED element E1 begins. Transistors M12, M15, and M16 are ON, and the supply of reset potential Vrst to the gate of drive transistor M11 begins. This state continues from time T11 to time T12. The period from time T11 to T12 is the reset period for the anode potential of OLED element E1 and the gate potential of drive transistor M11. The length of the period from time T11 to time T12 is 1H.

[0059] At time T12, the selection signal S_N+1 changes from High to Low. Also at time T12, the light emission control signal Em_N changes from Low to High. In response to the change in the selection signal S_N+1, transistor M17 changes from OFF to ON. In response to the change in the light emission control signal Em_N, transistor M15 changes from ON to OFF. As transistor M15 changes to OFF, the supply of the reset potential Vrst to the gate of drive transistor M11 stops.

[0060] At time T12, transistors M12, M14, M16, and M17 are ON. Transistors M13 and M15 are OFF. Since transistors M13 and M15 are OFF and transistors M12 and M14 are ON, the threshold compensation voltage is written to the retaining capacitor C10. At time T12, the writing of the threshold compensation voltage to the retaining capacitor C10 begins.

[0061] From time T12 to time T13, the potential levels of signals S_N, S_N+1, Em_N-1, and Em_N are maintained. At time T13, the selection signal S_N changes from Low to High. Furthermore, the light emission control signal Em_N-1 changes from High to Low.

[0062] In response to the change in the selection signal S_N, transistors M12, M14, and M16 change from ON to OFF. As a result, the writing of the threshold compensation voltage to the holding capacitor C10 is completed at time T13. The period from time T12 to T13 is the writing period for the threshold compensation voltage to the holding capacitor C10, and in the example in Figure 4, its length is 1H.

[0063] In response to the change in the light emission control signal Em_N-1 at time T13, transistor M13 changes from OFF to ON. With transistors M13 and M17 ON, the data signal Vdata is written to the retaining capacitor C10 via transistors M13 and M17. At time T13, the writing of the data signal Vdata to the retaining capacitor C10 begins. From time T13 to time T14, the potential levels of signals S_N, S_N+1, Em_N-1, and Em_N are maintained.

[0064] At time T14, the selection signal S_N+1 changes from Low to High. This causes transistor M17 to turn from ON to OFF, completing the data writing process to the Nth pixel circuit row. The period from time T13 to T14 is the data writing period to the Nth pixel circuit row, and its length is 1H. After time T14, the selection signal S_N+1 remains High.

[0065] At time T14, the light emission control signal Em_N changes from High to Low. This causes transistor M15 to change from OFF to ON. As a result, a drive current is supplied to the OLED element E1, and the OLED element begins to emit light.

[0066] In the above example, transistors M13 and M17 are controlled by different control signal pulses. Specifically, transistor M17 is controlled by the control signal pulse S_N+1, and transistor M13 is controlled by the control signal pulse Em_N-1.

[0067] Transistor M17 (an example of the first transistor) is turned ON at time T2 or T12 before the start of the data writing period by the starting edge of the pulse of control signal S_N+1. Transistor M13 (an example of the second transistor) is turned ON at time T3 or T13, the start of the data writing period, by the starting edge of the pulse of control signal Em_N-1. Transistor M17 is turned OFF at time T4 or T14, the end of the data writing period, by the ending edge of the pulse of control signal S_N+1.

[0068] In the timing chart explained with reference to Figure 4, the pulse width of the control signal is 2H, which is twice the data writing period. The threshold compensation period is the same as the data writing period. In the timing chart explained with reference to Figure 3, the pulse width of the control signal is 3H, which is three times the data writing period. The threshold compensation period is twice the data writing period. The pulse width of the control signal pulse can be made even longer, thereby extending the threshold compensation period.

[0069] By controlling transistors M13 and M17 with two or more different control signal pulses, a threshold compensation period can be formed before a 1H data writing period with fewer control signal pulses. Furthermore, a desired threshold compensation period can be formed by adjusting the pulse width of the control signal pulses.

[0070] Figure 5 schematically shows the layout of control signal lines that transmit control signals to the pixel circuit 200. The display area 25 includes multiple pixel circuits 200 that control the light emission of each OLED element of multiple pixels. In Figure 5, one pixel circuit is indicated by the code 200 as an example. In the configuration example of Figure 5, the pixel circuits 200 are arranged in a matrix. The layout of the pixel circuits is not particularly limited.

[0071] In a color OLED display device, each OLED element emits light of one of the following colors, for example, red, blue, or green. Multiple pixel circuits 200 constitute a pixel circuit array. In the configuration example shown in Figure 5, one pixel circuit row consists of multiple pixel circuits 200 arranged in the X-axis direction (left-right direction in Figure 5). Each pixel circuit row is controlled by a common control signal line.

[0072] The data lines (not shown) are connected to a single pixel circuit array, and each pixel circuit array is connected to a single pixel circuit in each pixel circuit row. The data lines transmit a data signal specifying the luminescence intensity to the pixel circuit of the selected pixel circuit row.

[0073] The first shift register 310 is included in the scan driver 31. The first shift register 310 includes a plurality of linked shift register units 312. Each shift register unit 312 is a flip-flop. In Figure 5, one shift register unit is indicated by the code 312 as an example. The (N-1) to (N+3) stage shift register units 312 are shown as examples. The code within a shift register unit 312 indicates the control signal output by that shift register unit 312. For example, shift register unit S_N outputs a selection signal S_N.

[0074] The second shift register 320 is included in the emission driver 32. The second shift register 320 includes a plurality of linked shift register units 322. Each shift register unit 322 is a flip-flop. In Figure 5, one shift register unit is indicated by the code 322 as an example. The code within a shift register unit 322 indicates the control signal that the shift register unit 322 outputs. For example, the shift register Em_N outputs the light emission control signal Em_N.

[0075] The first shift register 310 drives control signal lines 231A and 231B, which extend along the X-axis, according to a clock signal (not shown). Control signal lines 231A and 231B transmit the same control signal output from each shift register unit 312. In Figure 5, two control signal lines from one shift register unit 312 are indicated, for example, by reference numerals 231A and 231B.

[0076] The second shift register 320 drives control signal lines 232A and 232B, which extend along the X-axis, according to a clock signal (not shown). Control signal lines 232A and 232B transmit the same control signal output from each shift register unit 322. In Figure 5, two control signal lines from one shift register unit 322 are indicated, for example, by symbols 232A and 232B.

[0077] Control signal line 231A transmits the selection signal S_K output by the K-th (K is an integer) shift register unit 312 to the K-th pixel circuit row. Control signal line 231B transmits the selection signal S_K output by the K-th shift register unit 312 to the (K-1)-th pixel circuit row.

[0078] Control signal line 232A transmits the light emission control signal Em_K output by the K-stage shift register unit 322 to the K-stage pixel circuit row. Control signal line 232B transmits the light emission control signal Em_K output by the K-stage shift register unit 322 to the (K+1)-stage pixel circuit row.

[0079] The pixel circuits 200 that constitute a row of pixel circuits are connected to common control signal lines 231A, 231B, 232A, and 232B, and are controlled by the same control signal transmitted by these control signal lines. The control method of the pixel circuits 200 is described with reference to Figure 3 or 4.

[0080] The first shift register 310 sequentially outputs signal pulses according to a start pulse signal and a clock signal (not shown). The start pulse signal is a 1-frame period signal and has the same pulse width as the pulses output by each control signal line in Figures 3 and 4. In the example timing chart in Figure 3, the first shift register 310 shifts a signal pulse with a width of 3H from the previous stage to the next stage every 1H in the connected shift register unit 312. The reference output level of the shift register unit 312 is High, and the potential level of the signal pulse is Low.

[0081] In the example timing chart in Figure 4, the first shift register 310 shifts a signal pulse with a width of 2H from the preceding stage to the succeeding stage every 1H in the connected shift register unit 312.

[0082] The second shift register 320 sequentially outputs signal pulses according to a start pulse signal and a clock signal (not shown). The start pulse signal is a signal with a 1-frame period and has the same pulse width as the pulses output by each control signal line in Figure 3 or Figure 4. In the example timing chart in Figure 3, the second shift register 320 shifts a signal pulse with a width of 3H from the preceding stage to the succeeding stage every 1H in the connected shift register unit 322.

[0083] In this way, the second shift register 320 shifts the signal pulse for a pixel circuit row over a 3H period from the previous stage to the next stage every 1H. The reference output level of the shift register unit 322 is Low, and the signal pulse is High. In other words, the polarity of the signal pulse output by the second shift register 320 is the opposite of the polarity of the signal pulse output by the first shift register 310.

[0084] As shown in Figure 3, the phase of the signal pulses output by the same-stage shift register units, the first shift register 310 and the second shift register 320, differs by 1H. The pulse from the second shift register 320 lags behind the pulse from the first shift register 310 by 1H. In other words, the shift register units 312 of stages (K-1), K, and (K+1) and the shift register units 322 of stages (K-2), (K-1), and K output pulses during the same period.

[0085] In the example timing chart in Figure 4, the second shift register 320 shifts a signal pulse with a width of 2H from the preceding stage to the succeeding stage every 1H in the connected shift register unit 322. Other aspects are the same as in the example in Figure 3.

[0086] As described above, the first shift register 310 shifts the control signal pulse of the first polarity (Low) from the preceding stage to the succeeding stage in the pixel circuit row at regular intervals. The second shift register 320 shifts the control signal pulse of the opposite polarity (High) of the first polarity from the preceding stage to the succeeding stage in the pixel circuit row at regular intervals. The control signal pulses from the first shift register 310 and the control signal pulses from the second shift register 320 are synchronized.

[0087] The pixel circuit is controlled by two control signals S_N and S_N+1 from the first shift register 310 and two control signals Em_N-1 and Em_N from the second shift register 320. Controlling the pixel circuit with two control signals from different shift registers simplifies the layout of the control lines. Note that the circuit that generates the above control signals may include circuits other than shift registers. Also, the data writing period may be different from the clock period of the control signal pulses, for example, shorter than the clock period. These points are the same in other configuration examples described below.

[0088] Figure 6 shows different examples of pixel circuits and control signals. The main difference from the pixel circuit 200 shown in Figure 2 will be explained. The pixel circuit 210 shown in Figure 6 includes a retaining capacitor C20 instead of the retaining capacitor C10 of the pixel circuit 200 shown in Figure 2. The retaining capacitor C20 is composed of capacitors C21 and C22 connected in series between the power line 241 that transmits the anode power supply potential PVDD and the gate of the drive transistor M11.

[0089] A power line 241 is connected to one end of capacitor C22. One end of capacitor C21 is connected to the other end of capacitor C22. The gate of drive transistor M11 is connected to the other end of capacitor C21. The source / drain of transistors M14 and M13 are connected to the intermediate node between capacitors C21 and C22. The timing chart of the control signal that controls the pixel circuit 210 is the same as the timing chart shown in Figure 3 or 4, and the operation of the transistors is also the same.

[0090] Figure 7 shows different examples of pixel circuits and control signals. The main difference from the pixel circuit 200 shown in Figure 2 will be explained. The pixel circuit 220 shown in Figure 7 includes transistors M22 and M24 instead of transistors M12 and M14 of the pixel circuit 200 shown in Figure 2. Transistors M22 and M24 are the first threshold compensation transistor and the second threshold compensation transistor.

[0091] Transistors M22 and M24 are N-type transistors (the polarity of the transistor is N-type). For example, P-type transistors are low-temperature polysilicon TFTs, while N-type transistors are oxide semiconductor TFTs. Oxide semiconductor TFTs have lower leakage currents and can better maintain the charge of their retained capacitance compared to low-temperature polysilicon TFTs.

[0092] The gate of transistor M22 is input with the light emission control signal Em_N-1, and its ON / OFF state is controlled. The gate of transistor M24 is also input with the light emission control signal Em_N-1, and its ON / OFF state is controlled. The timing chart for the control signals that control the pixel circuit 220 is the same as the timing chart shown in Figure 3 or 4.

[0093] The operation of the pixel circuit 220 will be explained according to the example timing chart in Figure 3. At time T1, the selection signal S_N+1 is High, and transistor M17 is OFF. Also, the light emission control signal Em_N is Low, and transistor M15 is ON.

[0094] At time T1, the selection signal S_N changes from High to Low, and the light emission control signal Em_N-1 changes from Low to High. In response to the change in the selection signal S_N, transistor M16 changes from OFF to ON. In response to the change in the light emission control signal Em_N-1, transistors M22 and M24 change from OFF to ON, and transistor M13 changes from ON to OFF.

[0095] Transistor M16 turns ON, and the supply of reset potential Vrst to the anode of OLED element E1 begins. Transistors M22, M15, and M16 are ON, and the supply of reset potential Vrst to the gate of drive transistor M11 begins. This state continues from time T1 to time T2.

[0096] At time T2, the selection signal S_N+1 changes from High to Low. Also at time T2, the light emission control signal Em_N changes from Low to High. In response to the change in the selection signal S_N+1, transistor M17 changes from OFF to ON. In response to the change in the light emission control signal Em_N, transistor M15 changes from ON to OFF. As transistor M15 changes to OFF, the supply of the reset potential Vrst to the gate of drive transistor M11 stops.

[0097] At time T2, transistors M22, M24, M16, and M17 are ON. Transistors M13 and M15 are OFF. Since transistors M13 and M15 are OFF and transistors M22 and M24 are ON, the threshold compensation voltage is written to the retaining capacitor C10. At time T2, the writing of the threshold compensation voltage to the retaining capacitor C10 begins.

[0098] At time T3, the selection signal S_N changes from Low to High. Furthermore, the light emission control signal Em_N-1 changes from High to Low. In response to the change in the selection signal S_N, transistor M16 changes from ON to OFF. In response to the change in the light emission control signal Em_N-1, transistors M22 and M24 change from ON to OFF. Therefore, at time T3, the writing of the threshold compensation voltage to the holding capacitor C10 is completed.

[0099] In response to the change in the light emission control signal Em_N-1 at time T3, transistor M13 changes from OFF to ON. With transistors M13 and M17 ON, the data signal Vdata is written to the retention capacitor C10 via transistors M13 and M17. At time T3, the writing of the data signal Vdata to the retention capacitor C10 begins.

[0100] At time T4, the selection signal S_N+1 changes from Low to High. This causes transistor M17 to turn from ON to OFF, completing the data writing to the Nth pixel circuit row. At time T4, the light emission control signal Em_N changes from High to Low. This causes transistor M15 to turn from OFF to ON. This provides a drive current to the OLED element E1, causing the OLED element to start emitting light.

[0101] Figure 8 shows different examples of pixel circuits and control signals. The main difference from the pixel circuit 200 shown in Figure 2 will be explained. The pixel circuit 230 shown in Figure 8 includes transistors M22, M23, M24, and M27 instead of transistors M12, M13, M14, and M17 of the pixel circuit 200 shown in Figure 2. Transistors M22, M23, M24, and M27 are N-type transistors.

[0102] If the leakage current of threshold compensation transistors M22 and M24 is large, the gate potential will fluctuate during the data retention period, causing flicker. Also, if the leakage current of data writing transistors M23 and M27 is large, the data signal will leak into the potential of the retention capacitance, causing crosstalk. On the other hand, for the drive transistor M11, a transistor with high mobility is desirable to achieve high resolution and high frequency driving.

[0103] Therefore, the drive transistor M11 is made P-type, and the threshold compensation transistors M22 and M24 and the data writing transistors M23 and M27 are made N-type. Low-temperature polysilicon TFTs with high writing capability can be applied to the drive transistors, and oxide semiconductor TFTs with low leakage current can be applied to the threshold compensation transistors and data writing transistors. By combining transistors with different characteristics in this way, it is possible to simultaneously achieve high-resolution display and high-frequency driving, as well as low-frequency driving that enables low power consumption.

[0104] The gate of transistor M22 receives the light emission control signal Em_N-1, and its ON / OFF state is controlled. The gate of transistor M23 receives the selection signal S_N, and its ON / OFF state is controlled. The gate of transistor M24 receives the light emission control signal Em_N-1, and its ON / OFF state is controlled. The gate of transistor M27 receives the light emission control signal Em_N, and its ON / OFF state is controlled.

[0105] Compared to the control signal for pixel circuit 200 in Figure 2, the selection signal S_N+1 is omitted. The timing chart for the control signal controlling pixel circuit 230 is the same as the timing chart shown in Figure 3 or 4, but with the selection signal S_N+1 removed. The layout of the control signal lines is the same as the layout shown in Figure 5, but with the control signal line 231B removed.

[0106] The operation of the pixel circuit 230 will be explained according to the example timing chart in Figure 3. At time T1, the light emission control signal Em_N is Low, transistor M27 is OFF, and transistor M15 is ON.

[0107] At time T1, the selection signal S_N changes from High to Low, and the light emission control signal Em_N-1 changes from Low to High. In response to the change in the selection signal S_N, transistor M23 changes from ON to OFF, and transistor M16 changes from OFF to ON. In response to the change in the light emission control signal Em_N-1, transistors M22 and M24 change from OFF to ON.

[0108] Transistor M16 turns ON, and the supply of reset potential Vrst to the anode of OLED element E1 begins. Transistors M22, M15, and M16 are ON, and the supply of reset potential Vrst to the gate of drive transistor M11 begins. This state continues from time T1 to time T2.

[0109] At time T2, the light emission control signal Em_N changes from Low to High. In response to the change in the light emission control signal Em_N, transistor M27 (an example of the first transistor) changes from OFF to ON, and transistor M15 changes from ON to OFF. When transistor M15 changes to OFF, the supply of the reset potential Vrst to the gate of drive transistor M11 stops.

[0110] At time T2, transistors M22, M24, M16, and M27 are ON. Transistors M23 and M15 are OFF. Since transistors M23 and M15 are OFF and transistors M22 and M24 are ON, the threshold compensation voltage is written to the retaining capacitor C10. At time T2, the writing of the threshold compensation voltage to the retaining capacitor C10 begins.

[0111] At time T3, the selection signal S_N changes from Low to High. Furthermore, the light emission control signal Em_N-1 changes from High to Low. In response to the change in the selection signal S_N, transistor M16 changes from ON to OFF. In response to the change in the light emission control signal Em_N-1, transistors M22 and M24 change from ON to OFF. Therefore, at time T3, the writing of the threshold compensation voltage to the holding capacitor C10 is completed.

[0112] In response to the change in the selection signal S_N at time T3, transistor M23 (an example of a second transistor) changes from OFF to ON. With transistors M23 and 27 ON, the data signal Vdata is written to the retention capacitor C10 via transistors M23 and 27. At time T3, the writing of the data signal Vdata to the retention capacitor C10 begins.

[0113] At time T4, the light emission control signal Em_N changes from High to Low. This causes transistor M27 to turn from ON to OFF, completing the data writing to the Nth pixel circuit row. Furthermore, transistor M15 changes from OFF to ON. This provides a drive current to the OLED element E1, causing the OLED element to start emitting light.

[0114] Figure 9 shows different examples of pixel circuits and control signals. The main difference from the pixel circuit 200 shown in Figure 2 will be explained. The pixel circuit 240 shown in Figure 9 includes transistors M22, M23, M24, and M27 instead of transistors M12, M13, M14, and M17 of the pixel circuit 200 shown in Figure 2. Transistors M22, M23, M24, and M27 are N-type transistors.

[0115] In this example as well, by making the drive transistor M11 a P-type and the threshold compensation transistors M22 and M24 and data writing transistors M23 and M27 N-type, it is possible to apply a low-temperature polysilicon TFT with high writing capability to the drive transistor and an oxide semiconductor TFT with low leakage current to the threshold compensation transistor and data writing transistor. By combining transistors with different characteristics in this way, it is possible to simultaneously achieve high-resolution display and high-frequency driving, as well as low-frequency driving that enables low power consumption.

[0116] The gate of transistor M22 is input with the light emission control signal Em_N-1, and its ON / OFF state is controlled. The gate of transistor M23 is input with the light emission control signal Em_N, and its ON / OFF state is controlled. The gate of transistor M24 is input with the light emission control signal Em_N-1, and its ON / OFF state is controlled. The gate of transistor M27 is input with the light emission control signal Em_N+2, and its ON / OFF state is controlled.

[0117] Figure 10 shows an example of a timing chart for the signals that control the pixel circuit 240 shown in Figure 9. Figure 10 shows the time variation of the selection signal S_N, the light emission control signal Em_N-1, the light emission control signal Em_N, and the light emission control signal Em_N+2 over one frame. Figure 10 shows the change in signal potential level.

[0118] In the timing chart of Figure 10, the 1H period is the period during which the data signal Vdata is written to the pixel circuit, and is the period during which transistors M23 and M27 are ON. The threshold compensation period is 1H or longer, and is 2H in the example of Figure 10.

[0119] At time T1, the light emission control signal Em_N+2 is Low, and transistor M27 is OFF. Also, the light emission control signal Em_N is Low, transistor M15 is ON, and transistor M23 is OFF.

[0120] At time T1, the selection signal S_N changes from High to Low, and the light emission control signal Em_N-1 changes from Low to High. In response to the change in the selection signal S_N, transistor M16 changes from OFF to ON. In response to the change in the light emission control signal Em_N-1, transistors M22 and M24 change from OFF to ON.

[0121] Transistor M16 turns ON, and the supply of reset potential Vrst to the anode of OLED element E1 begins. Transistors M22, M15, and M16 are ON, and the supply of reset potential Vrst to the gate of drive transistor M11 begins. This state continues from time T1 to time T2. The period from time T1 to T2 is the reset period for the anode potential of OLED element E1 and the gate potential of drive transistor M11. The length of the period from time T1 to time T2 is 1H.

[0122] At time T2, the light emission control signal Em_N changes from Low to High. In response to the change in the light emission control signal Em_N, transistor M15 changes from ON to OFF, and transistor M23 (an example of the first transistor) changes from OFF to ON. When transistor M15 changes to OFF, the supply of the reset potential Vrst to the gate of drive transistor M11 stops.

[0123] At time T2, transistors M22, M24, M16, and M23 are ON. Transistors M27 and M15 are OFF. Since transistors M27 and M15 are OFF and transistors M22 and M24 are ON, the threshold compensation voltage is written to the retaining capacitor C10. At time T2, the writing of the threshold compensation voltage to the retaining capacitor C10 begins.

[0124] From time T2 to time T3, the potential levels of signals S_N, Em_N-1, Em_N, and Em_N+2 are maintained. At time T3, the selection signal S_N changes from Low to High. Furthermore, the light emission control signal Em_N-1 changes from High to Low. Also, the light emission control signal Em_N+2 changes from Low to High.

[0125] In response to a change in the selection signal S_N, transistor M16 changes from ON to OFF. In response to a change in the light emission control signal Em_N-1, transistors M22 and M24 change from ON to OFF. Therefore, at time T3, the writing of the threshold compensation voltage to the retaining capacitor C10 is completed. The period from time T2 to T3 is the writing period for the threshold compensation voltage to the retaining capacitor C10, and in the example in Figure 10, its length is 2H.

[0126] In response to the change in the light emission control signal Em_N+2 at time T3, transistor M27 (an example of a second transistor) changes from OFF to ON. With transistors M23 and M27 ON, the data signal Vdata is written to the retaining capacitor C10 via transistors M23 and M27. At time T3, the writing of the data signal Vdata to the retaining capacitor C10 begins. From time T3 to time T4, the potential levels of signals S_N, Em_N-1, Em_N, and Em_N+2 are maintained.

[0127] At time T4, the light emission control signal Em_N changes from High to Low. This causes transistor M23 to turn from ON to OFF, completing the data writing to the Nth pixel circuit row. The period from time T3 to T4 is the data writing period to the Nth pixel circuit row, and its length is 1H. After time T4, the light emission control signal Em_N remains Low.

[0128] At time T4, the light emission control signal Em_N changes from High to Low. This causes transistor M15 to change from OFF to ON. This provides a drive current to OLED element E1, causing the OLED element to start emitting light. Subsequently, 2H after time T4, the light emission control signal Em_N+2 changes from High to Low.

[0129] As a result, transistor M27 switches from ON to OFF. Regardless of the state change of transistor M27, the light emission of the OLED element E1 is maintained. Compared to the configuration in Figure 8, both transistors M23 and M27 are OFF, so leakage from the retaining capacitance to the data line can be reduced more effectively during the light emission period.

[0130] Figure 11 schematically shows the layout of the control signal lines that transmit control signals to the pixel circuit 240. The main difference from the configuration example shown in Figure 5 will be explained. Compared to the configuration example shown in Figure 5, control signal line 231B is omitted and control signal line 232C is added. Control signal line 232C transmits the light emission control signal Em_K output by the K-stage shift register unit 322 to the (K-2)-stage pixel circuit row.

[0131] Figure 12 shows another example of the pixel circuit and control signal configuration. The element configuration of the pixel circuit 250 shown in Figure 12 is the same as that of the pixel circuit 200 shown in Figure 2. The control signals for some transistors in the pixel circuit 250 differ from the control signals for the same transistors in the pixel circuit 200. Specifically, the selection signal S_N+1 is input to the gate of transistor M13. Also, the selection signal S_N+3 is input to the gate of transistor M17. In other respects, the pixel circuit 250 is the same as that of the pixel circuit 200.

[0132] Figure 13 shows an example of a timing chart for the signals that control the pixel circuit 250 shown in Figure 12. Figure 13 shows the time variation of the selection signal S_N, selection signal S_N+1, selection signal S_N+3, and light emission control signal Em_N over one frame. Figure 13 shows the change in signal potential level.

[0133] In the timing chart of Figure 13, the 1H period is the period during which the data signal Vdata is written to the pixel circuit, and is the period during which transistors M13 and M17 are ON. The threshold compensation period is 1H or longer, and is 2H in the example of Figure 13.

[0134] At time T1, selection signal S_N+1 is High, and transistor M13 is OFF. Selection signal S_N+3 is High, and transistor M17 is OFF. Light emission control signal Em_N is Low, and transistor M15 is ON.

[0135] At time T1, the selection signal S_N changes from High to Low. In response to the change in the selection signal S_N, transistors M12, M14, and M16 change from OFF to ON.

[0136] Transistor M16 turns ON, and the supply of reset potential Vrst to the anode of OLED element E1 begins. Transistors M12, M15, and M16 are ON, and the supply of reset potential Vrst to the gate of drive transistor M11 begins. This state continues from time T1 to time T2. The period from time T1 to T2 is the reset period for the anode potential of OLED element E1 and the gate potential of drive transistor M11. The length of the period from time T1 to time T2 is 1H.

[0137] At time T2, the selection signal S_N+1 changes from High to Low. Also at time T2, the light emission control signal Em_N changes from Low to High. In response to the change in the selection signal S_N+1, transistor M13 (example of the first transistor) changes from OFF to ON. In response to the change in the light emission control signal Em_N, transistor M15 changes from ON to OFF. As transistor M15 changes to OFF, the supply of the reset potential Vrst to the gate of drive transistor M11 stops.

[0138] At time T2, transistors M12, M13, M14, and M16 are ON. Transistors M15 and M17 are OFF. Since transistors M15 and M17 are OFF and transistors M12 and M14 are ON, the threshold compensation voltage is written to the retaining capacitor C10. At time T2, the writing of the threshold compensation voltage to the retaining capacitor C10 begins.

[0139] From time T2 to time T3, the potential levels of signals S_N, S_N+1, S_N+3, and Em_N are maintained. At time T3, the selection signal S_N changes from Low to High. Furthermore, the selection signal S_N+3 changes from High to Low.

[0140] In response to the change in the selection signal S_N, transistors M12, M14, and M16 change from ON to OFF. As a result, the writing of the threshold compensation voltage to the holding capacitor C10 is completed at time T3. The period from time T2 to T3 is the writing period to the threshold compensation voltage holding capacitor C10, and in the example in Figure 13, its length is 2H.

[0141] In response to the change in the selection signal S_N+3 at time T3, transistor M17 (an example of a second transistor) changes from OFF to ON. With transistors M13 and M17 ON, the data signal Vdata is written to the retaining capacitor C10 via transistors M13 and M17. At time T3, writing of the data signal Vdata to the retaining capacitor C10 begins. From time T3 to time T4, the potential levels of signals S_N, S_N+1, S_N+3, and Em_N are maintained.

[0142] At time T4, the selection signal S_N+1 changes from Low to High. This causes transistor M13 to turn from ON to OFF, completing the data writing process to the Nth pixel circuit row. The period from time T3 to T4 is the data writing period to the Nth pixel circuit row, and its length is 1H. After time T4, the selection signal S_N+1 remains High.

[0143] At time T4, the light emission control signal Em_N changes from High to Low. This causes transistor M15 to change from OFF to ON. This provides a drive current to the OLED element E1, causing the OLED element to start emitting light. Two hours after time T4, the selection signal S_N+3 changes from Low to High. Transistor M17 changes from ON to OFF at the end edge of the selection signal S_N+3. With both transistors M13 and M17 OFF, leakage from the holding capacitance to the data lines can be more effectively reduced during the light emission period.

[0144] Figure 14 schematically shows the layout of the control signal lines that transmit control signals to the pixel circuit 250. The main difference from the configuration example shown in Figure 5 will be explained. Compared to the configuration example shown in Figure 5, control signal line 232B is omitted and control signal line 231C is added. Control signal line 231C transmits the selection signal S_K output by the K-stage shift register unit 312 to the (K-3)-stage pixel circuit row.

[0145] Figure 15 shows another example of the pixel circuit and control signal configuration. The element configuration of the pixel circuit 260 shown in Figure 15 is the same as that of the pixel circuit 200 shown in Figure 2. The control signals for some transistors in the pixel circuit 260 differ from the control signals for the same transistors in the pixel circuit 200. Specifically, the selection signal S_N+1 is input to the gate of transistor M13 (example of the first transistor). Also, the selection signal S_N+2 is input to the gate of transistor M17. Other aspects of the pixel circuit 260 are the same as those of the pixel circuit 200.

[0146] Figure 16 shows an example of a timing chart for the signals that control the pixel circuit 260 shown in Figure 15. Figure 16 shows the time variation of the selection signal S_N, selection signal S_N+1, selection signal S_N+2, and light emission control signal Em_N over one frame. Figure 16 shows the change in signal potential level.

[0147] In the timing chart of Figure 16, the 1H period is the period during which the data signal Vdata is written to the pixel circuit, and is the period during which transistors M13 and M17 are ON. The threshold compensation period is 1H or longer, and is 1H in the example of Figure 16.

[0148] At time T11, selection signal S_N+1 is High and transistor M13 is OFF. Selection signal S_N+2 is High and transistor M17 is OFF. Light emission control signal Em_N is Low and transistor M15 is ON.

[0149] At time T11, the selection signal S_N changes from High to Low. In response to the change in the selection signal S_N, transistors M12, M14, and M16 change from OFF to ON.

[0150] Transistor M16 turns ON, and the supply of reset potential Vrst to the anode of OLED element E1 begins. Transistors M12, M15, and M16 are ON, and the supply of reset potential Vrst to the gate of drive transistor M11 begins. This state continues from time T11 to time T12. The period from time T11 to T12 is the reset period for the anode potential of OLED element E1 and the gate potential of drive transistor M11. The length of the period from time T11 to time T12 is 1H.

[0151] At time T12, the selection signal S_N+1 changes from High to Low. Also at time T12, the light emission control signal Em_N changes from Low to High. In response to the change in the selection signal S_N+1, transistor M13 changes from OFF to ON. In response to the change in the light emission control signal Em_N, transistor M15 changes from ON to OFF. As transistor M15 changes to OFF, the supply of the reset potential Vrst to the gate of drive transistor M11 stops.

[0152] At time T12, transistors M12, M13, M14, and M16 are ON. Transistors M15 and M17 are OFF. Since transistors M15 and M17 are OFF and transistors M12 and M14 are ON, the threshold compensation voltage is written to the retaining capacitor C10. At time T12, the writing of the threshold compensation voltage to the retaining capacitor C10 begins.

[0153] From time T12 to time T13, the potential levels of signals S_N, S_N+1, S_N+2, and Em_N are maintained. At time T13, the selection signal S_N changes from Low to High. Furthermore, the selection signal S_N+2 changes from High to Low.

[0154] In response to the change in the selection signal S_N, transistors M12, M14, and M16 change from ON to OFF. As a result, the writing of the threshold compensation voltage to the holding capacitor C10 is completed at time T13. The period from time T12 to T13 is the writing period to the threshold compensation voltage holding capacitor C10, and in the example in Figure 16, its length is 1H.

[0155] In response to the change in the selection signal S_N+2 at time T13, transistor M17 changes from OFF to ON. With transistors M13 and M17 ON, the data signal Vdata is written to the retaining capacitor C10 via transistors M13 and M17. At time T13, the writing of the data signal Vdata to the retaining capacitor C10 begins. From time T13 to time T14, the potential levels of signals S_N, S_N+1, S_N+2, and Em_N are maintained.

[0156] At time T14, the selection signal S_N+1 changes from Low to High. This causes transistor M13 to turn from ON to OFF, completing the data writing process to the Nth pixel circuit row. The period from time T13 to T14 is the data writing period to the Nth pixel circuit row, and its length is 1H. After time T14, the selection signal S_N+1 remains High.

[0157] At time T14, the light emission control signal Em_N changes from High to Low. This causes transistor M15 to change from OFF to ON. This provides a drive current to OLED element E1, causing the OLED element to start emitting light. 1H after time T14, the selection signal S_N+2 changes from Low to High, and transistor M17 changes from ON to OFF. With both transistors M13 and M17 OFF, leakage from the holding capacitance to the data lines can be more effectively reduced during the light emission period.

[0158] Figure 17 shows another example of a pixel circuit and control signal configuration. Main block 275_N-1 is the main block of the pixel circuit included in the (N-1)th row of pixel circuits. Pixel circuit 270_N is the pixel circuit included in the Nth row of pixel circuits, and main block 275_N is the main block of pixel circuit 270_N.

[0159] For illustrative purposes, OLED elements controlled by a pixel circuit including main block 275_N-1 are indicated by the code E1_N-1, and OLED elements controlled by pixel circuit 270_N are indicated by the code E1_N. OLED element E1_N-1 is included in the (N-1)th pixel row, and OLED element E1_N is included in the Nth pixel row. Main block 275_N-1 and transistor M13 (not shown in Figure 17) constitute the (N-1)th pixel circuit. The positional and circuit relationship between main block 275_N-1 and the corresponding transistor M13 is the same as the relationship between main block 275_N and transistor M13_N.

[0160] The following describes the pixel circuit 270_N. Compared to the pixel circuit 200 shown in Figure 2, the connection positions of transistor M17 (example of the first transistor) and transistor M13 (example of the second transistor) are different. In the configuration example in Figure 2, transistor M17 is connected between the data line and transistor M13. In the configuration example in Figure 17, transistor M13 is connected between the data line and transistor M17. The same operation is possible even if transistors M17 and M13 are swapped in this way.

[0161] In the pixel circuit 270_N that controls the light emission of the light-emitting element E1_N, transistor M17 is controlled by the selection signal S_N+1. Transistor M13_N of the pixel circuit 270_N is located away from the other components of the pixel circuit 270_N. The pixel circuit 270_N consists of a main block 275_N composed of transistor M13_N and other transistors and capacitive elements.

[0162] The main blocks of a pixel circuit row controlled by the same control line are arranged linearly along the X-axis, for example, as shown in Figure 5 or 14. The region that includes the main blocks of a pixel circuit row but does not include the components of the main blocks of other pixel circuit rows is called the pixel circuit row region (pixel circuit row region). A boundary line exists that separates adjacent pixel circuit row regions.

[0163] Figure 18 schematically shows multiple consecutive pixel circuit row regions. In Figure 18, the dashed rectangles indicate regions containing the main blocks of the pixel circuit; for example, a region containing one main block is indicated by reference numeral 401. Region 401 may contain components of pixel circuits different from the main block, but does not contain components of other main blocks. In Figure 18, for example, the (N-1)th row pixel circuit row region is indicated by reference numeral 411_N-1, and the Nth row pixel circuit row region is indicated by reference numeral 411_N. The boundary 412 between pixel circuit row region 411_N-1 and pixel circuit row region 411_N separates the two regions. In the example shown in Figure 18, the size (width) along the Y axis of each pixel circuit row region is common.

[0164] Returning to Figure 17, transistor M13_N is located within the (N-1)th row pixel circuit row region 411_N-1. Other transistors M11~M16 for controlling the light emission of the light-emitting element E1_N are located within the Nth row pixel circuit row region 411_N. Transistor M13_N is controlled by the light emission control signal Em_N-1. The block region 401 of the (N-1)th row pixel circuit row region 411_N-1 includes, for example, the main block 275_N-1 in addition to transistor M13_N. Also, the block region 401 of the Nth row pixel circuit row region 411_N includes, for example, the main block 275_N in addition to transistor M13_N+1.

[0165] Transistors M13_N and M17 are connected in series between data line 237 and the holding capacitors C11 and C12. Transistors M13_N and M17 are switch transistors for selecting the pixel circuit that supplies the data signal and for writing the data signal Vdata to the holding capacitor. The changes in the selection signal and the light emission control signal are the same as in the example described with reference to Figure 3.

[0166] As described above, transistor M13_N is located in the pixel circuit row region 411_N-1 of the (N-1)th row. Furthermore, transistor M13_N is controlled by the light emission control signal Em_N-1 of the pixel circuit row of a different row from row N, in the example of Figure 17, which is row (N-1). As a result, the number of control lines required to control the pixel circuit 270_N is reduced, and an efficient element layout becomes possible.

[0167] Figure 19 shows another example configuration of the pixel circuit and control signal. The main points to explain are the differences from the configuration example shown in Figure 17. Transistor M13_N-1 is a transistor for controlling the light emission of the OLED element E1_N-1.

[0168] Transistor M13_N (an example of a second transistor) is located in the pixel circuit row region 411_N of the Nth row. In the configuration example in Figure 19, the main block can be considered to include all the components of the pixel circuit. A transmission line (control line) 238, which branches off from control line 232B that transmits the light emission control signal Em_N-1 of the (N-1)th row, is connected to the gate of transistor M13_N. Control line 232B passes through the pixel circuit row region 411_N-1 of the (N-1)th row.

[0169] The light emission control signal Em_N-1 is supplied to the gate of transistor M13_N via transmission line 238. In this way, the signal controlling transistor M13_N of the Nth row pixel circuit is supplied by a transmission line branched from a control signal line located at a different position from the Nth row pixel circuit row region 411_N. This reduces the number of control lines required to control the pixel circuit 270_N and enables an efficient element layout.

[0170] In the examples in Figures 17 and 18, transistor M13_N is placed in the region 411_N-1 of the (N-1)th pixel circuit row. However, as a different example, it is also conceivable to place transistor M17_N of pixel circuit 270_N in the region of the (N+1)th pixel circuit row. In that configuration, transistor M17 is connected between transistor M13 and the data line, and transistor M13_N is placed in the pixel circuit row region 411_N of the Nth row.

[0171] Figure 20 shows an example of a pixel circuit and control signal having this configuration. The main points to explain are the differences from the configuration example shown in Figure 17. Figure 20 shows the pixel circuit 270_N in the Nth row of pixel circuits and the main block 275_N+1 of the pixel circuit in the (N+1)th row of pixel circuits. Transistor M17_N-1 is a transistor included in the (N-1)th row of pixel circuits.

[0172] The Nth pixel circuit row is controlled by control signals S_N, Em_N-1, Em_N, and S_N+1. The (N+1)th pixel circuit row is controlled by control signals S_N+1, Em_N, Em_N+1, and control signal S_N+2 (not shown in Figure 20).

[0173] In pixel circuit 270_N, the connection positions of transistor M13_N (an example of the second transistor) and transistor M17_N (an example of the first transistor) are swapped from the example in Figure 17. Transistor M17_N in pixel circuit 270_N is located away from the other components of pixel circuit 270_N.

[0174] The main block 275_N+1 consists of transistors M11 to M16 and capacitors C11 and C12, with transistor M17 (not shown in Figure 20) omitted. In other words, the main block of the pixel circuit 270_N is composed of the components of the pixel circuit 270_N excluding transistor M17_N.

[0175] Figure 21 schematically shows multiple consecutive pixel circuit row regions. The differences from Figure 18 will be explained. In the example configuration of Figure 21, control lines from the Nth-th stage shift register unit 312, and control lines from the (N-1)th and Nth-th stage shift register units 322 pass through the pixel circuit row region 411_N.

[0176] Transistor M17_N is located within the (N+1)th row pixel circuit row region 411_N+1. Other transistors M11~M16 of pixel circuit 270_N are located within the Nth row pixel circuit row region 411_N. The block region 401 of the (N+1)th row pixel circuit row region 411_N+1 includes, for example, the main block 275_N+1 in addition to transistor M17_N. Also, the block region 401 of the Nth row pixel circuit row region 411_N includes, for example, the main block of pixel circuit 270_N in addition to transistor M17_N-1.

[0177] Figure 22 shows a configuration example in which the control signal line of transistor M17 is routed from the region of an adjacent pixel circuit row, compared to the configuration example shown in Figure 19. The main difference from the configuration example in Figure 20 will be explained. Transistor M17_N is located in the pixel circuit row region 411_N of the Nth row. In the configuration example in Figure 22, the main block can be considered to include all the components of the pixel circuit. A transmission line (control signal line) 239, which is branched from the control signal line 231A that transmits the selection signal S_N+1 of the (N+1)th row, is connected to the gate of transistor 17_N. The control signal line 231A passes through the pixel circuit row region 411_N+1 of the (N+1)th row.

[0178] The selection signal S_N+1 is supplied to the gate of transistor 17_N via transmission line 239. In this way, the signal controlling transistor M17_N of the Nth row pixel circuit is supplied by a transmission line branched from a control signal line located at a different position from the Nth row pixel circuit region 411_N. This reduces the number of control lines required to control the pixel circuit 270_N and enables an efficient element layout.

[0179] While embodiments of the present disclosure have been described above, the present disclosure is not limited to the embodiments described above. Those skilled in the art can easily modify, add to, and transform each element of the above embodiments within the scope of the present disclosure. It is possible to replace parts of the configuration of one embodiment with the configuration of another embodiment, and to add the configuration of another embodiment to the configuration of one embodiment. [Explanation of symbols]

[0180] 1 OLED display device 10 TFT substrates 25 Display area 31 Scanning Driver 32 Emission Drivers 231A-231A, 232A-232C control signal lines 200, 210, 220, 230, 240, 250, 260 pixel circuits 310, 320 shift registers 312, 322 Shift Register Unit C10, C20 holding capacity E1 OLED element M11-M17, M22-M24, M27 Transistors

Claims

1. A display device, A display area including multiple pixel circuit rows, Includes a drive circuit, Each of the aforementioned rows of multiple pixel circuits includes multiple pixel circuits, Each of the aforementioned multiple pixel circuits is A drive transistor controls the amount of current supplied to the light-emitting element, A holding capacitor is configured to consist of a first capacitor element and a second capacitor element connected in series, with one end of the first capacitor element connected to the gate of the drive transistor, and to hold the gate-source voltage, which is the control voltage of the drive transistor. A first transistor and a second transistor connected in series transmit a data signal to the aforementioned holding capacitance, A threshold compensation transistor connected to the gate of the drive transistor and used to write the threshold compensation voltage of the drive transistor to the holding capacitance, Includes, The drive circuit shifts the control signal pulse from the preceding stage to the succeeding stage in the multiple pixel circuit row at regular intervals. The pulse width of the control signal pulse is at least twice the duration of the specified period. The aforementioned drive circuit is During the threshold compensation period, the threshold compensation transistor is kept ON, and the threshold compensation voltage is written to the holding capacitor. During the data writing period after the threshold compensation period, the threshold compensation transistor is kept OFF, and the first transistor and the second transistor are kept ON, and the data signal is written to the holding capacitor. The pulse width of the control signal pulse is at least twice the data writing period. The aforementioned drive circuit is The first transistor is controlled by the first control signal pulse, The second transistor is controlled by a second control signal pulse that is different from the first control signal pulse. The first control signal pulse and the second control signal pulse are both either a High pulse or a Low pulse, and the first control signal pulse and the second control signal pulse have the same pulse width. The aforementioned drive circuit is The first transistor is turned ON by the start edge of the first control signal pulse before the start of the data writing period. After the threshold compensation period ends, the first transistor is kept ON and the second transistor is turned ON by the start edge of the second control signal pulse to start the data writing period. The first transistor is turned OFF by the end edge of the first control signal pulse, thereby ending the data writing period. Display device.

2. A display device, A display area including multiple pixel circuit rows, Includes a drive circuit, Each of the aforementioned rows of multiple pixel circuits includes multiple pixel circuits, Each of the aforementioned multiple pixel circuits is A drive transistor controls the amount of current supplied to the light-emitting element, A holding capacitor is configured to consist of a first capacitor element and a second capacitor element connected in series, with one end of the first capacitor element connected to the gate of the drive transistor, and to hold the gate-source voltage, which is the control voltage of the drive transistor. A first transistor and a second transistor connected in series transmit a data signal to the aforementioned holding capacitance, A threshold compensation transistor connected to the gate of the drive transistor and used to write the threshold compensation voltage of the drive transistor to the holding capacitance, Includes, The drive circuit shifts the control signal pulse from the preceding stage to the succeeding stage in the multiple pixel circuit row at regular intervals. The pulse width of the control signal pulse is at least twice the duration of the specified period. The aforementioned drive circuit is During the threshold compensation period, the threshold compensation transistor is kept ON, and the threshold compensation voltage is written to the holding capacitor. During the data writing period after the threshold compensation period, the threshold compensation transistor is kept OFF, and the first transistor and the second transistor are kept ON, and the data signal is written to the holding capacitor. The pulse width of the control signal pulse is at least twice the data writing period. The aforementioned drive circuit is The first transistor is controlled by the first control signal pulse, The second transistor is controlled by a second control signal pulse that is different from the first control signal pulse. The first control signal pulse is either a High pulse or a Low pulse, the second control signal pulse is the other of the High pulse or Low pulse, and the first control signal pulse and the second control signal pulse have the same pulse width. The first transistor is turned ON by the start edge of the first control signal pulse before the start of the data writing period. After the threshold compensation period ends, the first transistor is kept ON and the second transistor is turned ON by the end edge of the second control signal pulse to start the data writing period. The first transistor is turned OFF by the end edge of the first control signal pulse, thereby ending the data writing period. Display device.

3. A display device according to claim 1 or 2, The pulse width of the control signal pulse is three times or more the data writing period. The threshold compensation period is at least twice the data writing period. Display device.

4. A display device according to claim 1 or 2, The system further includes a light-emitting control switch transistor that turns ON / OFF the supply of drive current from the drive transistor to the light-emitting element, The drive circuit keeps the light emission control switch transistor OFF during the threshold compensation period and the data writing period. After the data writing period ends, the light emission control switch transistor is turned ON. Display device.

5. A display device according to claim 1 or 2, A third transistor between the light-emitting element and the drive transistor, A fourth transistor connected to the node between the third transistor and the light-emitting element, It further includes, The threshold compensation transistor is located between the third transistor and the gate of the drive transistor. The aforementioned drive circuit is During the reset period prior to the threshold compensation period, a reset potential is supplied to the gate of the drive transistor via the fourth transistor, the third transistor, and the threshold compensation transistor. During the reset period, the first transistor and the second transistor are kept OFF. Display device.

6. A display device according to claim 5, The drive circuit turns on the first transistor at the start edge of the first control signal pulse at the start of the threshold compensation period. Display device.

7. A display device according to claim 2, The drive circuit includes a first driver and a second driver, The first driver shifts the first control signal pulse from the preceding stage to the succeeding stage in the plurality of pixel circuit rows at regular intervals. The second driver shifts the second control signal pulse from the preceding stage to the succeeding stage in the multiple pixel circuit row at regular intervals. The first control signal pulse from the first driver and the second control signal pulse from the second driver are synchronized. Display device.

8. A display device according to claim 7, The drive circuit controls each pixel circuit of the plurality of pixel circuits using two control signal pulses from the first driver and two control signal pulses from the second driver. Display device.

9. A display device according to claim 1, The drive circuit turns off the second transistor by the ending edge of the second control signal pulse during the period when the light-emitting element is emitting light. Display device.

10. A display device according to claim 1 or 2, The first transistor, the second transistor, and the threshold compensation transistor are N-type thin-film transistors. The aforementioned drive transistor is a P-type thin-film transistor. Display device.

11. A display device according to claim 10, The threshold compensation transistor is a first threshold compensation transistor, The display device is an N-type thin-film transistor and further includes a second threshold compensation transistor controlled by the same control signal as the first threshold compensation transistor. While the first threshold compensation transistor is ON, it puts the drive transistor into a diode connection state. The second threshold compensation transistor, while ON, provides a reference potential to the holding capacitance. Display device.

12. A display device according to claim 1 or 2, The first or second transistor of the pixel circuit of the Nth row of pixel circuit is located in a pixel circuit region different from the Nth row of pixel circuit region. Display device.

13. A display device according to claim 1 or 2, The first control signal pulse or the second control signal pulse that controls the Nth pixel circuit row controls the first transistor or the second transistor via a transmission line branched from a control signal line located at a different position from the Nth pixel circuit row region. Display device.

14. A display device according to claim 13, wherein the transmission line is branched from a control signal line that passes through a pixel circuit row region adjacent to the Nth pixel circuit row region, Display device.

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