Receiver synchronization for optical communication

Abstract

An optical communication system, receiver, and method for synchronizing a receiver with a transmitter to decode a data input stream transmitted by the transmitter and received at the receiver are provided, the method including receiving a data input stream at the receiver, the data input stream having a first data rate set based on a transmitter clock rate, generating a wave, obtaining a phase error between the data input stream and the generated wave, determining a synchronized clock rate by using the phase error to adjust a frequency of the generated wave to match the frequency of the generated wave to the transmitter clock rate of the data input stream, and using the synchronized clock rate to decode the data input stream to obtain data encoded in the data input stream.

Description

Technical Field

[0001] Technical Field The present disclosure relates to methods and systems for synchronizing a receiver for the purpose of decoding communications transmitted using an optical communication system, such as synchronizing a receiver clock to a received data input stream.

Background Art

[0002] Background Optical or optical communication systems in which light is modulated to encode data or information for communication between optical communication nodes are useful for various applications such as establishing an ad hoc network between peers. For example, in certain vehicle applications, such optical communication systems can be used for vehicle communication as described in U.S. Patent No. 11,245,469. However, such systems may include or rely on external synchronization to synchronize the receiver with the transmitter so that the encoded data can be properly decoded. Such external synchronization refers to a synchronization process that synchronizes the receiver with the transmitter using a different (separate) communication from the optical communication system having the receiver to be synchronized. For example, external synchronization may include notifying the receiver of the data or clock rate of the input stream to be transmitted by using a cellular network or dedicated short range communication (DSRC). There is a need for systems and methods that enable synchronization for ad hoc optical communication networks that do not rely on external communication such as internal synchronization for ad hoc optical communication networks, i.e., using DSRC or cellular communication, or providing a configuration to a vehicle during manufacture by setting all clock rates of optical communication nodes to the same.

[0003] U.S. Patent No. 11,245,469 teaches a vehicle line-of-sight optical communication system for use in ad-hoc networks formed by vehicles while they are traveling along a road. As discussed in that patent, vehicle-to-vehicle (V2V) and vehicle-to-infrastructure (V2I) networks offer the ability to significantly reduce vehicle collisions by enabling vehicles to exchange messages with other vehicles such as "lane change," "sudden braking," and "ice patch." Active and passive sensor-based vehicle object detection systems that do not include V2V and V2I communication rely on the interpretation of signals to determine the behavior of nearby vehicles and other objects. Signals can be corrupted or interfered with, leading to misinterpretation. Sensors can also fail, resulting in loss of function. V2V networks, on the other hand, rely on explicit information exchanged between vehicles in the form of data packets. If received without errors, these packets provide precise and clear information about the current status (e.g., position, speed, and direction of travel) and intentions (e.g., lane changes, sudden braking, right turns) of nearby vehicles. This information can be merged with information from existing sensors (e.g., cameras, radar, lidar) to improve driving.

[0004] In realistic traffic conditions (e.g., busy main roads), the number of vehicles, the speeds they are traveling at, their continuously changing positions, and their directions of travel relative to each other make achieving low-latency, reliable V2V and / or V2I networks extremely difficult.

[0005] V2V networks that rely on radio frequency (RF) communication, such as those using DSRC, are widely assumed to address this problem. However, these RF networks have inherent drawbacks due to the propagation characteristics of RF signals. RF signals tend to propagate in a plane in an omnidirectional pattern. As a result, more vehicles than intended will receive the RF signal transmitted from the host vehicle. Therefore, DSRC-based network architectures may require additional processing and hardware overhead to determine which vehicles form subnets, manage orthogonal channel assignments (e.g., time, frequency, code, and space) to those subnets, and then route packets between vehicles within those subnets. Moreover, because the position and orientation of vehicles relative to each other are constantly changing, these networks must be able to perform these tasks very quickly.

[0006] In some embodiments, synchronization between a transmitter, such as one or more light sources, and a receiver may be performed using external communication such as Wi-Fi®, Bluetooth®, or other DSRC. Nevertheless, as described above, it has been found that there is a need for systems and methods to enable internal synchronization for ad-hoc optical communication networks, i.e., synchronization for ad-hoc optical communication networks that do not rely on external communication such as any of the DSRCs described above, or by constraining the system to certain characteristics or parameters. [Overview of the Initiative] [Means for solving the problem]

[0007] overview One aspect of the present disclosure provides a method for synchronizing a receiver with a transmitter to decode a data input stream transmitted by the transmitter and received in a receiver. The method includes receiving a data input stream in a receiver, the data input stream having a first data rate set based on a transmitter clock rate; generating a wave; obtaining a phase error between the data input stream and the generated wave; determining a synchronization clock rate by using the phase error to adjust the frequency of the generated wave to match the transmitter clock rate of the data input stream; and using the synchronization clock rate to decode the data input stream to obtain encoded data in the data input stream.

[0008] According to various embodiments, this method may further include any one of the following features, or a technically feasible combination of some or all of these features:

[0009] -This method further includes inputting the phase error to a proportional integral (PI) controller, which is connected to a wave generator used to generate the generated wave. - The wave generator includes a phase generator and a direct digital synthesizer (DDS). - The PI controller outputs the phase step that is input to the phase generator, and the phase generator is operablely connected to the DDS. -The generated wave output by the DDS is mixed or multiplied with the data input stream to generate a phase error. - The synchronization clock rate is determined based on a feedback process that corrects the frequency and / or phase of the generated wave until the phase error falls below a predetermined threshold at which the transmitter clock rate of the data input stream and the frequency of the generated wave are considered to match. - Obtaining the phase error is performed recursively or iteratively until the phase error between the data input stream and the generated wave falls below a predetermined threshold at which the transmitter clock rate of the data input stream and the frequency of the generated wave are considered to match. - The generated wave is a sine wave. -This method is performed by an optical communication node having a receiving device configured to perform this method, and / or - The initial frequency is used to generate the wave initially, and the initial frequency is predetermined.

[0010] According to another aspect of the present disclosure, an optical communication receiver is provided. The optical communication receiver includes a photodetector for receiving a data input stream, and a clock extraction module having a phase generator, a direct digital combiner (DDS) operably connected to the output of the phase generator, and a proportional-integral (PI) controller whose output is operably connected to the phase generator. The output of the DDS is used to acquire a phase error that is input to the PI controller. The clock extraction module is configured to perform a feedback process that includes adjusting the frequency of the generated wave based on the acquired phase error until the phase error falls below a predetermined threshold at which the transmitter clock rate of the data input stream and the frequency of the generated wave are considered to match. The optical communication receiver is configured to decode the data input stream using a synchronized clock rate determined based on the feedback process in order to acquire data.

[0011] According to various embodiments, this automated topology determination system may further include any one of the following features, or a technically feasible combination of some or all of these features:

[0012] - The synchronized clock rate is determined based on the tuned frequency of the generated wave when the transmitter clock rate of the data input stream is considered to match the frequency of the generated wave.

[0013] - The PI controller is used to generate phase steps as an output operably connected to the phase generator, and the phase steps are generated based on the phase error. - Phase error is obtained by mixing or multiplying the data input stream with the generated wave. - The synchronized clock rate is internally synchronized to the data input stream without using external communication. - The clock extraction module is configured to provide a synchronized clock rate to a finite state machine, and / or - A finite state machine is operablely connected to a processor to provide data to the processor.

[0014] Brief explanation of the drawing Preferred exemplary embodiments are described below in conjunction with the accompanying drawings, where similar reference numerals indicate similar elements. [Brief explanation of the drawing]

[0015] [Figure 1] This figure shows an optical communication system including a transmitting device and a receiving device according to one embodiment. [Figure 2] This is a schematic diagram of exemplary components of the transmitter of the transmitting device shown in Figure 1, according to one embodiment. [Figure 3] This figure shows an example of encoding a byte using an exemplary 4-cycle encoding scheme according to one embodiment. [Figure 4] This is a schematic diagram of exemplary components of the receiver of the receiving device shown in Figure 1, according to one embodiment. [Figure 5] This is a schematic diagram of exemplary components of the clock extraction module of the receiver shown in Figure 4, according to one embodiment. [Figure 6] This is a schematic diagram of exemplary components of the proportional-integral (PI) controller of the clock extraction module shown in Figure 5, according to one embodiment. [Figure 7]A flowchart of a method for synchronizing a receiver with a transmitter to decode a data input stream transmitted by the transmitter and received at the receiver according to an embodiment. [Figure 8] A flowchart of a method for synchronizing a receiver with a transmitter to decode a data input stream transmitted by the transmitter and received at the receiver according to an embodiment. [Figure 9] A graph of an example of square wave input data generated according to an embodiment. [Figure 10] A graph of an example of a sine wave generated by a direct digital synthesizer (DDS) of a clock extraction module according to an embodiment. [Figure 11] A graph of the product of two signals in FIGS. 9 and 10 according to an embodiment. [Figure 12] A graph of a filtered signal based on the filtering of the signal in FIG. 11 according to an embodiment. [Figure 13] A graph of the phase step (ΔΦ) of a PI controller according to an embodiment. [Figure 14] A diagram of a unit circle located around and indicating values used by a DDS according to an embodiment. [Figure 15] A diagram of a sawtooth function representing the phase of a generated signal according to an embodiment. [Figure 16] A diagram of a vehicle communication system including a host vehicle and other vehicles communicating using an optical communication system according to an embodiment. [Figure 17] A diagram of the host vehicle in FIG. 16 including a plurality of optical communication modules according to an embodiment.

Embodiments for Carrying Out the Invention

[0016] Detailed Description The systems and methods described herein enable the synchronization of communication between two electronic devices performed using optics or optical communication, according to at least some embodiments, and in particular, the systems and methods enable internal ad-hoc synchronization of such communication. Such electronic devices having optics or optical communication capabilities, such as line-of-sight optical communication capabilities, may each be referred to as an optical communication node and may include one or more transmitters for transmitting light to transmit data to another node, and / or one or more receivers for receiving light to receive data transmitted by the other node. The “optical” or “optical” communication described herein means not only visible light, but also light invisible to the human eye having wavelengths suitable for use in line-of-sight communication, including at least a portion of the infrared (IR), visible light, and ultraviolet (UV) light spectrum. The transmitter encodes or modulates data using light at or in accordance with the transmitter clock rate and transmits such encoded data as a data input stream, which is then received by the receiver. In at least some embodiments, in order to properly decode and / or interpret the data input stream to obtain data being communicated by the transmitter, the receiver synchronizes a clock that matches the clock used by the transmitter to encode the data input stream. In this embodiment, the synchronized clock is then used to decode the data input stream to obtain data.

[0017] According to at least some embodiments, a method is provided for synchronizing a receiver with a transmitter in order to decode a data input stream transmitted by the transmitter and received in a receiver. According to an embodiment, the method includes receiving a data input stream in a receiver, the data input stream having a first data rate set based on the transmitter clock rate; generating a wave; obtaining a phase error between the data input stream and the generated wave; determining a synchronization clock rate by using the phase error to adjust the frequency of the generated wave so that the phase and / or frequency of the generated wave match the transmitter clock rate of the data input stream; and using the synchronization clock rate to decode the data input stream in order to obtain encoded data in the data input stream.

[0018] According to some embodiments, an optical communication receiver is provided, comprising a photodetector for receiving a data input stream, and a clock extraction module having a phase generator, a direct digital combiner (DDS) operably connected to the output of the phase generator, and a proportional-integral (PI) controller whose output is operably connected to the phase generator. In this embodiment, the output of the DDS is used to acquire a phase error input to the PI controller and to acquire a synchronized clock rate when the frequency of the generated wave matches the transmitter data rate of the data input stream. According to this embodiment, the clock extraction module is configured to perform a feedback process that includes adjusting the frequency of the generated wave based on the acquired phase error until the phase error falls below a predetermined threshold at which the transmitter clock rate of the data input stream and the frequency of the generated wave are considered to match. According to at least this embodiment, the optical communication receiver is configured to decode the data input stream using the synchronized clock rate determined based on the feedback process.

[0019] Referring to Figure 1, an optical communication system 10 having a transmitting device 12 and a receiving device 14 is shown. The transmitting device 12 has a transmitter 16 used to communicate data with a receiver 18 of the receiving device 14. In one embodiment, the transmitting device 12 is a first vehicle, such as a first automobile, and the receiving device 14 is a second vehicle, such as a second automobile. The transmitter 16, which may consist of one or more light sources and a transmit processing circuit, transmits data by modulating or encoding the data using the emitted light, and this emission of light having encoded data is referred to as a data input stream. The data input stream is received in a receiver 18, which may consist of a receive processing circuit having a photodetector 19, and in some embodiments, the receiver 18 may include certain components or circuits of a receive processing circuit 78 or a dedicated receive processing circuit 78' as described in U.S. Patent No. 11,245,469, which is incorporated herein by reference.

[0020] The transmitter 16 may consist of one or more light sources, such as one or more light-emitting diodes (LEDs), and other transmit processing circuits, such as an integrated driver circuit 76 and / or a dedicated driver circuit 76' as described in U.S. Patent No. 11,245,469, which is incorporated herein by reference. According to at least some embodiments, in order to transmit a message, the transmit processing circuit (or other transmitter control unit) may encode or modulate (pulse) the light emitted by the transmitter 16, such as one or more LEDs, using a transmit signal that is modulated according to the message to be transmitted. Thus, the light sources (e.g., LEDs) are effective for optically communicating a message from the transmitter 16. Various encoding techniques may be used, such as time, frequency, or digital encoding, for example, using frequency shift keying (FSK) to digitally transmit the message as binary data. The message may be transmitted in a data packet using error checking, encryption, and other data messaging techniques used as required or desirable for a particular application.

[0021] Referring to Figure 2, a transmitter 16 is shown, which includes a power supply 20, an electronic controller 22 shown as a field-programmable gate array (FPGA), and a light source 24. It should be understood that other types of processors or controllers may be used instead of, or in addition to, the FPGA for the electronic controller 22. The electronic controller 22 can acquire data transmitted in digital form, which may be encoded such that a clock signal (or transmitter clock rate) can be derived or extracted using the receiver 18. In one embodiment, each bit is transmitted using four clock cycles or phases, which allows for consistent extraction of the clock signal through the use of the internal synchronization method described herein. For example, referring to Figure 3, an example is shown using this four-cycle encoding scheme to encode binary data bytes 11000010 (as shown in 25a-h). In other embodiments, an N-cycle encoding scheme may be used where N is a number other than 4. In at least some embodiments, the data is encoded in such a way that only a clock signal is transmitted, thereby ensuring that all pulses are in phase with each other and that there are no secondary data frequencies to lock onto the receiver 18 (specifically, the clock extraction module 30 of the receiver 18, as described above with respect to Figure 4). This is achieved by transmitting a clock signal and assigning four clock cycles to each bit. When a zero bit is transmitted, a single clock cycle goes low, as shown in Figure 3.

[0022] The receiver 18 may consist of a receiver processing circuit which may include components and / or circuits of a receiver processing circuit 78 and / or a dedicated receiver processing circuit 78' as described in U.S. Patent No. 11,245,469, which is incorporated herein by reference. Referring to Figures 1 and 4, the receiver 18 is shown which includes a photodetector 19 (Figure 1), a clock extraction module 30, a finite-state machine (FSM) 32, a system clock 34, a processor 36, and memory 37. The photodetector 19 may include one or more photodiodes (e.g., pn photodiode, PIN photodiode, avalanche photodiode) and / or other photodetector elements such as a metal-semiconductor-metal (MSM) photodetector. The receiver 18 is also shown as having an analog-to-digital converter (ADC) 38 which can convert a data input stream from analog format (indicated by 51) to digital format (indicated by 52) before the data is supplied to the clock extraction module 30, as shown in Figure 4.

[0023] Referring to Figure 5, the clock extraction module 30 is shown to include a mixer / multiplier 42, a proportional-integral (PI) controller 44, a phase generator 46, and a direct digital combiner (DDS) 48. As shown in 52, the clock extraction module 30, which takes a digital data input stream as input, provides a synchronized clock output (indicating a synchronized clock rate) 66 synchronized with the data input stream. In at least some embodiments, the purpose of the clock extraction module (or clock-data recovery (CDR) module) 30 is to extract the clock rate (transmitter clock rate) of the data input stream and replicate a clock with a matching frequency (synchronized clock rate) at the receiver 18. This allows the receiver to properly decode the data input stream by using the synchronized clock rate. As shown in Figure 5, the mixer / multiplier 42 is used to acquire the phase error, as shown in 54, which is then supplied to the PI controller 44.

[0024] Referring to Figure 6, the PI controller 44 is shown to take the acquired phase error 54 and the regulated clock (referred to as the “synchronous ongoing clock”) as inputs, as shown in 56, and provides a phase step (ΔΦ) (used as clock control feedback) used to control the frequency of the wave generated by the DDS 48, as shown in 60. In at least some embodiments, the DDS 48 operates as a wave generator to generate a start wave or base wave at an initial frequency. The phase generator 46 is used to control the frequency of the DDS 48. The DDS 48 uses a 12-bit lookup table corresponding to values ​​around the unit circle. The phase generator 46 outputs a sawtooth function representing the phase of the signal being generated. As the PI controller 44 corrects by increasing or decreasing the frequency, the phase step (ΔΦ) of the sawtooth function increases or decreases to match, as shown in 60. The phase generator 46 and the DDS 48 are used as wave generators to generate the wave that is supplied as input to the clock extraction module 30, as shown in 62. As shown in the figure, the phase step 60 is determined by the PI controller 44 via feedback from the DDS 48, as shown in 62, which allows for correction until the phase and frequency (i.e., clock or data rate) of the data input stream and the generated wave match, and the extracted clock rate or synchronized clock rate is determined, as shown in 66, which allows for decoding the data input stream and acquiring data. As shown in Figure 5, the phase step 60 is then used by the phase generator 46 to generate a phase input 61, which is supplied to the DDS 48 and used to generate the wave.

[0025] The PI controller 44 includes an accumulator 70 that takes a phase error 54 and a synchronous ongoing clock 56 as inputs, and the PI controller 44 then outputs a phase step (ΔΦ) 60 used to adjust the generated wave. The accumulator 70 is used to provide input to the integral gain component 72 of the PI controller 44, which is then used together with the proportional gain component 74 to provide the phase step (ΔΦ) 60.

[0026] Referring to Figure 7, one embodiment of method 200 is shown in which a receiver is synchronized with a transmitter to decode a data input stream transmitted by the transmitter and received in the receiver. According to at least some embodiments, method 200 is performed by a receiver 18 of a receiving device 14, and therefore method 200 may include the use of one or more components of the receiving device 14, as will be understood by those skilled in the art in light of the following description. Although steps 210 to 250 are described as being performed in a particular order, it will also be understood that the steps may be performed in any suitable and technically feasible order.

[0027] Method 200 begins with step 210, in which a data input stream is received at a receiver, and the data input stream is transmitted at a first data rate set based on the transmitter clock rate. As used herein, the term “transmitter clock rate” refers to the rate of the clock used by the transmitter as part of the encoded data of the data input stream transmitted to the receiver. Also as used herein, the term “data rate” refers to the rate at which bits of data are provided over time, such as the rate at which bits of data are transmitted by the transmitter. According to at least some embodiments and models, such as when Method 200 is used for certain vehicle-to-everything (V2X) communication, such actual differences are negligible, and it is assumed that the data rate at which the data input stream is transmitted is the same as the data input stream received at the receiver. Method 200 continues with step 220.

[0028] In step 220, a wave is generated, and the wave has an initial frequency. In at least some embodiments, the wave is a sine wave generated by the DDS48. The initial frequency may be predetermined and stored in memory, such as the memory 37 of the receiver 18. The wave can be generated by a wave generator, such as the DDS48, which can generate a wave based on a phase input 61, for example, in Figure 5. The phase input 61 can be generated by a phase generator 46. As shown in Figure 5, the clock extraction module 30 implements a feedback loop in which the frequency and / or phase of the generated wave are adjusted. Method 200 continues to step 230.

[0029] In step 230, the phase error between the data input stream and the generated wave is obtained. As shown in Figure 5, in one embodiment, the mixer / multiplier 42 of the clock extraction module 30 is used to generate the phase error 54 based on the data input stream 52 and the generated wave 62. The sine wave of the generated wave 62 is multiplied with the data input stream, and the resulting product is similar to the trigonometric identity sin(x) × sin(y) = 1 / 2[cos(xy) - cos(x+y)]. In this identity, the cos(xy) term represents the phase difference between the two signals. After removing cos(x+y) using a low-pass filter, the resulting signal is used as the phase error 54.

[0030] In the examples shown in Figures 9 to 12, the square wave input data 400 (Figure 9) is transmitted at 10 kHz, while the DDS sine wave 420 generates a 10.5 kHz sine wave (Figure 10). The product of these two signals 440 (Figure 11) is a signal obtained by adding a 0.5 kHz signal to a 20.5 kHz signal. After filtering out the 20.5 kHz signal, only the 0.5 kHz signal representing the phase difference 460 (Figure 12) remains. Method 200 continues to step 240.

[0031] In step 240, the synchronized clock rate is determined by using a phase error to adjust the frequency of the generated wave so that the frequency of the generated wave matches the transmitter clock rate of the data input stream. The synchronized clock rate is also sometimes referred to as the extracted clock rate, as it is extracted from the data input stream. In at least some embodiments, the phase error is supplied as an input to the PI controller 44, which controls the frequency of the sine wave generated by the DDS 48, meaning that as the phase error 54 approaches zero, the frequency of the sine wave converges to a value in the received data input stream 52. For example, as shown in Figure 13, the phase step (ΔΦ) 60 of the PI controller 44 is shown as converging over time, as shown in 480. A phase generator 46 is used to control the frequency of the DDS 48. In the illustrated embodiment, the DDS 48 is a 12-bit lookup table corresponding to values ​​around a unit circle 500, as shown in Figure 14. The phase generator 46 outputs a sawtooth function representing the phase of the generated signal, as shown in 520 in Figure 15. When the PI controller 44 corrects by increasing or decreasing the frequency, the phase step (ΔΦ) 60 of the sawtooth function increases or decreases to match the transmitter clock rate. Method 200 continues to step 250.

[0032] In step 250, the data input stream is decoded using the synchronization clock rate to obtain the encoded data within the data input stream. Since the transmitter clock rate of the data input stream is extracted as the synchronization clock rate, the data input stream can be interpreted by the receiver. For example, receiver 18 can use the synchronization clock rate to demodulate or otherwise decode the data by dividing the data input stream into segments, each represented by four periods, as shown in Figure 3, for example. Method 200 ends.

[0033] Referring to Figure 8, one embodiment of method 300 is shown in which a receiver is synchronized with a transmitter to decode a data input stream transmitted by the transmitter and received in the receiver. According to at least some embodiments, method 300 is performed by a receiver 18 of a receiving device 14. Method 300 may include the use of one or more components of the receiving device 14, as will be understood by those skilled in the art in light of the following description. In step 310, a data input stream is received, which is analogous to step 210 of method 200, and the discussion of that step will be attributed to step 310. Method 300 then proceeds to step 320.

[0034] In step 320, the clock rate is extracted through a feedback clock rate matching process 322. In at least one embodiment, the feedback clock rate matching process includes steps 210-240 of method 200 described above. In some embodiments, the feedback clock rate matching process includes tuning or adjusting the frequency of a generated wave, such as a sine wave, until its frequency matches the transmitter clock rate, which is the clock rate used to encode the data being transmitted by the transmitter. In some embodiments, by using encoding in which each bit is represented by four periods of the transmitter clock rate, it becomes possible to extract the transmitter clock rate at the receiver through the use of the feedback clock rate matching process. The feedback clock rate matching process is the process of multiplying and mixing the wave being generated in the DDS48 with the data input stream, as described above, and then adjusting the frequency of the generated wave using the PI controller 44, phase generator 46 and DDS48 until its frequency matches the transmitter clock rate. Method 300 continues to step 330.

[0035] In step 330, the data input stream is decoded using the extraction clock rate to obtain the encoded data within the data input stream. This step is similar to step 250 of method 200, and its discussion is attributed to this step 330. Method 300 then ends.

[0036] In some embodiments, the extraction / synchronization clock rate of a particular transmitting device may be stored in the memory of a receiving device 14, such as the memory 37 of a receiver 18, and used for communication with that particular transmitting device. For example, the device ID of a transmitting device may be transmitted using a data input stream or generated by the receiving device 14, which can assign the generated device ID to each unique device it detects. The generated ID, along with the extraction clock rate, may be stored in the memory 37 and used for communication with that device.

[0037] In at least some embodiments, Method 200 and / or Method 300 enable ad-hoc data communication synchronization so that for each data input stream transmitted and received at the receiver 18, the receiver 18 or receiving device 14 can determine the synchronization or extraction clock rate of that data input stream. In such embodiments, the synchronization or extraction clock rate does not need to be stored, as it can be easily determined using steps 220-240 of Method 200 or step 320 of Method 300.

[0038] As will be understood by those skilled in the art, Method 200, Method 300, and / or Optical Communication System 10 may be adapted to extract a clock rate from a data input stream so that the data input stream can be decoded to obtain data being communicated between a transmitting device and a receiving device, for purposes such as communicating information between a transmitting device 12 and a receiving device 14. Various specific vehicle applications will be obvious to those skilled in the art.

[0039] Figure 16 provides one such example for vehicle applications in which the components and / or features of the systems 10 and methods 200, 300 described above can be used. In particular, Figure 16 shows a vehicle communication system 600 including a first vehicle or host vehicle 610, a second vehicle 611, a third vehicle 612, a fourth vehicle 613, a fifth vehicle 614, a sixth vehicle 615, and roadside equipment (RSE) 617. Each of the vehicles 610-616 and the RSE 617 may include one or more optical communication modules including transmitting and / or receiving devices, and thus may be referred to as optical communication nodes 612-617 communicating with each other in an ad-hoc optical communication network 601. For example, each of the optical communication nodes 612-617 may include one or more transmitting devices and one or more receiving devices for purposes such as performing bidirectional communication with other optical communication nodes 612-617 in the ad-hoc optical communication network 601. Each of the optical communication nodes 612-617 may be a transmitting device characterized above as transmitting device 12. Each of the optical communication nodes 612-617 may be a transmitting device characterized above as receiving device 14. The description of the ad hoc line-of-sight optical communication network described in U.S. Patent No. 11,245,469 is incorporated herein by reference and belongs to the vehicle communication system 600.

[0040] Figure 17 shows a host vehicle 610, which is shown as including vehicle electronics 611 having a left headlight communication module 621, a right headlight communication module 622, a left taillight communication module 623, a right taillight communication module 624, a center taillight communication module 625, a left side mirror communication module 626, and a right side mirror communication module 627. Each of these optical communication modules 621-627 includes a transmitting device and a receiving device for bidirectional optical communication and is integrated into an existing headlight or taillight of the host vehicle 610 as described in U.S. Patent No. 11,245,469, which is incorporated herein by reference and is attributed to the host vehicle 610 unless otherwise specified in relation to the clear description of the host vehicle 610 herein. Furthermore, it should be understood that in other embodiments, the transmitting devices and / or receiving devices of the optical communication modules 621-627 may be integrated into other components of the host vehicle 610 (instead of headlights or other external vehicle light / lamp modules) and / or the configuration and number may differ.

[0041] Each transmitting device of communication modules 621-627 may be a transmitting device characterized above as transmitting device 12. Each receiving device of communication modules 621-627 may be a transmitting device characterized above as receiving device 14. Each of the other optical communication nodes 612-617 may similarly have optical communication modules similar to the optical communication modules 621-627 of the host vehicle 610, and these optical communication modules may be used for bidirectional communication in the ad hoc optical communication network 601. In at least some embodiments, the optical communication in such embodiments is line-of-sight optics or optical communication, so the ad hoc optical communication network 601 is a line-of-sight ad hoc optical communication network. Each of the optical communication modules described above may implement methods 200 and / or 300 for the purpose of synchronizing communication between optical communication modules in the ad hoc optical communication network 601.

[0042] It should be understood that the foregoing description pertains to one or more embodiments of the present invention. The present invention is not limited to the specific embodiments disclosed herein, but rather is defined solely by the appended claims. Furthermore, the statements contained herein should not be construed as limitations on the definitions of terms used in the scope of the present invention or in the claims, except in relation to the disclosed embodiments where the terms or phrases are clearly defined above. Various other embodiments, as well as various changes and modifications to the disclosed embodiments, will be apparent to those skilled in the art.

[0043] Where used herein and in the claims, the terms “for example,” “for instance,” “such as,” and “etc.,” as well as the verbs “to have,” “to possess,” “to include,” and their other verb forms, when used in conjunction with an enumeration of one or more components or other items, should each be interpreted as open-ended, meaning that the enumeration should not be considered to exclude any other additional components or items. Other terms should be interpreted using their broadest reasonable meaning unless used in a context requiring a different interpretation. Furthermore, the term “and / or” should be interpreted as logical disjunction. Thus, for example, the phrase “A, B, and / or C” should be interpreted as encompassing all of “A,” “B,” “C,” “A and B,” “A and C,” “B and C,” and “A, B, and C.”

Claims

1. A method for synchronizing a receiver with a transmitter so as to decode a data input stream transmitted by the transmitter and received by the receiver, The receiver receives a data input stream, the data input stream having a first data rate set based on the transmitter clock rate, Generating waves and To obtain the phase error between the data input stream and the generated wave, This includes inputting the phase error to a proportional integral (PI) controller, the PI controller being connected to a wave generator used to generate the generated wave, the wave generator including a phase generator and a direct digital synthesizer (DDS), The synchronization clock rate is determined by using the phase error to adjust the frequency of the generated wave so that the frequency of the generated wave matches the transmitter clock rate of the data input stream, The synchronized clock rate is used to decode the data input stream in order to obtain the encoded data in the data input stream. Methods that include...

2. The method according to claim 1, wherein the PI controller outputs a phase step input to the phase generator, and the phase generator is operably connected to the DDS.

3. The method according to claim 2, wherein the generated wave output by the DDS is mixed or multiplied with the data input stream to generate the phase error.

4. The method according to claim 1, wherein the synchronization clock rate is determined based on a feedback process that modifies the frequency and / or phase of the generated wave until the phase error falls below a predetermined threshold at which the transmitter clock rate of the data input stream and the frequency of the generated wave are considered to match.

5. The method of claim 4, wherein the acquisition of the phase error is performed recursively or iteratively until the phase error between the data input stream and the generated wave falls below a predetermined threshold at which the transmitter clock rate of the data input stream and the frequency of the generated wave are considered to match.

6. The method according to claim 1, wherein the generated wave is a sine wave.

7. The method according to claim 1, wherein the method is performed by an optical communication node having a receiving device configured to perform the method.

8. The method according to claim 1, wherein an initial frequency is used to initially generate the wave, and the initial frequency is predetermined.

9. An optical communication receiver, A photodetector for receiving a data input stream, A clock extraction module having a phase generator, a direct digital synthesizer (DDS) operably connected to the output of the phase generator, and a proportional integral (PI) controller whose output is operably connected to the phase generator, wherein the output of the DDS is used to acquire a phase error input to the PI controller. Equipped with, The clock extraction module is configured to perform a feedback process that includes adjusting the frequency of the generated wave based on the acquired phase error until the phase error falls below a predetermined threshold at which the transmitter clock rate of the data input stream and the frequency of the generated wave are considered to match. The optical communication receiver is configured to decode the data input stream using a synchronized clock rate determined based on the feedback process in order to acquire data.

10. The optical communication receiver according to claim 9, wherein the synchronization clock rate is determined based on the adjusted frequency of the generated wave when the transmitter clock rate of the data input stream is considered to match the frequency of the generated wave.

11. The optical communication receiver according to claim 9, wherein the PI controller is used to generate a phase step as the output operably connected to the phase generator, the phase step being generated based on the phase error.

12. The optical communication receiver according to claim 9, wherein the phase error is obtained by mixing or multiplying the data input stream with the generated wave.

13. The optical communication receiver according to claim 9, wherein the synchronized clock rate is internally synchronized to the data input stream without using external communication.

14. The optical communication receiver according to claim 9, wherein the clock extraction module is configured to provide the synchronized clock rate to a finite state machine.

15. The optical communication receiver according to claim 14, wherein the finite state machine is operably connected to the processor to provide the processor with the data.

16. A method for synchronizing a receiver with a transmitter so as to decode a data input stream transmitted by the transmitter and received by the receiver, The receiver receives a data input stream, the data input stream having a first data rate set based on the transmitter clock rate, Generating waves and To obtain the phase error between the data input stream and the generated wave, The synchronization clock rate is determined by using the phase error to adjust the frequency of the generated wave to match the transmitter clock rate of the data input stream, wherein the synchronization clock rate is determined based on a feedback process that modifies the frequency and / or phase of the generated wave until the phase error falls below a predetermined threshold at which the transmitter clock rate of the data input stream and the frequency of the generated wave are considered to match. The synchronized clock rate is used to decode the data input stream in order to obtain the encoded data in the data input stream. Methods that include...

17. The method according to claim 16, further comprising inputting the phase error to a proportional integral (PI) controller, the PI controller being connected to a wave generator used to generate the generated wave, the wave generator comprising a phase generator and a direct digital synthesizer (DDS).

18. The method according to claim 17, wherein the PI controller outputs a phase step input to the phase generator, and the phase generator is operably connected to the DDS.

19. The method of claim 18, wherein the generated wave output by the DDS is mixed or multiplied with the data input stream to generate the phase error.

20. The method according to claim 16, wherein the acquisition of the phase error is performed recursively or iteratively until the phase error between the data input stream and the generated wave falls below a predetermined threshold at which the transmitter clock rate of the data input stream and the frequency of the generated wave are considered to match.

21. The method according to claim 16, wherein the generated wave is a sine wave.

22. The method according to claim 16, wherein the method is performed by an optical communication node having a receiving device configured to perform the method.

23. The method according to claim 16, wherein an initial frequency is used to initially generate the wave, and the initial frequency is predetermined.

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