Display boards and display devices

Abstract

The present disclosure provides a display substrate and a display device, the display substrate including a base, a plurality of pixel units disposed on the base, and a scan line, the pixel unit including a plurality of sub-pixels and a light-shielding layer, the plurality of sub-pixels are sequentially arranged along a first direction, the sub-pixels include a sub-pixel driving circuit and a light-emitting element that are mutually coupled, the sub-pixel driving circuit is used to provide a driving signal to the light-emitting element, at least a portion of the light-shielding layer is located between the sub-pixel driving circuit and the base, the scan line includes at least a portion extending along the first direction, the scan line is coupled to a corresponding sub-pixel driving circuit, and the scan line is disposed in the same layer as the light-shielding layer.

Description

Technical Field

[0001] The present disclosure relates to the field of display technologies, and particularly to display substrates and display devices.

Background Art

[0002] Currently, the mature technologies in the display field include liquid crystal display technology and active matrix organic light-emitting diode (OLED) display technology. OLED display products excite spectra of various wavelengths and form patterns through the direct recombination of electrons and holes. The display device formed by OLED display technology has a fast response speed and can achieve the maximization of contrast at the same time. Therefore, OLED display devices are expected to become the mainstream products of the next generation of displays.

[0003] When OLED display devices are applied in the field of large-size and high-resolution, the pixel layout space is limited, and they are affected by rules such as line width and line spacing. The resistance-capacitance delay (RC Delay) of the signal lines is too large, which affects the performance of the device.

Summary of the Invention

Problems to be Solved by the Invention

[0004] An object of the present disclosure is to provide a display substrate and a display device.

Means for Solving the Problems

[0005] To achieve the above object, the present disclosure provides the following technical solutions.

[0006] In a first aspect of the present disclosure, a display substrate is provided. The display substrate includes a base and a plurality of pixel units disposed on the base. The pixel units include a plurality of sub-pixels and a light-shielding layer. The plurality of subpixels are sequentially arranged along a first direction, and the subpixels include interconnected subpixel driving circuits and light-emitting elements, the subpixel driving circuits are used to provide driving signals to the light-emitting elements. At least a portion of the light-shielding layer is located between the subpixel driving circuit and the base, The display substrate further includes scan lines, the scan lines including at least a portion extending along the first direction, the scan lines being coupled to a corresponding subpixel driving circuit, and the scan lines being installed in the same layer as the light-shielding layer.

[0007] Selectively, the thickness d of the scan line in a direction perpendicular to the direction of the base satisfies 0.5 μm ≤ d ≤ 1.5 μm.

[0008] Selectively, the scanning lines are installed in the same layer and material as the light-shielding layer.

[0009] The display board may optionally include scanning guide lines. The scanning guide line is located on the opposite side of the base of the corresponding scanning line, and the scanning guide line is coupled to the corresponding scanning line and to the subpixel driving circuit within the corresponding subpixel.

[0010] Selectively, the scanning auxiliary line includes a first scanning auxiliary pattern, a second scanning auxiliary pattern, and a third scanning auxiliary pattern, the third scanning auxiliary pattern being located between the first scanning auxiliary pattern and the second scanning auxiliary pattern, the first scanning auxiliary pattern and the second scanning auxiliary pattern being coupled to a subpixel driving circuit within the corresponding subpixel, and the third scanning auxiliary pattern being coupled to the corresponding scanning line, the first scanning auxiliary pattern, and the second scanning auxiliary pattern, respectively. The scan lines coupled to the third scanning aid pattern include a first boundary and a second boundary arranged along a second direction, the second direction intersecting the first direction, the orthogonal projection of the first boundary onto the base partially overlaps with the orthogonal projection of the first scanning aid pattern onto the base, and the orthogonal projection of the second boundary onto the base partially overlaps with the orthogonal projection of the second scanning aid pattern onto the base.

[0011] The display board may optionally include data lines and data auxiliary lines. The data line includes at least a portion extending along a second direction, the second direction intersecting the first direction, and the data line is coupled to a corresponding subpixel driving circuit. The data auxiliary lines are coupled to the corresponding data lines, are located between the corresponding data lines and the base, and are installed in the same layer and material as the light-shielding layer.

[0012] Selectively, the scan line includes a first scan portion and a second scan portion, both of which extend along the first direction. In a direction perpendicular to the first direction, the width of the first scanning portion is smaller than the width of the second scanning portion. The orthogonal projection of the first scanning portion onto the base overlaps at least partially with the orthogonal projection of the data lines onto the base.

[0013] Selectively, the data auxiliary line includes at least two data auxiliary patterns, the at least two data auxiliary patterns are arranged along the second direction, and the at least two data auxiliary patterns are each connected to a corresponding data line.

[0014] Selectively, the orthogonal projection of the scan line onto the base is located between the orthogonal projections of adjacent data auxiliary patterns onto the base.

[0015] The display board may optionally include power lines and auxiliary power lines. The power line includes at least a portion extending along the second direction, and the power line is coupled to the corresponding subpixel drive circuit. The power supply auxiliary wire is coupled to the corresponding power supply wire, is located between the power supply wire and the base, and is installed in the same layer and material as the light-shielding layer.

[0016] Selectively, the power supply auxiliary line includes at least two power supply auxiliary patterns, the at least two power supply auxiliary patterns are arranged along the second direction, and the at least two power supply auxiliary patterns are each coupled to a corresponding power supply line.

[0017] Selectively, the orthogonal projection of at least one of the scan lines onto the base lies between the orthogonal projections of adjacent power-assisted patterns onto the base.

[0018] The display board may optionally include sensing lines and sensing auxiliary lines. The sensing line includes at least a portion that extends along the second direction, The sensing guide line is coupled to the sensing line, is located between the sensing line and the base, is installed in the same layer and material as the light-shielding layer, includes at least a portion extending along the first direction, and is coupled to the corresponding subpixel driving circuit.

[0019] Selectively, the subpixel driving circuit includes a driving transistor, a writing transistor, a sensing transistor, and a storage capacitor. The first pole of the drive transistor is coupled to the power line, and the second pole of the drive transistor is coupled to the light-emitting element. The gate of the writing transistor is coupled to the scan line, the first pole of the writing transistor is coupled to the data line, and the second pole of the writing transistor is coupled to the gate of the drive transistor. The gate of the sensing transistor is coupled to the scanning line, the first pole of the sensing transistor is coupled to the second pole of the driving transistor, and the second pole of the sensing transistor is coupled to the sensing line. The first electrode plate of the storage capacitor is coupled to the gate of the driving transistor, and the second electrode plate of the storage capacitor is coupled to the second pole of the driving transistor.

[0020] Optionally, the writing transistor includes a writing active layer, and the sensing transistor includes a sensing active layer. In the same pixel unit, the orthographic projection of the writing active layer onto the base is located on a first side of the orthographic projection of the scanning line coupled to the writing transistor onto the base, the orthographic projection of the sensing active layer onto the base is located on a second side of the orthographic projection of the scanning line onto the base, and the first side and the second side face each other along the second direction.

[0021] Optionally, the driving transistor includes a driving active layer, and at least a part of the orthographic projection of the writing active layer onto the base is located between the orthographic projection of the driving active layer onto the base and the orthographic projection of the scanning line onto the base.

[0022] Optionally, the sub-pixel further includes a pixel defining layer, and the pixel defining layer defines a pixel aperture. In the same sub-pixel, the orthographic projection of the sensing active layer onto the base is located between the orthographic projection of the pixel aperture onto the base and the orthographic projection of the scanning line onto the base.

[0023] Optionally, the first electrode plate is disposed in the same layer and made of the same material as the driving active layer, the second electrode plate is disposed in the same layer and made of the same material as the data line, the second electrode plate is coupled to the light shielding layer, and the orthographic projection of the second electrode plate onto the base at least partially overlaps with the orthographic projection of the light shielding layer onto the base.

[0024] Selectively, the driving active layer includes a driving channel portion, and the orthogonal projection of the light-shielding layer onto the base at least partially overlaps with the orthogonal projection of the driving channel portion onto the base.

[0025] Based on the technical solution for the display board described above, a second aspect of this disclosure provides a display device including the display board described above. [Brief explanation of the drawing]

[0026] [Figure 1] This is a circuit diagram of a subpixel driving circuit according to an embodiment of the present disclosure. [Figure 2] This is a schematic diagram of the layout of a pixel unit according to an embodiment of the present disclosure. [Figure 3] Figure 2 is a schematic diagram of the layout of the light-shielding layer. [Figure 4] Figure 2 is a schematic diagram of the active layer layout. [Figure 5] Figure 2 is a schematic diagram of the gate metal layer layout. [Figure 6] This is a schematic diagram of a via hole formed by the CNT process according to an embodiment of the present disclosure. [Figure 7] This is a schematic diagram of a via hole formed by patterning an interlayer insulating layer according to an embodiment of the present disclosure. [Figure 8] Figure 2 is a schematic diagram of the source-drain metal layer layout. [Figure 9] Figure 2 is a schematic diagram of the color resistance pattern layout. [Figure 10] Figure 2 is a schematic diagram of the anode layer layout. [Figure 11] Figure 2 is a schematic diagram of the layout of the pixel aperture region. [Figure 12] Figure 2 is a schematic diagram of the layout of the light-shielding layer and the active layer. [Figure 13] Figure 12 is a schematic diagram with a gate metal layer added. [Figure 14] Figure 13 is a schematic diagram with via holes added using the CNT process. [Figure 15] Figure 14 is a schematic diagram with via holes added to the interlayer insulation layer. [Figure 16] Figure 15 is a schematic diagram showing the addition of a source-drain metal layer. [Figure 17] Figure 16 is a schematic diagram with a color resistance pattern added. [Figure 18] Figure 17 is a schematic diagram with an anode layer added. [Modes for carrying out the invention]

[0027] The drawings described above are used to provide a further understanding of the Disclosure and constitute part of the Disclosure. The exemplary embodiments and descriptions thereof are used to interpret the Disclosure and do not constitute an unreasonable limitation to the Disclosure.

[0028] To further describe the display substrate and display device according to the embodiments of this disclosure, they will be described in detail below with reference to the drawings of the specification.

[0029] As shown in Figures 1, 2, and 3, embodiments of the present disclosure provide a display substrate comprising a base and a plurality of pixel units mounted on the base, wherein each pixel unit comprises a plurality of subpixels and a light-shielding layer 10. The plurality of subpixels are sequentially arranged along a first direction, and the subpixels include a coupled subpixel driving circuit and a light-emitting element (EL), the subpixel driving circuit is used to provide a driving signal to the light-emitting element (EL), At least a portion of the light-shielding layer 10 is located between the subpixel driving circuit and the base, The display substrate further includes a scan line GA, the scan line GA including at least a portion extending along the first direction, the scan line GA being coupled to a corresponding subpixel driving circuit, and the scan line GA being installed in the same layer as the light-shielding layer 10.

[0030] Exemplary, the plurality of pixel units are distributed in an array on the base. The plurality of pixel units can be divided into a plurality of row pixel units and a plurality of column pixel units, wherein the plurality of row pixel units are arranged along a second direction, and each row of pixel units includes a plurality of pixel units arranged along a first direction, and the plurality of column pixel units are arranged along the first direction, and each column of pixel units includes a plurality of pixel units arranged along the second direction.

[0031] For example, the first direction includes the horizontal direction, and the second direction includes the vertical direction.

[0032] Exemplary, the pixel unit includes a red subpixel, a green subpixel, a cyan subpixel, and a white subpixel.

[0033] Exemplary, the subpixel includes a subpixel driver circuit and a light-emitting element (EL), the subpixel driver circuit being coupled to the anode in the light-emitting element (EL) and used to provide a drive signal to the anode. Exemplary, the subpixel driver circuit includes, but is not limited to, a 3T1C (i.e., three transistors and one capacitor) structure. The cathode of the light-emitting element (EL) receives a negative power supply signal VSS.

[0034] As shown in Figures 2 to 11, 17 and 18, the display substrate, exemplary, includes a stacked light-shielding layer 10, an active layer, a gate insulating layer, a gate metal layer, an interlayer insulating layer, a source-drain metal layer, a passivation layer, a color film layer 50, a flat layer, an anode layer 60, a pixel definition layer, a light-emitting functional layer, and a cathode layer, which are sequentially formed along the direction away from the base. The pixel definition layer can define a pixel aperture, and the region where the pixel aperture is located forms a pixel aperture region 30.

[0035] Figures 6 and 14 schematically show via holes formed by the CNT via hole process. Figures 7 and 15 schematically show via holes formed by masking the interlayer insulating layer.

[0036] After forming the interlayer insulating layer, a CNT process is first performed to create semi-via holes in the interlayer insulating layer that do not penetrate it. Subsequently, the interlayer insulating layer is masked once to form via holes that penetrate it. After masking the interlayer insulating layer, some of the via holes can penetrate the interlayer insulating layer and extend to the light-shielding layer, while others penetrate only the interlayer insulating layer.

[0037] Exemplary, at least a portion of the light-shielding layer 10 is located between the active layer included in the subpixel driving circuit and the base.

[0038] Exemplary, the orthogonal projection of the light-shielding layer 10 onto the base at least partially overlaps with the orthogonal projection of the active layer contained in the sub-transistor within the sub-pixel driving circuit onto the base.

[0039] For example, the light-shielding layer 10 is made using a conductive metallic material such as metallic copper.

[0040] Exemplary, the display board includes a plurality of scan line GAs, each of which corresponds one-to-one with the plurality of rows of pixel units, and each scan line GA is coupled to a subpixel driving circuit contained in each subpixel within the corresponding row of pixel units.

[0041] For example, the scan line GA is used to transmit a scan signal. The scan line GA is coupled to the gate of a corresponding transistor in a subpixel driving circuit and is used to transmit the scan signal to the gate of the corresponding transistor.

[0042] Exemplary, the scan line GA extends along the first direction. The fact that the scan line GA extends along the first direction means that The scan line GA includes a primary portion and a secondary portion connected to the primary portion, wherein the primary portion is a line, line segment, or rod, the primary portion extends along the first direction, and the length of the primary portion extending along the first direction is greater than the length of the secondary portion extending along other directions.

[0043] According to the display substrate according to the embodiment of the present disclosure, the scan line GA is installed in the same layer as the light-shielding layer 10 so as to be close to the base. By increasing the thickness of the scan line GA in this way, the electrical resistance of the scan line GA can be reduced, the load on the scan line GA can be effectively reduced, excessive signal delay can be avoided when the scan line GA transmits a scanning signal, a high refresh rate can be achieved, the display effect can be optimized, the operational stability of the display substrate can be guaranteed, and the service life of the display substrate can be improved.

[0044] Furthermore, because the scan line GA is close to the base, there is a large distance between the scan line GA and other conductive structures in the display substrate in the direction perpendicular to the base, which can reduce the parasitic capacitance formed between the scan line GA and other conductive structures. Therefore, according to the embodiment of the present disclosure, there is no need to install a thick insulating layer to reduce parasitic capacitance, which can effectively reduce the difficulty of the manufacturing process of the display substrate and improve the possibility of mass production of the display substrate.

[0045] Furthermore, because the thick scan line GA is in close proximity to the base, the scan line GA can be preferentially manufactured in the display substrate manufacturing process flow, thereby reducing the likelihood of distortion in the base and effectively decreasing the risk of fragmentation.

[0046] In some embodiments, the thickness d of the scan line GA in the direction perpendicular to the direction of the base satisfies 0.5 μm ≤ d ≤ 1.5 μm.

[0047] For example, the thickness of the scan line GA in a direction perpendicular to the direction of the base includes 1 μm.

[0048] By setting the scan line GA within the above thickness range, the load on the scan line GA can be effectively reduced, excessive signal delay can be avoided when the scan line GA transmits scanning signals, a high refresh rate can be achieved, the display effect can be optimized, the operational stability of the display board can be guaranteed, and the lifespan of the display board can be improved.

[0049] As shown in Figure 3, in some embodiments, the scan line GA is installed in the same layer and material as the light-shielding layer 10. As described above, by placing the scan line GA on the same layer and material as the light-shielding layer 10, the scan line GA and the light-shielding layer 10 can be formed simultaneously in the same patterning process, further simplifying the display substrate manufacturing process flow and reducing the manufacturing cost of the display substrate.

[0050] As shown in Figures 3, 5 and 13, in some embodiments, the display substrate further includes a scanning auxiliary line GAF. The scanning auxiliary line GAF is located on the opposite side of the base of the corresponding scanning line GA, and the scanning auxiliary line GAF is coupled to the corresponding scanning line GA and to the subpixel driving circuit within the corresponding subpixel.

[0051] For example, the display substrate includes a plurality of scanning guide line GAFs, and each scanning guide line GAF corresponds one-to-one with a subpixel included in the display substrate.

[0052] Exemplary, multiple scanning guide line GAFs located in the same row along the first direction are each coupled to the corresponding identical scanning line GA. Exemplary, multiple scanning guide line GAFs located in the same row along the first direction are arranged at intervals. Exemplary, multiple scanning guide line GAFs located in the same row along the first direction are formed as a single unit.

[0053] For example, the scanning auxiliary line GAF is fabricated using the gate metal layer.

[0054] Exemplary, the scanning auxiliary line GAF is formed integrally with the gate of a transistor in the corresponding coupled subpixel driving circuit.

[0055] For example, the orthogonal projection of the scan auxiliary line GAF onto the base has an overlapping region with the orthogonal projection of the scan line GA onto the base.

[0056] As shown in Figure 8, exemplary, the pixel unit further includes a plurality of first conductive connectors 41, each of which includes at least a portion extending along the first direction, and each first conductive connector 41 is coupled to the scan line GA and the corresponding scan auxiliary line GAF. Exemplarily, the first conductive connector 41 is located on the opposite side of the scan auxiliary line GAF from the base. Exemplarily, the first conductive connector 41 is located on the same layer and in the same material as the data line DA in the display substrate.

[0057] By configuring the pixel unit to further include a scanning auxiliary line GAF coupled to the scanning line GA, it is possible not only to guarantee the connection performance between the scanning line GA and the corresponding subpixel driving circuit, but also to reduce the electrical resistance of the scanning line GA, better avoid excessive signal delay when the scanning line GA transmits scanning signals, better achieve a high refresh rate, optimize the display effect, guarantee the operational stability of the display board, and improve the service life of the display board.

[0058] As shown in Figures 2, 5 and 13, in some embodiments, the scanning auxiliary line GAF includes a first scanning auxiliary pattern 210, a second scanning auxiliary pattern 211 and a third scanning auxiliary pattern 212, wherein the third scanning auxiliary pattern 212 is located between the first scanning auxiliary pattern 210 and the second scanning auxiliary pattern 211, the first scanning auxiliary pattern 210 and the second scanning auxiliary pattern 211 are each coupled to a subpixel driving circuit in the corresponding subpixel, and the third scanning auxiliary pattern 212 is each coupled to the corresponding scanning line GA, the first scanning auxiliary pattern 210 and the second scanning auxiliary pattern 211. The scan line GA coupled to the third scanning aid pattern 212 includes a first boundary and a second boundary arranged along a second direction, the second direction intersecting the first direction, the orthogonal projection of the first boundary onto the base partially overlaps with the orthogonal projection of the first scanning aid pattern 210 onto the base, and the orthogonal projection of the second boundary onto the base partially overlaps with the orthogonal projection of the second scanning aid pattern 211 onto the base.

[0059] For example, the first scanning assist pattern 210, the second scanning assist pattern 211, and the third scanning assist pattern 212 are formed as an integral structure.

[0060] For example, the first scanning assist pattern 210 is multiplexed as the gate of the sensing transistor T2, and the second scanning assist pattern 211 is multiplexed as the gate of the writing transistor T1.

[0061] Exemplary, the first scanning aid pattern 210 includes at least a portion extending along the second direction, the second scanning aid pattern 211 includes at least a portion extending along the second direction, and the third scanning aid pattern 212 includes at least a portion extending along the first direction.

[0062] Exemplary, the orthogonal projection of the third scanning aid pattern 212 onto the base lies within the orthogonal projection of the scan line GA onto the base.

[0063] Exemplary, the first conductive connection portion 41 is coupled to the scan line GA and the corresponding third scanning auxiliary pattern 212, respectively.

[0064] Exemplary, the orthogonal projection of the first boundary onto the base partially overlaps with the orthogonal projection of the first scanning aid pattern 210 onto the base, and the orthogonal projection of the second boundary onto the base partially overlaps with the orthogonal projection of the second scanning aid pattern 211 onto the base.

[0065] Exemplary, the orthogonal projection of the first boundary onto the base partially overlaps with the orthogonal projection of the third scanning aid pattern 212 onto the base, and the orthogonal projection of the second boundary onto the base partially overlaps with the orthogonal projection of the third scanning aid pattern 212 onto the base.

[0066] As described above, by setting the scanning auxiliary line GAF to include a first scanning auxiliary pattern 210, a second scanning auxiliary pattern 211, and a third scanning auxiliary pattern 212, not only is good connection performance between the scanning line GA and the subpixel driving circuit guaranteed, but the difficulty of laying out the display board is also effectively reduced.

[0067] As shown in Figures 1, 2, 3, 8, and 16, in some embodiments, the display board further includes data lines DA and data auxiliary lines DAF. The data line DA includes at least a portion extending along a second direction, the second direction intersecting the first direction, and the data line DA is coupled to a corresponding subpixel driving circuit. The data auxiliary line DAF is coupled to the corresponding data line, is located between the corresponding data line DA and the base, and is installed in the same layer and material as the light-shielding layer 10.

[0068] For example, the data line DA is used to transmit a data signal. The data line DA is coupled to a corresponding transistor in a subpixel driver circuit and is used to transmit the data signal to the corresponding transistor.

[0069] Exemplary, the display board further includes a plurality of data line DAs. The display board includes a plurality of subpixels, the plurality of subpixels being divided into a plurality of subpixel rows, the plurality of subpixel rows corresponding one-to-one with the plurality of data line DAs. Each data line DA is coupled to a subpixel driver circuit in a corresponding subpixel row.

[0070] Exemplary, the display board includes a plurality of data auxiliary line DAFs, each data line DA corresponds to a plurality of the data auxiliary line DAFs, and each data line DA is coupled to the corresponding plurality of the data auxiliary line DAFs. Exemplary, each data line DA is arranged sequentially at intervals along the second direction to correspond to a plurality of the data auxiliary line DAFs.

[0071] For example, the data line DA is fabricated using the source-drain metal layer.

[0072] Exemplary, the orthogonal projection of the data auxiliary line DAF onto the base at least partially overlaps with the orthogonal projection of the corresponding data line DA onto the base, and the data auxiliary line DAF and the corresponding data line DA are joined via a via hole at the overlapping location.

[0073] For example, the orthogonal projection of the data auxiliary line DAF onto the base lies inside the orthogonal projection of the corresponding data line DA onto the base.

[0074] Exemplary, the data auxiliary line DAF includes at least a portion extending along the second direction.

[0075] As described above, by setting the data auxiliary line DAF to be coupled to the data line DA, the electrical resistance of the data line DA is effectively reduced, the load on the data line DA is effectively reduced, delays during data signal transmission on the data line DA are avoided, a high refresh rate is achieved, and the operational stability of the display board is guaranteed.

[0076] Furthermore, because the thickness of the light-shielding layer 10 is greater in the direction perpendicular to the base, the data auxiliary line DAF is installed in the same layer and material as the light-shielding layer 10, thereby allowing for a better reduction in the electrical resistance of the data line DA.

[0077] Furthermore, as described above, by installing the data auxiliary line DAF on the same layer and material as the light-shielding layer 10, the data auxiliary line DAF and the light-shielding layer 10 can be formed simultaneously in the same patterning process, thereby effectively simplifying the display substrate manufacturing process flow and reducing the manufacturing cost of the display substrate.

[0078] As shown in Figures 1, 2, 3, 8 and 16, in some embodiments, the scan line GA includes a first scan portion 201 and a second scan portion 202, both of which extend along the first direction. In a direction perpendicular to the first direction, the width d1 of the first scanning portion 201 is smaller than the width d2 of the second scanning portion 202. The orthogonal projection of the first scanning portion 201 onto the base at least partially overlaps with the orthogonal projection of the data line DA onto the base.

[0079] Exemplary, the first scanning portion 201 and the second scanning portion 202 are formed as an integrated structure.

[0080] For example, in the same scan line GA, the first scan portion 201 and the second scan portion 202 are arranged alternately along the first direction.

[0081] For example, in a direction parallel to the base and perpendicular to the first direction, the width of the first scanning portion 201 is smaller than the width of the second scanning portion 202.

[0082] Exemplary, the orthogonal projection of the first scanning portion 201 onto the base at least partially overlaps with the orthogonal projection of the data line DA onto the base, and the orthogonal projection of the second scanning portion 202 onto the base at least partially overlaps with the orthogonal projection of the data line DA onto the base.

[0083] Exemplary, the orthogonal projection of the first scanning portion 201 onto the base at least partially overlaps with the orthogonal projection of the data line DA onto the base, while the orthogonal projection of the second scanning portion 202 onto the base does not overlap with the orthogonal projection of the data line DA onto the base.

[0084] Exemplary, the orthogonal projection of the first scanning portion 201 onto the base at least partially overlaps the orthogonal projection of the power line VDD onto the base.

[0085] As described above, by setting the width of the first scanning portion 201 to be smaller than the width of the second scanning portion 202, and the orthogonal projection of the first scanning portion 201 onto the base to overlap at least partially with the orthogonal projection of the data line DA onto the base, it is advantageous to reduce the overlap area between the scan line GA and the data line DA and to reduce the parasitic capacitance formed between the scan line GA and the data line DA.

[0086] As shown in Figure 3, in some embodiments, the data auxiliary line DAF includes at least two data auxiliary patterns DAF1, the at least two data auxiliary patterns DAF1 are arranged along the second direction, and the at least two data auxiliary patterns DAF1 are each coupled to a corresponding data line DA.

[0087] Exemplary, the at least two data support patterns DAF1 are arranged at intervals along the second direction.

[0088] Exemplary, the data auxiliary pattern DAF1 includes at least a portion that extends along the second direction.

[0089] For example, the orthogonal projection of the data auxiliary pattern DAF1 onto the base overlaps at least partially with the orthogonal projection of the corresponding data line DA onto the base.

[0090] For example, the orthogonal projection of the data auxiliary pattern DAF1 onto the base lies within the orthogonal projection of the corresponding data line DA onto the base.

[0091] As described above, by configuring the data auxiliary line DAF to include at least two data auxiliary patterns DAF1, it is possible not only to effectively reduce the electrical resistance of the data line DA, but also to reduce the risk of short circuits occurring between the data auxiliary line DAF and other conductive structures (e.g., the light-shielding layer 10 and conductive structures installed in the same layer as the light-shielding layer 10), and to effectively reduce the difficulty of laying out the data auxiliary patterns DAF1.

[0092] As shown in Figures 1, 2, 3, 8, and 16, in some embodiments, the orthogonal projection of the scan line GA onto the base lies between the orthogonal projections of the adjacent data auxiliary pattern DAF1 onto the base.

[0093] As described above, by setting the orthogonal projection of the scan line GA onto the base to be located between the orthogonal projections of the adjacent data auxiliary pattern DAF1 onto the base, it is advantageous not only to reduce the difficulty of laying out the display board but also to ensure the reliability and stability of the display board.

[0094] As shown in Figures 2, 3, 8, and 16, in some embodiments, the display board further includes a power line VDD and an auxiliary power line VDDF. The power line VDD includes at least a portion extending along the second direction, and the power line VDD is coupled to the corresponding subpixel drive circuit. The power supply auxiliary line VDDF is coupled to the corresponding power supply line VDD, is located between the power supply line VDD and the base, and is installed in the same layer and material as the light-shielding layer 10.

[0095] Exemplary, the power line VDD is used to transmit a power signal (e.g., a positive power signal). The power line VDD is coupled to a corresponding transistor in the subpixel driver circuit and is used to transmit the power signal to the corresponding transistor.

[0096] For example, the power line VDD is fabricated using the source-drain metal layer.

[0097] Exemplary, the orthogonal projection of the power supply auxiliary line VDDF onto the base at least partially overlaps with the orthogonal projection of the corresponding power supply line VDD onto the base, and the power supply auxiliary line VDDF and the corresponding power supply line VDD are coupled via a via hole at the overlapping location.

[0098] Exemplary, the orthogonal projection of the power supply auxiliary line VDDF onto the base lies within the orthogonal projection of the corresponding power supply line VDD onto the base.

[0099] Exemplary, the power supply auxiliary line VDDF includes at least a portion extending along the second direction.

[0100] As described above, by setting the power supply auxiliary line VDDF to be coupled to the power supply line VDD, the electrical resistance of the power supply line VDD can be effectively reduced, and the load on the power supply line VDD can be effectively reduced.

[0101] Furthermore, because the thickness of the light-shielding layer 10 is greater in the direction perpendicular to the base, the power supply auxiliary line VDDF is installed in the same layer and material as the light-shielding layer 10, thereby allowing for a better reduction in the electrical resistance of the power supply line VDD.

[0102] Furthermore, as described above, by installing the power supply auxiliary line VDDF in the same layer and material as the light-shielding layer 10, the power supply auxiliary line VDDF and the light-shielding layer 10 can be formed simultaneously in the same patterning process, thereby effectively simplifying the display substrate manufacturing process flow and reducing the manufacturing cost of the display substrate.

[0103] As shown in Figures 2, 3, 8, and 16, in some embodiments, the power supply auxiliary line VDDF includes at least two power supply auxiliary patterns VDDF1, the at least two power supply auxiliary patterns VDDF1 are arranged along the second direction, and the at least two power supply auxiliary patterns VDDF1 are each coupled to the corresponding power supply line VDD.

[0104] Exemplary, the at least two power supply auxiliary patterns VDDF1 are arranged at intervals along the second direction.

[0105] Exemplary, the power supply auxiliary pattern VDDF1 includes at least a portion that extends along the second direction. Exemplary, the orthogonal projection of the power supply auxiliary pattern VDDF1 onto the base at least partially overlaps the orthogonal projection of the corresponding power line VDD onto the base.

[0106] Exemplary, the orthogonal projection of the power supply auxiliary pattern VDDF1 onto the base lies within the orthogonal projection of the corresponding power line VDD onto the base.

[0107] As described above, by configuring the power supply auxiliary line VDDF to include at least two power supply auxiliary patterns VDDF1, it is possible not only to effectively reduce the electrical resistance of the power supply line VDD, but also to reduce the risk of short circuits occurring between the power supply auxiliary line VDDF and other conductive structures (e.g., the light-shielding layer 10 and conductive structures installed in the same layer as the light-shielding layer 10), and to effectively reduce the difficulty of laying out the power supply auxiliary patterns VDDF1.

[0108] As shown in Figures 2, 3, 8, and 16, in some embodiments, the orthogonal projection of at least one of the scan line GA onto the base lies between the orthogonal projections of the adjacent power supply auxiliary pattern VDDF1 onto the base.

[0109] As described above, by setting the orthogonal projection of the scan line GA onto the base to be located between the orthogonal projections of the adjacent power supply auxiliary pattern VDDF1 onto the base, it is advantageous not only to reduce the difficulty of laying out the display board but also to ensure the reliability and stability of the display board.

[0110] As shown in Figures 2, 3, 8, and 16, in some embodiments, the display board further includes a sensing line SE and a sensing auxiliary line SEF. The sensing line SE includes at least a portion that extends along the second direction, The sensing guide line SEF is coupled to the sensing line SE, is located between the sensing line SE and the base, is installed in the same layer and material as the light-shielding layer 10, includes at least a portion extending along the first direction, and is coupled to the corresponding subpixel driving circuit.

[0111] For example, the display board includes a plurality of sensing lines SE, the plurality of pixel units within the display board are divided into a plurality of rows of pixel units, the plurality of sensing lines SE correspond one-to-one with the plurality of rows of pixel units, and the sensing lines SE are coupled to each subpixel driving circuit included in the corresponding row of pixel units.

[0112] For example, the sensing wire SE is fabricated using a source-drain metal layer.

[0113] For example, the sensing line SE can supply a reference signal to reset the anode layer 60 of the light-emitting element EL during the time period in which a data signal is being written. The sensing line SE can further transmit the sensing signal sensed from the anode layer 60 during the sensing time period.

[0114] Exemplary, the sensing auxiliary line SEF includes at least a portion extending along the first direction.

[0115] Exemplary, the display board includes a plurality of sensing guide lines SEF, each of which corresponds one-to-one with a plurality of pixel units within the display board, and each sensing guide line SEF is coupled to each subpixel driving circuit and corresponding sensing line SE within the corresponding pixel unit.

[0116] Exemplary, the orthogonal projection of the sensing auxiliary line SEF onto the base at least partially overlaps with the orthogonal projection of the corresponding sensing line SE onto the base, and the sensing auxiliary line SEF is interconnected with the sensing line SE at the overlapping location.

[0117] Exemplary, the sensing guideline SEF is coupled to the corresponding transistor included in each subpixel driving circuit within the corresponding pixel unit.

[0118] As described above, by setting the sensing auxiliary line SEF to be coupled to the sensing line SE, the electrical resistance of the sensing line SE can be effectively reduced, and the load on the sensing line SE can be effectively reduced.

[0119] Furthermore, because the light-shielding layer 10 is thicker in the direction perpendicular to the base, the sensing auxiliary line SEF is installed in the same layer and material as the light-shielding layer 10, thereby allowing for a more effective reduction in the electrical resistance of the sensing line SE.

[0120] Furthermore, as described above, by installing the sensing guide line SEF in the same layer and material as the light-shielding layer 10, the sensing guide line SEF and the light-shielding layer 10 can be formed simultaneously in the same patterning process, thereby effectively simplifying the display substrate manufacturing process flow and reducing the manufacturing cost of the display substrate.

[0121] In the display board according to the above embodiment, assuming that no new processes are required, the electrical resistance of the scan line GA, data line DA, sensing line SE, and power line VDD can be effectively reduced, improving the delay phenomenon that occurs when the corresponding signals are transmitted by the signal lines. At the same time, the IR drop when the power signal is transmitted by the power line VDD can be significantly reduced.

[0122] As shown in Figures 1, 2, and 13, in some embodiments, the subpixel driving circuit includes a driving transistor T3, a writing transistor T1, a sensing transistor T2, and a storage capacitor Cst. The first pole of the drive transistor T3 is coupled to the power line VDD, and the second pole of the drive transistor T3 is coupled to the light-emitting element EL. The gate of the writing transistor T1 is coupled to the scan line GA, the first pole of the writing transistor T1 is coupled to the data line DA, and the second pole of the writing transistor T1 is coupled to the gate T3-G of the drive transistor T3. The gate of the sensing transistor T2 is coupled to the scan line GA, the first pole of the sensing transistor T2 is coupled to the second pole of the drive transistor T3, and the second pole of the sensing transistor T2 is coupled to the sensing line SE. The first plate Cst1 of the storage capacitor Cst is coupled to the gate T3-G of the drive transistor T3, and the second plate Cst2 of the storage capacitor Cst is coupled to the second pole of the drive transistor T3.

[0123] Furthermore, as shown in Figure 4, within each pixel unit, the area of ​​the first electrode plate Cst1 of the storage capacitor Cst contained in at least two subpixels may be made different in order to accommodate the different subpixel requirements for the capacitance value of the storage capacitor.

[0124] For example, the first pole of the drive transistor T3 is coupled to the power line VDD, and the second pole of the drive transistor T3 is coupled to the anode layer 60 of the light-emitting element EL.

[0125] For example, both the writing transistor T1 and the sensing transistor T2 function as switch transistors.

[0126] For example, the writing transistor T1 is turned on or off under the control of the scanning signal from the scan line GA. The sensing transistor T2 is turned on or off under the control of the scanning signal from the scan line GA.

[0127] Exemplary, the subpixel driving circuit includes a 3T1C structure, and the pixel unit includes one scanline GA.

[0128] For example, the orthogonal projection of the first plate Cst1 of the storage capacitor Cst onto the base at least partially overlaps with the orthogonal projection of the second plate Cst2 of the storage capacitor Cst onto the base.

[0129] By reducing the load on the scan line GA, delays in the transmission of scan signals by the scan line GA can be avoided, and the charge level at which the data line DA writes data signals to the gate T3-G of the drive transistor T3 can be guaranteed, thereby enabling the display board to meet the requirements for a high refresh rate. At the same time, the transmission of sensing signals and reference signals is also guaranteed.

[0130] As shown in Figures 2 to 4, in some embodiments, the writing transistor T1 includes a writing active layer T1-S, the sensing transistor T2 includes a sensing active layer T2-S, and in the same pixel unit, the orthogonal projection of the writing active layer T1-S onto the base is located on the first side of the orthogonal projection of the scan line GA coupled to the writing transistor T1 onto the base, and the orthogonal projection of the sensing active layer T2-S onto the base is located on the second side of the orthogonal projection of the scan line GA onto the base, with the first side and the second side facing each other along the second direction.

[0131] Exemplary, in the same pixel unit, at least a portion of the orthogonal projection of the scan line GA onto the base lies between the orthogonal projection of the write active layer T1-S onto the base and the orthogonal projection of the sense active layer T2-S onto the base.

[0132] For example, both the writing active layer T1-S and the sensing active layer T2-S are fabricated using transparent materials. For example, both the writing active layer T1-S and the sensing active layer T2-S are fabricated using transparent metal oxide materials.

[0133] Exemplary, the writing active layer T1-S includes at least a portion that extends along the first direction.

[0134] For example, the writing active layer T1-S and the first plate Cst1 of the storage capacitor Cst are formed as an integral structure.

[0135] Exemplary, the sensing active layer T2-S includes at least a portion that extends along the first direction.

[0136] For example, the orthogonal projection of the scan line GA onto the base does not overlap with the orthogonal projection of the write active layer T1-S onto the base.

[0137] For example, the orthogonal projection of the scan line GA onto the base does not overlap with the orthogonal projection of the sensing active layer T2-S onto the base.

[0138] As described above, by setting the orthogonal projection of the scan line GA onto the base to be located between the orthogonal projection of the writing active layer T1-S onto the base and the orthogonal projection of the sensing active layer T2-S onto the base, it is advantageous to reduce the difficulty of laying out the pixel unit within a limited layout space and to ensure that the display substrate has a high resolution.

[0139] As shown in Figures 2 to 4, in some embodiments, the installed drive transistor T3 includes a drive active layer T3-S, and at least a portion of the orthogonal projection of the write active layer T1-S onto the base lies between the orthogonal projection of the drive active layer T3-S onto the base and the orthogonal projection of the scan line GA onto the base.

[0140] Exemplary, the driving active layer T3-S includes at least a portion that extends along the second direction.

[0141] For example, the driving active layer T3-S is fabricated using a transparent material. For example, the driving active layer T3-S is fabricated using a transparent metal oxide material.

[0142] Exemplary, the gate T3-G of the drive transistor T3 includes at least a portion that extends along the first direction.

[0143] The above-described configuration method is advantageous in reducing the difficulty of arranging the pixel units within a limited layout space and in ensuring that the display board has a high resolution.

[0144] As shown in Figures 2 and 11, in some embodiments, the subpixel further includes a pixel definition layer, the pixel definition layer defines the pixel aperture, Within the same subpixel, the orthogonal projection of the sensing active layer T2-S onto the base is located between the orthogonal projection of the pixel aperture onto the base and the orthogonal projection of the scan line GA onto the base.

[0145] Exemplary, the location of the pixel aperture forms a pixel aperture region 30, and the pixel aperture region 30 includes at least a portion extending along the second direction.

[0146] For example, the orthogonal projection of the pixel aperture onto the base does not overlap with the orthogonal projection of the subpixel driving circuit onto the base.

[0147] As described above, by setting the orthogonal projection of the sensing active layer T2-S onto the base in the same subpixel to be located between the orthogonal projection of the pixel aperture onto the base and the orthogonal projection of the scan line GA onto the base, the orthogonal projection of the pixel aperture onto the base is aligned with the orthogonal projection of the subpixel driving circuit onto the base along the second direction, thereby ensuring that the pixel aperture occupies a sufficiently large layout space and guaranteeing the pixel aperture ratio of the display substrate. At the same time, the above setting method can further reduce the difficulty of laying out the pixel unit.

[0148] As shown in Figure 4, in some embodiments, the first electrode plate Cst1 is installed in the same layer and material as the drive active layer T3-S, the second electrode plate Cst2 is installed in the same layer and material as the data line DA, the second electrode plate Cst2 is bonded to the light-shielding layer 10, and the orthogonal projection of the second electrode plate Cst2 onto the base at least partially overlaps with the orthogonal projection of the light-shielding layer 10 onto the base.

[0149] As described above, by installing the first electrode plate Cst1 in the same layer and material as the driving active layer T3-S, the first electrode plate Cst1 and the driving active layer T3-S can be formed simultaneously in the same patterning process, further simplifying the display substrate manufacturing process flow and reducing the manufacturing cost of the display substrate.

[0150] Similarly, by placing the second electrode plate Cst2 in the same layer and material as the data line DA, the second electrode plate Cst2 and the data line DA can be formed simultaneously in the same patterning process, further simplifying the display substrate manufacturing process flow and reducing the manufacturing cost of the display substrate.

[0151] The above-described setting method is advantageous in improving the operational stability of the storage capacitor Cst.

[0152] As shown in Figures 2 to 4, in some embodiments, the driving active layer T3-S includes a driving channel portion, and the orthogonal projection of the light-shielding layer 10 onto the base at least partially overlaps with the orthogonal projection of the driving channel portion onto the base.

[0153] Exemplary, the drive active layer T3-S includes a drive channel portion, a first pole portion for forming the drive transistor T3, and a second pole portion for forming the drive transistor T3. The orthogonal projection of the drive channel portion onto the base lies within the orthogonal projection of the gate T3-G of the drive transistor T3 onto the base.

[0154] As described above, by setting the orthogonal projection of the light-shielding layer 10 onto the base to at least partially overlap with the orthogonal projection of the drive channel portion onto the base, the effects of light leakage on the drive transistor T3 can be effectively reduced, and the operational stability of the drive transistor T3 can be ensured.

[0155] The embodiments of this disclosure further provide a display device including a display substrate according to the above embodiments.

[0156] Exemplary, the display device includes an extra-large size, high resolution, bottom-emission OLED display device. Exemplary, the display device includes an active-matrix organic light-emitting diode display device.

[0157] The display device may be any product or component having a display function, such as a television, display, digital photo frame, mobile phone, or tablet, and the display device further includes a flexible circuit board, printed circuit board, and backplane.

[0158] In the display substrate according to the above embodiment, the scan line GA is installed in the same layer as the light-shielding layer 10 so that the scan line GA is close to the base. By increasing the thickness of the scan line GA in this way, the electrical resistance of the scan line GA can be reduced, the load on the scan line GA can be effectively reduced, excessive signal delay can be avoided when the scan line GA transmits a scanning signal, a high refresh rate can be achieved, the display effect can be optimized, the operational stability of the display substrate can be guaranteed, and the service life of the display substrate can be improved. Furthermore, because the scan line GA is close to the base, there is a large distance between the scan line GA and other conductive structures in the display substrate in the direction perpendicular to the base, which can reduce the parasitic capacitance formed between the scan line GA and other conductive structures. Therefore, according to the above embodiment, there is no need to install a thick insulating layer to reduce parasitic capacitance, the difficulty of the manufacturing process of the display substrate can be effectively reduced, and the possibility of mass production of the display substrate can be improved.

[0159] Furthermore, because the thick scan line GA is in close proximity to the base, the scan line GA can be preferentially manufactured in the display substrate manufacturing process flow, thereby reducing the likelihood of distortion in the base and effectively decreasing the risk of fragmentation.

[0160] Therefore, if the display device according to the embodiment of this disclosure includes the above-mentioned display substrate, it will similarly have the above-mentioned beneficial effects, and a detailed explanation will be omitted here.

[0161] In the embodiments of this disclosure, "same layer" may refer to a film layer located on the same structural layer. Alternatively, for example, a film layer on the same layer may be a layer structure formed by forming a film layer for a specific pattern using the same deposition process, and then patterning the film layer through a primary patterning process using the same mask template. Depending on the differences in the specific pattern, the primary patterning process may include multiple exposure, development, or etching processes, but the specific pattern in the formed layer structure may be continuous or discontinuous. These specific patterns may be at different heights or at different thicknesses.

[0162] In the embodiments of each method of the present disclosure, the numbering of each step cannot be used to limit the priority of each step, and for those skilled in the art, changes in the priority of each step are also within the scope of the disclosure without requiring any creative work.

[0163] In this specification, each embodiment is described progressively, and similar parts between embodiments can be referenced to one another. Each embodiment will be described with an emphasis on its differences from the others. In particular, the method embodiments are substantially similar to the product embodiments and are therefore described relatively briefly; however, for correlations, please refer to the partial description of the product embodiments.

[0164] Unless otherwise defined, technical or scientific terms used in this disclosure should have the ordinary meaning understood by a person with general skill in the art to which this disclosure belongs. The terms “first,” “second,” and similar terms used in this disclosure are not intended to indicate order, number, or importance, but are used to distinguish different components. Similar terms such as “includes” or “has” mean that the element or object preceding the term covers the elements or objects and their equivalents listed after the term without excluding other elements or objects. Similar terms such as “connected,” “joined,” or “linked” are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. Terms such as “up,” “down,” “left,” and “right” are used only to describe relative positions, and if the absolute position of the described object changes, its relative position may change accordingly.

[0165] When it is stated that an element such as a layer, film, region, or substrate is located "above" or "below" another element, it will be understood that the element may be located "directly" above or below the other element, or an intermediate element may be present.

[0166] In the description of the embodiments above, specific features, structures, materials, or characteristics may be combined in an appropriate manner in any one or more embodiments or examples.

[0167] The foregoing description is merely a specific embodiment of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any technician familiar with the present art can easily conceive of modifications and substitutions within the scope of the technology disclosed herein, and such modifications and substitutions should be included within the scope of protection of the present disclosure. Accordingly, the scope of protection of the present disclosure must be the same as the claims.

Claims

1. A display board, It includes a base and a plurality of pixel units installed on the base, the pixel units including a plurality of subpixels and a light-shielding layer, The plurality of subpixels are sequentially arranged along a first direction, and the subpixels include interconnected subpixel driving circuits and light-emitting elements, the subpixel driving circuits are used to provide driving signals to the light-emitting elements. At least a portion of the light-shielding layer is located between the subpixel driving circuit and the base, The display substrate further includes scan lines, the scan lines including at least a portion extending along the first direction, the scan lines coupled to a corresponding subpixel driving circuit, and the scan lines installed in the same layer as the light-shielding layer. The display board further includes scanning auxiliary lines, The scanning guide line is located on the opposite side of the base of the corresponding scanning line, the scanning guide line is coupled to the corresponding scanning line, and the scanning guide line is coupled to the subpixel driving circuit within the corresponding subpixel. The display board further includes data lines and data auxiliary lines, The data line includes at least a portion extending along a second direction, the second direction intersecting the first direction, and the data line is coupled to a corresponding subpixel driving circuit. A display substrate wherein the data auxiliary lines are coupled to the corresponding data lines, the data auxiliary lines are located between the corresponding data lines and the base, and the data auxiliary lines are installed in the same layer and material as the light-shielding layer.

2. The thickness d of the scan line in the direction perpendicular to the direction of the base satisfies 0.5 μm ≤ d ≤ 1.5 μm. The display board according to claim 1.

3. The scanning line is installed in the same layer and material as the light-shielding layer. The display board according to claim 1.

4. The scanning guide line includes a first scanning guide pattern, a second scanning guide pattern, and a third scanning guide pattern, the third scanning guide pattern being located between the first scanning guide pattern and the second scanning guide pattern, the first scanning guide pattern and the second scanning guide pattern being coupled to a subpixel driving circuit in the corresponding subpixel, and the third scanning guide pattern being coupled to the corresponding scanning guide line, the first scanning guide pattern, and the second scanning guide pattern, The scan lines coupled to the third scanning aid pattern include a first boundary and a second boundary arranged along a second direction, the second direction intersects the first direction, the orthogonal projection of the first boundary onto the base partially overlaps with the orthogonal projection of the first scanning aid pattern onto the base, and the orthogonal projection of the second boundary onto the base partially overlaps with the orthogonal projection of the second scanning aid pattern onto the base. The display board according to claim 1.

5. The scan line includes a first scan portion and a second scan portion, and both the first scan portion and the second scan portion extend along the first direction. In a direction perpendicular to the first direction, the width of the first scanning portion is smaller than the width of the second scanning portion. The orthogonal projection of the first scanning portion onto the base at least partially overlaps the orthogonal projection of the data lines onto the base. The display board according to claim 1.

6. The data auxiliary line includes at least two data auxiliary patterns, the at least two data auxiliary patterns are arranged along the second direction, and the at least two data auxiliary patterns are each connected to a corresponding data line. The display board according to claim 1.

7. The orthogonal projection of the scan line onto the base is located between the orthogonal projections of adjacent data auxiliary patterns onto the base. The display board according to claim 6.

8. The aforementioned display board further includes power lines and auxiliary power lines, The power line includes at least a portion extending along the second direction, and the power line is coupled to the corresponding subpixel drive circuit. The display substrate according to claim 1, wherein the power supply auxiliary line is coupled to the corresponding power supply line, the power supply auxiliary line is located between the power supply line and the base, and the power supply auxiliary line is installed in the same layer and material as the light shielding layer.

9. The power supply auxiliary line includes at least two power supply auxiliary patterns, the at least two power supply auxiliary patterns are arranged along the second direction, and the at least two power supply auxiliary patterns are each coupled to a corresponding power supply line. The display board according to claim 8.

10. The orthogonal projection of at least one of the scan lines onto the base lies between the orthogonal projections of adjacent power assist patterns onto the base. The display board according to claim 9.

11. The display board further includes sensing lines and sensing auxiliary lines, The sensing line includes at least a portion that extends along the second direction, The sensing guide line is coupled to the sensing line, is located between the sensing line and the base, is installed in the same layer and material as the light-shielding layer, includes at least a portion extending along the first direction, and is coupled to the corresponding subpixel driving circuit. The display board according to claim 8.

12. The subpixel driving circuit includes a driving transistor, a writing transistor, a sensing transistor, and a storage capacitor. The first pole of the drive transistor is coupled to the power line, and the second pole of the drive transistor is coupled to the light-emitting element. The gate of the writing transistor is coupled to the scan line, the first pole of the writing transistor is coupled to the data line, and the second pole of the writing transistor is coupled to the gate of the drive transistor. The gate of the sensing transistor is coupled to the scan line, the first pole of the sensing transistor is coupled to the second pole of the drive transistor, and the second pole of the sensing transistor is coupled to the sensing line. The first plate of the storage capacitor is coupled to the gate of the drive transistor, and the second plate of the storage capacitor is coupled to the second pole of the drive transistor. The display board according to claim 11.

13. The writing transistor includes a writing active layer, and the sensing transistor includes a sensing active layer. In the same pixel unit, the orthogonal projection of the writing active layer onto the base is located on the first side of the orthogonal projection of the scan line coupled to the writing transistor onto the base, and the orthogonal projection of the sensing active layer onto the base is located on the second side of the orthogonal projection of the scan line onto the base, with the first side and the second side facing each other along the second direction. The display board according to claim 12.

14. The drive transistor includes a drive active layer, and at least a portion of the orthogonal projection of the write active layer onto the base is located between the orthogonal projection of the drive active layer onto the base and the orthogonal projection of the scan line onto the base. The display board according to claim 13.

15. The subpixel further includes a pixel definition layer, the pixel definition layer defines a pixel aperture, The display substrate according to claim 14, wherein, in the same subpixel, the orthogonal projection of the sensing active layer onto the base is located between the orthogonal projection of the pixel aperture onto the base and the orthogonal projection of the scan line onto the base.

16. The first electrode plate is installed in the same layer and material as the drive active layer, the second electrode plate is installed in the same layer and material as the data line, the second electrode plate is bonded to the light-shielding layer, and the orthogonal projection of the second electrode plate onto the base at least partially overlaps with the orthogonal projection of the light-shielding layer onto the base. The display board according to claim 14.

17. The driving active layer includes a driving channel portion, and the orthogonal projection of the light-shielding layer onto the base at least partially overlaps with the orthogonal projection of the driving channel portion onto the base. The display board according to claim 14.

18. A display device comprising a display board according to any one of claims 1 to 17.

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