Information processing device

Abstract

To effectively perform software update.SOLUTION: The information processor having a communication interface stores a compressed file containing firmware for updating a communication interface and performs signature verification and decompression of at least a portion of the compressed data in the compressed file in parallel.SELECTED DRAWING: Figure 2

Description

Technical Field

[0004] , , ,

[0001] The present invention relates to an information processing apparatus.

Background Art

[0002] Data storage is a basic function of a computer system. In many computer systems, when handling a large amount of data, it is stored in a storage system. The storage system stores data in a storage medium (storage drive) such as a HDD (Hard Disk Drive) or SSD (Solid State Drive), and performs data writing and reading processes in response to an external command.

[0003] As background art of the present disclosure, there is International Publication No. 2020 / 1^{}22024. International Publication No. 2020 / 122024 discloses "reducing the impact on the availability of a system due to rewriting of circuit information of a network interface card (NIC) equipped with a programmable logic circuit. The NIC includes a programmable logic circuit that processes an input packet according to the recorded circuit information, an input terminal of the programmable logic circuit, and an output terminal, and a pair of switches respectively arranged at the input terminal and the output terminal, which can switch between a first mode of sending a packet to the programmable logic circuit and a second mode of bypassing without passing through the programmable logic circuit, a computer-side interface that transmits the packet to a computer equipped with a processor capable of executing an application program capable of executing packet processing instead of the programmable logic circuit, and a switch control circuit that switches the pair of switches to the second mode when rewriting the circuit information of the programmable logic circuit." This technology requires switches and a control circuit for program rewriting during service continuation.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

[0005] For example, with the increasing sophistication of storage system interface devices (also called network devices), the size of the software executed on these interface devices is also increasing. For instance, a smart NIC equipped with a processor capable of handling demanding tasks may run not only the OS and applications running on the OS, but also software for ASICs.

[0006] As described above, the large software size of the interface device means that updating it may require significant resources. Furthermore, in storage systems that are required to operate continuously, it is necessary to update the interface device software without interrupting I / O, making it difficult to allocate a large amount of memory to the interface device. Therefore, software updates for the interface device must be performed appropriately within capacity limitations. [Means for solving the problem]

[0007] One aspect of the present invention The feelings The information processing unit is The system includes a controller and a plurality of interface devices, and the controller is before Note: Multiple I Interface Device of For each interface device It stores a compressed file containing the firmware update, The blocks separated from the compressed file are sequentially transmitted to each of the aforementioned interface devices. The aforementioned Each interface device , Each block The signature verification process and the decompression process are executed in parallel. Then, store the unzipped data. do. [Effects of the Invention]

[0009] According to one aspect of this disclosure, software updates can be performed effectively. [Brief explanation of the drawing]

[0010] [Figure 1] This document shows an example configuration of a storage controller and smart NIC according to one embodiment of this specification. [Figure 2] This is a schematic diagram illustrating the firmware update of a smart NIC according to one embodiment of this specification. [Figure 3] An example of data included in smart NIC firmware is shown. [Figure 4] This document shows a flowchart illustrating the overall process of updating the firmware of a smart NIC according to one embodiment of this specification. [Figure 5] This shows an example configuration of the CHB FW update status management table maintained by the storage controller. [Figure 6] This shows an example of the configuration of the CHB management table maintained by the storage controller. [Figure 7] This indicates the trigger for updating the CHB firmware. [Figure 8] This shows the criteria for determining whether to update the CHB firmware. [Figure 9] This shows an example configuration for the CHB FW update status management table. [Figure 10] An example of the FW version control table configuration is shown. [Figure 11] This diagram shows the overall process of updating the firmware of a smart NIC according to one embodiment of this specification. [Figure 12] This is a conceptual diagram illustrating the firmware update process using a smart NIC. [Figure 13] This is a conceptual diagram illustrating the firmware update process for smart NICs in a configuration that includes multiple CHBs. [Figure 14] This shows the initial sequence diagram for updating the SmartNIC firmware. [Figure 15] This diagram shows the sequence of operations for a single block of the OS image during a SmartNIC firmware update. [Figure 16] This is a sequence diagram of the firmware termination and surface switching processes for the smart NIC.

Best Mode for Carrying Out the Invention

[0011] Hereinafter, embodiments of the present invention will be described in detail based on the drawings. In the following description, the same components are generally denoted by the same reference numerals, and repeated descriptions are omitted. Note that the embodiments described below are merely examples for realizing the present invention, and it should be noted that they do not limit the technical scope of the present invention.

[0012] FIG. 1 shows a configuration example of a storage controller 10 and a smart NIC (Network Interface Card) 20 according to an embodiment of this specification. These are implemented in a storage system which is an example of an information processing device. The smart NIC 20 is an example of an interface device or a network device and is included in a channel board (CHB). In the example described below, the smart NIC 20 is assumed to be an interface for communication between the host and the storage controller 10. Note that the smart NIC of this embodiment can also be used as an interface device between storage devices or between storage controllers.

[0013] The storage controller 10 includes a SSD (Solid State Drive) 101 which is a non-volatile memory, a controller 102, and a DRAM 104 which is a volatile memory. The controller 102 includes a plurality of processor cores 103. The processor core 103 is a processor, and a plurality of CPUs each including one or more processor cores may be implemented.

[0014] DRAM 104 stores the programs executed by the controller 102 and the information it references. Specifically, it stores the NIC FW update status management table 105 and the CHB management table 106. FW stands for firmware. Furthermore, it stores the I / O processing program 107 and the maintenance processing program 108. The data stored in DRAM 104 is loaded, for example, from the SSD 101. The controller 102 operates as a predetermined functional unit by operating according to the program.

[0015] The I / O processing program 107 performs processing in response to I / O requests received from the host device. The maintenance processing program 108 sends maintenance commands (commands that the user can operate via the GUI) to the smart NIC 20 and performs network settings for communication with the host device, firmware updates, etc. Firmware updates include replacing part or all of the existing firmware.

[0016] The smart NIC 20 includes a NIC ASIC 201, a controller 202, DRAM 204, flash memory 210, and embedded memory 215 which is a non-volatile memory card. The controller 202 includes multiple processor cores 203. The processor cores 203 are processors, and multiple CPUs, each containing one or more processor cores, may be implemented.

[0017] DRAM204 stores the programs executed by the controller 202 and the information it references. Specifically, it stores the smart NIC FW update status management table 205, the FW version management table 206, the I / O processing program 207, the maintenance processing program 208, and the network protocol processing program 209. In addition, DRAM204 stores an OS (not shown).

[0018] The network protocol processing program 209 performs conversions between the communication protocol with the host device and the communication protocol within the storage system. The I / O processing program 207 generates commands for communication with the storage controller 10 in response to requests received from the host device and performs data transfer processing to the host device / storage controller 10.

[0019] The maintenance program 208 applies the settings to the smart NIC 20 based on the maintenance command information received from the storage controller 10, and also performs a firmware update.

[0020] Flash memory 210 stores the firmware (NIC FW) 211 of the NIC ASIC 201. Embedded memory 215 stores the OS image 216, bootloader 217, and configuration information / version information 218. Embedded memory 215 also temporarily stores temporary information 219 during smart NIC firmware updates. Although not shown in Figure 1, embedded memory 215 also stores the controller that stores the temporary information 219. Details of the operation of this controller will be described later.

[0021] The OS image 216 contains the OS and programs 207 to 209 that the controller 202 will run. The Bootloader 217 is the OS boot program. The configuration information / version information 218 contains tables 205, 206 and other management information stored in the DRAM 204.

[0022] Figure 2 is a schematic diagram illustrating the operation of a firmware update for a smart NIC 20 according to one embodiment of this specification. The following describes an example where the entire old firmware is replaced with new firmware. The firmware update for the smart NIC 20 described herein can be applied to an information processing device different from a storage system, such as a smart NIC 20 implemented in a server. It can also be applied to an interface device or communication processing device different from the smart NIC.

[0023] The management server 30 creates a smart NIC FW from a new OS image 216 and NIC FW 211, and generates compressed data 301 (also called a compressed file). A signature is added to the compressed data 301. Here, the OS image 216 is assumed to include the boot program Bootloader 217. The storage controller 10 receives the compressed data 301 of the smart NIC FW and its header information from the management server 30 via a management network (not shown) and stores it in the SSD 101. Because the data is compressed, the storage area required by the storage controller 10 can be reduced.

[0024] Figure 3 shows an example of the data contained in the smart NIC FW300. The smart NIC FW includes SNIC FW header information 305 and SNIC FW data 307. The SNIC FW header information 305 includes information about the SNIC FW data 307, such as version information of the SNIC FW data 307, date and time of generation information, and the compressed data size of the SNIC FW data 307, the signature scheme, and the signatures of the OS image 216 and NIC FW 211.

[0025] The SNIC FW data 307 includes the NIC FW 211 and the OS image 216. As mentioned above, the OS image 216 here also includes the Bootloader 217. The compressed data 301 written from the management server 30 to the SSD 101 of the storage controller 10 includes the compressed SNIC FW data 307 and the uncompressed SNIC FW header information 305.

[0026] Returning to Figure 2, the front-end module 130 of the storage controller 10 includes an I / O processing program 107 and a maintenance processing program 108. The front-end module 130 stores the compressed data 301 of the smart NIC FW in the SSD 101. The front-end module 130 divides the compressed data into multiple blocks and transfers the divided blocks to the smart NIC 20 via the DRAM 104 in the order of the block arrangement, starting from the first block. By transferring the compressed data in blocks, the number of transfers can be reduced. The DRAM 104 does not store all blocks at the same time, but temporarily stores only one or more of the blocks. For example, each block is read from the SSD to the DRAM 104 and transferred without storing multiple blocks simultaneously. The compressed data may also be divided within the DRAM 104.

[0027] The front-end module 230 of the smart NIC 20 includes an I / O processing program 207 and a maintenance processing program 208. The controller 202 executes the front-end module 230, performing signature verification processing, decompression processing, and writing processing to the embedded memory 215 for each divided and transferred block in parallel. As shown in Figure 1, the controller 202 includes multiple cores 203. Different cores perform the block signature verification processing and decompression and writing processing in parallel. This increases the processing speed. For example, once the write request for one block to the embedded memory 215 is completed, the next block is stored in the DRAM 204. The operation of the front-end module 230 of the smart NIC 20, which will be described later, is also performed by the controller 202.

[0028] The front-end module 130 of the storage controller 10 passes information about the total size of the compressed data to the smart NIC 20 before the transfer of the divided blocks of compressed data begins. It also informs each block of which part of the entire compressed data the block being transferred belongs to and what size it will be sent in the transfer.

[0029] The Smart NIC 20's front-end module 230 performs some of the signature verification processes that can be executed for each block, and also performs block decompression and writing to the embedded memory 215. Once the signature verification of the last block is complete, the signature verification of the entire compressed data can be completed from the signature verification results of each block. The decompressed blocks are then integrated into the OS image or NIC firmware through address associations.

[0030] As described above, by splitting the compressed data 301, the DRAM area of ​​the storage controller 10 and smart NIC 20 required for firmware updates can be reduced. This suppresses the reduction in the host data cache area of ​​the storage controller 10 or the host data buffer area of ​​the CHB. Alternatively, the signature verification, decompression, and writing processes may be performed on the compressed data 301 as a whole without splitting. Furthermore, known techniques can be used for signature verification and decompression of the split blocks.

[0031] The signature verification process for the entire compressed data 301 consists of partial processing on blocks. The controller 202 can complete the signature verification process for the entire compressed data 301 by performing signature verification on all blocks in array order, starting from the first block.

[0032] The controller 202 writes the decompressed blocks to the storage area of ​​the embedded memory 215 via the DRAM 204. The NIC FW211 is stored in the temporary storage area of ​​the embedded memory 215, and then stored in the flash memory 210. The decompressed portions of the OS image 216 are sequentially stored in the storage area of ​​the embedded memory 215 from the DRAM 204.

[0033] The flash memory 210 contains two logical partitions (storage areas) on the front and side. The new NIC FW211 is stored on the side of the flash memory 210. The old NIC FW211, before the update, is stored on the front of the flash memory 210. The storage area of ​​the embedded memory 215 also contains two logical partitions on the front and side. The new OS image 216 is stored on the side of the embedded memory 215.

[0034] The old OS image 216, prior to the update, is stored on the front of the flash memory 210. As described later, after the new firmware is successfully stored on the side, a switch between the front and side is performed. Due to the switch, the source from which the firmware is read changes from the front before the switch to the side before the switch. When the firmware is loaded again, it can boot on the front after the switch. Since no writing is performed to the currently running side and the data is stored on the side, host service (access from the host) can continue.

[0035] Figure 4 shows a flowchart of the overall process for updating the firmware of the smart NIC 20 according to one embodiment of this specification. First, the management server 30 integrates the OS image and the NIC FW to generate smart NIC FW data 307 (S11). The management server 30 further compresses the smart NIC FW data 307 to generate compressed data 301 including smart NIC FW header information 305 (S12). The compressed data 301 is signed. This improves security and reliability.

[0036] The controller 102 of the storage controller 10 receives the compressed data 301 from the management server 30 and stores it in the SSD 101. The controller 102 divides the compressed data 301 and sequentially transfers it to the smart NIC 20 via the DRAM 104 (S13).

[0037] The front-end module 230 (controller 202) of the smart NIC20 performs signature verification, decompression, writing to the storage area of ​​the embedded memory 215, and writing the NIC FW to the flash memory 210 (NIC FW update) in units of transfer (divided block units) (S14).

[0038] Next, the front-end module 230 reintegrates multiple decompressed blocks (parts) of the new OS image 216 stored in the memory area of ​​the embedded memory 215 and multiple decompressed blocks (parts) of the new NIC FW211 stored in the flash memory 210, respectively, by address association (S15).

[0039] Next, the front-end module 230 switches the boot side of the storage area of ​​the embedded memory 215 and the flash memory 210 from the front to the side (S16). Furthermore, the front-end module 230 restarts the smart NIC 20 (S17). This executes the new firmware stored on the new front side. If the restart is not performed successfully (S18: NO), the smart NIC 20 becomes blocked (S19). If the restart is successful (S18: YES), the smart NIC 20 resumes processing with the new firmware.

[0040] This section describes the information held by the storage controller 10 and the smart NIC 20. Figure 5 shows an example configuration of the CHB FW update status management table 105 held by the storage controller 10. The CHB FW update status management table 105 manages the status of the CHB firmware update process. Here, the number of smart NICs implemented in each CHB is 1, and the information about the CHB firmware update process refers to the information about the smart NIC update process.

[0041] The CHB FW update status management table 105 includes a CHB ID column 151, a firmware update acceptance status column 152, a firmware update in progress column 153, and a panel switching status column 154. The storage controller 10 updates the CHB FW update status management table 105 as needed in response to the response from the smart NIC 20.

[0042] The CHB ID field 151 shows the CHB identifier (ID), which can be considered the smart NIC ID. The firmware update acceptance status field 152 indicates whether the CHB is able to accept firmware update processing. The firmware update in progress field 153 indicates whether the CHB is in the process of updating the firmware. The face switching status field 154 indicates whether the CHB is able to perform face switching processing.

[0043] Figure 6 shows an example configuration of the CHB management table 106 maintained by the storage controller 10. The CHB management table 106 includes the CHB firmware version and other attribute information.

[0044] In the example in Figure 6, the CHB management table 106 includes a CHB ID column 161, an operating status column 162, a firmware version column 163, and a network information column 164. The storage controller 10 manages and updates the CHB management table 106.

[0045] The operating status column 162 indicates whether the CHB is currently operating normally. The operating status column 162 is updated as needed in response to the Smart NIC 20. The firmware version column 163 shows the firmware version of the CHB held by the storage controller. The network information column 164 shows information about the CHB's communication, such as the IP address and the packet size of data transfer.

[0046] Figures 7 and 8 illustrate other information that the storage controller 10 has pre-stored. Figure 7 shows the trigger for updating the CHB firmware. In response to the trigger shown in Figure 7, the storage controller 10 initiates the sequence shown in Figure 11 to perform the necessary firmware update for the CHB.

[0047] Figure 8 shows the criteria for determining whether to update the CHB firmware. The determination of whether or not to update the firmware is based on the update firmware held by the storage controller 10, the current CHB firmware version, and the setting of the forced execution mode. Note that the determination may be based on only one of these factors, for example, only the relationship between the firmware versions, or other conditions may be used.

[0048] In the example shown in Figure 8, if the firmware version for the update is the same as the current CHB firmware version, the firmware update will not be performed regardless of whether forced execution mode is enabled or disabled. If the firmware version for the update is less than (older than) the current CHB firmware version, the firmware update will be performed if forced execution mode is ON, and not if it is OFF. If the firmware version for the update is greater than (newer than) the current CHB firmware version, the firmware update will be performed regardless of whether forced execution mode is enabled or disabled.

[0049] Figures 9 and 10 show examples of management information held by the smart NIC 20. Figure 9 shows an example configuration of the CHB FW update status management table 205. The CHB FW update status management table 205 manages the status of the CHB during the firmware update process. The CHB FW update status management table 205 is updated as needed by the controller 202.

[0050] In the example shown in Figure 9, the CHB FW update status management table 205 includes a CHB ID column 251, a firmware update acceptance status column 252, a firmware transfer status column 253, a face switch acceptance ready status column 254, a face switch in progress column 255, and a reset waiting column 256.

[0051] The firmware update acceptance status column 252 indicates whether the smart NIC 20 is able to accept a firmware update. The firmware transfer status column 253 indicates the current status of the firmware update process. In the example shown in Figure 9, the signature verification execution status column indicates the block for which signature verification is currently being performed. The decompression / write status column indicates the block for which decompression / write processing is currently being performed. The NIC FW decompression status column indicates whether the decompression of the NIC FW is complete.

[0052] The "Side Switching Acceptance Status" column 254 indicates whether the smart NIC 20 can accept a side switching request. Side switching is the switching between the front and side of the embedded memory 215 and the flash memory 210. The "Side Switching in Progress" column 255 indicates the execution status of the side switching, showing whether the side switching has been completed or is in progress. The "Waiting for Reset" column 256 indicates whether the smart NIC 20 can perform a reset process.

[0053] Figure 10 shows an example configuration of the FW version management table 206. The FW version management table 206 manages the current firmware version of the smart NIC 20. In the example shown in Figure 10, the FW version management table 206 includes a CHB ID column 261, a firmware version column 262, and an update time column 263. The firmware version column 262 shows the current firmware version of the smart NIC 20, and the update time column 263 shows the update time (including the date).

[0054] Figure 11 shows a sequence diagram of the overall process for updating the firmware of the smart NIC 20 according to one embodiment of this specification. The storage controller 10 requests the current smart NIC firmware version from the smart NIC 20 (S31). The storage controller 10 can start the firmware update process at the trigger described with reference to Figure 7. The storage controller 10 can also determine whether or not to start the firmware update by referring to the CHB FW update status management table 105.

[0055] The controller 202 of the smart NIC 20 returns its firmware version information to the storage controller 10 (S32). The firmware version information is stored in the FW version management table 206. The storage controller 10 compares the current firmware version of the smart NIC 20 received with the firmware version shown in the CHB management table 106 to determine whether the smart NIC 20's firmware needs to be updated. This determination can be based on the information described with reference to Figure 8.

[0056] If a firmware update is required, the storage controller 10 and the smart NIC 20 perform steps S33 to S36 for each segmented block of the compressed data.

[0057] The storage controller 10 stages a compressed block of firmware data for update from the SSD 106 to the DRAM 104 (S33) and sends a firmware update request to the smart NIC 20 (S34). The smart NIC 20 receives the block via DMA (S35) and performs signature verification, decompression, and writing in parallel, as described with reference to Figure 2. The NIC firmware is temporarily stored in the embedded memory 215 and then written to the flash memory 210 (S36). Once the smart NIC 20's controller 202 has finished processing the block, it returns a response to the storage controller 10.

[0058] Once the above processing is complete for all blocks, the storage controller 10 sends a switching request to the smart NIC 20 (S37). Whether or not the request is accepted may be based on the CHB FW update status management table 105. The controller 202 of the smart NIC 20 receives the request, performs the switching (S38), and returns a response to the storage controller 10.

[0059] The following section will explain the firmware update process using Smart NIC20 in more detail. Figure 12 is a conceptual diagram illustrating the firmware update process using Smart NIC20.

[0060] The compressed data, including the NIC firmware 211 and the OS image 216, is sequentially transferred via DMA from the storage controller's DRAM 104 to the smart NIC 20's DRAM 204. The smart NIC 20 performs signature verification, decompression, and writing for each individual compressed data block. Signature verification, decompression, and writing are executed in parallel by different cores 203. For example, after one block is written, the next block is transferred.

[0061] The SmartNIC20 determines the success or failure of the process once all blocks have been collected. Success is only achieved if both signature verification and decompression (and writing) are completed successfully. While the entire compressed data cannot be processed until all blocks are collected, performing possible processing on each block reduces the required memory area.

[0062] Figure 13 is a conceptual diagram illustrating the firmware update process for the smart NIC 20 in a configuration including multiple CHBs. The storage controller 10 transfers a common block in parallel to all CHBs that perform firmware updates under its management. This enables efficient firmware updates. Each CHB operates as described with reference to Figure 12.

[0063] The firmware update process for the Smart NIC 20 will be explained below with reference to several sequence diagrams. Figure 14 shows the initial sequence diagram for the Smart NIC 20 firmware update. In the part shown in Figure 14, the update firmware is sent from the management server 30 to the storage controller 10, and the signature verification and decompression of the NIC firmware 211 are performed.

[0064] First, the management server 30 creates compressed data for the smart NIC 20 firmware (S101) and stores it in the SSD 11 of the storage controller 10 (S102). The front-end module 130 of the storage controller 10 stages a block, which is part of the compressed data on the SSD 101, into the DRAM 104 (S103). Here, it is assumed that all of the compressed data for the NIC firmware 211 is stored in a single block. The front-end module 130 requests the smart NIC 20 to transfer the block stored in the DRAM 104 (S104).

[0065] The front-end module 230 (controller 202) of the smart NIC 20 uses DMA transfer to store blocks stored in the DRAM 104 of the storage controller 10 in its own DRAM 204 (S105, S106).

[0066] The front-end module 230 reads a block from the DRAM 204 (S107), and performs signature verification of the block (S108) and decompression / writing (S109) in parallel. The front-end module 230 requests the controller 501 of the embedded memory 215 to stage the decompressed NIC firmware 211 (block) (S110). The controller 501 temporarily stores the decompressed NIC firmware 211 in the storage area 502 of the embedded memory 215 (S111).

[0067] Subsequently, the front-end module 230 writes the NIC firmware 211 from the memory area 502 to the sub-side of the flash memory 210 (S112). Furthermore, the front-end module 230 responds to the storage controller 10 regarding the success or failure of the processing of the NIC firmware 211 (S113).

[0068] Figure 15 shows the sequence of operations for one block of the OS image 216 during a firmware update of the smart NIC 20. The sequence shown in Figure 15 is executed for each block of the OS image 216.

[0069] First, the front-end module 130 of the storage controller 10 stages the blocks of the SSD 101 into the DRAM 104 (S151). The front-end module 130 requests the smart NIC 20 to transfer the blocks stored in the DRAM 104 (S152).

[0070] The front-end module 230 of the smart NIC 20 uses DMA transfer to move a block stored in the DRAM 104 of the storage controller 10 to its DRAM 204 (S153, S154).

[0071] The front-end module 230 reads a block from the DRAM 204 (S155), and performs signature verification of the block (S156) and decompression / writing (S157) in parallel. The front-end module 230 requests the embedded memory controller 501 to write the decompressed OS image block (S158).

[0072] The controller 501 stores the decompressed blocks on the sub-surface of the OS image in the storage area 502 of the embedded memory (S159). After writing the data, the controller 501 returns a response to the front-end module 230 (S160). The front-end module 230 responds to the storage controller 10 regarding the success or failure of the block processing (S161).

[0073] Next, the firmware termination and switching processes will be explained. Figure 16 is a sequence diagram of the firmware termination and switching processes of the smart NIC 20. The front-end module 130 of the storage controller 10 stages the termination block of the SSD 101 to the DRAM 104 (S181).

[0074] The front-end module 130 requests the smart NIC 20 to transfer the block stored in the DRAM 104 (S182). Subsequently, signature verification and decompression / write processes are performed as described with reference to Figure 15.

[0075] Next, the front-end module 230 of the smart NIC 20 performs a flash operation on the data stored in the embedded memory 215 (S183) to ensure that the data can be written to the embedded memory 215. Then, the front-end module 230 checks the signature verification results of all blocks to confirm that the signature verification of the entire compressed data is complete (S184).

[0076] If signature verification is complete, it means that the firmware stored on the sub-side of the embedded memory 215 can boot. Therefore, the front-end module 230 updates the Bootloader 217 (boot program) stored in the embedded memory 215 (S185). Finally, the front-end module 230 updates the CHB FW update status management table 205 and sets the smart NIC 20 to a state where it can accept side switching.

[0077] The storage controller 10 receives a response from the smart NIC 20 indicating whether the firmware update was successful or unsuccessful (S187). If the update is successful, the storage controller 10 requests the smart NIC 20 to switch sides (S188).

[0078] The front-end module 230 of the smart NIC 20 performs a switchover in the embedded memory 215 and flash memory 210 (S189) and updates the FW version management table 206 (S190). The front-end module 230 returns a response to the storage controller 10 indicating the success or failure of the switchover (S191).

[0079] The present invention is not limited to the embodiments described above, and includes various modifications. For example, the embodiments described above are described in detail to make the present invention easier to understand, and are not necessarily limited to those having all the configurations described. Furthermore, it is possible to replace parts of the configuration of one embodiment with the configuration of another embodiment, and it is also possible to add configurations from other embodiments to the configuration of one embodiment. In addition, it is possible to add, delete, or replace parts of the configuration of each embodiment with other configurations.

[0080] Furthermore, each of the above-mentioned configurations, functions, and processing units may be implemented in hardware, either partially or entirely, by designing them as integrated circuits, for example. Alternatively, each of the above-mentioned configurations and functions may be implemented in software by having the processor interpret and execute programs that implement each function. Information such as programs, tables, and files that implement each function can be stored in memory, a recording device such as a hard disk or SSD (Solid State Drive), or a recording medium such as an IC card or SD card.

[0081] Furthermore, the control lines and information lines shown are those deemed necessary for explanatory purposes, and not all control lines and information lines are necessarily shown in the actual product. In practice, it is reasonable to assume that almost all components are interconnected.

[0082] Several aspects of this disclosure are described below. (1) An information processing device, Controller and Includes an interface device, The aforementioned controller, It stores a compressed file containing the firmware for updating the interface device, At least a portion of the compressed data from the compressed file is transmitted to the interface device. The interface device is an information processing device that performs signature verification processing and decompression processing of the received compressed data in parallel. (2) (1) The information processing device described above, The controller sequentially transmits the blocks separated from the compressed file to the interface device. The aforementioned interface device is an information processing device that performs signature verification and decompression processing for each block in parallel. (3) (1) The information processing device described above, The interface device includes non-volatile memory, The non-volatile memory includes a first area for storing the currently running firmware and a second area different from the first area. The aforementioned interface device The data obtained by decompressing the aforementioned compressed data is written to the second area. An information processing device that, after all of the update firmware has been written to the second area, switches the source of the firmware to be used from the first area to the second area. (4) (2) The information processing device described above, The aforementioned interface device It includes non-volatile memory and volatile memory, The block received from the controller is stored in the volatile memory. An information processing device that performs the signature verification process and the decompression process of a block stored in the volatile memory in parallel, and stores the decompressed block in the non-volatile memory. (5) (1) The information processing device described above, The controller is an information processing device that determines whether or not to update the firmware of the interface device based on the relationship between the current firmware version of the interface device and the update firmware version, and the setting of the forced update mode. (6) (2) The information processing device described above, Includes multiple interface devices, The controller is an information processing device that transmits a common block in parallel to the plurality of interface devices. (7) Network device, Processor and First memory and Includes the second memory, The aforementioned processor, The first memory receives compressed data, which includes at least a portion of the firmware for updating the network device, from another device and stores it in the first memory. A network device that performs signature verification and decompression processing of the compressed data in parallel, and stores the decompressed data in the second memory. (8) (7) Network device as described above, The aforementioned processor is a network device that sequentially receives segmented blocks of the compressed file of the update firmware and performs signature verification and decompression processing for each segmented block in parallel. (9) A method for updating the firmware of a network device, The network device receives compressed data, including at least a portion of the firmware update, from another device and stores it in the first memory. A method wherein the network device performs signature verification processing and decompression processing of the compressed data in parallel, and stores the decompressed data in a second memory. (10) (9) The method described in (9), A method comprising the network device sequentially receiving segmented blocks of the compressed file for the update firmware, and executing signature verification and decompression processes for each segmented block in parallel. [Explanation of Symbols]

[0083] 10 Storage Controllers 20 Smart NIC 101 SSD 102 Controllers 103 processor cores 104 DRAM 107 IO Processing Program 108 Maintenance Processing Program 130 Front-end module 201 NIC ASIC 202 Controller 203 processor cores 204 DRAM 207 IO Processing Program 208 Maintenance Processing Program 209 Network Protocol Processing Program 210 Flash Memory 211 NIC firmware 215 Embedded Memory 216 OS images 230 Front-end module 301 Compressed data

Claims

1. An information processing device, Controller and Includes multiple interface devices, The aforementioned controller, A compressed file containing update firmware is stored in each of the aforementioned plurality of interface devices. The blocks separated from the compressed file are sequentially transmitted to each of the aforementioned interface devices. Each of the aforementioned interface devices is an information processing device that performs signature verification and decompression processing of each block in parallel and stores the decompressed data.

2. An information processing device according to Claim 1, Each of the aforementioned interface devices includes a non-volatile memory, The non-volatile memory includes a first area for storing the currently running firmware and a second area different from the first area. Each of the aforementioned interface devices is The data obtained by decompressing the aforementioned block is written to the second area. An information processing device that, after all of the update firmware has been written to the second area, switches the source of the firmware to be used from the first area to the second area.

3. An information processing apparatus according to Claim 1, Each of the aforementioned interface devices is It includes non-volatile memory and volatile memory, The blocks separated from the compressed file are stored in the volatile memory. An information processing device that performs the signature verification process and the decompression process of a block stored in the volatile memory in parallel, and stores the decompressed data in the non-volatile memory.

4. An information processing device according to Claim 1, The controller is an information processing device that determines whether or not to update the firmware of each interface device based on the relationship between the current firmware version of each interface device and the update firmware version, and the setting of the forced update mode.

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