Optical receiver

Abstract

An optical receiver comprising: a light receiving element; a carrier substrate; a dielectric layer; a base; a first electrically conductive film; a second electrically conductive film; an electrical conductor; and a transimpedance. The first electrically conductive film is provided between the light receiving element and the carrier substrate. The second electrically conductive film is provided between the carrier substrate and the dielectric layer, and has a parasitic capacitance between the second electrically conductive film and a first wiring pattern of the first electrically conductive film. The electrical conductor is electrically connected to the first wiring pattern and to the second electrically conductive film. The transimpedance has a first pad electrically connected to the first wiring pattern via a wire. The capacitance between the second electrically conductive film and a major surface of the base is greater than the parasitic capacitance. The inductance of the electrical conductor is smaller than the inductance of the wire.

Description

Technical Field

[0001] The present disclosure relates to an optical receiver. This application claims priority based on Japanese Application No. 2021-134911 filed on August 20, 2021, and incorporates by reference all the descriptions described in the Japanese application.

Background Art

[0002] Patent Document 1 discloses an optical receiver including a light receiving element and a trans-impedance amplifier (TIA). In this optical receiver, an electrical signal output from the light receiving element is amplified by the TIA and then output to the outside of the optical receiver.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

[0004] An optical receiver according to an embodiment includes a light receiving element, a carrier substrate on which the light receiving element is mounted, a dielectric layer on which the carrier substrate is mounted, a base having a conductive main surface as a reference potential and on which the dielectric layer is mounted, a first wiring pattern electrically connected to the cathode electrode of the light receiving element, a first conductive film provided between the light receiving element and the carrier substrate, a second conductive film provided between the carrier substrate and the dielectric layer and having a parasitic capacitance with the first wiring pattern, a conductor provided on the carrier substrate and electrically connected to the first wiring pattern and the second conductive film, a first pad electrically connected to the first wiring pattern via a wire, and a trans-impedance having a second pad electrically connected to the anode electrode of the light receiving element amplifier and. The capacitance between the second conductive film and the main surface of the base is larger than the parasitic capacitance. The inductance of the conductor is smaller than the inductance of the wire. [Brief explanation of the drawing]

[0005] [Figure 1] Figure 1 is a plan view showing the internal structure of an optical receiver according to one embodiment. [Figure 2] Figure 2 is a cross-sectional view showing the optical receiver in Figure 1. [Figure 3] Figure 3 is a plan view showing an enlarged view of the surrounding structure of the photodetector and transimpedance amplifier in the optical receiver shown in Figure 1. [Figure 4] Figure 4 is a cross-sectional view along the line B1-B1 in Figure 3. [Figure 5] Figure 5 is a cross-sectional view along the line B2-B2 in Figure 3. [Figure 6] Figure 6 is a cross-sectional view along the line B3-B3 in Figure 3. [Figure 7] Figure 7 shows how the photodetector and carrier are connected via a flip-chip connection. [Figure 8] Figure 8 is an equivalent circuit diagram between the photodetector and the transimpedance amplifier in the optical receiver shown in Figure 1. [Figure 9] Figure 9 is an equivalent circuit diagram extracted from a portion of Figure 8. [Figure 10] Figure 10 is a graph showing the simulation results of the relationship between insertion loss and signal frequency in the optical receiver shown in Figure 1. [Figure 11] Figure 11 is a cross-sectional view showing an optical receiver according to Modification 1. [Figure 12] Figure 12 is a cross-sectional view showing an optical receiver according to a modified example 2. [Figure 13] Figure 13 is a cross-sectional view showing an optical receiver according to modified example 3. [Figure 14] Figure 14 is a cross-sectional view showing an optical receiver according to Modification 4. [Figure 15] Figure 15 is a plan view showing carriers in an optical receiver according to Modification 5. [Figure 16] Figure 16 is a graph showing the simulation results of the relationship between insertion loss and signal frequency in the optical receiver shown in Figure 15. [Figure 17] Figure 17 is a cross-sectional view showing an optical receiver according to Comparative Example 1. [Figure 18] Figure 18 is an equivalent circuit diagram between the photodetector and the transimpedance amplifier in the optical receiver shown in Figure 17. [Figure 19] Figure 19 is an equivalent circuit diagram extracted from a portion of Figure 18. [Figure 20] Figure 20 is a graph showing the simulation results of the relationship between insertion loss and signal frequency in the optical receiver shown in Figure 17. [Figure 21] Figure 21 is a cross-sectional view showing an optical receiver according to Comparative Example 2. [Figure 22] Figure 22 is an equivalent circuit diagram between the photodetector and the transimpedance amplifier in the optical receiver shown in Figure 21. [Figure 23] Figure 23 is a graph showing the simulation results of the relationship between insertion loss and signal frequency in the optical receiver shown in Figure 21. [Figure 24] Figure 24 is a cross-sectional view showing an optical receiver according to Comparative Example 3. [Figure 25] Figure 25 is an equivalent circuit diagram between the photodetector and the transimpedance amplifier in the optical receiver shown in Figure 24. [Figure 26] Figure 26 is a graph showing the simulation results of the relationship between insertion loss and signal frequency in the optical receiver shown in Figure 24. [Modes for carrying out the invention]

[0006] [Issues this disclosure aims to address] In the optical receiver described in Patent Document 1, the photodetector and the TIA are sometimes connected via a wire. However, in such a configuration, the existence of a resonant frequency due to the parasitic capacitance between the photodetector and the TIA and the inductance of the wire can be a problem. Due to the recent increase in the speed of optical communication, the frequency of optical signals is constantly increasing, and high-frequency bands of several tens of GHz or more are being used. Furthermore, it is even anticipated that high-frequency bands of 100 GHz or more will be used. If a resonant frequency exists in such a high-frequency band, an opaque band of the signal may be created, potentially leading to degradation of the signal waveform and a decrease in communication quality, such as inter-channel crosstalk. To reduce the inductance between the photodetector and the TIA, it is conceivable to connect the photodetector and the TIA using a flip-chip connection. However, in that case, a TIA with pads specifically for flip-chip connections is required, and a general-purpose TIA cannot be used, which may increase manufacturing costs.

[0007] [Effects of this disclosure] According to the optical receiver of this disclosure, a photodetector and a transimpedance are connected via a wire. amplifier By connecting these devices while shifting the opaque bandwidth caused by resonance, the degradation of communication quality can be suppressed.

[0008] [Description of Embodiments in this Disclosure] First, the contents of the embodiments of this disclosure will be listed and described. An optical receiver according to one embodiment includes a photodetector, a carrier substrate on which the photodetector is mounted, a dielectric layer on which the carrier substrate is mounted, a base having a conductive main surface which is a reference potential and on which the dielectric layer is mounted, a first conductive film provided between the photodetector and the carrier substrate and having a first wiring pattern electrically connected to the cathode electrode of the photodetector, a second conductive film provided between the carrier substrate and the dielectric layer and having parasitic capacitance between it and the first wiring pattern, a conductor provided on the carrier substrate and electrically connected to the first wiring pattern and the second conductive film, a first pad electrically connected to the first wiring pattern via a wire, and a second pad electrically connected to the anode electrode of the photodetector, having a transimpedance amplifierThe device is equipped with the following features: The capacitance between the second conductive film and the main surface of the base is greater than the parasitic capacitance. The inductance of the conductor is less than the inductance of the wire.

[0009] In the optical receiver described above, a conductor is provided that is electrically connected to the first wiring pattern of the first conductive film and the second conductive film, and the conductor inductance This is connected in parallel with the parasitic capacitance between the first wiring pattern and the second conductive film. A dielectric layer is provided between the second conductive film and the main surface of the base, and the capacitance between the second conductive film and the main surface of the base is connected in series with the parasitic capacitance between the first conductive film and the second conductive film. The inductance of the conductor is smaller than the inductance of the wire, and the capacitance between the second conductive film and the main surface of the base is larger than the parasitic capacitance. In this configuration, the resonant frequency due to this capacitance and the inductance of the wire becomes dominant, and the resonant frequency can be set low. This allows the resonant frequency to be shifted to a lower frequency side than the high frequency band of tens of GHz or 100 GHz. In other words, the opaque band due to resonance can be removed from the signal frequency band. As a result, degradation of the signal waveform and the deterioration of communication quality such as inter-channel crosstalk can be suppressed.

[0010] In the optical receiver described above, the first conductive film may further include a second wiring pattern electrically connected to the anode electrode of the photodetector and a third wiring pattern electrically connected to the cathode electrode of the photodetector. The first and third wiring patterns may be arranged on either side of the second wiring pattern, respectively. The conductor may be electrically connected to at least one of the first and third wiring patterns and to the second conductive film. In this way, when the first and third wiring patterns are arranged on either side of the second wiring pattern, the magnetic fields created by the current flowing through the photodetector cancel each other out, making it difficult for the magnetic field to leak outside the first and third wiring patterns. This reduces crosstalk due to electromagnetic coupling to other wiring patterns.

[0011] In the optical receiver described above, the dielectric layer may have a surface facing the second conductive film and a back surface facing the main surface of the base. A first metal film electrically connected to the second conductive film may be provided on the surface of the dielectric layer. A second metal film electrically connected to the main surface of the base may be provided on the back surface of the dielectric layer. In this case, bonding of the dielectric layer to the first metal film and the second metal film becomes easier.

[0012] In the optical receiver described above, the first metal film, the dielectric layer, and the second metal film may constitute a chip capacitor. In this case, a dielectric layer having a capacitance greater than the parasitic capacitance between the first conductive film and the second conductive film can be easily realized.

[0013] In the optical receiver described above, the first metal film, the dielectric layer, and the second metal film may constitute a MIM capacitor. In this case, a dielectric layer having a capacitance greater than the parasitic capacitance between the first conductive film and the second conductive film can be easily realized.

[0014] In the optical receiver described above, the dielectric layer may be an insulating film. In this case, the dielectric layer constituting the MIM capacitor can be suitably realized.

[0015] In the optical receiver described above, the dielectric layer may include at least one of silicon nitride, silicon oxide, and silicon nitride oxide. In this case, the dielectric layer constituting the MIM capacitor can be easily formed.

[0016] In the optical receiver described above, the conductor may extend through the carrier substrate between the first wiring pattern and the second conductive film, and may have vias connected to the first wiring pattern and the second conductive film. The conductor may have multiple vias. The multiple vias may be spaced apart from each other in a plan view of the carrier substrate. In this case, a conductor with an inductance smaller than the wire inductance and connected in parallel with the parasitic capacitance between the first wiring pattern and the second conductive film can be easily realized. Furthermore, by configuring the first wiring pattern and the second conductive film to be connected by vias, the degree of freedom in wiring design is increased.

[0017] In the optical receiver described above, the carrier substrate may have a surface on which a first conductive film is provided, a back surface on which a second conductive film is provided, and a side surface connecting the surface and the back surface. The conductor may have a side conductive film provided on the side surface. The side conductive film may extend from the first wiring pattern to the second conductive film on the side surface and may be connected to the first wiring pattern and the second conductive film. In this case, a conductor can be easily formed that is connected in parallel with the parasitic capacitance between the first wiring pattern and the second conductive film and has an inductance smaller than the inductance of the wire.

[0018] The optical receiver described above may further include a metal substrate provided between the dielectric layer and the base, and electrically connected to the main surface of the base. In this case, even if the dielectric layer is formed thinly to increase capacitance, the presence of the metal substrate allows the height of the dielectric layer and carriers on the metal substrate to be maintained high, thus improving the carrier and transimpedance. amplifier The height difference between the first conductive film on the carrier and the transimpedance can be kept small. amplifier This prevents the wire connecting to the upper first pad from becoming too long, and also prevents the photodetector from having to use a transimpedance. amplifier Connection loss between Loss It can be suppressed.

[0019] The optical receiver described above may further include an insulating substrate provided between the dielectric layer and the base. The insulating substrate may have a surface facing the dielectric layer and a back surface facing the main surface of the base. Back side It is electrically connected to the main surface of the base. Back side A metal film may be provided on the insulating substrate. surface This is via vias that penetrate the interior of the insulating substrate. Back side A metal film and an electrically connected surfaceA metal film may be provided. In this case, even if the dielectric layer is formed thinly to increase capacitance, the presence of the surface metal film, insulating substrate, and back metal film allows the height of the dielectric layer and carriers on the surface metal film to be maintained high, thus controlling the carrier and transimpedance. amplifier The height difference between the first conductive film on the carrier and the transimpedance can be kept small. amplifier This prevents the wire connecting to the upper first pad from becoming too long, and also prevents the photodetector from having to use a transimpedance. amplifier Connection loss between Loss It can be suppressed.

[0020] [Details of the embodiments of this disclosure] A specific example of an optical receiver according to one embodiment will be described below with reference to the drawings. This disclosure is not limited to these examples, but is as defined by the claims, and all modifications within the meaning and scope of the claims are intended to be included. In the description of the drawings, the same elements are denoted by the same reference numerals, and redundant descriptions are omitted where appropriate.

[0021] Figure 1 is a plan view showing the internal structure of the optical receiver 1 according to this embodiment. Figure 2 is a cross-sectional view showing the optical receiver 1. In Figure 1, the optical receiver 1 is shown with the lid of the package 11 removed. The optical receiver 1 is used as a ROSA (Receiver Optical Sub Assembly) of an optical transceiver. As shown in Figure 1, the optical receiver 1 comprises a package 11. The package 11 is a hollow container in the shape of a roughly rectangular parallelepiped. The package 11 has metal side walls 12 and a metal bottom plate 13.

[0022] The bottom plate 13 is a rectangular flat plate. The bottom plate 13 extends along direction A1 and direction A2 intersecting direction A1. The bottom plate 13 includes a bottom surface 13a facing inward into the package 11. At least the bottom surface 13a of the bottom plate 13 is conductive, and the bottom surface 13a is set to a reference potential. The bottom plate 13 may be made of a metal such as copper molybdenum or copper tungsten. If the bottom plate 13 is made of a material with good thermal conductivity, it is possible to improve the heat dissipation of the bottom plate 13.

[0023] The side wall 12 has a rectangular frame shape and is positioned along the periphery of the bottom plate 13. The opening on the side wall 12 opposite to the bottom plate 13 is sealed by a lid. The side wall 12 includes side wall portions 12a and 12b aligned along direction A1. An opening is formed in side wall portion 12a, and a bush 14 is provided in this opening. The receptacle of the optical receiver 1 is fixed to side wall portion 12a via the bush 14. Inside the bush 14, for example, an optical window 15 (see Figure 2) is positioned. As shown in Figure 2, signal light L emitted from the optical fiber connected to the receptacle passes through the optical window 15 and is taken into the package 11. The signal light L is, for example, a multiplexed signal light having multiple signal light components.

[0024] As shown in Figures 1 and 2, the optical receiver 1 further comprises an optical axis converter 21, an optical demultiplexer 22, multiple lenses 23, multiple photodetectors 24, a TIA 25 (transimpedance amplifier), and a feedthrough 26. The optical axis converter 21, optical demultiplexer 22, multiple lenses 23, multiple photodetectors 24, and TIA 25 are housed inside the package 11 and are arranged in this order from the side wall 12a side in direction A1. As shown in Figure 2, the optical receiver 1 further comprises a carrier 31 on which multiple photodetectors 24 are mounted, and a capacitor 32 on which the carrier 31 is mounted.

[0025] The feedthrough 26 is provided in the side wall 12b and makes an electrical connection to the external circuit. The feedthrough 26 is, for example, constructed by laminating multiple ceramic substrates and assembled to fit into an opening formed in the side wall 12b. Multiple terminals 26a for making an electrical connection to the external circuit are provided on the outer portion of the feedthrough 26 located outside the side wall 12b. Multiple terminals for making an electrical connection to the TIA 25 are provided on the inner portion of the feedthrough 26 located inside the side wall 12b. The multiple terminals on the inner portion of the side wall 12b and the multiple terminals 26a on the outer portion of the side wall 12b are short-circuited to each other by wiring embedded inside the feedthrough 26.

[0026] As shown in Figure 2, the optical axis converter 21 converts the optical axis of the signal light L input from the optical window 15 into the inside of the package 11. The optical axis converter 21 has a pair of mirrors 21a and 21b. The pair of mirrors 21a and 21b are arranged to face each other in direction A3, which intersects with directions A1 and A2. One of the pair of mirrors 21a, 21b, is positioned opposite the optical window 15 in direction A1. Mirror 21a reflects the signal light L input from the optical window 15 in direction A1 towards the bottom plate 13 in direction A3. The other mirror 21b of the pair of mirrors 21a, 21b is installed on the bottom plate 13 and reflects the signal light L input from mirror 21a in direction A3 towards the side wall 12b in direction A1. In the following description, viewing from direction A3 may be referred to as a "plan view".

[0027] The signal light L reflected by the mirror 21b enters the optical demultiplexer 22 in direction A1. The optical demultiplexer 22 separates the signal light L, which is a multiplexed signal light, into multiple signal light components with different wavelengths. Multiple lenses 23 are positioned between the optical demultiplexer 22 and multiple photodetectors 24 in direction A1 and are aligned along direction A2 (see Figure 1). Each lens 23 is incident on each signal light component separated by the optical demultiplexer 22. Each lens 23 focuses each separated signal light component and guides it to each photodetector 24.

[0028] Multiple photodetectors 24 are mounted on a carrier 31 and are arranged along direction A2 so as to face direction A1 with respect to multiple lenses 23. Each photodetector 24 is, for example, a waveguide-type photodetector. Each photodetector 24 is optically coupled to an optical demultiplexer 22 via each lens 23. Signal light components from each lens 23 are incident on, for example, the side of each photodetector 24. Each photodetector 24 converts the corresponding signal light components into electrical signals. In the example shown in Figure 1, four photodetectors 24 are shown, but the number of photodetectors 24 is not particularly limited. The number of photodetectors 24 may be any number of one or more.

[0029] The TIA25 is mounted on the bottom surface 13a of the package 11 and is positioned between the multiple photodetectors 24 and the feedthrough 26 in direction A1. The TIA25 is electrically connected to each photodetector 24. The TIA25 converts the current signals from each photodetector 24 into voltage signals. The TIA25 is electrically connected to the wiring of the feedthrough 26 via wires. The voltage signal output from the TIA25 is output to the outside of the optical receiver 1 via the feedthrough 26.

[0030] Figure 3 is a plan view showing an enlarged view of the surrounding structure of the photodetector 24 and TIA25. Figure 4 is a cross-sectional view along the line B1-B1 in Figure 3. Figure 5 is a cross-sectional view along the line B2-B2 in Figure 3, and Figure 6 is a cross-sectional view along the line B3-B3 in Figure 3.

[0031] The photodetector 24 is, for example, rectangular and has a front surface 24a, a back surface 24b, and a side surface 24c. The front surface 24a and the back surface 24b are aligned along direction A3. The front surface 24a faces away from the bottom plate 13 in direction A3. The back surface 24b faces the carrier 31 in direction A3. The side surface 24c faces the TIA 25 in direction A1. The side surface 24c connects the front surface 24a and the back surface 24b in direction A3. A conductive film 28 is provided on the back surface 24b. The conductive film 28 is a metal film fixed to the back surface 24b of the photodetector 24. The conductive film 28 is electrically connected to the cathode electrode and the anode electrode of the photodetector 24.

[0032] The carrier 31 is a rectangular parallelepiped member on which the photodetector 24 is mounted. The carrier 31 is positioned between the photodetector 24 and the bottom surface 13a in direction A3. The carrier 31 has an insulating carrier substrate 35. The material of the carrier substrate 35 is, for example, quartz. The carrier substrate 35 has a front surface 35a, a back surface 35b, and a pair of side surfaces 35c and 35d. The front surface 35a and the back surface 35b are aligned along direction A3. The front surface 35a faces the back surface 24b of the photodetector 24 in direction A3. The back surface 35b faces the capacitor 32 in direction A3. The pair of side surfaces 35c and 35d are aligned along direction A1 and connect the front surface 35a and the back surface 35b in direction A3. One of the side surfaces 35c faces the TIA 25 in direction A1. Of the pair of sides 35c and 35d, the other side 35d is positioned on the opposite side from side 35c in direction A1.

[0033] The carrier 31 further comprises a first conductive film 36 provided on the surface 35a and a second conductive film 37 provided on the back surface 35b. The first conductive film 36 is a metal film fixed to the surface 35a. The second conductive film 37 is a metal film fixed to the back surface 35b. A parasitic capacitance C exists between the first conductive film 36 and the second conductive film 37. cq (See Figure 4) is occurring. Parasitic capacity C cq For example, this range is between 10 fF and 100 fF.

[0034] The carrier 31 and the photodetector 24 are connected by flip-chip bonding (FCB). That is, the photodetector 24 is mounted on the carrier 31 in a flip-type configuration. Figure 7 shows how the photodetector 24 and the carrier 31 are connected by flip-chip bonding. As shown in Figure 7, the conductive film 28 provided on the back surface 24b of the photodetector 24 has an anode pad 28a, a first cathode pad 28b, a second cathode pad 28c, a third cathode pad 28d, and a fourth cathode pad 28e.

[0035] The first cathode pad 28b and the second cathode pad 28c are spaced apart along direction A2, and the anode pad 28a is positioned between the first cathode pad 28b and the second cathode pad 28c. Therefore, the first cathode pad 28b and the second cathode pad 28c are positioned on either side of the anode pad 28a in direction A2. The third cathode pad 28d and the fourth cathode pad 28e are spaced apart along direction A2 and are positioned in a direction A1, respectively, that is aligned with the first cathode pad 28b and the second cathode pad 28c.

[0036] An anode pattern 28h extending linearly along direction A1 is connected to the anode pad 28a. The tip of the anode pattern 28h facing the anode pad 28a is the anode electrode of the photodetector 24, and the photodetector 24 is electrically connected to the anode electrode (i.e., the tip of the anode pattern 28h). The first cathode pad 28b and the third cathode pad 28d are connected by a cathode pattern 28f extending linearly along direction A1. The second cathode pad 28c and the fourth cathode pad 28e are connected by a cathode pattern 28g extending linearly along direction A1. The cathode patterns 28f and 28g are arranged on both sides of the anode pattern 28h in direction A2.

[0037] A cathode pattern 28j is connected to the third cathode pad 28d, extending linearly toward the anode pattern 28h in direction A2. The first cathode pad 28b and the third cathode pad 28d are electrically connected to the cathode electrode of the photodetector 24 via cathode patterns 28f and 28j. A cathode pattern 28k is connected to the fourth cathode pad 28e, extending linearly toward the anode pattern 28h in direction A2. The second cathode pad 28c and the fourth cathode pad 28e are electrically connected to the cathode electrode of the photodetector 24 via cathode patterns 28g and 28k. The width of the anode pattern 28h is smaller than the width of each cathode pattern 28f, 28g, 28j, and 28k.

[0038] The first conductive film 36 provided on the surface 35a of the carrier 31 has an anode wiring pattern 36a and a cathode wiring pattern 36b. The anode wiring pattern 36a is a linear wiring pattern extending along direction A1. The cathode wiring pattern 36b is a U-shaped wiring pattern opening on one side in direction A1. The anode wiring pattern 36a is positioned in the opening of the cathode wiring pattern 36b and is surrounded by the cathode wiring pattern 36b. The anode wiring pattern 36a is positioned to overlap with the anode pad 28a of the photodetector 24 in a plan view. The anode wiring pattern 36a is electrically connected to the anode pad 28a, for example, via a pillar 51 (see Figures 5 and 6). The anode wiring pattern 36a may also be electrically connected to the anode pad 28a via bumps.

[0039] The cathode wiring pattern 36b has a first portion 36c (first wiring pattern) and a second portion 36d, which are provided on both sides of the anode wiring pattern 36a in direction A2. In a plan view, the first portion 36c is, Second cathode pad 28c and fourth cathode pad 28e It is positioned in a position that overlaps with it. The second part 36d, in plan view, First cathode pad 28b and third cathode pad 28d It is positioned in a position that overlaps with it. The cathode wiring pattern 36b is electrically connected to the cathode pads 28b, 28c, 28d, and 28e, for example, via the pillar 52 (see Figures 4 and 6). The cathode wiring pattern 36b may also be electrically connected to the cathode pads 28b, 28c, 28d, and 28e via bumps.

[0040] Referring to FIG. 4 again. The capacitor 32 is a rectangular parallelepiped member carrying the carrier 31. The capacitor 32 is mounted on the bottom surface 13a of the bottom plate 13. Therefore, the capacitor 32 is disposed between the carrier 31 and the bottom surface 13a in the direction A3. The capacitor 32 is a capacitive element such as a chip capacitor, for example. The capacitor 32 has a dielectric layer 41, a first metal film 42, and a second metal film 43. The dielectric layer 41 is sandwiched between the first metal film 42 and the second metal film 43 in the direction A3. The dielectric layer 41 functions as an insulating layer that electrically insulates between the first metal film 42 and the second metal film 43. The thickness of the dielectric layer 41 is thicker than the thicknesses of the first metal film 42 and the second metal film 43, respectively, for example. The dielectric layer 41 has a front surface 41a and a back surface 41b arranged along the direction A3. The front surface 41a faces the back surface 35b of the carrier 31. The first metal film 42 is provided on the front surface 41a. Therefore, the first metal film 42 is disposed between the second conductive film 37 provided on the back surface 35b of the carrier 31 and the dielectric layer 41. The first metal film 42 is conductively joined to the second conductive film 37 via a conductive adhesive such as solder.

[0041] The back surface 41b of the dielectric layer 41 faces the bottom surface 13a of the bottom plate 13. The second metal film 43 is provided on the back surface 41b. Therefore, the second metal film 43 is disposed between the dielectric layer 41 and the bottom surface 13a. The second metal film 43 is conductively joined to the bottom surface 13a via a conductive adhesive such as solder. The capacitance C of the capacitor 32 c is generated between the first metal film 42 and the second metal film 43 sandwiching the dielectric layer 41. The capacitance C of the capacitor 32 c is the parasitic capacitance C generated between the first conductive film 36 and the second conductive film 37 cq and is connected in series thereto. The capacitance C of the capacitor 32 c is the parasitic capacitance C cq and is sufficiently larger than it. The parasitic capacitance C cq is, for example, 10 fF or more and 100 fF or less, while the capacitance C of the capacitor 32 c is, for example, 10 pF or more.

[0042] TIA25 is mounted on the bottom surface 13a of the base plate 13 and is electrically connected to the bottom surface 13a. Therefore, the ground potential (reference potential) of TIA25 matches the potential of the bottom surface 13a. TIA25 is positioned next to the photodetector 24 in direction A1. TIA25 has, for example, a rectangular parallelepiped shape and has a front surface 25a and a back surface 25b. The front surface 25a and the back surface 25b are aligned along direction A3. The back surface 25b is electrically bonded to the bottom surface 13a via a conductive adhesive such as solder. The front surface 25a is positioned on the opposite side from the bottom surface 13a in direction A3.

[0043] The TIA25 further includes a signal pad 25c, a first bias pad 25d, and a second bias pad 25e. The signal pad 25c, the first bias pad 25d, and the second bias pad 25e are provided on the surface 25a of the TIA25. The first bias pad 25d and the second bias pad 25e are arranged on either side of the signal pad 25c in direction A2. The signal pad 25c is connected to the anode wiring pattern 36a of the first conductive film 36 via a wire 71 (see Figure 3). That is, one end of the wire 71 is connected to the signal pad 25c, and the other end of the wire 71 is connected to the anode wiring pattern 36a.

[0044] The first bias pad 25d is connected to the first portion 36c of the cathode wiring pattern 36b via wire 72 (see Figure 3). That is, one end of wire 72 is connected to the first bias pad 25d, and the other end of wire 72 is connected to the first portion 36c of the cathode wiring pattern 36b. The second bias pad 25e is connected to the second portion 36d of the cathode wiring pattern 36b via wire 73. That is, one end of wire 73 is connected to the second bias pad 25e, and the other end of wire 73 is connected to the second portion 36d of the cathode wiring pattern 36b.

[0045] A ground layer 27 is provided inside the TIA25. The ground layer 27 extends along directions A1 and A2 inside the TIA25. The ground layer 27 is located between the surface 25a and the back surface 25b, closer to the surface 25a. The ground layer 27 is connected to the back surface 25b via a via 29. The via 29 penetrates the TIA25 between the ground layer 27 and the back surface 25b in direction A3. The ground layer 27 is electrically connected to the bottom surface 13a of the bottom plate 13 via the via 29. Therefore, the ground potential is supplied to the ground layer 27.

[0046] As shown in Figure 4, the carrier 31 further has a plurality of vias 38. The plurality of vias 38 are made of a conductive material. The plurality of vias 38 penetrate the carrier substrate 35 in direction A3 and are connected to the first conductive film 36 and the second conductive film 37 that sandwich the carrier substrate 35. Thus, the first conductive film 36 and the second conductive film 37 are electrically connected to each other via the plurality of vias 38. In this case, the inductance L of each via 38 via Each wire 72, 73 The combined inductance L wire They are connected in parallel to each other. As shown in Figure 3, the multiple vias 38 are formed only in the region that overlaps with the cathode wiring pattern 36b in a plan view. That is, the multiple vias 38 are formed only in the region between the cathode wiring pattern 36b and the second conductive film 37 in direction A3. Therefore, the multiple vias 38 are not formed in the region that overlaps with the anode wiring pattern 36a in a plan view, i.e., the region between the anode wiring pattern 36a and the second conductive film 37 in direction A3.

[0047] As shown in Figures 3 and 7, the multiple vias 38 are spaced apart from each other and arranged at equal intervals in a plan view. The inner diameter of each of the multiple vias 38 may be set to be the same, for example. The combined inductance L of the multiple vias 38 via The combined inductance L of wires 72 and 73 is wire It is sufficiently small compared to the combined inductance L of wires 72 and 73. wireFor example, while the combined inductance L of multiple vias 38 is between 0.1 nH and 0.5 nH, via For example, the value is 0.05 nH or less. In the examples shown in Figures 3 and 7, seven vias 38 are shown, but the number of vias 38 is not limited to seven and can be any number. The number of vias 38 may be one, two, three, or eight or more. In the examples shown in Figures 3 and 7, the multiple vias 38 are positioned so as not to overlap with the anode pad 28a and the cathode pads 28b, 28c, 28d, and 28e of the photodetector 24, but they may also be positioned so as to overlap with these pads.

[0048] <Effects and Effects> The effects obtained by the optical receiver 1 according to this embodiment, as described above, will be explained along with the problems of the comparative example. Figure 8 is an equivalent circuit diagram between the photodetector 24 and the TIA 25 in the optical receiver 1 according to this embodiment. Figure 9 is an equivalent circuit diagram extracted from a part of Figure 8. In Figure 8, "Port 1" indicates a portion set between the anode (A) and cathode (C) of the photodetector 24, and "Port 2" indicates a portion set between the signal pad 25c and the ground layer 27 of the TIA 25.

[0049] As shown in Figure 8, in the optical receiver 1, the cathode (C) of the photodetector 24 is connected to the first bias pad 25d and the second bias pad 25e of the TIA 25 via wires 72 and 73. The anode (A) of the photodetector 24 is connected to the signal pad 25c of the TIA 25 via wire 71. The ground layer 27 of the TIA 25 is electrically connected to the bottom surface 13a of the bottom plate 13. There is a parasitic capacitance C between the cathode wiring pattern 36b and the second conductive film 37. cq Furthermore, in this embodiment, a capacitor 32 is provided between the second conductive film 37 and the bottom plate 13, and a plurality of vias 38 are formed between the cathode wiring pattern 36b and the second conductive film 37. Therefore, as shown in Figure 9, the capacitance C of the capacitor 32 c Parasitic capacity C cq Connected in series with each via 38, the inductance Lvia Parasitic capacity C cq It is connected in parallel to it.

[0050] The first portion 36c and the second portion 36d of the cathode wiring pattern 36b receive a power supply (bias) voltage via wires 72 and 73 from the first bias pad 25d and the second bias pad 25e of the TIA 25. When signal light L is incident on the photodetector 24, the photodetector 24 outputs a current signal (high-frequency current) of a magnitude corresponding to the amount of light. This current signal is input from the anode (A) of the photodetector 24 to the signal pad 25c of the TIA 25 via the anode pad 28a, the anode wiring pattern 36a, and wire 71. The TIA 25 converts the input current signal into a voltage signal. This voltage signal is provided to an external source of the optical receiver 1 or to other electronic components within the optical receiver 1.

[0051] Figure 17 is a cross-sectional view showing an optical receiver 101 according to Comparative Example 1. Unlike the optical receiver 1 according to this embodiment, the optical receiver 101 does not have multiple vias formed on the carrier substrate 135, and no capacitor is provided between the carrier substrate 135 and the bottom plate 13. Therefore, the optical receiver 101 has a configuration in which the carrier substrate 135 is directly mounted on the bottom plate 13. Figure 18 is an equivalent circuit diagram between the photodetector 24 and the TIA 25 in the optical receiver 101. Figure 19 is an equivalent circuit diagram extracted from a part of Figure 18. In the equivalent circuit diagram shown in Figure 18, the current signal from the photodetector 24 travels, for example, from the anode (A) of the photodetector 24 through wire 71 and signal pad 25c to the ground layer 27 of the TIA 25, and then capacitively couples to the first bias pad 25d and second bias pad 25e of the TIA 25. The current signal then flows back to the cathode (C) of the photodetector 24 via wires 72 and 73.

[0052] Here, between the first conductive film 36 and the second conductive film 37, there is a parasitic capacitance C cq Because this is occurring, this parasitic capacity C cq The combined inductance L of wires 72 and 73 wireThis constitutes a parallel resonant circuit where the elements are connected in parallel. Figure 19 shows the inductance L wire and parasitic capacity C cq This shows a parallel resonant circuit composed of the following. The resonant frequency f1 of this parallel resonant circuit is expressed by the following equation (1). The resonant frequency f1 is the frequency bandwidth of the transmission signal (for example, several tens of G As the frequency approaches Hz or higher, the return current from TIA25 to the photodetector 24 decreases. At this time, the flow of the current signal from the photodetector 24 to TIA25 is obstructed, resulting in signal opacity.

number

[0053] Figure 20 is a graph showing the simulation results of the relationship between insertion loss (unit: dB) and signal frequency (unit: GHz) in the optical receiver 101. In optical communication systems, 100G transmission is the mainstream within branch lines and data centers, and between branch lines and data centers, and higher speeds such as 800G transmission are planned for the future. At such transmission speeds, the frequency bandwidth of the transmitted signal is several tens of G The frequency range is from Hz to around 100 GHz. In contrast, in the optical receiver 101, as shown in Figure 20, the insertion loss drops significantly around 30 GHz, indicating that the resonant frequency f1 is located around 30 GHz. In this case, the resonant frequency f1 overlaps with the frequency band of the transmitted signal, resulting in an opaque band of the transmitted signal as described above. As a result, there is a risk of degradation of the signal waveform and a decrease in communication quality, such as inter-channel crosstalk.

[0054] Figure 21 is a cross-sectional view showing the optical receiver 102 according to Comparative Example 2. Figure 22 is an equivalent circuit diagram between the photodetector 24 and the TIA 25 in the optical receiver 102. Figure 23 is a graph showing the simulation results of the relationship between insertion loss (unit: dB) and signal frequency (unit: GHz) in the optical receiver 102.

[0055] The optical receiver 102 has a configuration in which a ceramic substrate 150 is further added between the carrier substrate 135 and the bottom plate 13 in the optical receiver 101 according to Comparative Example 1. The ceramic substrate 150 has a capacitance C of, for example, 10 fF or more and 100 fF or less. s This configuration has the following characteristics. Thus, by placing the ceramic substrate 150 under the carrier substrate 135, it is conceivable that the capacitance between the first conductive film 36 on the carrier substrate 135 and the bottom plate 13 can be reduced, and the resonant frequency can be shifted to the high-frequency side. In this configuration, as shown in Figure 22, the capacitance C of the ceramic substrate 150 s This is the parasitic capacitance C between the first conductive film 36 and the second conductive film 37. cq It is connected in series with respect to the parallel resonant circuit shown in Figure 22, and the resonant frequency f2 of the parallel resonant circuit is expressed by the following equation (2).

number

[0056] However, in the optical receiver 102, parasitic capacitance C cq Capacitance C s If the noise cannot be reduced sufficiently, the resonant frequency f2 cannot be moved sufficiently to the high-frequency side. As shown in Figure 23, the resonant frequency f2 of the parallel resonant circuit in the optical receiver 102 is only slightly higher in frequency than the resonant frequency f1 in Comparative Example 1, and is located around 40 GHz. This resonant frequency f2 is in the frequency band of the transmitted signal. region and They overlap. Therefore, as in Comparative Example 2, the measure of placing the ceramic substrate 150 under the carrier substrate 135 does not sufficiently shift the resonant frequency f2.

[0057] Figure 24 is a cross-sectional view showing the optical receiver 103 according to Comparative Example 3. Figure 25 is an equivalent circuit diagram between the photodetector 24 and the TIA 25 in the optical receiver 103. Figure 26 is a graph showing the simulation results of the relationship between insertion loss (unit: dB) and signal frequency (unit: GHz) in the optical receiver 103.

[0058] The optical receiver 103 according to Comparative Example 3 has a configuration in which a plurality of vias 138 are formed on the carrier substrate 135 of the optical receiver 102 according to Comparative Example 2. In other words, the optical receiver 103 has a carrier substrate 235 on which a plurality of vias 138 are formed, instead of the carrier substrate 135 of the optical receiver 102. In this configuration, the plurality of vias 138 penetrate the interior of the carrier substrate 235 and are connected to the first conductive film 36 and the second conductive film 37 that sandwich the carrier substrate 235. In this case, as shown in the parallel resonant circuit of Figure 25, the combined inductance L of the plurality of vias 138 is via This is the parasitic capacitance C between the first conductive film 36 and the second conductive film 37. cq It is connected in parallel to it.

[0059] Here, the inductance L via is the inductance L wire Sufficiently smaller than, parasitic capacity C cq The capacitance C of the ceramic substrate 150 s Because it is sufficiently smaller than, the inductance L via and parasitic capacity C cq Approximating this to zero, the resonant frequency f3 of the parallel resonant circuit shown in Figure 25 is expressed by the following equation (3). Therefore, in the optical receiver 103, the inductance L wire and capacitance C s These two factors dominate the resonant frequency f3.

number

[0060] In contrast, the optical receiver 1 according to this embodiment includes a carrier 31 on which a plurality of vias 38 are formed, and a capacitor 32 provided between the carrier 31 and the bottom plate 13. In the optical receiver 1, the combined inductance L of the plurality of vias 38 via This is the parasitic capacitance C between the first conductive film 36 and the second conductive film 37. cqIt is connected in parallel with the capacitance C of capacitor 32. s Parasitic capacity C cq It is connected in series with the inductance L. via is the inductance L wire Sufficiently smaller than, parasitic capacity C cq capacitance C c Because it is sufficiently smaller than, the inductance L via and parasitic capacity C cq Approximating L to be zero, the resonant frequency f of the parallel resonant circuit shown in Figure 9 is expressed by the following equation (4). Therefore, in this embodiment, the inductance L wire and capacitance C c These two factors dominate the resonant frequency f.

number

[0061] Here, capacitance C c This is the capacitance C related to Comparative Example 3. s It is sufficiently larger than . Therefore, the resonant frequency f becomes lower than the resonant frequency f3 in Comparative Example 3, and shifts significantly to the lower frequency side. Figure 10 is a graph showing the simulation results of the relationship between insertion loss (unit: dB) and signal frequency (unit: GHz) in the optical receiver 1 according to this embodiment. As shown in Figure 10, the resonant frequency f has shifted to the extremely low frequency side, for example, below 5 GHz, and it can be seen that it does not exist in the frequency band of the transmission signal, such as tens of GHz or 100 GHz. In this way, in this embodiment, the resonant frequency f can be sufficiently shifted to the lower frequency side than the frequency band of the transmission signal. In other words, the opaque band due to resonance can be removed from the frequency band of the transmission signal. As a result, degradation of the signal waveform and the deterioration of communication quality such as inter-channel crosstalk can be suppressed. Furthermore, in this embodiment, unlike when the photodetector and TIA are connected with a flip-chip connection, there is no need to use a TIA with pads dedicated to flip-chip connection, so there is a high degree of freedom in the combination of the photodetector and TIA.

[0062] On the higher frequency side of the transmission signal's frequency band, the inductance Lvia and parasitic capacity C cq It is thought that a resonant frequency exists. This resonant frequency is thought to shift to the higher frequency side as the number of vias 38 increases, and does not exist in the frequency band of the transmitted signal. In the optical receiver 1 according to this embodiment, the capacitance C of capacitor 32 c Since it is sufficiently large and can be considered to short-circuit at high frequencies, it can be considered that wires 72 and 73 and via 38 are connected in parallel to ground. In this case, the more vias 38 there are, the greater the combined inductance L via Because it appears to decrease, the inductance L via and parasitic capacity C cq The resonant frequency is thought to shift to the higher frequency side. On the other hand, in the optical receiver 103 according to Comparative Example 3, the capacitance C of capacitor 32 c Compared to the capacitance C of ceramic substrate 150 s Because it is small, it cannot be considered that wires 72 and 73 and via 138 are connected in parallel with respect to ground, resulting in a combined inductance L via It is thought that the signal is lowered and therefore not visible. For this reason, unlike the optical receiver 1 according to this embodiment, it is thought that the optical receiver 103 has a resonance point (see Figure 26) around 100 GHz on the high-frequency side.

[0063] In this embodiment, the first portion 36c and the second portion 36d of the cathode wiring pattern 36b are arranged on either side of the anode wiring pattern 36a, respectively. In this case, the magnetic fields created by the current flowing through the photodetector 24 cancel each other out, making it difficult for the magnetic field to leak outside the cathode wiring pattern 36b. This reduces crosstalk caused by electromagnetic coupling to other wiring patterns.

[0064] In this embodiment, a first metal film 42 electrically connected to a second conductive film 37 is provided on the surface 41a of the dielectric layer 41, and a second metal film 43 electrically connected to the bottom surface 13a of the bottom plate 13 is provided on the back surface 41b of the dielectric layer 41. This facilitates bonding of the dielectric layer 41 to the first metal film 42 and the second metal film 43.

[0065] In this embodiment, the first metal film 42, the dielectric layer 41, and the second metal film 43 constitute a chip capacitor. This results in parasitic capacitance C cq Capacitance C is larger than c A capacitor 32 having the above characteristics can be easily realized.

[0066] In this embodiment, a plurality of vias 38 penetrate the interior of the carrier 31 and are connected to the first conductive film 36 and the second conductive film 37. The plurality of vias 38 are arranged at positions spaced apart from each other in a plan view. In this case, the parasitic capacitance C cq It is connected in parallel with respect to and has an inductance L wire A configuration with a smaller inductance can be easily realized. Furthermore, by connecting the first conductive film 36 and the second conductive film 37 by via 38, the degree of freedom in wiring design can be increased.

[0067] The optical receiver 1 relating to this disclosure is not limited to the embodiments described above. The optical receiver 1 relating to this disclosure may be modified in any way that does not depart from the spirit of the claims.

[0068] <Example 1> Figure 11 is a cross-sectional view showing an optical receiver 1A according to Modification 1. In the embodiment described above, the case in which the capacitor 32 is a chip capacitor was illustrated. In Modification 1, the case in which the capacitor 32A is a MIM (Metal-Insulator-Metal) capacitor is illustrated. The capacitor 32A has a dielectric layer 41A, a first metal film 42, and a second metal film 43, with the dielectric layer 41A sandwiched between the first metal film 42 and the second metal film 43. The dielectric layer 41A is formed thinner than the dielectric layer 41 according to the embodiment described above. For example, the thickness of the dielectric layer 41A may be the same as the thickness of the first metal film 42 or the thickness of the second metal film 43. The dielectric layer 41A is configured as an insulating film that electrically insulates between the first metal film 42 and the second metal film 43. The dielectric layer 41A may be composed of at least one of SiN (silicon nitride), SiO (silicon oxide), and SiON (silicon nitride oxide).

[0069] In the optical receiver 1A, the capacitor 32A is mounted on the back surface 35b of the carrier substrate 35. In this case, the first metal film 42 of the capacitor 32A is integrally formed with the second conductive film 37 provided on the back surface 35b of the carrier substrate 35. Therefore, when manufacturing the optical receiver 1A, the dielectric layer 41A and the second metal film 43 are formed on the back surface 35b of the carrier substrate 35, and then the carrier substrate 35 with the dielectric layer 41A and the second metal film 43 formed on it is mounted on a metal substrate 81, which will be described later. Capacitance C of capacitor 32A c This is the parasitic capacitance C between the first conductive film 36 and the second conductive film 37. cq It is significantly larger than that. Capacitance C of capacitor 32A c It is 10pF or more. Capacitance C of capacitor 32A c This may, for example, be the same as the capacitance of the chip capacitor.

[0070] The optical receiver 1A further includes a metal substrate 81 provided between the capacitor 32A and the base plate 13. The metal substrate 81 is a substrate made of a metallic material and is conductive. The metal substrate 81 has a surface 81a that is conductively bonded to the second metal film 43 of the capacitor 32A, and a back surface 81b that is conductively bonded to the bottom surface 13a of the base plate 13. Therefore, the second metal film 43 is electrically connected to the base plate 13 via the metal substrate 81. Depending on the thickness of the metal substrate 81, the height of the capacitor 32A on the metal substrate 81 and the height of the carrier substrate 35 on the capacitor 32A vary. Therefore, the thickness of the metal substrate 81 may be set so that the height of the carrier substrate 35 matches the height of the TIA 25.

[0071] Even with this configuration, the same effects as in the above-described embodiment can be obtained. Furthermore, in the optical receiver 1A, the capacitor 32A is composed of the first metal film 42, the dielectric layer 41A, and the second metal film 43, which makes it possible to reduce the thickness of the capacitor 32A and parasitic capacitance C cq A capacitor 32A having a larger capacitance than can be easily realized. The dielectric layer 41A is composed of at least one of silicon nitride, silicon oxide, and silicon nitride oxide, and insulates between the first metal film 42 and the second metal film 43. This makes it easy to form the dielectric layer 41A and to achieve the desired capacitance C between the first metal film 42 and the second metal film 43. c We can be sure to secure it.

[0072] Furthermore, in the optical receiver 1A, a metal substrate 81 is provided between the capacitor 32A and the bottom plate 13. As a result, even if the dielectric layer 41A is formed thinly to increase capacitance, the presence of the metal substrate 81 allows the height of the capacitor 32A and the carrier substrate 35 on the metal substrate 81 to be maintained high, thus keeping the height difference between the carrier substrate 35 and the TIA 25 small. Consequently, the situation in which the wires 71, 72, and 73 between the carrier substrate 35 and the TIA 25 become long can be suppressed, and connection loss between the photodetector 24 and the TIA 25 can be reduced. Loss It can be suppressed.

[0073] <Modification 2> Figure 12 is a cross-sectional view showing an optical receiver 1B according to Modification 2. The optical receiver 1B has a configuration in which the metal substrate 81 is replaced with an insulating substrate 82 in the optical receiver 1A according to Modification 1. In other words, the optical receiver 1B is equipped with a capacitor 32A instead of a capacitor 32, and an insulating substrate 82 instead of a metal substrate 81. The insulating substrate 82 is a substrate made of an insulating material and has electrical insulating properties. The insulating substrate 82 is provided between the capacitor 32A and the bottom plate 13. The insulating substrate 82 has a surface surface 82a facing the capacitor 32A and a back surface 82b facing the bottom plate 13. The surface surface 82a is provided with a surface metal film 83 which is conductively bonded to the second metal film 43 of the capacitor 32A. The back surface 82b is provided with a back surface metal film 84 which is conductively bonded to the bottom surface 13a of the bottom plate 13. The surface metal film 83 and the back surface metal film 84 are connected by a plurality of vias 85 that penetrate the insulating substrate 82 in direction A3.

[0074] Therefore, the surface metal film 83 and the back metal film 84 are electrically connected to each other via a plurality of vias 85. In other words, the second metal film 43 of the capacitor 32A is electrically connected to the bottom surface 13a of the bottom plate 13 via the surface metal film 83, the back metal film 84, and the plurality of vias 85. Depending on the thickness of the insulating substrate 82, insulation The height of the capacitor 32A on the substrate and the height of the carrier substrate 35 on the capacitor 32A fluctuate. Therefore, the thickness of the insulating substrate 82 may be set so that the height of the carrier substrate 35 matches the height of the TIA 25. The configuration for electrically connecting the surface metal film 83 and the back metal film 84 does not have to be multiple vias 85; any conductor capable of electrically connecting the surface metal film 83 and the back metal film 84 may be used. For example, the surface metal film 83 and the back metal film 84 may be electrically connected by a metal film provided on the side surface of the insulating substrate 82.

[0075] Even in this configuration, the same effects as in the above-described embodiment can be obtained. Furthermore, in the optical receiver 1B, the dielectric layer 41 A Because an insulating substrate 82 is provided between the bottom plate 13 and the dielectric layer 41 to increase capacitanceA Even if the substrate is formed thinly, the presence of the insulating substrate 82 allows the height of the capacitor 32A and the carrier substrate 35 to be maintained at a high level. This keeps the height difference between the carrier substrate 35 and the TIA 25 small. As a result, the situation in which the wires 71, 72, and 73 between the carrier substrate 35 and the TIA 25 become long can be suppressed, and connection loss between the photodetector 24 and the TIA 25 can be reduced. Loss It can be suppressed.

[0076] <Variation 3> Figure 13 is a cross-sectional view showing the optical receiver 1C according to Modification 3. Similar to the optical receiver 1A according to Modification 1, the optical receiver 1C is equipped with a capacitor 32A instead of capacitor 32. However, in the optical receiver 1C, the capacitor 32A is mounted on a metal substrate 81 instead of the back surface 35b of the carrier substrate 35. In this case, the second metal film 43 of the capacitor 32A is formed integrally with the metal substrate 81. Therefore, when manufacturing the optical receiver 1C, the dielectric layer 41A and the first metal film 42 are formed on the surface 81a of the metal substrate 81, and then the carrier substrate 35 is mounted on the first metal film 42. Even with this configuration, the same effects as the embodiments described above are achieved. Furthermore, in the optical receiver 1C, the step of mounting the capacitor 32A on the metal substrate 81 can be easily incorporated into the manufacturing process of the optical receiver 1C, thus suppressing the complexity of the manufacturing process of the optical receiver 1C.

[0077] <Modification 4> Figure 14 is a cross-sectional view showing an optical receiver 1D according to Modification 4. In the embodiments described above, an example was given in which a plurality of vias 38 are formed on the carrier substrate 35. However, in the optical receiver 1D shown in Figure 14, an example is given in which a pair of side metal films 91 and 92 are formed on the carrier substrate 35A. In other words, in the optical receiver 1D, the carrier substrate 35A has a pair of side metal films 91 and 92 instead of a plurality of vias 38. The pair of side metal films 91 and 92 are formed of a metallic material and are conductive.

[0078] One side metal film 91 is provided on the side surface 35c of the carrier substrate 35A. The side metal film 91 extends from the first conductive film 36 to the second conductive film 37 on the side surface 35c and is connected to the first conductive film 36 and the second conductive film 37. The other side metal film 92 is provided on the side surface 35d of the carrier substrate 35A. The side metal film 92 extends from the first conductive film 36 to the second conductive film 37 on the side surface 35d and is connected to the first conductive film 36 and the second conductive film 37. Therefore, the first conductive film 36 and the second conductive film 37 are electrically connected to each other via the side metal films 91 and 92. The side metal film 91 may be formed to cover the entire surface of the side surface 35c, or to cover a portion of the side surface 35c. Similarly, the side metal film 92 may be formed to cover the entire surface of the side surface 35d, or to cover a portion of the side surface 35d.

[0079] Even in this configuration, the same effects as those of the embodiments described above can be achieved. Furthermore, by configuring the first conductive film 36 and the second conductive film 37 to be connected by side metal films 91 and 92, a configuration for electrically connecting the first conductive film 36 and the second conductive film 37 can be easily realized. The side metal film may be provided on only one of the side surfaces 35c and 35d of the carrier substrate 35A. The side metal film 91 may be configured as a part of the first conductive film 36 or as a part of the second conductive film 37. In this case, the first conductive film 36 or the second conductive film 37 may have an extended portion that extends over the side surface 35c, and this extended portion may be configured as the side metal film 91. Similarly, the side metal film 92 may be configured as a part of the first conductive film 36 or as a part of the second conductive film 37. In this case, the first conductive film 36 or the second conductive film 37 may have an extended portion that extends over the side surface 35d, and this extended portion may be configured as the side metal film 92.

[0080] <Modification 5> Figure 15 shows the optical receiver 1E according to modified example 5. planeThis is a diagram. Figure 16 is a graph showing the simulation results of the relationship between insertion loss (unit: dB) and signal frequency (unit: GHz) in the optical receiver 1E shown in Figure 15. In the optical receiver 1E, the carrier substrate 35B has more vias 38A than the carrier substrate 35 according to the embodiment described above. Figure 15 shows 18 vias 38A, but the number of vias 38A is not limited to the example shown in Figure 15. The number of vias 38A may be other numbers, such as 4 or 8. Each via 38A is arranged at equal intervals in a region that overlaps with the cathode wiring pattern 36b in a plan view, for example. Each via 38A is arranged symmetrically with respect to the anode wiring pattern 36a in direction A2, for example.

[0081] Even when the number of vias 38A is increased in this way, as shown in Figure 16, it can be seen that there is no resonant frequency in the high-frequency band of tens of GHz or 100 GHz. Therefore, even in this configuration, the same effects as the embodiment described above are achieved. Furthermore, as described above, the parasitic capacitance C increases as the number of vias 38A increases. cq and inductance L via Since the resonant frequency is expected to increase, increasing the number of vias 38A will more reliably remove the opaque band caused by resonance from the signal frequency band.

[0082] The optical receiver according to this disclosure is not limited to the embodiments and their respective modifications described above, and various other modifications are possible. For example, the embodiments and their respective modifications described above may be combined with each other depending on the necessary purpose and effect. The configuration of the optical receiver is not limited to the embodiments and their respective modifications described above, and can be changed as appropriate. For example, the first conductive film provided on the carrier may have a configuration other than one in which cathode wiring patterns are provided on both sides of the anode wiring pattern. Multiple vias do not need to be arranged at equal intervals, and may be arranged at unequal intervals. [Explanation of symbols]

[0083] 1, 1A, 1B, 1C, 1D, 1E… Optical receivers 11…Package 12…Side wall 12a, 12b...Side wall part 13...Bottom plate 13a…Bottom surface 14…Bush 15…Optical window 21…Optical axis converter 21a, 21b…Mirror 22...Optical demultiplexer 23... Lens 24…Photodetector 24a…Surface 24b…Back side 24c...side 25…TIA 25a…Surface 25b…Back side 25c... Signal pad 25d…1st bias pad 25e...2nd bias pad 26…Feedthrough 26a... Terminal 27... Ground Layer 28... Conductive film 28a... Anode pad 28b...First cathode pad 28c...Second cathode pad 28d...Third cathode pad 28e...4th cathode pad 28f, 28g, 28j, 28k… Cathode patterns 28h... Anode pattern 29... Beer 31…Career 32,32A…Capacitor 35, 35A, 35B… Carrier board 35a…Surface 35b…Back side 35c,35d…side 36…First conductive film 36a... Anode wiring pattern 36b... Cathode wiring pattern 36c…Part 1 36d…Second part 37…Second conductive film 38,38A… Via 41,41A...Dielectric layer 41a…Surface 41b…Back side 42...first metal film 43…Second metal film 51, 52... Pillar 71, 72, 73… wire 81…Metal substrate 81a... Surface 81b…Reverse side 82...Insulating substrate 82a…Surface 82b…Back side 83…Surface metal film 84…Metal film on the back 85... Beer 91,92…side metal film C c ...capacitance C cq ...parasitic capacitance L via ,L wire ...inductance L…Signal light

Claims

1. A light-receiving element, A carrier substrate on which the aforementioned photodetector is mounted, The dielectric layer on which the carrier substrate is mounted, An insulating substrate on which the dielectric layer is mounted, A base having a conductive main surface that is a reference potential, on which the insulating substrate is mounted, A first conductive film is provided between the light-receiving element and the carrier substrate, having a first wiring pattern electrically connected to the cathode electrode of the light-receiving element, A second conductive film is provided between the carrier substrate and the dielectric layer, and has parasitic capacitance between itself and the first wiring pattern. A conductor provided on the carrier substrate and electrically connected to the first wiring pattern and the second conductive film, A transimpedance amplifier having a first pad electrically connected to the first wiring pattern via a wire, and a second pad electrically connected to the anode electrode of the photodetector, Equipped with, The capacitance between the second conductive film and the main surface of the base is greater than the parasitic capacitance. The inductance of the conductor is smaller than the inductance of the wire. The insulating substrate has a surface facing the dielectric layer and a back surface facing the main surface of the base, The back surface of the insulating substrate is provided with a back metal film that is electrically connected to the main surface of the base. The surface of the insulating substrate is provided with a surface metal film that is electrically connected to the back metal film via vias that penetrate the interior of the insulating substrate. Optical receiver.

2. The first conductive film is A second wiring pattern electrically connected to the anode electrode of the light-receiving element, The light-receiving element further comprises a third wiring pattern electrically connected to the cathode electrode of the light-receiving element, The first wiring pattern and the third wiring pattern are arranged on either side of the second wiring pattern, respectively. The optical receiver according to claim 1, wherein the conductor is electrically connected to at least one of the first wiring pattern and the third wiring pattern and the second conductive film.

3. The dielectric layer has a surface facing the second conductive film and a back surface facing the surface of the insulating substrate, A first metal film electrically connected to the second conductive film is provided on the surface of the dielectric layer. The optical receiver according to claim 1, wherein a second metal film is provided on the back surface of the dielectric layer, which is electrically connected to the surface metal film of the insulating substrate.

4. The optical receiver according to claim 3, wherein the dielectric layer comprises at least one of silicon nitride, silicon oxide, and silicon nitride oxide.

5. The optical receiver according to claim 1, wherein the conductor extends between the first wiring pattern and the second conductive film so as to penetrate the carrier substrate and has vias connected to the first wiring pattern and the second conductive film.

6. The conductor has a plurality of the aforementioned euros, The optical receiver according to claim 5, wherein the plurality of vias are arranged at positions spaced apart from each other in a plan view of the carrier substrate.

7. The carrier substrate has a surface on which the first conductive film is provided, a back surface on which the second conductive film is provided, and a side surface connecting the surface and the back surface. The conductor has a side conductive film provided on the side surface, The optical receiver according to claim 1, wherein the side conductive film extends from the first wiring pattern to the second conductive film on the side surface and is connected to the first wiring pattern and the second conductive film.

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