Memory devices and their program operation

Abstract

To provide a memory device and an operation method thereof.SOLUTION: In some embodiments, a memory device includes an array of memory cells and a peripheral circuit coupled to the array of the memory cells. At least one of the memory cells is set to one of 2N levels corresponding to an N-bit data element, where N is an integer greater than 1. The peripheral circuit is configured to: apply a first program voltage to a selected row of the memory cells; execute a first verification of the selected row of the memory cells in the final level of the 2N levels after applying the first program voltage; execute a first VFC based on a result of the first verification and a first verify failure count (VFC) criterion; apply a second program voltage higher than the first program voltage to the selected row of the memory cells after executing the first VFC; and execute a second VFC based on the result of the first verification and a second VFC criterion different from the first VFC criterion, during a period when the second program voltage is applied.SELECTED DRAWING: Figure 8B

Description

[Technical Field]

[0001] Cross-reference of related applications This application claims the benefit of priority of U.S. Provisional Application No. 63 / 436,441, filed on 30 December 2022, which is incorporated herein by reference in its entirety.

[0002] This disclosure relates to a memory device and a method for operating the same. [Background technology]

[0003] Flash memory is a low-cost, high-density, non-volatile solid-state storage medium that can be electrically erased and reprogrammed. Flash memory includes NOR flash memory and NAND flash memory. Various operations, such as reading, programming (writing), and erasing, can be performed by flash memory. In the case of NAND flash memory, erasing operations can be performed at the block level, while programming or reading operations can be performed at the page level. [Overview of the project] [Means for solving the problem]

[0004] In one embodiment, the memory device includes an array of memory cells and peripheral circuits coupled to the array of memory cells. At least one of the memory cells corresponds to two elements of N-bit data. N It is set to one of the levels, where N is an integer greater than 1. The peripheral circuit applies a first program voltage to the selected row of memory cells, and after applying the first program voltage, 2 NThe peripheral circuit is configured to perform a first verification of the selected row of memory cells at the final level of the individual levels. The peripheral circuit is also configured to perform a first verify fail count (VFC) based on the results of the first verification and a first verify fail count (VFC) criterion. After performing the first VFC, the peripheral circuit is further configured to apply a second program voltage higher than the first program voltage to the selected row of memory cells and to perform a second VFC based on a second VFC criterion different from the results of the first verification and the first VFC criterion during the period in which the second program voltage is applied.

[0005] In some implementations, the peripheral circuitry is configured to apply a second program voltage in response to the result of the first verification not meeting the first VFC criterion.

[0006] In some implementations, peripheral circuits are further configured to perform a second verification of selected rows of memory cells at the final level in response to the result of the first verification not meeting the second VFC criterion, and to perform a third VFC based on the result of the second verification and the third VFC criterion.

[0007] In some implementations, peripheral circuits are further configured to skip the second verification and the third VFC in response to the result of the first verification meeting the second VFC criterion.

[0008] In some implementations, the third VFC standard is the same as the first VFC standard.

[0009] In some implementations, the memory device further includes word lines coupled to each row of memory cells. In some implementations, to perform a first verification, the peripheral circuitry includes a word line driver configured to apply a verify voltage to the selected word lines coupled to the selected rows of memory cells, the verify voltage being 2 N It corresponds to the final level among the individual levels.

[0010] In some implementations, to perform the first VFC, the peripheral circuitry includes a page buffer configured to obtain the number of failed memory cells in the selected row of memory cells that do not pass the first verification, and control logic configured to compare the number of failed memory cells against the first VFC criterion.

[0011] In some implementations, the second VFC standard is less stringent than the first VFC standard.

[0012] In another embodiment, the system includes a memory device configured to store data and a memory controller configured to be coupled to the memory device and to control the memory device. The memory device includes an array of memory cells and peripheral circuits coupled to the array of memory cells. At least one of the memory cells corresponds to two elements of N-bit data. N It is set to one of the levels, where N is an integer greater than 1. The peripheral circuit applies a first program voltage to the selected row of memory cells, and after applying the first program voltage, 2 N The peripheral circuit is configured to perform a first verification of the selected row of memory cells at the final level of the individual levels. The peripheral circuit is also configured to perform a first VFC based on the results of the first verification and a first VFC criterion. In response to the results of the first verification not meeting the first VFC criterion, the peripheral circuit is further configured to apply a second program voltage higher than the first program voltage to the selected row of memory cells after performing the first VFC, and to perform a second VFC based on a second VFC criterion different from the results of the first verification and the first VFC criterion during the period in which the second program voltage is applied.

[0013] In some implementations, peripheral circuits are further configured to perform a second verification of selected rows of memory cells at the final level in response to the result of the first verification not meeting the second VFC criterion, and to perform a third VFC based on the result of the second verification and the third VFC criterion.

[0014] In some implementations, the peripheral circuit is further configured to skip the second verification and the third VFC in response to the result of the first verification meeting the second VFC criterion.

[0015] In some implementations, the third VFC criterion is the same as the first VFC criterion.

[0016] In some implementations, to perform the first VFC, the peripheral circuit includes a page buffer configured to obtain the number of failed memory cells in the selected row of memory cells that fail the first verification, and control logic configured to compare the number of failed memory cells with the first VFC criterion.

[0017] In some implementations, the second VFC criterion is not more stringent than the first VFC criterion.

[0018] In yet another aspect, a method for programming a memory device is provided. The memory device includes rows of memory cells. At least one of the memory cells is set to one of two levels corresponding to an element of N-bit data, where N is an integer greater than 1. A first program voltage is applied to the selected row of the memory cells. After applying the first program voltage, a first verification of the selected row is performed at the final level of the two levels. A first VFC is performed based on the result of the first verification and the first VFC criterion. After performing the first VFC, a second program voltage higher than the first program voltage is applied to the selected row. A second VFC is performed based on a second VFC criterion different from the result of the first verification and the first VFC criterion during the period when the second program voltage is being applied. N In some implementations, a second program voltage is applied in response to the result of the first verification not meeting the first VFC criterion. N After applying the first program voltage, a first verification of the selected row is performed at the final level of the two levels. A first VFC is performed based on the result of the first verification and the first VFC criterion. After performing the first VFC, a second program voltage higher than the first program voltage is applied to the selected row. A second VFC is performed based on a second VFC criterion different from the result of the first verification and the first VFC criterion during the period when the second program voltage is being applied.

[0019] In some implementations, a second program voltage is applied in response to the result of the first verification not meeting the first VFC criterion.

[0020] In some implementations, in response to the result of the first verification not meeting the second VFC criterion, a second verification of the selected row is performed at the final level, and a third VFC is performed based on the result of the second verification and the third VFC criterion.

[0021] In some implementations, the second verification and the third VFC are skipped in response to the result of the first verification meeting the second VFC criterion.

[0022] In some implementations, the third VFC criterion is the same as the first VFC criterion.

[0023] In some implementations, to perform the first verification, the verification voltage corresponding to the final level among 2 N levels is applied to the selected row.

[0024] In some implementations, to perform the first VFC, the number of failed memory cells in the selected row that fail the first verification is obtained, and the number of failed memory cells is compared against the first VFC criterion.

[0025] In some implementations, the second VFC criterion is not more stringent than the first VFC criterion.

[0026] The accompanying drawings, which are incorporated herein and form a part of this specification, illustrate embodiments of the present disclosure and, together with the description, further serve to explain the principles of the present disclosure and to enable one skilled in the art to make and use the present disclosure.

Brief Description of the Drawings

[0027] [Figure 1] FIG. is a schematic diagram of a memory device including a peripheral circuit according to some embodiments of the present disclosure. [Figure 2] FIG. is a side cross-sectional view of a memory cell array including a NAND memory string according to some embodiments of the present disclosure. [Figure 3]This is a block diagram of a memory device including a memory cell array and peripheral circuits according to some aspects of the present disclosure. [Figure 4] This figure shows the threshold voltage distribution of a memory cell during programmed operation according to several aspects of this disclosure. [Figure 5A] This figure shows the waveform of the word line voltage applied to the selected word line during program operation according to some aspects of the present disclosure. [Figure 5B] This figure shows the waveform of the word line voltage applied to the selected word line during program operation according to some aspects of the present disclosure. [Figure 6A] This figure shows the standard final level verification failure count (VFC) method used in program operation. [Figure 6B] This figure shows the standard final level verification failure count (VFC) method used in program operation. [Figure 7A] This figure shows the predicted final level VFC scheme in program operation. [Figure 7B] This figure shows the predicted final level VFC scheme in program operation. [Figure 8A] This figure shows an adaptive final level VFC scheme in program operation according to several aspects of this disclosure. [Figure 8B] This figure shows an adaptive final level VFC scheme in program operation according to several aspects of this disclosure. [Figure 8C] This figure shows an adaptive final level VFC scheme in program operation according to several aspects of this disclosure. [Figure 9] This figure shows the threshold voltage distribution of the memory cell with respect to the VFC during programmed operation according to some aspects of this disclosure. [Figure 10] This is a detailed block diagram of the peripheral circuitry in Figure 3, according to several aspects of the present disclosure. [Figure 11] This is a flowchart of a method for programming a memory device according to some aspects of the present disclosure. [Figure 12] A block diagram of a system having a memory device, according to some aspects of the present disclosure. [Figure 13A] A diagram of a memory card having a memory device, according to some aspects of the present disclosure. [Figure 13B] A diagram of a solid state drive (SSD) having a memory device, according to some aspects of the present disclosure.

MODE FOR CARRYING OUT THE INVENTION

[0028] The present disclosure will be described with reference to the accompanying drawings.

[0029] Generally, terms may be understood, at least in part, from their usage in context. For example, the term "one or more" as used herein may be used, at least in part, depending on the context, to represent any feature, structure, or property in a singular sense, or to represent a combination of features, structures, or properties in a plural sense. Similarly, terms such as "a", "an", or "the" may also, in this case, be understood, at least in part, depending on the context, to convey a singular use or a plural use. Additionally, the term "based on" may be understood as not necessarily intended to convey an exclusive set of factors, and instead, in this case as well, depending on the context, it may be allowed that the presence of additional factors is not necessarily clearly indicated.

[0030] Memory devices, such as NAND flash memory devices, can store information exceeding a single bit in each memory cell having multiple states in order to increase the storage capacity and reduce the cost per bit. In a program operation, data is at a program time (t PROGTo conserve resources, programs may be initially programmed (written) into single-level cell (SLC) blocks and later combined into xLC blocks such as multi-level cell (MLC), triple-level cell (TLC), and quad-level cell (QLC) blocks. The programming operation of a NAND flash memory device involves several program and verify cycles and can terminate after either the program or verify cycle, depending on the specific final-level VFC scheme employed by the program operation. Therefore, the program time of the program operation may be affected by the final-level VFC scheme, which determines when the program operation terminates. Some final-level VFC schemes (also called standard final-level VFC schemes) always execute the final-level VFC after the verify cycle to terminate the program operation. To save program time, some final-level VFC schemes (also called predictive final-level VFC schemes) may skip the final verify cycle after a program cycle and terminate the program operation by performing the final-level VFC within a program cycle using a predictive VFC criterion that is less stringent than the standard VFC criterion (e.g., has a larger fail-bit threshold) that predicts whether the next program cycle is the final program cycle of the program operation.

[0031] On the other hand, there is a limit to the maximum number of fail bits (VFC) that can be counted by the peripheral circuitry of the memory device. Due to variability in VFC capability and / or word line variability, the predicted final level VFC scheme can skip the final verify cycle, thereby shortening the program time only if its VFC capability is sufficient to cover the memory cells that passed the last verification. Otherwise, the program operation will require extra program / verify cycles, which effectively increases the program time.

[0032] To address one or more of the aforementioned problems, this disclosure introduces an adaptive final-level VFC scheme that can adaptively switch between a standard final-level VFC scheme and a predictive final-level VFC scheme based on the VFC capability of the peripheral circuitry. If the VFC capability is sufficient to cover memory cells that have passed the last verification, the adaptive final-level VFC scheme can skip the final verify cycle after the program cycle and terminate the program operation by performing the final-level VFC within the program cycle using a predictive VFC criterion. If the VFC capability is not sufficient to cover memory cells that have passed the last verification, the adaptive final-level VFC scheme can terminate the program operation by performing the final-level VFC after the verify cycle, thereby avoiding introducing extra program / verify cycles into the program operation. In some implementations, the final-level VFC is performed after the verify cycle using a standard VFC criterion and within the program cycle using a predictive VFC criterion, so that the program operation can terminate either after the verify cycle or after the program cycle. That is, the timing of the program operation termination can be adaptive to the VFC capability and variability between word lines. As a result, the average program time across different word lines using the adaptive final-level VFC method disclosed herein may be shorter compared to either the standard final-level VFC method or the predictive final-level VFC method.

[0033] Figure 1 shows a schematic circuit diagram of a memory device 100 including peripheral circuits according to several embodiments of the present disclosure. The memory device 100 may include a memory cell array 101 and peripheral circuits 102 coupled to the memory cell array 101. The memory cell array 101 may be a NAND flash memory cell array in which memory cells 106 are provided, each in the form of an array of NAND memory strings 108, each extending vertically over a substrate (not shown). In some implementations, each NAND memory string 108 includes a plurality of memory cells 106 coupled in series and stacked vertically. Each memory cell 106 may hold a continuous analog value, such as voltage or charge, which depends on the number of electrons trapped within the region of the memory cell 106. Each memory cell 106 may be either a floating-gate type memory cell including a floating-gate transistor, or a charge-trap type memory cell including a charge-trap transistor.

[0034] In some implementations, each memory cell 106 is an SLC having two possible levels (memory states) and therefore capable of storing 1 bit of data. For example, the first level "0" can correspond to a first range of threshold voltage, and the second level "1" can correspond to a second range of threshold voltage. In some implementations, each memory cell 106 is an xLC having more than four levels and capable of storing more than one bit of data. For example, an xLC may store 2 bits per cell (MLC), 3 bits per cell (TLC), or 4 bits per cell (QLC). Each xLC has a possible nominal storage value (i.e., 2 bits of N-bit data). N It can be programmed to exhibit a range (corresponding to an element). In some implementations, at least one of the memory cells 106 corresponds to 2 elements of N-bit data. N It is set to one of the individual levels, where N is an integer greater than 1.

[0035] As shown in Figure 1, each NAND memory string 108 may also include a source select gate (SSG) transistor 110 at its source end and a drain select gate (DSG) transistor 112 at its drain end. The SSG transistor 110 and DSG transistor 112 may be configured to activate selected NAND memory strings 108 (array columns) during read and program operations. In some implementations, the sources of NAND memory strings 108 within the same block 104 are connected through the same source line (SL) 114, for example, a common SL. In other words, all NAND memory strings 108 within the same block 104 have an array common source (ACS), according to some implementations. The drain of each NAND memory string 108 is connected, according to some implementations, to a respective bit line 116 from which data can be read or written via an output bus (not shown). In some implementations, each NAND memory string 108 is configured to be selected or deselected by applying a selection voltage or deselection voltage to the gate of each DSG transistor 112 through one or more DSG lines 113, and / or by applying a selection voltage or deselection voltage to the gate of each SSG transistor 110 through one or more SSG lines 115.

[0036] As shown in Figure 1, a NAND memory string 108 can be organized into multiple blocks 104, each of which may have a common source line 114, for example, coupled to an ACS. In some implementations, each block 104 is a basic data unit for erase operations, i.e., all memory cells 106 on the same block 104 are erased simultaneously. To erase the memory cells 106 in a selected block 104, the source lines 114 coupled to the selected block 104 and to non-selected blocks 104 in the same plane as the selected block 104 may be biased with an erase voltage (Vers), such as a positive high bias voltage (e.g., 20V or higher). Memory cells 106 of adjacent NAND memory strings 108 may be coupled through word lines 118 that select which rows of the memory cells 106 are acted upon by read and program operations. In some implementations, each word line 118 is coupled to a page 120 of the memory cell 106, which is a basic data unit for read and program operations. The size of one page 120 in bits can relate to the number of NAND memory strings 108 joined by word lines 118 within one block 104. Each word line 118 may include multiple control gates (gate electrodes) in each memory cell 106 within each page 120, and gate lines that join the control gates.

[0037] As shown in Figure 1, the memory cell array 101 can include an array of memory cells 106 in multiple rows and multiple columns within each block 104. According to some implementations, one row of memory cell 106 corresponds to one or more pages 120, and one column of memory cell corresponds to one NAND memory string 108. Multiple rows of memory cell 106 may each be coupled to a word line 118, and multiple columns of memory cell 106 may each be coupled to a bit line 116. Peripheral circuits 102 may be coupled to the memory cell array 101 through the bit line 116 and the word line 118.

[0038] Figure 2 shows a cross-sectional side view of a memory cell array 101 including a NAND memory string 108 according to several embodiments of the present disclosure. As shown in Figure 2, the NAND memory string 108 can extend vertically over the substrate 202 through the memory stack 204. The substrate 202 may include silicon (e.g., single-crystal silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), germanium-on-insulator (GOI), or any other suitable material.

[0039] The memory stack 204 may include interleaved gate conductive layers 206 and intergate dielectric layers 208. The number of pairs of gate conductive layers 206 and intergate dielectric layers 208 in the memory stack 204 can determine the number of memory cells 106 in the memory cell array 101. The gate conductive layers 206 may include, but are not limited to, conductive materials such as tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof. In some implementations, each gate conductive layer 206 includes a metal layer such as a tungsten layer. In some implementations, each gate conductive layer 206 includes a doped polysilicon layer. Each gate conductive layer 206 may include a control gate surrounding a memory cell 106, the gate of a DSG transistor 112, or the gate of an SSG transistor 110, and may extend laterally as a DSG line 113 at the top of the memory stack 204, an SSG line 115 at the bottom of the memory stack 204, or a word line 118 between the DSG line 113 and the SSG line 115.

[0040] As shown in Figure 2, the NAND memory string 108 includes a channel structure that extends vertically through the memory stack 204. In some implementations, the channel structure includes channel holes filled with semiconductor material (e.g., as a semiconductor channel) and dielectric material (e.g., as a memory film). It is understood that additional components of the memory cell array 101 may be formed, including, but are not limited to, gate line slits / source contacts, local contacts, interconnection layers, etc., although these are not shown in Figure 2.

[0041] Referring again to Figure 1, the peripheral circuit 102 may be coupled to the memory cell array 101 through bit lines 116, word lines 118, source lines 114, SSG lines 115, and DSG lines 113. The peripheral circuit 102 may include any suitable analog, digital, and mixed-signal circuits to facilitate the operation of the memory cell array 101 by applying and sensing voltage and / or current signals to and from each selected memory cell 106 through bit lines 116, word lines 118, source lines 114, SSG lines 115, and DSG lines 113. The peripheral circuit 102 may include various types of peripheral circuits formed using metal-oxide-semiconductor (MOS) technology. For example, Figure 3 shows some exemplary peripheral circuits including a page buffer / sense amplifier 304, a column decoder / bit line driver 306, a row decoder / word line driver 308, a voltage generator 310, control logic 312, registers 314, an interface (I / F) 316, and a data bus 318. In some examples, it is understood that additional peripheral circuits not shown in Figure 3 may also be included.

[0042] The page buffer / sense amplifier 304 may be configured to sense (read) and program (write) data to and from the memory cell array 101 according to control signals from the control logic 312. In one example, the page buffer / sense amplifier 304 may store one page of program data (write data, referred to herein as a “data page”) to be programmed into one page 120 of the memory cell array 101. In another example, the page buffer / sense amplifier 304 may verify the programmed selected memory cell 106 in each program / verify cycle of the program operation to ensure that data is correctly programmed into the memory cell 106 coupled to the selected word line 118. In yet another example, the page buffer / sense amplifier 304 may also sense a low-power signal from the bit line 116 representing the data bits stored in the memory cell 106 and amplify small voltage fluctuations to a recognizable logic level during the read operation. As will be explained in detail below, in program operation, the page buffer / sense amplifier 304 may include a module for recording and counting the number of memory cells 106 that do not pass verification, i.e., the number of failed memory cells (also called fail bits), during the program / verify cycle.

[0043] The column decoder / bit line driver 306 may be controlled by control logic 312 and configured to select one or more NAND memory strings 108 by applying bit line voltages generated from a voltage generator 310. The row decoder / word line driver 308 may be controlled by control logic 312 and a select / deselect block 104 of the memory cell array 101 and configured to select / deselect the word line 118 of block 104. The row decoder / word line driver 308 may be further configured to drive the word line 118 using the word line voltages generated from the voltage generator 310. In some implementations, the row decoder / word line driver 308 can also select / deselect and drive the SSG line 115 and DSG line 113 as well. The voltage generator 310 may be controlled by control logic 312 and configured to generate word line voltages (e.g., read voltage, program voltage, channel pass voltage, local voltage, verify voltage, etc.), bit line voltages, and source line voltages to be supplied to the memory cell array 101.

[0044] The control logic 312 may be coupled to each of the peripheral circuits described above and configured to control the operation of each peripheral circuit. In programmed operation, as described below in detail and in accordance with the scope of this disclosure, the control logic 312 may include modules for performing VFC based on the number of failed memory cells and VFC criteria that are adaptive to their VFC capabilities.

[0045] Register 314 may be coupled to the control logic 312 and may include a status register, a command register, and an address register for storing status information, command operation codes (opcodes), and command addresses for controlling the operation of each peripheral circuit. Interface 316 may be coupled to the control logic 312 and can function as a control buffer for buffering and relaying control commands received from a memory controller (not shown) and / or a host (not shown) to the control logic 312, and for buffering and relaying status information received from the control logic 312 to the memory controller and / or host. Interface 316 may also be coupled to the column decoder / bit line driver 306 via the data bus 318 and can function as a data input / output (I / O) interface and data buffer for buffering and relaying data to and from the memory cell array 101.

[0046] Figure 4 shows the threshold voltage distribution of memory cells during programmed operation in some embodiments of this disclosure. In some implementations, each memory cell 106 corresponds to 2 elements of N-bit data. N It is possible to set to one of the following levels, where N is an integer greater than 1 (for example, N=2 for MLC, N=3 for TLC, N=4 for QLC, etc.). Each level is 2 of the memory cells 106 NIt can correspond to one of the following threshold voltage (Vth) ranges. Taking a TLC with N=3, for example, as shown in Figure 4, the memory cell 106 may be programmed to one of eight levels (L0-L7), including one level (L0) for the erased state and seven levels (L1-L7) for the programmed state. Each level may correspond to the respective threshold voltage (Vth) range of the memory cell 106. For example, the level corresponding to the lowest threshold voltage range (the leftmost threshold voltage distribution in Figure 4) may be considered level 0 (L0), the level corresponding to the second lowest threshold voltage range (the second threshold voltage distribution from the left in Figure 4) may be considered level 1 (L1), and so on up to level 7 (L7), which corresponds to the highest threshold voltage range (the rightmost threshold voltage distribution in Figure 4). N The final level among these levels is also referred to herein as Level K (Lk), such as Level 3 (L3) for MLC, Level 7 (L7) for TCL, and Level 15 (L15) for QLC, and Level (2 N -1) refers to, where K=2 N It is -1. On the other hand, each level is 2 of the N-bit data that will be stored in the selected memory cell 106. N It can correspond to one of the elements. In some implementations, 2 of N-bit data N Each element is based on Gray code. N It may be mapped to individual levels. Gray code (also called alternating binary code (RBC) or alternating binary (RB)) is a binary number system ordering such that two consecutive values ​​differ by only one bit (binary digit).

[0047] In addition to the page buffer / sense amplifier 304 providing each selected memory cell 106 with corresponding elements of N-bit data to perform a program operation, the row decoder / word line driver 308 may be configured to apply a program voltage and a verify voltage to the selected word line 118 coupled to the selected row of the memory cell 106 in one or more program / verify cycles to raise the threshold voltage of each selected memory cell 106 to a desired level (within a desired range of threshold voltages) based on the corresponding elements of N-bit data. For example, Figures 5A and 5B show waveforms of word line voltages applied to the selected word line in a program operation according to some aspects of the present disclosure.

[0048] As shown in Figure 5A, the program operation includes one or more program / verify cycles (also called loops) 502. As shown in Figure 5B, within each program / verify cycle 502, the row decoder / word line driver 308 may be configured to apply a program voltage (Vpgm) on the selected word line 118 to the selected row of the memory cell 106 in the program cycle 504, and to continuously apply one or more verify voltages (Vvfy) with incremental changes in voltage level to verify the selected row of the memory cell 106 in the verify cycle 506. That is, the peripheral circuit 102 can apply the program voltage in the program cycle 504 and then perform verification of the selected row of the memory cell 106 at one or more levels in the verify cycle 506. The number of verify voltages applied in the verify cycle 506 depends on the level being programmed by a particular program / verify cycle 502, according to some implementations. Taking a TLC with N=3, for example, during the program / verify cycle 502 corresponding to level 6 (L6), two verify voltages (L6 Vvfy and L7 Vvfy) may be applied by the peripheral circuit 102 to continuously verify the selected memory cell 106 at levels 6 (L6) and 7 (L7). During the final level, i.e., the program / verify cycle 502 corresponding to level 7 (L7), only one verify voltage (L7 Vvfy) may be applied by the peripheral circuit 102 to verify the selected memory cell 106 at level 7 (L7). As a result, at the end of the program operation, the selected memory cell 106 is determined based on the corresponding N bits of data to be stored in the selected memory cell 106. N It can be programmed at one of the individual levels.

[0049] Figures 6A and 6B illustrate a standard final-level VFC scheme in program operation. As shown in Figures 6A and 6B, the word line driver 308 of the peripheral circuit 102 applies the nth program voltage (Vpgm_n) onto the selected word line 118, followed by two verifications (L(k-1) vfy and Lk vfy) corresponding to the last two levels (L(k-1) and L(k)). Then, the word line driver 308 applies the (N+1)th program voltage (Vpgm_n+1), which is higher than the nth program voltage, onto the selected word line 118. For example, during the period in which the (N+1)th program voltage is applied, the page buffer 304 and control logic 312 of the peripheral circuit 102 execute the second-to-last level VFC (L(k-1) vfc) in parallel with the (N+1)th program voltage. The second-to-last level VFC (shown as a filled-in box) must meet the standard VFC criteria, for example, in response to the second-to-last level verification (L(k-1) vfy) not passing and the number of selected memory cells 106 that do not exceed the standard fail bit threshold, only the final level verification (Lk vfy) should be performed after the (N+1)th program voltage.

[0050] As shown in Figures 6A and 6B, the final level VFC (Lk vfc) is performed after the final level verification and before the next (N+2) program voltage (Vpgm_n+2) is applied, rather than waiting for the next (N+2) program voltage (Vpgm_n+2) to be applied. As shown in Figure 6A, the program operation is terminated without requiring the application of the (N+2) program voltage in response to the final level VFC (shown as a filled box) meeting the standard VFC criteria, for example, if the number of selected memory cells 106 that do not pass the final level verification (Lk vfy) does not exceed the standard fail bit threshold, the final level verification is passed. In contrast, as shown in Figure 6B, if the final level VFC (shown as a dotted box) does not meet the standard VFC criteria, for example, if the number of selected memory cells 106 that do not pass the final level verification (Lk vfy) exceeds the standard fail bit threshold, the final level verification fails, and the program operation must continue by applying a (N+2) program voltage (Vpgm_n+2) that is higher than the (N+1) program voltage. In this case as well, after applying the (N+2) program voltage, another final level verification (Lk vfy) must be performed, followed by another final level VFC (Lk vfc) to determine whether the final level VFC here meets the standard VFC criteria. As shown in Figure 6B, if the second final level VFC (shown as a filled box) meets the standard VFC criteria, the second final level verification passes, and the program operation terminates without requiring the application of a (N+3) program voltage. Otherwise, the (N+3)th program voltage may need to be run again along with the third final level verification and the third final level VFC (not shown), or the program operation may be aborted as a failure.

[0051] Figures 7A and 7B illustrate the predicted final level VFC scheme in program operation. As shown in Figures 7A and 7B, the word line driver 308 of the peripheral circuit 102 applies the nth program voltage (Vpgm_n) onto the selected word line 118, followed by two verifications (L(k-1) vfy and Lk vfy) corresponding to the last two levels (L(k-1) and L(k)). Then, the word line driver 308 applies the (N+1)th program voltage (Vpgm_n+1), which is higher than the nth program voltage, onto the selected word line 118. For example, during the period in which the (N+1)th program voltage is applied, the page buffer 304 and control logic 312 of the peripheral circuit 102 execute the second-to-last level VFC (L(k-1) vfc) in parallel with the (N+1)th program voltage. The second-to-last level VFC (shown as a filled-in box) must meet the standard VFC criteria, for example, in response to the second-to-last level verification (L(k-1) vfy) not passing and the number of selected memory cells 106 that do not exceed the standard fail bit threshold, only the final level verification (Lk vfy) should be performed after the (N+1)th program voltage.

[0052] Unlike the standard final level VFC method in Figures 6A and 6B, where the final level VFC (Lk vfc) is performed using the same standard VFC criterion before the next (N+2) program voltage is applied, in the predictive final level VFC method shown in Figures 7A and 7B, for example, during the period in which the (N+2) program voltage is applied, the predictive final level VFC (Lk vfc_p) is performed in parallel with the (N+2) program voltage (Vpgm_n+2), which is higher than the (N+1) program voltage. Furthermore, since a higher program voltage (Vpgm_n+2) that can be drawn is applied after the first final level verification, it is reasonable to assume that more selected memory cells 106 have passed the final level verification. Therefore, the predicted final level VFC (Lk vfc_p) is performed using a less stringent predicted VFC criterion than the standard VFC criterion (used, for example, by the second-to-last level VFC), for example, with a larger fail-bit threshold to pass the final level VFC, making it easier for the final level VFC to meet the predicted VFC criterion.

[0053] As shown in Figure 7A, in response to the final level VFC (shown as a filled box) meeting the predicted VFC criteria, for example, the number of selected memory cells 106 that do not pass the final level verification (Lk vfy) does not exceed a larger fail bit threshold, the program operation ends after the final level verification is passed and the (N+2)th program voltage is applied without requiring a second final level verification to be performed, as shown in Figure 6B. In other words, compared to the standard final level VFC method, the predicted final level VFC method may skip the second final level verification and the second final level VFC.

[0054] However, as shown in Figure 7B, the final level verification fails in response to the final level VFC (shown as a dotted box) not meeting the predicted VFC criteria, for example, if the number of selected memory cells 106 that do not pass the final level verification (Lk vfy) still exceeds a larger fail bit threshold. In this case, the program operation must continue by performing another final level verification (Lk vfy) and applying a (N+3) program voltage (Vpgm_n+3) that is higher than the (N+2) program voltage. In this case as well, after applying the (N+3) program voltage, another predicted final level VFC (Lk vfc_p) must be performed in parallel with applying the (N+3) program voltage to determine whether the final level VFC here meets the predicted VFC criteria. As shown in Figure 7B, the second final level verification passes in response to the second final level VFC (shown as a filled box) meeting the predicted VFC criteria, and the program operation terminates without requiring the third final level verification to be performed. Otherwise, the third final level verification, the third predicted final level VFC, and the (N+4)th program voltage may need to be executed again (not shown), or the program operation may be aborted as a failure.

[0055] It is understood that the final level VFC may not meet the predicted VFC criteria as shown in Figure 7B due to various reasons, such as the VFC capability of the peripheral circuit 102 being insufficient to cover the relaxed predicted VFC criteria (e.g., too many memory cells 106 to be counted), and / or variations between word lines (e.g., causing more fail bits in some rows of memory cells 106). Therefore, the predicted final level VFC scheme may shorten program execution time in some situations (e.g., comparing Figure 7A with Figure 6B), but may lengthen program execution time in some other situations. Furthermore, also due to variations between word lines, it is difficult to find the optimal predicted VFC criteria for programming different rows of memory cells 106.

[0056] To combine the advantages of both the standard final level VFC scheme and the predictive final level VFC scheme described above, consistent with the scope of this disclosure, Figures 8A–8C illustrate an adaptive final level VFC scheme in program operation according to several aspects of this disclosure. To implement the adaptive final level VFC scheme, for example, Figure 10 shows a detailed block diagram of the peripheral circuitry 102 in Figure 3, including control logic 312, a page buffer 304, and a word line driver 308, according to several aspects of this disclosure.

[0057] As shown in Figures 3 and 10, in some implementations, peripheral circuits 102, including control logic 312, row decoder / word line driver 308, voltage generator 310, page buffer / sense amplifier 304, register 314, and any other preferred components (e.g., column decoder / bit line driver 306), work together to perform programmed operations in selected memory cells 106 in the memory cell array 101 coupled to selected word line 118. To perform programmed operations, the page buffer 304 may include counters 1004 and latches 1006, along with any other preferred components not shown in Figure 10. The counters 1004 and latches 1006 may be digital circuits, analog circuits, and / or mixed-signal circuits, as will be described in more detail below. To execute programmed operations, the control logic 312 may include a program / verify controller 1008 and a VFC controller 1010, along with any other suitable components not shown in Figure 10, such as a processor (e.g., a microcontroller unit (MCU)) and memory (e.g., random access memory (RAM)). Each of the program / verify controller 1008 and VFC controller 1010 may be implemented as a firmware module stored in RAM and executed by the MCU. Each of the program / verify controller 1008 and VFC controller 1010 may also be implemented as an application-specific integrated circuit (ASIC) including digital circuits, analog circuits, and / or mixed-signal circuits.

[0058] To execute the program operation, the peripheral circuit 102 may be configured to apply a program voltage to the row of selected memory cells 106 coupled to the selected word line 118, and after applying the program voltage, to perform verification of the selected row of memory cells at various levels. In some implementations, as shown in Figure 10, the program / verify controller 1008 of the control logic 312 sends commands to the voltage generator 310 to control the voltage generator 310 to generate a series of program voltages and provide those program voltages to the word line driver 308. The voltage levels of the program voltages can be stored in a register 314 and retrieved by the control logic 312. The control logic 312 can also send commands to the word line driver 308 to control the word line driver 308 to apply the program voltage to the selected word line 118. In some implementations, the program / verify controller 1008 of the control logic 312 sends commands to the voltage generator 310 to control the voltage generator 310 to generate a series of verify voltages and provide those verify voltages to the word line driver 308. The voltage level of the verify voltage can correspond to a preferred level for setting the selection memory cell 106. The control logic 312 can also send commands to the word line driver 308 to control the word line driver 308 to apply one or more verify voltages to the selection word line 118 after applying each program voltage to the selection word line 118 to perform verification.

[0059] In some implementations, as shown in Figure 10, the program / verify controller 1008 of the control logic 312 also sends a command to the page buffer / sense amplifier 304 to check whether the threshold voltage of each programmed select memory cell 106 has reached the verify voltage after the word line driver 308 has applied the verify voltage. For example, the page buffer / sense amplifier 304 may determine whether the threshold voltage of each programmed select memory cell 106 has reached a certain voltage by detecting the current flow through each bit line 116 coupled to the programmed select memory cell 106, i.e., the voltage, which indicates whether it is greater than or equal to the threshold voltage for turning on each programmed select memory cell 106. That is, the page buffer / sense amplifier 304 may be configured to continuously check whether the threshold voltage of each programmed select memory cell 106 has reached the verify voltage after the word line driver 308 has applied the verify voltage.

[0060] As shown in Figures 8A to 8C, for example, a word line driver 308 of peripheral circuit 102 may apply an Nth program voltage (Vpgm_n), such as a voltage pulse signal, to the selected row of memory cell 106 via the selection word line 118. The Nth program voltage may be applied to the control gate of each selected memory cell 106 to program the selected memory cell 106. After applying the Nth program voltage, the peripheral circuit 102 may perform two verifications of the selected row of memory cell 106 (L(k-1) vfy and Lk vfy) by applying two verify voltages corresponding to the last two levels (L(k-1) and L(k)), such as two voltage pulse signals, sequentially to the selection word line 118 by the word line driver 308. A verify voltage may be applied to the control gate of each selected memory cell 106 to compare the threshold voltage of each programmed selected memory cell 106 with the verify voltage by checking whether the verify voltage can turn on each programmed selected memory cell 106. Next, a program voltage (Vpgm_n+1) higher than the Nth program voltage may be applied to the selected word line 118 by the word line driver 308.

[0061] To execute the program operation, the peripheral circuit 102 can be configured to perform VFC based on the verification result and the VFC criteria, e.g., whether the verification result meets the VFC criteria. In some implementations, as shown in FIG. 10, the VFC controller 1010 of the control logic 312 controls the page buffer 304 to send a command to the page buffer 304 to obtain the number of failed memory cells (also referred to as the number of verification-failed memory cells) in the selected row of the memory cells 106 that do not pass the verification. In response, the latch 1006 of the page buffer 304 can record each time that the threshold voltage of the programmed selected memory cell 106 is lower than the verify voltage (e.g., Vth < Vvfy). Each latch 1006 can be responsible for recording events according to some sets of conditions. In some examples, it is understood that a single latch 1006 may be used in a time-division multiplexing (TDM) manner to achieve the same function as a plurality of latches 1006. The counter 1004 of the page buffer 304 can be coupled to the latch 1006 and can count the recorded number of times, which is the number of verification-failed memory cells. As shown in FIG. 9, the shaded area 900 defined by the verify voltage (Vvfy) in the threshold voltage distribution at the final level (Lk) can indicate all the programmed selected memory cells 106 that do not pass the verification when their threshold voltages do not reach the verify voltage (lower than it) (e.g., Vth < Vvfy at Lk).

[0062] In some implementations, as shown in Figure 10, the VFC controller 1010 of the control logic 312 obtains the number of verification failure memory cells from the counter 1004 of the page buffer 304 and the VFC criterion 1012, which is stored, for example, in register 314. In some implementations, the VFC controller 1010 then compares the number of verification failure memory cells to the VFC criterion to determine whether the verification will pass or fail. The VFC criterion 1012, according to some implementations, includes any preferred criterion used to determine whether the verification result (e.g., the number of verification failure memory cells) indicates that the verification will pass or fail. For example, the VFC criterion 1012 may be a fail bit threshold indicating the maximum number of verification failure memory cells that will pass the verification. As described herein, the VFC criterion 1012 may include a standard VFC criterion and a predictive VFC criterion that is less stringent than the standard VFC criterion, i.e., a relaxed VFC criterion. According to some implementations, the predictive VFC criterion is used for the final level VFC, while the standard VFC criterion is used for other levels of VFC. For example, the standard VFC criterion may be a first fail-bit threshold, and the predicted VFC criterion may be a second fail-bit threshold that is greater than the first fail-bit threshold.

[0063] As shown in Figures 8A to 8C, for example, the second-to-last level VFC (L(k-1) vfc) may be performed by the page buffer 304 and control logic 312 of the peripheral circuit 102 in parallel with the (N+1)th program voltage, for example, during the period in which the (N+1)th program voltage is applied. In response that the second-to-last level VFC (shown as a filled box) satisfies the standard VFC criteria, for example, that the number of selected memory cells 106 that do not pass the second-to-last level verification (L(k-1) vfy) does not exceed the standard fail bit threshold, the second-to-last level verification passes, and after the (N+1)th program voltage, only the final level verification (Lk vfy) needs to be performed.

[0064] As shown in Figures 8A to 8C, for example, the final level verification (Lk vfy) may be performed by the word line driver 308 and page buffer 304 of the peripheral circuit 102. After applying the (N+1)th program voltage and performing the second-to-last level VFC, the peripheral circuit 102 may perform verification of one of the selected rows of memory cells 106 at the final level (Lk) (Lk vfy) by applying a verify voltage corresponding to the final level, such as a voltage pulse signal, to the selected word line 118 by the word line driver 308. A verify voltage may be applied to the control gate of each selected memory cell 106 to compare the threshold voltage of each programmed selected memory cell 106 with the verify voltage by checking whether the verify voltage can turn on each programmed selected memory cell 106.

[0065] As shown in Figures 8A to 8C, for example, instead of waiting to apply the next (N+2)th program voltage (Vpgm_n+2), the page buffer 304 and control logic 312 of the peripheral circuit 102 may perform a standard final level VFC (Lk vfc) after the final level verification is performed and before the (N+2)th program voltage is applied. As shown in Figure 8A, in response to the standard final level VFC (shown as a filled box) meeting the standard VFC criteria, for example, the number of selected memory cells 106 that do not pass the final level verification does not exceed the standard fail bit threshold, the program operation may pass the final level verification and terminate without requiring the application of the (N+2)th program voltage. In this case, the adaptive final level VFC method employs the standard final level VFC method (comparing Figure 8A with Figure 6A), which shortens the program operation time by eliminating the (N+2)th program voltage, depending on the implementation form.

[0066] In contrast, as shown in Figures 8B and 8C, if the standard final level VFC (shown as a dotted box) does not meet the standard VFC criteria, for example, if the number of selected memory cells 106 that do not pass the final level verification exceeds the standard fail bit threshold, the final level verification may fail, and the program operation may need to be continued by applying a (N+2) program voltage (Vpgm_n+2) that is higher than the (N+1) program voltage.

[0067] As shown in Figures 8B and 8C, for example, during the period in which the (N+2)th program voltage is applied, a predicted final level VFC (Lk vfc_p) may be executed by, for example, the page buffer 304 and control logic 312 of the peripheral circuit 102, in parallel with the (N+2)th program voltage. Furthermore, since a higher program voltage (Vpgm_n+2) that can be drawn out is applied after the first final level verification, it is reasonable to assume that more selected memory cells 106 have passed the final level verification. Therefore, a predicted VFC criterion that is less stringent than the standard VFC criterion (used by, for example, the standard final level VFC), for example, with a larger fail-bit threshold for passing the final level VFC, may be executed to make it easier for the final level VFC to satisfy the predicted VFC criterion.

[0068] As shown in Figure 8B, in response to the predicted final level VFC (shown as a filled box) meeting the predicted VFC criteria, for example, the number of selected memory cells 106 that do not pass the final level verification (Lk vfy) does not exceed a larger fail bit threshold, the program operation is completed after the final level verification is passed and the (N+2)th program voltage is applied without requiring the second final level verification to be performed again. In this case, the adaptive final level VFC method employs the predicted final level VFC method (comparing Figure 8B and Figure 7A), which shortens the program operation time by eliminating the second final level verification (for example, in Figure 6B), depending on the implementation form.

[0069] In contrast, as shown in Figure 8C, if the predicted final level VFC (shown as a dotted box) does not meet the predicted VFC criteria, for example, if the number of selected memory cells 106 that do not pass the final level verification (Lk vfy) still exceeds a larger fail bit threshold, the final level verification fails again, and the program operation must continue by performing yet another final level verification (Lk vfy). However, instead of waiting to apply the next (N+3) program voltage (Vpgm_n+3, as shown in Figure 7B of the predicted final level VFC scheme), another standard final level VFC (Lk vfc) may be performed by the page buffer 304 and control logic 312 of the peripheral circuit 102 after the second final level verification and before the application of the (N+3) program voltage. Similar to the first standard final level VFC, the second standard final level VFC may be performed by comparing the result of the second final level verification against a standard VFC criterion. For example, the two standard VFC criteria used by the first and second standard final level VFCs may be the same.

[0070] As shown in Figure 8C, in response to the second standard final level VFC (shown as a filled box) meeting the standard VFC criteria, the second final level verification passes and the program operation terminates without requiring the application of the next (N+3)th program voltage. Otherwise, the (N+3)th program voltage may need to be applied, and the second predicted final level VFC may need to be executed in parallel with the (N+3)th program voltage (not shown), or the program operation may be aborted as a failure. In this case, the adaptive final level VFC scheme employs a standard final level VFC scheme that, according to some implementations, shortens the program operation time by eliminating the (N+3)th program voltage (for example, in Figure 7B).

[0071] As shown in Figures 8A to 8C, the standard final level VFC (Lk vfc) between the application of the program voltage and the verification and application of the predicted final level VFC (Lk vfc_p) may be performed alternately according to an adaptive final level VFC scheme in parallel with the application of the program voltage, so as soon as the verification is passed, the program operation will be terminated. Unlike the standard final level VFC scheme, which always terminates the program operation after verification (for example, in Figures 6A and 6B), and the predicted final level VFC scheme, which always terminates the program operation after the application of the program voltage (for example, in Figures 7A and 7B), the adaptive final level VFC scheme disclosed herein can flexibly terminate the program operation by switching between the standard final level VFC scheme and the predicted final level VFC scheme.

[0072] Figure 11 shows a flowchart of method 1100 for programming a memory device according to several aspects of the present disclosure. The memory device may be any suitable memory device disclosed herein, such as memory device 100. Method 1100 may be implemented by peripheral circuits 102, such as a row decoder / word line driver 308, a page buffer / sense amplifier 304, and control logic 312. It is understood that the operations shown in method 1100 are not exhaustive, and that other operations may be performed before, after, or between any of the illustrated operations. Furthermore, some of the operations may be performed simultaneously or in an order different from that shown in Figure 11.

[0073] Referring to Figure 11, method 1100 begins in operation 1102, in which a first program voltage is applied to a selected row of memory cells. At least one of the memory cells corresponds to two elements of N-bit data. NIt is set to one of the n levels, where N is an integer greater than 1. For example, as shown in Figures 8A to 8C and Figure 10, during program operation, the word line driver 308 of the peripheral circuit 102 may apply the (N+1)th program voltage (Vpgm_n+1, "first program voltage") to the selected row of the memory cell 106 via the selected word line 118.

[0074] Method 1100 involves applying a first program voltage, as shown in Figure 11, followed by 2 N The first validation of the selected row is performed at the final level of the individual levels, and the process proceeds to operation 1104. In some implementations, to perform the first validation, 2 N A verify voltage corresponding to the final level among the individual levels is applied to the selected row. For example, as shown in Figures 8A to 8C and Figure 10, in program operation, after the word line driver 308 and page buffer 304 of peripheral circuit 102 apply the (N+1) program voltage, the first final level verification (Lk vfy, 2 N The first verification at the final level among the individual levels may be performed.

[0075] Method 1100 proceeds to operation 1106, in which a first VFC is performed based on the results of the first verification and the first VFC criterion, as shown in Figure 11. In some implementations, in order to perform the first VFC, the number of failed memory cells in the selected row that does not pass the first verification is obtained, and the number of failed memory cells is compared against the first VFC criterion. In some implementations, the first verification passes if the results of the first verification satisfy the first VFC criterion, and fails if the results of the first verification do not satisfy the first VFC criterion. For example, as shown in Figures 8A to 8C and Figure 10, in program operation, after a first final level verification, but before the next (N+2) program voltage is applied by the page buffer 304 and control logic 312 of the peripheral circuit 102, a first standard final level VFC (Lk vfc, "first VFC") may be performed based on the results of the first final level verification and a standard VFC criterion ("first VFC criterion"). In one example, the number of memory cells that fail verification in the first final level verification may be recorded and counted by the latch 1006 and counter 1004 of the page buffer 304, respectively, and then compared against a default VFC criterion 1012 for the VFC controller 1010 of the control logic 312 to determine whether the first final level verification passes or fails.

[0076] Method 1100 proceeds to operation 1108, in which, after performing a first VFC, a second program voltage higher than the first program voltage is applied to the selected row, as shown in Figure 11. The second program voltage may be applied in response to the result of the first verification not meeting the first VFC criterion. Otherwise, the second program voltage may be skipped to terminate the program operation. For example, as shown in Figures 8B, 8C, and 10, in a program operation, if the result of the first final level verification (shown as a dotted box, i.e., the first final level verification fails) does not meet the standard VFC criterion, then after performing the first standard final level VFC, a second (N+2) program voltage (Vpgm_n+2, "second program voltage") higher than the first (N+1) program voltage may be applied to the selected row of the memory cell 106 via the selected word line 118 by the word line driver 308 of the peripheral circuit 102. Otherwise, as shown in Figures 8A and 10, in program operation, when the result of the first final level verification (shown as a filled box, i.e., passing the first final level verification) satisfies the standard VFC criterion, the (N+2)th program voltage may be skipped after the first standard final level VFC has been executed in order to terminate the program operation.

[0077] Method 1100 proceeds to operation 1110, in which a second VFC is applied based on the results of the first verification and a second VFC criterion different from the first VFC criterion, during the period in which a second program voltage is applied, as shown in Figure 11. The second VFC criterion does not have to be stricter than the first VFC criterion. For example, as shown in Figures 8B, 8C, and 10, in the program operation, a first predicted final level VFC (Lk vfc_p, "second VFC") may be performed based on the results of the first final level verification and a predicted VFC criterion ("second VFC criterion") during the period in which the page buffer 304 and control logic 312 of the peripheral circuit 102 apply the (N+2)th program voltage. The predicted VFC criterion does not have to be stricter than the standard VFC criterion and may have, for example, a larger fail bit threshold. In one example, the number of memory cells that fail verification in the first final level verification may be recorded and counted by the latch 1006 and counter 1004 of the page buffer 304, respectively, and then compared against a relaxed VFC criterion 1012 for the VFC controller 1010 of the control logic 312 to determine whether the first final level verification will pass or fail.

[0078] Method 1100 proceeds to operation 1112, in which a second verification of the selected row at the final level is performed in response to the result of the first verification not meeting the second VFC criterion, as shown in Figure 11. For example, in a program operation, as shown in Figures 8C and 10, if the result of the first final-level verification does not meet the predicted VFC criterion (shown as a dotted box, i.e., the first final-level verification fails again under the relaxed VFC criterion after the (N+2)th program voltage is applied), a second final-level verification (Lk vfy, "second verification at the final level") may be performed after the word line driver 308 and page buffer 304 of the peripheral circuit 102 apply the (N+2)th program voltage.

[0079] Method 1100 proceeds to operation 1114, in which a third VFC is performed based on the results of the second verification and a third VFC criterion, as shown in Figure 11. In some implementations, the third VFC criterion is the same as the first VFC criterion. For example, as shown in Figures 8C and 10, in a programmed operation, after the second final level verification, but before the next (N+3) programmed voltage is applied by the page buffer 304 and control logic 312 of the peripheral circuit 102, a second standard final level VFC (Lk vfc, "third VFC") may be performed based on the results of the second final level verification and a standard VFC criterion ("third VFC criterion"). The standard VFC criterion may be the same for the first and second standard final level VFCs. In one example, the number of memory cells that fail verification in the second final level verification may be recorded and counted by the latch 1006 and counter 1004 of the page buffer 304, respectively, and then compared against a default VFC criterion 1012 in order for the VFC controller 1010 of the control logic 312 to determine whether the first final level verification will pass or fail.

[0080] In some implementations, the second and third VFCs are skipped in response to the result of the first verification satisfying the second VFC criterion. For example, as shown in Figures 8B and 10, in program operation, when the result of the first final level verification (shown as a filled box, i.e., passing the first final level verification under relaxed VFC criteria after applying the (N+2)th program voltage) satisfies the predicted VFC criterion, the second final level verification and the second standard final level VFC may be skipped after the first predicted final level VFC is executed in order to terminate the program operation.

[0081] Figure 12 shows a block diagram of a system 1200 having a memory device according to several aspects of the present disclosure. System 1200 may be a mobile phone, a desktop computer, a laptop computer, a tablet, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having storage therein. As shown in Figure 12, system 1200 may include a memory system 1202 having a host 1208, and one or more memory devices 100 (shown in Figure 1) and a memory controller 1206. The host 1208 may be a processor of an electronic device, such as a central processing unit (CPU) or a system-on-a-chip (SoC) such as an application processor (AP). The host 1208 may be configured to send or receive data to and from the memory device 100.

[0082] The memory device 100 may be any memory device disclosed in this disclosure. The memory controller 1206, according to some implementations, is coupled to the memory device 100 and the host 1208 and configured to control the memory device 100. The memory controller 1206 can manage the data stored in the memory device 100 and communicate with the host 1208. In some implementations, the memory controller 1206 is designed to operate in low-duty-cycle environments, such as Secure Digital (SD) cards, CompactFlash (CF) cards, Universal Serial Bus (USB) flash drives, or other media for use in electronic devices such as personal computers, digital cameras, and mobile phones. In some implementations, the memory controller 1206 is designed to operate in high-duty-cycle environments, such as SSDs or embedded multimedia cards (eMMCs) used as data storage for mobile devices such as smartphones, tablets, and laptop computers, and for enterprise storage arrays. The memory controller 1206 may be configured to control the operation of the memory device 100, such as read operations, erase operations, and program operations. The memory controller 1206 may also be configured to manage various functions relating to data stored in or to be stored in the memory device 100, including, but not limited to, bad block management, garbage collection, logical-to-physical address translation, and wear leveling. In some implementations, the memory controller 1206 may be further configured to handle error correction codes (ECC) relating to data read from or written to the memory device 100. Any other preferred functions, such as formatting the memory device 100, may also be performed by the memory controller 1206. The memory controller 1206 may communicate with an external device (e.g., host 1208) according to a specific communication protocol.For example, the memory controller 1206 may communicate with an external device through at least one of various interface protocols, such as the USB protocol, Multimedia Card (MMC) protocol, Peripheral Component Interconnect (PCI) protocol, PCI Express (PCI-E) protocol, Advanced Technology Attachment (ATA) protocol, Serial ATA protocol, Parallel ATA protocol, Small Computer Small Interface (SCSI) protocol, Expansion Small Disk Interface (ESDI) protocol, Integrated Drive Electronics (IDE) protocol, and Firewire protocol.

[0083] The memory controller 1206 and one or more memory devices 100 can be integrated into various types of storage devices, for example, included in the same package such as a Universal Flash Storage (UFS) package or an eMMC package. In other words, the memory system 1202 can be implemented and packaged in different types of final electronic products. In one example, as shown in Figure 13A, the memory controller 1206 and a single memory device 100 may be integrated into a memory card 1302. The memory card 1302 may include PC cards (PCMCIA, International Association for Personal Computer Memory Cards), CF cards, SmartMedia (SM) cards, Memory Sticks, Multimedia Cards (MMC, RS-MMC, MMCmicro), SD cards (SD, miniSD, microSD, SDHC), UFS, etc. The memory card 1302 may further include a memory card connector 1304 that connects the memory card 1302 to a host (for example, the host 1208 in Figure 12). In another example, as shown in Figure 13B, a memory controller 1206 and multiple memory devices 100 may be integrated into the SSD 1306. The SSD 1306 may further include an SSD connector 1308 that connects the SSD 1306 to a host (for example, the host 1208 in Figure 12). In some implementations, the storage capacity and / or operating speed of the SSD 1306 is greater than that of the memory card 1302.

[0084] The above descriptions of specific implementations may be readily modified and / or adapted for various applications. Such adaptations and modifications shall therefore be within the meaning and scope of the equivalents of the disclosed implementations, based on the teachings and guidance provided herein.

[0085] The breadth and scope of this disclosure should not be limited by any of the exemplary implementations described above, but should be defined solely by the following claims and their equivalents.

[0086] While specific configurations and arrangements are described, it should be understood that this is done for illustrative purposes only. Therefore, other configurations and arrangements may be used without departing from the scope of this disclosure. Furthermore, the subject matter described in this disclosure may also be used in a variety of other applications. The functional and structural features described in this disclosure can be combined, adjusted, modified, and rearranged in a manner consistent with the scope of this disclosure. [Explanation of symbols]

[0087] 100 memory devices 101 memory cell array 102 Peripheral Circuits 104 blocks 106 memory cells 108 NAND memory string 110 Source Select Gate (SSG) Transistor 112 Drain-Selected Gate (DSG) Transistor 113 DSG Line 114 Source Line (SL) 115 SSG Line 116-bit line 118 Wordlines 120 pages 202 circuit boards 204 memory stack 206 Gate conductive layer 208 Intergate dielectric layer 304 Page Buffer / Sense Amplifier 306-column decoder / bitline driver 308-line decoder / wordline driver 310 Voltage Generator 312 Control Logic 314 registers 316 Interface (I / F) 318 Data Bus 502 Program / Verify Cycle 504 Program Cycle 506 Verify cycle 1004 counter 1006 Latch 1008 Program / Verify Controller 1010 VFC Controller 1012 VFC standard 1200 System 1202 Memory System 1206 Memory Controller 1208 Hosts 1302 Memory Card 1304 Memory card connector 1306 SSD 1308 SSD connector

Claims

1. A memory device, A memory array including memory cells, wherein at least one of the memory cells is set to one of 2N levels corresponding to elements of N-bit data, where N is an integer greater than 1; The memory array is coupled with peripheral circuits, and the peripheral circuits are During the first programming period of the program operation, a first program voltage is applied to the word line coupled to the memory cell, During the first programming period, the first Verification Failure Count (VFC) is performed, During the first verification period of the program operation, the first verification of the memory cell is performed at the final level of the 2N levels. During the first verification period, a second VFC is executed based on the results of the first verification. A memory device configured to perform the following actions.

2. The peripheral circuit further comprises: During the second programming period of the program operation, a second program voltage is applied to the word line. Executing a third VFC during the second programming period, wherein the second programming period precedes the first programming period. A memory device according to claim 1, configured to perform the following:

3. The peripheral circuit further comprises: During the second verification period of the program operation, the second verification of the memory cell is performed in at least one of the 2N levels, which is different from the final level among the 2N levels, provided that the VFC does not exist during the second verification period. A memory device according to claim 2, configured to perform the following:

4. The peripheral circuit further comprises: Performing the first verify failure count (VFC) based on the first VFC criterion, The second VFC is performed based on the results of the first verification and a second VFC criterion that differs from the first VFC criterion. A memory device according to claim 1, configured to perform the following:

5. The peripheral circuit further comprises: During the third programming period of the program operation, a third program voltage is applied to the word line, During the third programming period, the third VFC is executed based on a third VFC criterion different from the first VFC criterion, It is configured to do the following: The memory device according to claim 4, wherein the third programming period follows the first programming period.

6. The memory device according to claim 5, wherein the third VFC standard is less stringent than the second VFC standard.

7. The peripheral circuit further In response that the third VFC satisfies the third VFC criterion, the first verification is skipped and the program operation terminates. The memory device according to claim 5, configured as described above.

8. The peripheral circuit further comprises: In response to the third VFC failing to meet the third VFC criterion, the third verification of the memory cell is performed at the final level. Based on the results of the third verification and the fourth VFC criteria, the fourth VFC will be performed. A memory device according to claim 5, configured to perform the following:

9. The memory device according to claim 8, wherein the fourth VFC criterion is the same as the second VFC criterion.

10. The peripheral circuit further The memory device according to claim 5, configured to apply a third program voltage in response to the result of the first verification not meeting the second VFC criterion.

11. The memory device according to claim 5, wherein the third program voltage is greater than the first program voltage.

12. A memory system, A memory device configured to store data, wherein the memory device A memory array including memory cells, wherein at least one of the memory cells is set to one of 2N levels corresponding to elements of N-bit data, where N is an integer greater than 1; Peripheral circuits coupled to the memory array, During the first programming period of the program operation, a first program voltage is applied to the word line coupled to the memory cell, During the first programming period, the first Verification Failure Count (VFC) is performed, During the first verification period of the program operation, the first verification of the memory cell is performed at the final level of the 2N levels. During the first verification period, a second VFC is performed based on the results of the first verification. A peripheral circuit configured to perform the following: A memory controller coupled to the memory device and configured to control the memory device, A memory system equipped with the following features.

13. A method for programming a memory device, wherein the memory device comprises a memory array including memory cells, at least one of the memory cells is set to one of 2N levels corresponding to elements of N-bit data, where N is an integer greater than 1, and the method The steps include applying a first program voltage to the word line coupled to the memory cell during a first programming period of the program operation, During the first programming period, the steps include performing a first verify failure count (VFC), During the first verification period of the program operation, the first verification of the memory cell is performed at the final level among the 2N levels. During the first verification period, the step of performing a second VFC based on the results of the first verification, Methods that include...

14. The step of applying a second program voltage to the word line during a second programming period of the program operation, A step of executing a third VFC during the second programming period, wherein the second programming period is prior to the first programming period. The method according to claim 13, further comprising:

15. The method of claim 14, further comprising the step of performing a second verification of the memory cell in at least one of the 2N levels, which is different from the final level, during a second verification period of the program operation, wherein no VFC exists during the second verification period.

16. A step of performing the first verify failure count (VFC) based on the first VFC criterion, The steps include performing the second VFC based on the first verification and a second VFC criterion different from the first VFC criterion, The third programming period of the program operation includes the step of applying a third program voltage to the word line, The steps include: during the third programming period, executing a third VFC based on a third VFC criterion different from the first VFC criterion; It further includes, The method according to claim 13, wherein the third programming period follows the first programming period.

17. The method according to claim 16, wherein the third VFC criterion is not stricter than the second VFC criterion.

18. The method according to claim 16, further comprising the step that the first verification is skipped and the program operation terminates in response that the third VFC satisfies the third VFC criterion.

19. In response that the third VFC does not meet the third VFC criterion, the third verification of the memory cell is performed at the final level, The steps include: performing the fourth VFC based on the results of the third verification and the fourth VFC criteria; Further including The method according to claim 16, wherein the fourth VFC criterion is the same as the second VFC criterion.

20. The method of claim 16, further comprising the step of applying the third program voltage in response that the result of the first verification does not satisfy the second VFC criterion.

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