Readout circuit and memory system

Abstract

A control circuit 13 is a circuit for reading data from a memory array 11 having bit lines BL electrically connecting memory cells MC, said circuit comprising: an amplification unit 33 which has read lines RL connected to the bit lines BL, and which, during a data read operation, charges the bit lines BL via the read lines RL and then amplifies the electrical signals of the bit lines BL at sense nodes SN on the read lines RL; and inverters 35 which determine, on the basis of voltages of the sense nodes SN, data stored in memory cells MC connected to the bit lines BL and selected at the time of the data read operation. The amplification unit 33 includes switching elements 29, 31, of which switching elements 31 charge the bit lines on the basis of power supplied from a first power supply having a first voltage VDDQ, and switching elements 29 turn on / off on the basis of power supplied from a second power supply having a second voltage VDD higher than the first voltage VDDQ.

Claims

1. A read circuit for reading data from a memory array having multiple bit lines, which are line-shaped wiring sections that electrically connect multiple memory cells, The first amplification unit has a read line, which is a linear wiring section electrically connected to the bit line, and during the data reading operation, charges the bit line via the read line and then amplifies the electrical signal of the bit line at the voltage of a sense node on the read line. The system includes a second amplifier that outputs a determination signal based on the voltage of the sense node, which determines the data stored in the memory cell connected to the bit line and selected during the data reading operation. The first amplification unit includes a first switching element electrically connected between the bit line and the read line, which conducts a current corresponding to the electrical signal of the bit line, and a second switching element which turns the connection between the power supply and the read line on and off. The second switching element charges the bit line based on power supplied from a first power supply having a first voltage, The first switching element operates based on power supplied from a second power source having a second voltage higher than the first voltage. The first amplifier further comprises a switching circuit that switches the connection between the power supply line connected to the second switching element of the first amplifier and the first power supply and the second power supply, The switching circuit switches the connection of the power supply line from the first power source to the second power source after the second switching element has charged the bit line. Readout circuit.

2. The parasitic capacitance of the read line is smaller than the parasitic capacitance of the bit line. The readout circuit according to claim 1.

3. The second switching element turns on / off the connection between the first power supply or the second power supply and the read line. The second amplification unit senses the voltage of the sense node at the timing after the second switching element has been turned off. The readout circuit according to claim 1.

4. The first switching element is configured to supply current in accordance with the electrical signal of the bit line, which changes in accordance with the data storage state of the memory cell connected to the bit line when it is being charged by the first amplification unit. The readout circuit according to claim 1.

5. The switching circuit includes a linear regulator connected to the second power supply that converts the second voltage to a predetermined voltage and outputs it, and a switching element that switches the connection between the output of the first power supply, the output of the linear regulator, and the power supply line. The readout circuit according to claim 1.

6. A readout circuit according to any one of claims 1 to 5, The memory array includes a plurality of memory cells electrically connected to the read circuit via a plurality of bit lines, A memory system equipped with the following features.

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