Loosely coupled slice target file data

Abstract

The system may determine that two instructions can be combined based on the processing power of the processor and the sizes of the instructions, fuse the two instructions into a pair, map the two instructions using a single register tag, write the register tag to a mapper with a bit indicating that the register tag is for a first instruction of the two instructions, write the register tag to the mapper with a bit indicating that the register tag is for a second instruction of the two instructions, write the fused instruction pair to an issue queue, issue the fused instruction pair to a vector scalar translation unit (VSU), and execute the two instructions.

Description

Technical Field

[0001] Aspects of the present invention relate to a vector scalar conversion unit (VSU), and more specifically, aspects relate to sparse coupled slice target file (STF) data.

Background Art

[0002] The processor chip POWER10 is a 7-nanometer (nm) CMOS design with a die size of 602 mm2 using an 18-layer metal stack. It is available in single-chip or dual-chip sockets. The top-level system architecture characteristics are captured in Table I. Two of the major and notable operational features of POWER10 over POWER9 are: (a) a significant improvement in energy efficiency; and (b) core AI enhancement featuring ISA extensions and in-line MMA (Matrix-Multiply Assist) acceleration.

[0003] A scalar processor processes one data at a time. A vector processor processes multiple data with a single instruction.

Summary of the Invention

[0004] The present invention provides a method, a computer program product, and a system for creating loosely coupled slice target file (STF) data. In some embodiments, the method includes the steps of: determining whether two instructions can be combined based on the processing capacity of the processor and the size of the instructions; fusing the two instructions into a pair; mapping the two instructions using a single register tag; writing the register tag to a mapper with a bit indicating that the register tag corresponds to the first instruction of the two instructions; writing the register tag to the mapper with a bit indicating that the register tag corresponds to the second instruction of the two instructions; writing the fusing instruction pair to an issue queue; issuing the fusing instruction pair to a vector scalar conversion unit (VSU); and executing the two instructions.

[0005] Furthermore, some embodiments of the present invention may be illustrated by a computer program product comprising a computer-readable storage medium in which program instructions are embodied, wherein the program instructions are executable by the processor to cause the processor to execute a method, the method comprising the steps of: determining whether two instructions can be combined based on the processing capacity of the processor and the size of the instructions; fusing the two instructions into a pair; mapping the two instructions using a single register tag; writing the register tag to a mapper with a bit indicating that the register tag corresponds to the first instruction of the two instructions; writing the register tag to the mapper with a bit indicating that the register tag corresponds to the second instruction of the two instructions; writing the fusing instruction pair to an issue queue; issuing the fusing instruction pair to a vector-scalar unit (VSU); and executing the two instructions.

[0006] Some embodiments of the present invention may be exemplified by a system comprising a processor and a memory in communication with the processor, the memory including program instructions configured to cause the processor to execute a method when executed by the processor, the method comprising the steps of: determining whether two instructions can be combined based on the processing capacity of the processor and the size of the instructions; fusing the two instructions into a pair; mapping the two instructions using a single register tag; writing the register tag to a mapper with a bit indicating that the register tag corresponds to the first instruction of the two instructions; writing the register tag to the mapper with a bit indicating that the register tag corresponds to the second instruction of the two instructions; writing the fusing instruction pair to an issue queue; issuing the fusing instruction pair to a vector-scalar unit (VSU); and executing the two instructions. [Brief explanation of the drawing]

[0007] [Figure 1] This is a block diagram of a processor core according to various embodiments of the present invention.

[0008] [Figure 2] This figure illustrates an exemplary method for combining STF data according to various embodiments of the present invention.

[0009] [Figure 3] This is a block diagram of an exemplary microarchitecture of a processor configured to combine STF data, according to an embodiment of the present invention.

[0010] [Figure 4] This figure shows a computer system according to various embodiments of the present invention. [Modes for carrying out the invention]

[0011] Aspects of the present invention relate to the creation of loosely coupled slice target file (STF) data. While the present invention is not necessarily limited to such applications, various aspects of the present invention can be understood through discussion of various examples using this context.

[0012] Modern processing units contain multiple cores capable of independently processing multiple instructions. For example, the POWER10 processor has four Vector-Scalar Unit (VSU) execution units, which can execute a total of four VSU instructions per cycle (i.e., four 128-bit vector instructions, or four 64-bit scalar instructions, or a mixture of four 128-bit vector and 64-bit scalar instructions).

[0013] The novel horizontal fusion design proposed by this disclosure enables the core to improve the execution speed of scalar instructions. For example, in the POWER10 processing unit, aspects of the invention may enable an improvement in execution speed from 4 to 8 per cycle. Using this novel design, the core may be able to execute vector instructions equal to the maximum processing capacity for each unit, and / or multiple smaller vector instructions, without adding additional VSU processing pipes. For example, the POWER10 processing unit can execute up to four VSU 128-bit vector instructions, or eight VSU 64-bit scalar instructions, or a combination of both.

[0014] Microprocessor architectures utilize various registers to store data for instruction execution / operation. To track which registers (or locations within registers) store the data for a particular instruction, the microprocessor uses a register file (or one or more register files). The register file holds the register locations required for various instructions executed by hardware threads within a superslice. In some processors, the register file may be divided into multiple blocks. For example, in some POWER® processors, the register file is called a slice target register file (STF), which consists of four smaller STF blocks that work together to provide a larger register file for the core. (POWER is a registered trademark owned by International Business Machine Corporation.)

[0015] To ensure that multiple instructions do not attempt to store different data in the same location, a microprocessor assigns register tags to instructions. In some cases, register tags may be referred to herein as slice target register file tags (STF tags), although other names or types of tags are possible. Unused register tags may be kept in a free list (e.g., an STF free list). In some cases, the free list continues to track unassigned physical registers. When an instruction is received in dispatch, the processor checks the available registers. If a register is available, the processor assigns a register tag from the free list to the instruction, and the instruction can proceed with the associated tag. Once a register tag is assigned, it is removed from the free list, and the corresponding entry (and therefore the register location) in the register file cannot be assigned to a new instruction. The use of register tags and register files allows the processor to ensure that instructions do not collide (e.g., one instruction overwrites data that is still needed).

[0016] In some embodiments, the proposed system may load multiple instructions onto a single register tag that is processed within a single pipeline.

[0017] In some embodiments, write / read (W / R) operations are allocated so that fused pairs can be issued from an issue queue (ISQ). For example, each STF (e.g., register tag) block may have 2W / 6R operations for 128 bits of data. In this example, the 6R operations are allocated to allow fused scalar pairs to be issued from the ISQ.

[0018] In some embodiments, write / read (W / R) operations are assigned so that a scalar instruction can write identical results to both halves of a single STF register entry, as in a tightly coupled STF design. A dependent instruction can read the same scalar data from either half of the STF entry.

[0019] In some embodiments, write / read (W / R) operations are assigned such that a scalar instruction can write results to only half of the STF entry, as in a loosely coupled STF design. The scalar result can only be written to either the right half or the left half of the STF entry. Dependent instructions must know whether the operand data lies on the left or right half of the STF entry.

[0020] Embodiments of the present invention are discussed herein with reference to the figures.

[0021] Referring now to FIG. 1, a high-level block diagram of the various components of an exemplary microprocessor system 100 according to an embodiment of the present invention is illustrated. The microprocessor system 100 includes an instruction dispatch unit (IDU) 102, an instruction sequencing unit (ISU) 104, a load store unit (LSU) 108, a vector / scalar unit (VSU) 106, and completion and exception handling logic 110.

[0022] The IDU 102 is a processing unit responsible for orchestrating the fetching of program instructions from memory and their execution in the appropriate order. The IDU 102 is often regarded as part of the control unit of a central processing unit (CPU) (e.g., the unit responsible for instructing the operation of the processor). In some embodiments, as described in FIG. 2, the IDU may fuse two adjacent scalar instructions.

[0023] The ISU 104 is a computing unit responsible for dispatching instructions to an issue queue, renaming registers to support out-of-order execution, issuing instructions from the issue queue to an execution pipeline, completing in-execution instructions, and handling exceptions. The ISU 104 includes an issue queue that issues all instructions once the dependencies and combinations of the instructions are resolved.

[0024] The VSU 106 is a computing unit that maintains ownership of a slice target file (STF). The STF holds all of the register data sourced by an instruction. As an example, taking a store instruction without a target, the STF holds the registers required for the store address operand and the store data to be sent to the LSU 108 for execution.

[0025] The LSU 108 is an execution unit responsible for executing all load and store instructions, managing the interface between the core of the processor and the rest of the system using an integrated cache, and performing address translation. For example, the LSU 108 generates virtual addresses for load and store operations, and the LSU 108 loads data from memory (for a load operation) or stores data from a register to memory (for a store operation). The LSU 108 may include a queue for memory instructions, and the LSU 108 may operate independently from other units.

[0026] The completion and exception handling logic 110 (hereinafter "completion logic" 110) is responsible for completing instructions. If an instruction causes an exception, the completion logic 110 flushes the instruction and sends a signal to the IDU to refetch the instruction.

[0027] It should be understood that the components 102-110 shown in FIG. 1 are provided for illustrative purposes and to explain the principles of embodiments of the present invention. Some processor architectures may include more, fewer, or different components, and the various functions of components 102-110 may be performed by different components in some embodiments. For example, exception and completion handling may be performed by the ISU 104.

[0028] Furthermore, the processor may include more than one of the components 102-110. For example, a multi-core processor may include one or more instruction fetch units (IDUs) 102 per core. Furthermore, embodiments of the present invention are generally discussed in reference to POWER (registered trademark) processors, but this is for illustrative purposes. The present invention may be implemented by other processor architectures and is not limited to POWER processors.

[0029] Figure 2 shows an exemplary method 200 for loosely coupled register tag data. The operation of method 200 can be performed by one or more computer systems, such as the system described in Figure 3 below.

[0030] Method 200 begins with operation 202, in which an instruction dispatch unit (IDU) (e.g., IDU 102 from Figure 1) determines, based on the unit's processing capacity and the size of the instructions, that two instructions can be combined. If the unit has the capacity to process two instructions simultaneously, the IDU may determine that the instructions can be combined. For example, if a VSU slice can execute a 128-bit vector instruction and the system has two 64-bit scalar instructions, the IDU may determine that the two 64-bit scalar instructions can be combined and processed simultaneously by the VSU slice. These instructions may be referred to herein as left instructions and right instructions, but this distinction does not imply any physical limitations on the processor; it is simply a way of differentiating the two instructions. Similarly, later, a vector scalar unit (VSU) may be referred to as having a left side and a right side. Furthermore, the statement that part of the VSU's 128-bit capacity is allocated to left instructions and part of the capacity is allocated to right instructions is not intended to indicate anything unique about either the left or right "side" / instructions, but is used for illustrative purposes and for clarity of discussion.

[0031] Method 200 may be followed by an operation 204 that merges two adjacent instructions into a pair. For example, the instructions may be scalar instructions. In some cases, adjacent instructions are instructions that can be executed simultaneously. For example, adjacent instructions are not dependent on each other. In some embodiments, adjacent instructions are instructions that can be completed simultaneously and are not directly dependent on each other.

[0032] In some embodiments, the dispatch logic within the processor may write an instruction tag (ITAG) for an received instruction to a mapper. In some cases, the data mapper performs bidirectional data transfer between persistent data stores, such as relational databases, and in-memory data representations, such as domain layers. Save and Restore Buffers (SRBs) track previous mappings to a given register. For example, if the processor has written to a particular general-purpose register (GPR) or vector scalar register (VSR) five times, the mapper will only have the most recent one, while the SRB may store four previous ITAGs. The purpose of the SRB is to back up the processor state in case the processor needs to perform a flush. The dispatch logic also dispatches instructions to the ISQ. In some embodiments, these operations are performed without assigning register tags to the instructions.

[0033] In some embodiments, a fused instruction may have two ITAGs. In some embodiments, the first ITAG is an even ITAG. For example, the IDU may select the least significant bit and make it even (e.g., 0) for the first tag. In that case, the IDU only needs to send the first ITAG, because the least significant bit may later be inverted to obtain the second ITAG (e.g., to make it odd 1).

[0034] ITAGs are instruction tags that facilitate instruction tracking. A processor assigns a tag to every instruction coming down the line so that it can be tracked. ITAGs track instructions from decoding to completion. ITAGs can be implemented as a set of binary bits.

[0035] In some cases, the W bit is a written bit that indicates in binary terms whether data is ready or available. The W bit can be provided in the form of yes / no, affirmative / negative, etc. If the W bit is positive, the system has less interest in the ITAG because the data is already there and it is less important which element provided the data. If the W bit is negative, the ITAG indicates which elements the process is waiting for before the instruction can be executed. The W bit is sometimes referred to as the data availability written bit.

[0036] Method 200 may proceed to operation 206, in which the IDU may transmit the fused instructions to an instruction sequencing unit (ISU). For example, the IDU may transmit the fused instructions to an ISU on a paired lane. A paired lane is a serially connected data transmission lane. Each lane consists of two pairs of wires, one for transmission and the other for reception.

[0037] Method 200 may proceed to operation 208 in which an instruction sequencing unit (e.g., ISU 104) maps the left and right instructions. In some embodiments, the left and right instructions may be mapped separately. For example, the left and right instructions may be processed separately, have separate solutions, and therefore the mappings may need to be separate.

[0038] In some embodiments, the system may write an ITAG to a completion table and mark the ITAG as atomic (i.e., both ITAGs must be completed together). For example, the ISU may write the even and odd ITAGs for a fused pair into the completion table.

[0039] The mapper can access a free list of STF tags and assign a single available STF tag (e.g., a register tag) (128 bits) to the fused pair. For example, the mapper may be part of an ISU and may receive a free list of available STF tags. The mapper may select a free STF tag for the fused pair.

[0040] In some embodiments, the ISU may write the STF tag to the mapper along with two bits indicating whether the STF_tag corresponds to the left bit or the right bit of the STF tag. Since the fused instruction issues a single STF_tag, the system needs to determine which instruction information for the STF tag is left instruction data and which is right instruction data. For example, the destination logic register (RT) for the fused scalar pair is used to index to the mapper for the write operation. Even ITAG instructions can be recorded in both the STF tag and the STF tag_left bit (e.g., having an even bit "10"). Odd ITAG instructions can be recorded in the STF tag along with the STF tag_right bit (e.g., having an odd bit tag "01").

[0041] With respect to vector instructions, only one mapper position can be written using the corresponding RT field, and both STF_tag_left and STF tag_right can be active (e.g., even and odd bits "11").

[0042] Where used herein, the “source STF tag” is the STF tag that identifies which physical register an instruction is reading from in order to perform an operation. The source STF tag resides within the ISQ330 before an instruction begins to be issued. The “destination STF tag” is the STF tag associated with the register that an instruction is actually writing to. The destination STF tag is fed back to the ISQ330, mapper 320, and SRB340 for instructions that have not been issued or depend on it. For example, suppose there are a series of instructions that use a specific register (REG1). The first instruction writes to REG1, and the second instruction reads from REG1 and performs some operation on the data read from REG1. The destination STF tag for the first instruction is fed back to the ISQ (e.g., the ISQ330 in Figure 3), mapper (e.g., mapper 320 in Figure 3), and SRB (e.g., SRB340 in Figure 3) so that the second instruction can identify the appropriate register from which to read the data. In other words, the destination STF tag for the first instruction functions as the source STF tag for the second instruction.

[0043] Method 200 may follow Operation 210, in which the ISU may write the fused instruction pair to an issue queue (ISQ) entry (e.g., a full issue queue). In some embodiments, the fused scalar pair may be held in the ISQ until all six operands are ready, for example, operands executed by one or more MUXs (e.g., MUX315 and MUX316 from Figure 3). Operand transfer (or data transfer) is an optimization within a pipelining CPU to limit performance defects resulting from pipeline stalls.

[0044] Method 200 may proceed to operation 212, in which the fused pair is issued to the VSU. In some embodiments, the fused pair may not be issued to the VSU until all six operands are ready.

[0045] In some embodiments, the ISQ may broadcast an even number of ITAGs (having fused pair indices) to the mapper and the ISQ to initiate ITAG dependency.

[0046] In some embodiments, the ISQ and mapper may compare an even ITAG with an even instruction, invert the LSB of the even ITAG to generate an odd ITAG, which is then used for comparison with an odd instruction.

[0047] Method 200 may lead to operation 214 in which the VSU executes both scalar instructions simultaneously.

[0048] In some embodiments, the fused instruction causes the system (e.g., VSU) to read information from both STF_left and STF_right in a physical register (e.g., physical register file 318). If either of the operands of the fused instruction is in the opposite STF bank (left relative to STF right, or right relative to STF left), the logic may steer the instruction to the correct operand latch.

[0049] In some embodiments, the scalar result is written to the correct register tag (left or right) based on the STF tag, STF tag_left, and STF tag_right bits. In some embodiments, the VSU (left and / or right) result can also be bypassed to a dependent scalar or fused scalar pair by an operand transfer mux (e.g., transfer mux314A or 314B).

[0050] In some embodiments, the VSU may then terminate the instruction according to a “normal” procedure (for example, the default procedure for the system in the absence of a particular variable).

[0051] Method 200 may proceed to operation 216, in which the system completes both halves of the fused scalar instruction together. In some embodiments, completing both halves together means that the instructions are completed in the same cycle, or the results are transferred simultaneously, or the results are transferred within the same package, and / or reported as completed simultaneously.

[0052] In some embodiments, if a fused instruction triggers an exception, the completion logic may flush both halves of the fused instruction and instruct the IDU to refetch the fused instruction as two unfused instructions. For example, if processing either the left or right instruction would generate an error, the system may not trust the execution of either the left or right instruction. In cases where an exception is detected, the system may process each instruction individually. In some embodiments, the system may resume execution of the unfused instructions from the first half of the original fused pair, and then from the second half of the original fused pair.

[0053] In some embodiments, an exception may be applied to the appropriate scalar half of the original fused instruction, and the appropriate scalar half may be processed in the same way that the system normally processes an instruction with an exception.

[0054] Referring here to Figure 3, a block diagram of an exemplary microprocessor 300 configured to combine register tag data according to an embodiment of the present invention is illustrated. The microprocessor 300 includes dispatch lanes (Ins0) 310A and (Ins1) 310B, a mapper 320, an issue queue (ISQ) 330, an STF free list 325, a save and restore buffer (SRB) 340, a vector scalar unit (VSU) 360, a left operand latch 390, and a right operand latch 392. While various components in Figure 3 are shown as standalone components, it should be understood that these various components can actually be subcomponents of larger components. It should also be understood that the microprocessor 300 can be configured so that one of its subcomponents performs the actions of another subcomponent without departing from the scope of the present invention.

[0055] In some embodiments, left scalar instructions are provided to the left operand latch 390, and right scalar instructions are provided to the right operand latch 392. Each operand latch may direct the instruction (left or right) to execution on the left or right side of the VSU 360.

[0056] A mux (e.g., issue mux312A, issue mux312B, transfer mux314A, and / or transfer mux314B) can be a multiplexer that can select between different streams and transfer the selected stream to further downstream in the process. A mux can be used to orient a left or right STF towards the corresponding STF_left381 or STF_right382 side of the physical register file 318.

[0057] An instruction dispatch unit (IDU) (e.g., IDU102) includes two dispatch lanes 310A and 310B for dispatching instructions (e.g., VSUs). The instruction dispatch unit fuses two adjacent instructions into a pair. The fused instructions may have two instruction tags (ITAGs). In some embodiments, the first ITAG is always an even ITAG. For example, the IDU (e.g., IDU102) may select the least significant bit and make it even (e.g., 0) for the first tag. In this case, the IDU only needs to send the first ITAG, because the least significant bit may later be inverted to obtain the second ITAG (e.g., to make it odd, 1). The instruction dispatch unit dispatches the instructions to the ISQ330. The instruction dispatch unit also sends a logical register to the mapper 320, which is mapped to the STF tag.

[0058] The instruction dispatch unit reads mapper 320 to identify the producer ITAG and source STF tags. It should be understood that this is a simplified example for illustrative purposes and that there are usually more than one source register, each of which may have a different producer instruction.

[0059] In mapper 320, the VSR producer ITAG is compared to the ITAG within mapper 320. This is done using comparison logic. At the matching location (i.e., where the producer ITAG matches the ITAG for the instruction in mapper 320), the ready bit is set (e.g., W=1) to indicate that the data required by the instruction is stored in the register.

[0060] In ISQ330, the VSR producer ITAG is compared to the source ITAG within ISQ330. At the matching location (i.e., where the producer ITAG matches the source ITAG for the instruction within ISQ330), the ready bits are set (for example, W=1).

[0061] In SRB340, the VSR producer ITAG is compared with the ITAG within SRB340. At the matching position (i.e., the position where the producer ITAG matches the ITAG for the instruction in SRB340), the ready bit is set (for example, W=1).

[0062] In some embodiments, a flash request may cause several number instructions to be flashed. In some embodiments, the microprocessor 300 may have multiple flash modes. For example, the microprocessor 300 may be configured to flash after an NTC instruction has not received a tag during a given number of cycles. Further or alternatively, the microprocessor 300 may be configured to flash if it determines that an instruction is not executing at the expected speed (e.g., the instruction is slowly leaving the ISQ330, which may indicate a shortage of available STF tags). In some embodiments, the microprocessor 300 may be configured to flash in response to the number of available STF tags in the free list being below a threshold. In some embodiments, the microprocessor 300 may flash an instruction if one of the fused instructions causes an exception. In some embodiments, the microprocessor 300 may consider combinations of the above (with or without other considerations) when determining whether to flash. The type of flash (e.g., full flash vs. mini hangbuster) may be determined based on which flash criteria have been met and / or the extent of the identified problem.

[0063] After flashing, the data is read from the SRB340 to the mapper320, which can restore the previous state of the microprocessor300.

[0064] In exemplary embodiments, the system (e.g., microprocessor system 100) includes a computer system 01 as shown in Figure 4, which may perform one or more of the functions / processes described above. Computer system 01 is merely one example of a computer system and is not intended to imply any limitations on the use or scope of functionality of embodiments of the present invention. Nevertheless, computer system 01 may be implemented and / or capable of performing any of the functions / operations of the present invention.

[0065] Computer system 01 includes computer system / server 12, which can operate with a number of other general-purpose or dedicated computing system environments or configurations. Examples of well-known computing systems, environments, and / or configurations that may be suitable for use with computer system / server 12 include, but are not limited to, personal computer systems, server computer systems, thin clients, thick clients, handheld or laptop devices, multiprocessor systems, microprocessor-based systems, set-top boxes, programmable consumer electronics, network PCs, minicomputer systems, mainframe computer systems, and distributed cloud computing environments that include any of the above systems or devices.

[0066] The computer system / server 12 can be described in the general context of computer system executable instructions executed by the computer system, such as program modules. Generally, program modules may include routines, programs, objects, components, logic, and / or data structures that perform a specific task or implement a specific abstract data type. The computer system / server 12 can be put into practical use in a distributed cloud computing environment where tasks are performed by remote processing devices linked through a communication network. In a distributed cloud computing environment, program modules may reside in both local computer system storage media, including memory storage devices, and remote computer system storage media.

[0067] As shown in Figure 4, the computer system / server 12 in computer system 01 is represented in the form of a general-purpose computing device. The components of the computer system / server 12 may include, but are not limited to, one or more processors or processing units 16, system memory 28, and a bus 18 that connects various system components, including the system memory 28, to the processor 16.

[0068] Bus 18 represents one or more of several types of bus structures, including memory buses or memory controllers, peripheral buses, accelerated graphics ports, and processor or local buses using any of the various bus architectures. Examples, but not limited to, such architectures include industry standard architecture (ISA) buses, microchannel architecture (MCA) buses, extended ISA (EISA) buses, video electronics standards association (VESA) local buses, and peripheral component interconnect (PCI) buses.

[0069] The computer system / server 12 typically includes various computer system-readable media. Such media can be any available media accessible by the computer system / server 12, and include both removable and non-removable media, both volatile and non-volatile.

[0070] The system memory 28 may include computer system-readable media in the form of volatile memory, such as random access memory (RAM) 30 and / or cache memory 32. The computer system / server 12 may further include other removable / non-removable, volatile / non-volatile computer system storage media. For example only, a storage system 34 may be provided for reading from and writing to a non-removable, non-volatile magnetic medium (not shown, commonly referred to as a “hard drive”). Not shown, a magnetic disk drive may be provided for reading from and writing to a removable, non-volatile magnetic disk (e.g., a “floppy disk”), and an optical disk drive may be provided for reading from and writing to a removable, non-volatile optical disk, such as a CD-ROM, DVD-ROM, or other optical medium. In such cases, each may be connected to the bus 18 by one or more data medium interfaces. As further shown and described below, the memory 28 may include at least one program product having a set of program modules (e.g., at least one) configured to perform the functions / operations of embodiments of the present invention.

[0071] The program / utility 40 has a set (at least one) of program modules 42, which may be stored in memory 28, not as an example but as an limitation. An exemplary program module 42 may include an operating system, one or more application programs, other program modules, and program data. Each of the operating system, one or more application programs, other program modules, and program data, or any combination thereof, may include an implementation of a networking environment. The program module 42 generally performs the functions and / or methods of embodiments of the present invention.

[0072] The computer system / server 12 may also communicate with one or more external devices 14, such as a keyboard, a pointing device, a display 24, one or more devices that enable a user to interact with the computer system / server 12, and / or any devices that enable the computer system / server 12 to communicate with one or more other computing devices (e.g., a network card, a modem, etc.). Such communication may occur via an input / output (I / O) interface 22. Furthermore, the computer system / server 12 may communicate with one or more networks, such as a local area network (LAN), a general wide area network (WAN), and / or a public network (e.g., the Internet), via a network adapter 20. As shown in the illustration, the network adapter 20 communicates with other components of the computer system / server 12 via a bus 18. It should be understood that other hardware and / or software components, not shown in the illustration, may be used in conjunction with the computer system / server 12. Examples include, but are not limited to, microcode, device drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives, and data archive storage systems.

[0073] The present invention may also be an integrated system, method, and / or computer program product at any possible level of technical detail. The computer program product may include a computer-readable storage medium (or a plurality of computer-readable storage media) having computer-readable program instructions for causing a processor to perform aspects of the present invention.

[0074] A computer-readable storage medium can be a tangible device capable of holding and storing instructions for use by an instruction execution device. A computer-readable storage medium may, but is not limited to, electronic storage devices, magnetic storage devices, optical storage devices, electromagnetic storage devices, semiconductor storage devices, or any preferred combination thereof. A non-exhaustive list of more specific examples of computer-readable storage media includes portable computer diskettes, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM) or flash memory, static random access memory (SRAM), compact disc read-only memory (CD-ROM), digital versatile disk (DVD), memory sticks, floppy disks, mechanically encoded devices such as punch cards or grooved structures on which instructions are recorded, and any preferred combination thereof. As used herein, a computer-readable storage medium itself is not considered to be a radio wave or other freely propagating electromagnetic wave, an electromagnetic wave propagating through a waveguide or other transmission medium (e.g., an optical pulse passing through an optical fiber cable), or a transient signal such as an electrical signal transmitted through a wire.

[0075] The computer-readable program instructions described herein may be downloaded from a computer-readable storage medium to each computing / processing device, or to an external computer or external storage device via a network, such as the Internet, a local area network, a wide area network, and / or a wireless network. The network may include copper transmission cables, optical transmission fibers, wireless transmissions, routers, firewalls, switches, gateway computers, and / or edge servers. A network adapter card or network interface within each computing / processing device receives computer-readable program instructions from the network and transfers the computer-readable program instructions for storage in the computer-readable storage medium within each computing / processing device.

[0076] The computer-readable program instructions for performing the operation of the present invention may be assembler instructions, instruction set architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, state setting data, configuration data for integrated circuits, or source code or object code written in any combination of one or more programming languages, including Smalltalk®, C++ or similar object-oriented programming languages, and procedural programming languages ​​such as the "C" programming language or similar programming languages. The computer-readable program instructions may run as a standalone software package entirely on the user's computer, partially on the user's computer, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In the latter scenario, the remote computer may be connected to the user's computer via any type of network, including a local area network (LAN) or wide area network (WAN), or the connection may be made to an external computer (for example, via the Internet using an Internet service provider). In some embodiments, to carry out aspects of the present invention, an electronic circuit including, for example, a programmable logic circuit, a field-programmable gate array (FPGA), or a programmable logic array (PLA) may execute computer-readable program instructions to customize the electronic circuit by utilizing state information of computer-readable program instructions.

[0077] Aspects of the present invention are described herein with reference to flowcharts and / or block diagrams of methods, apparatuses (systems), and computer program products according to embodiments of the present invention. It will be understood that each block in the flowcharts and / or block diagrams, and combinations of blocks within the flowcharts and / or block diagrams, can be implemented by computer-readable program instructions.

[0078] These computer-readable program instructions may be provided to the processor of a general-purpose computer, a dedicated computer, or other programmable data processing device to generate a machine, and the instructions executed via the processor of the computer or other programmable data processing device will create means for implementing functions / operations specified in one or more blocks of a flowchart and / or block diagram. These computer-readable program instructions may also be stored in a computer-readable storage medium that can instruct a computer, a programmable data processing device, and / or other device to function in a particular manner, and the computer-readable storage medium having the instructions stored therein will comprise a product containing instructions that implement modes of functions / operations specified in one or more blocks of a flowchart and / or block diagram.

[0079] Computer-readable program instructions may also be loaded onto a computer, other programmable data processing device, or other device to execute a series of operational steps on the computer, other programmable device, or other device, thereby generating a computer implementation process, the instructions executed on the computer, other programmable device, or other device, which implement the functions / operations specified in one or more blocks of a flowchart and / or block diagram.

[0080] The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of the system, method, and computer program product according to various embodiments of the present invention. In this regard, each block in the flowchart or block diagram may represent a module, segment, or portion of instructions containing one or more executable instructions for implementing a specified logical function. In some alternative implementations, the functions described within a block may occur in an order different from the order shown in the drawings. For example, two consecutively shown blocks may actually be executed substantially simultaneously, or the blocks may be executed in reverse order depending on the related functions. It should also be noted that each block in the block diagram and / or flowchart diagram, and combinations of blocks in the block diagram and / or flowchart diagram, may be implemented by a dedicated hardware-based system that performs a specified function or operation, or a combination of dedicated hardware and computer instructions.

[0081] The descriptions of various embodiments of the present invention are presented for illustrative purposes only and are not intended to be exhaustive or limitful to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope of the described embodiments. The terms used herein have been selected to describe the principles of the embodiments, their practical applications, or technological improvements beyond the technology available on the market, or to enable other those skilled in the art to understand the embodiments disclosed herein.

Claims

1. memory, and Processor that communicates with the aforementioned memory The processor is equipped with: Determining whether two instructions can be combined based on the processing capacity of the processor and the size of the two instructions; To merge the two aforementioned instructions into a pair; Mapping the two instructions to a single register tag; Writing the single register tag to the mapper, along with a first instruction bit indicating that the single register tag corresponds to the first instruction of the two instructions; Writing the single register tag to the mapper, along with a second instruction bit indicating that the single register tag corresponds to the second instruction of the two instructions; The fused instruction pair is written to the issue queue; By referring to the mapper, issue the fused instruction pair to a vector scalar conversion unit (VSU); and Execute the two aforementioned instructions A system configured to perform a process that includes the following:

2. The system according to claim 1, wherein the determination is based on the processing capacity of the vector scalar unit (VSU) and the size of the two instructions.

3. The system according to claim 1, wherein the two instructions are adjacent instructions.

4. The aforementioned process further: Reading information from the physical register from the first instruction bit and the second instruction bit. The system according to claim 1, comprising:

5. The aforementioned process further: Steering the operands of the fused instruction to one or more correct operand latches based on the position of the fused instruction. The system according to claim 4, comprising:

6. The aforementioned process further: The scalar result of the fused instruction is written to the correct register tag in the physical register file based on the first instruction bit and the second instruction bit. The system according to claim 5, comprising:

7. The two instructions mentioned above have two ITAGs, The two ITAGs mentioned above are identical except for the least significant bit; The least significant bit is even for the first instruction; The least significant bit is odd for the second instruction. The system according to claim 1.

8. A step of determining whether two instructions can be combined, based on the processing power of the processor and the size of the two instructions; The step of fusing the two aforementioned instructions into a pair; The step of mapping the two instructions to a single register tag; A step of writing the single register tag to the mapper, along with a first instruction bit indicating that the single register tag corresponds to the first instruction of the two instructions; A step of writing the single register tag to the mapper, along with a second instruction bit indicating that the single register tag corresponds to the second instruction of the two instructions; The step of writing the aforementioned fused instruction pair to the issue queue; The step of issuing the fused instruction pair to a vector-scalar conversion unit (VSU) with reference to the mapper; and The stage of executing the two aforementioned instructions. A method for providing this.

9. The method according to claim 8, wherein the determination step is based on the processing capacity of the vector scalar conversion unit (VSU) and the size of the two instructions.

10. The method according to claim 8, wherein the two instructions are adjacent instructions.

11. The aforementioned method further: Step of reading information in the physical register from the first instruction bit and the second instruction bit. The method according to claim 8, comprising:

12. The aforementioned method further: The step of steering the operands of the fused instruction to one or more correct operand latches based on the position of the fused instruction. The method according to claim 11, comprising:

13. The aforementioned method further: The step of writing the scalar result of the fused instruction to the correct register tag in the physical register file based on the first and second instruction bits. The method according to claim 12, comprising:

14. The two instructions mentioned above have two ITAGs, The two ITAGs mentioned above are identical except for the least significant bit; The least significant bit is even for the first instruction; The least significant bit is odd for the second instruction. The method according to claim 8.

15. A computer program for causing a processor to perform the method described in any one of claims 8 to 13.

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