Semiconductor equipment

Abstract

To provide a display device capable of narrowing a frame and having excellent display characteristics.SOLUTION: A display device has a switch portion or a buffer portion, a logic circuit portion, and a pixel portion. The pixel portion has a first inverted staggered thin film transistor and a pixel electrode connected to a wiring of the first inverted staggered thin film transistor. The switch portion or the buffer portion has a second inverted staggered thin film transistor having a first gate electrode and a second gate electrode sandwiching a first insulating layer, a semiconductor layer, and a second insulating layer therebetween. The logic circuit portion has an inverter circuit composed of a third inverted staggered thin film transistor and a fourth inverted staggered thin film transistor. The first to fourth inverted staggered thin film transistors have the same polarity. The inverter circuit is an EDMOS circuit.SELECTED DRAWING: Figure 7

Claims

1. It has first to sixth transistors, The source electrode or drain electrode of the first transistor is always in contact with the output signal line. The source electrode or the other drain electrode of the first transistor is always in contact with the clock signal line. The source electrode or drain electrode of the second transistor is always in conductivity with the output signal line. The source electrode or the other drain electrode of the second transistor is always in electrical contact with the power line. The source electrode or drain electrode of the third transistor is always in electrical contact with the gate electrode of the first transistor. The gate electrode of the third transistor is always in conductivity with the first signal line. The source electrode or drain electrode of the fourth transistor is always in electrical contact with the gate electrode of the second transistor. The gate electrode of the fourth transistor is always in conductivity with the first signal line. The source electrode or drain electrode of the fifth transistor is always in electrical contact with the gate electrode of the first transistor. The gate electrode of the fifth transistor is always in electrical contact with the gate electrode of the second transistor. The source electrode or drain electrode of the sixth transistor is always in electrical contact with the gate electrode of the second transistor. The gate electrode of the sixth transistor is always in conductivity with the gate electrode of the first transistor. When the source electrode or drain electrode of the third transistor is in a conductive state with the gate electrode of the first transistor and the gate electrode of the sixth transistor via at least the channel forming region of the third transistor, the potential that turns on the first transistor and the potential that turns on the sixth transistor are input to the gate electrode of the first transistor and the gate electrode of the sixth transistor via at least the channel forming region of the third transistor. When the source electrode or drain electrode of the fourth transistor is in a conductive state with the gate electrode of the second transistor and the gate electrode of the fifth transistor via at least the channel forming region of the fourth transistor, the potential that turns off the second transistor and the potential that turns off the fifth transistor are input to the gate electrode of the second transistor and the gate electrode of the fifth transistor via at least the channel forming region of the fourth transistor. When the source electrode or drain electrode of the fifth transistor is in a conductive state with the gate electrode of the first transistor and the gate electrode of the sixth transistor via at least the channel forming region of the fifth transistor, the potential that turns off the first transistor and the potential that turns off the sixth transistor are input to the gate electrode of the first transistor and the gate electrode of the sixth transistor via at least the channel forming region of the fifth transistor. When the source electrode or drain electrode of the sixth transistor is in a conductive state with the gate electrode of the second transistor and the gate electrode of the fifth transistor via at least the channel forming region of the sixth transistor, the potential that turns off the second transistor and the potential that turns off the fifth transistor are input to the gate electrode of the second transistor and the gate electrode of the fifth transistor via at least the channel forming region of the sixth transistor. The first conductive layer having a region that functions as the gate electrode of the second transistor is always electrically connected to the third conductive layer having a region that functions as the gate electrode of the fifth transistor, via the second conductive layer having a region that functions as either the source electrode or the drain electrode of the fourth transistor. The second conductive layer has a region that intersects with a fourth conductive layer, which has a region that functions as the gate electrode of the third transistor and a region that functions as the gate electrode of the fourth transistor. A semiconductor device in which, in a plan view, the channel length directions of the first to sixth transistors are aligned in the same direction.

2. It has first to sixth transistors, The source electrode or drain electrode of the first transistor is always in contact with the output signal line. The source electrode or the other drain electrode of the first transistor is always in contact with the clock signal line. The source electrode or drain electrode of the second transistor is always in conductivity with the output signal line. The source electrode or the other drain electrode of the second transistor is always in electrical contact with the power line. The source electrode or drain electrode of the third transistor is always in electrical contact with the gate electrode of the first transistor. The gate electrode of the third transistor is always in conductivity with the first signal line. The source electrode or drain electrode of the fourth transistor is always in electrical contact with the gate electrode of the second transistor. The gate electrode of the fourth transistor is always in conductivity with the first signal line. The source electrode or drain electrode of the fifth transistor is always in electrical contact with the gate electrode of the first transistor. The gate electrode of the fifth transistor is always in electrical contact with the gate electrode of the second transistor. The source electrode or drain electrode of the sixth transistor is always in electrical contact with the gate electrode of the second transistor. The gate electrode of the sixth transistor is always in conductivity with the gate electrode of the first transistor. When the source electrode or drain electrode of the third transistor is in a conductive state with the gate electrode of the first transistor and the gate electrode of the sixth transistor via at least the channel forming region of the third transistor, the potential that turns on the first transistor and the potential that turns on the sixth transistor are input to the gate electrode of the first transistor and the gate electrode of the sixth transistor via at least the channel forming region of the third transistor. When the source electrode or drain electrode of the fourth transistor is in a conductive state with the gate electrode of the second transistor and the gate electrode of the fifth transistor via at least the channel forming region of the fourth transistor, the potential that turns off the second transistor and the potential that turns off the fifth transistor are input to the gate electrode of the second transistor and the gate electrode of the fifth transistor via at least the channel forming region of the fourth transistor. When the source electrode or drain electrode of the fifth transistor is in a conductive state with the gate electrode of the first transistor and the gate electrode of the sixth transistor via at least the channel forming region of the fifth transistor, the potential that turns off the first transistor and the potential that turns off the sixth transistor are input to the gate electrode of the first transistor and the gate electrode of the sixth transistor via at least the channel forming region of the fifth transistor. When the source electrode or drain electrode of the sixth transistor is in a conductive state with the gate electrode of the second transistor and the gate electrode of the fifth transistor via at least the channel forming region of the sixth transistor, the potential that turns off the second transistor and the potential that turns off the fifth transistor are input to the gate electrode of the second transistor and the gate electrode of the fifth transistor via at least the channel forming region of the sixth transistor. The first conductive layer having a region that functions as the gate electrode of the second transistor is always electrically connected to the third conductive layer having a region that functions as the gate electrode of the fifth transistor, via the second conductive layer having a region that functions as either the source electrode or the drain electrode of the fourth transistor. The second conductive layer has a region that intersects with a fourth conductive layer in a region extending in the first direction, which has a region that functions as the gate electrode of the third transistor and a region that functions as the gate electrode of the fourth transistor. A semiconductor device in which, in a plan view, the channel length direction of the first to fourth transistors is aligned with the first direction.

3. It has transistors 1 through 8, The source electrode or drain electrode of the first transistor is always in contact with the first output signal line. The source electrode or the other drain electrode of the first transistor is always in contact with the clock signal line. The source electrode or drain electrode of the second transistor is always in conductivity with the first output signal line. The source electrode or the other drain electrode of the second transistor is always in electrical contact with the power line. The source electrode or drain electrode of the third transistor is always in electrical contact with the gate electrode of the first transistor. The gate electrode of the third transistor is always in conductivity with the first signal line. The source electrode or drain electrode of the fourth transistor is always in electrical contact with the gate electrode of the second transistor. The gate electrode of the fourth transistor is always in conductivity with the first signal line. The source electrode or drain electrode of the fifth transistor is always in electrical contact with the gate electrode of the first transistor. The gate electrode of the fifth transistor is always in electrical contact with the gate electrode of the second transistor. The source electrode or drain electrode of the sixth transistor is always in electrical contact with the gate electrode of the second transistor. The gate electrode of the sixth transistor is always in conductivity with the gate electrode of the first transistor. The source electrode or drain electrode of the seventh transistor is always in contact with the second output signal line. The source electrode or the other drain electrode of the seventh transistor is always in conductivity with the clock signal line. The gate electrode of the seventh transistor is always in electrical contact with the gate electrode of the first transistor. The source electrode or drain electrode of the eighth transistor is always in conductivity with the second output signal line. The source electrode or the other drain electrode of the eighth transistor is always in electrical contact with the power line. The gate electrode of the eighth transistor is always in electrical contact with the gate electrode of the second transistor. When the source electrode or drain electrode of the third transistor is in a conductive state with the gate electrode of the first transistor, the gate electrode of the sixth transistor, and the gate electrode of the seventh transistor via at least the channel forming region of the third transistor, the potential that turns on the first transistor, the potential that turns on the sixth transistor, and the potential that turns on the seventh transistor are input to the gate electrode of the first transistor, the gate electrode of the sixth transistor, and the gate electrode of the seventh transistor via at least the channel forming region of the third transistor, When the source electrode or drain electrode of the fourth transistor is in a conductive state with the gate electrode of the second transistor, the gate electrode of the fifth transistor, and the gate electrode of the eighth transistor via at least the channel forming region of the fourth transistor, the potential that turns off the second transistor, the potential that turns off the fifth transistor, and the potential that turns off the eighth transistor are input to the gate electrode of the second transistor, the gate electrode of the fifth transistor, and the gate electrode of the eighth transistor via at least the channel forming region of the fourth transistor, When the source electrode or drain electrode of the fifth transistor is in a conductive state with the gate electrode of the first transistor, the gate electrode of the sixth transistor, and the gate electrode of the seventh transistor via at least the channel forming region of the fifth transistor, the potential that turns off the first transistor, the potential that turns off the sixth transistor, and the potential that turns off the seventh transistor are input to the gate electrode of the first transistor, the gate electrode of the sixth transistor, and the gate electrode of the seventh transistor via at least the channel forming region of the fifth transistor, When the source electrode or drain electrode of the sixth transistor is in a conductive state with the gate electrode of the second transistor, the gate electrode of the fifth transistor, and the gate electrode of the eighth transistor via at least the channel forming region of the sixth transistor, the potential that turns off the second transistor, the potential that turns off the fifth transistor, and the potential that turns off the eighth transistor are input to the gate electrode of the second transistor, the gate electrode of the fifth transistor, and the gate electrode of the eighth transistor via at least the channel forming region of the sixth transistor. The first conductive layer having a region that functions as the gate electrode of the second transistor is always electrically connected to the third conductive layer having a region that functions as the gate electrode of the fifth transistor, via the second conductive layer having a region that functions as either the source electrode or the drain electrode of the fourth transistor. The second conductive layer has a region that intersects with a fourth conductive layer, which has a region that functions as the gate electrode of the third transistor and a region that functions as the gate electrode of the fourth transistor. A semiconductor device in which, in a plan view, the channel length directions of the first to sixth transistors are aligned in the same direction.

4. It has transistors 1 through 8, The source electrode or drain electrode of the first transistor is always in contact with the first output signal line. The source electrode or the other drain electrode of the first transistor is always in contact with the clock signal line. The source electrode or drain electrode of the second transistor is always in conductivity with the first output signal line. The source electrode or the other drain electrode of the second transistor is always in electrical contact with the power line. The source electrode or drain electrode of the third transistor is always in electrical contact with the gate electrode of the first transistor. The gate electrode of the third transistor is always in conductivity with the first signal line. The source electrode or drain electrode of the fourth transistor is always in electrical contact with the gate electrode of the second transistor. The gate electrode of the fourth transistor is always in conductivity with the first signal line. The source electrode or drain electrode of the fifth transistor is always in electrical contact with the gate electrode of the first transistor. The gate electrode of the fifth transistor is always in electrical contact with the gate electrode of the second transistor. The source electrode or drain electrode of the sixth transistor is always in electrical contact with the gate electrode of the second transistor. The gate electrode of the sixth transistor is always in conductivity with the gate electrode of the first transistor. The source electrode or drain electrode of the seventh transistor is always in contact with the second output signal line. The source electrode or the other drain electrode of the seventh transistor is always in conductivity with the clock signal line. The gate electrode of the seventh transistor is always in electrical contact with the gate electrode of the first transistor. The source electrode or drain electrode of the eighth transistor is always in conductivity with the second output signal line. The source electrode or the other drain electrode of the eighth transistor is always in electrical contact with the power line. The gate electrode of the eighth transistor is always in electrical contact with the gate electrode of the second transistor. When the source electrode or drain electrode of the third transistor is in a conductive state with the gate electrode of the first transistor, the gate electrode of the sixth transistor, and the gate electrode of the seventh transistor via at least the channel forming region of the third transistor, the potential that turns on the first transistor, the potential that turns on the sixth transistor, and the potential that turns on the seventh transistor are input to the gate electrode of the first transistor, the gate electrode of the sixth transistor, and the gate electrode of the seventh transistor via at least the channel forming region of the third transistor, When the source electrode or drain electrode of the fourth transistor is in a conductive state with the gate electrode of the second transistor, the gate electrode of the fifth transistor, and the gate electrode of the eighth transistor via at least the channel forming region of the fourth transistor, the potential that turns off the second transistor, the potential that turns off the fifth transistor, and the potential that turns off the eighth transistor are input to the gate electrode of the second transistor, the gate electrode of the fifth transistor, and the gate electrode of the eighth transistor via at least the channel forming region of the fourth transistor, When the source electrode or drain electrode of the fifth transistor is in a conductive state with the gate electrode of the first transistor, the gate electrode of the sixth transistor, and the gate electrode of the seventh transistor via at least the channel forming region of the fifth transistor, the potential that turns off the first transistor, the potential that turns off the sixth transistor, and the potential that turns off the seventh transistor are input to the gate electrode of the first transistor, the gate electrode of the sixth transistor, and the gate electrode of the seventh transistor via at least the channel forming region of the fifth transistor, When the source electrode or drain electrode of the sixth transistor is in a conductive state with the gate electrode of the second transistor, the gate electrode of the fifth transistor, and the gate electrode of the eighth transistor via at least the channel forming region of the sixth transistor, the potential that turns off the second transistor, the potential that turns off the fifth transistor, and the potential that turns off the eighth transistor are input to the gate electrode of the second transistor, the gate electrode of the fifth transistor, and the gate electrode of the eighth transistor via at least the channel forming region of the sixth transistor. The first conductive layer having a region that functions as the gate electrode of the second transistor is always electrically connected to the third conductive layer having a region that functions as the gate electrode of the fifth transistor, via the second conductive layer having a region that functions as either the source electrode or the drain electrode of the fourth transistor. The second conductive layer has a region that intersects with a fourth conductive layer in a region extending in the first direction, which has a region that functions as the gate electrode of the third transistor and a region that functions as the gate electrode of the fourth transistor. A semiconductor device in which, in a plan view, the channel length direction of the first to fourth transistors is aligned with the first direction.

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