Semiconductor equipment

Abstract

A novel shift register is provided. A transistor 101, a transistor 102, a transistor 103, and a transistor A first terminal of the transistor 101 is connected to a wiring 111. The second terminal of the transistor 101 is connected to the wiring 112. The first terminal of the transistor 102 is connected to the wiring 112. The first terminal of the transistor 102 is connected to a wiring 113, and the second terminal of the transistor 102 is connected to a wiring 112. The first terminal of the transistor 103 is connected to the wiring 113, and the gate of the transistor 103 is connected to the wiring 113. The first terminal of the transistor 104 is connected to the wiring 111 or the wiring 119. The second terminal of the transistor 104 is connected to the second terminal of the transistor 103. The gate of transistor 104 is connected to the gate of transistor 102. and is connected.

Claims

1. A device comprising a first transistor to a seventh transistor and a first wiring to a sixth wiring, Either the source or the drain of the first transistor is electrically connected to the first wiring. The source or drain of the first transistor, the other of which is electrically connected to the second wiring, Either the source or the drain of the second transistor is electrically connected to the third wiring. The source or drain of the second transistor, the other of which is electrically connected to the first wiring, Either the source or the drain of the third transistor is electrically connected to the third wiring. The source or drain of the third transistor is electrically connected to the source or drain of the fourth transistor. The gate of the third transistor is electrically connected to the fourth wiring. The source or drain of the fourth transistor, the other of which is electrically connected to the gate of the first transistor, The gate of the fourth transistor is electrically connected to the gate of the second transistor. Either the source or the drain of the fifth transistor is electrically connected to the gate of the first transistor. The source or drain of the fifth transistor, the other of which is electrically connected to the fifth wiring, The gate of the fifth transistor is electrically connected to the fifth wiring, Either the source or the drain of the sixth transistor is electrically connected to the gate of the second transistor. The source or drain of the sixth transistor, the other of which is electrically connected to the sixth wiring, The gate of the sixth transistor is electrically connected to the sixth wiring, Either the source or the drain of the seventh transistor is electrically connected to the third wiring. The source or drain of the seventh transistor, the other of which is electrically connected to the gate of the second transistor, The gate of the seventh transistor is electrically connected to the gate of the first transistor. The fourth wiring is to which the first clock signal is input. Semiconductor equipment.

2. A device comprising a first transistor to a seventh transistor and a first wiring to a sixth wiring, Either the source or the drain of the first transistor is electrically connected to the first wiring. The source or drain of the first transistor, the other of which is electrically connected to the second wiring, Either the source or the drain of the second transistor is electrically connected to the third wiring. The source or drain of the second transistor, the other of which is electrically connected to the first wiring, Either the source or the drain of the third transistor is electrically connected to the third wiring. The source or drain of the third transistor is electrically connected to the source or drain of the fourth transistor. The gate of the third transistor is electrically connected to the fourth wiring. The source or drain of the fourth transistor, the other of which is electrically connected to the gate of the first transistor, The gate of the fourth transistor is electrically connected to the gate of the second transistor. Either the source or the drain of the fifth transistor is electrically connected to the gate of the first transistor. The source or drain of the fifth transistor, the other of which is electrically connected to the fifth wiring, The gate of the fifth transistor is electrically connected to the fifth wiring, Either the source or the drain of the sixth transistor is electrically connected to the gate of the second transistor. The source or drain of the sixth transistor, the other of which is electrically connected to the sixth wiring, The gate of the sixth transistor is electrically connected to the sixth wiring, Either the source or the drain of the seventh transistor is electrically connected to the third wiring. The source or drain of the seventh transistor, the other of which is electrically connected to the gate of the second transistor, The gate of the seventh transistor is electrically connected to the gate of the first transistor. The first wiring has the function of outputting a first signal, The second wiring is input to the second clock signal. The third wiring is supplied with the first power supply voltage. The fourth wiring is input to the first clock signal. The fifth wiring is input to the second signal. The sixth wiring is to receive the third clock signal. Semiconductor equipment.

3. A device comprising a first transistor to a seventh transistor and a first wiring to a sixth wiring, Either the source or the drain of the first transistor is electrically connected to the first wiring. The source or drain of the first transistor, the other of which is electrically connected to the second wiring, Either the source or the drain of the second transistor is electrically connected to the third wiring. The source or drain of the second transistor, the other of which is electrically connected to the first wiring, Either the source or the drain of the third transistor is electrically connected to the third wiring. The source or drain of the third transistor is electrically connected to the source or drain of the fourth transistor. The gate of the third transistor is electrically connected to the fourth wiring. The source or drain of the fourth transistor, the other of which is electrically connected to the gate of the first transistor, The gate of the fourth transistor is electrically connected to the gate of the second transistor. Either the source or the drain of the fifth transistor is electrically connected to the gate of the first transistor. The source or drain of the fifth transistor, the other of which is electrically connected to the fifth wiring, The gate of the fifth transistor is electrically connected to the fifth wiring, Either the source or the drain of the sixth transistor is electrically connected to the gate of the second transistor. The source or drain of the sixth transistor, the other of which is electrically connected to the sixth wiring, The gate of the sixth transistor is electrically connected to the sixth wiring, Either the source or the drain of the seventh transistor is electrically connected to the third wiring. The source or drain of the seventh transistor, the other of which is electrically connected to the gate of the second transistor, The gate of the seventh transistor is electrically connected to the gate of the first transistor. The fourth transistor has a larger ratio of channel width to channel length than the seventh transistor. The fourth wiring is to which the first clock signal is input. Semiconductor equipment.

4. A device comprising a first transistor to a seventh transistor and a first wiring to a sixth wiring, Either the source or the drain of the first transistor is electrically connected to the first wiring. The source or drain of the first transistor, the other of which is electrically connected to the second wiring, Either the source or the drain of the second transistor is electrically connected to the third wiring. The source or drain of the second transistor, the other of which is electrically connected to the first wiring, Either the source or the drain of the third transistor is electrically connected to the third wiring. The source or drain of the third transistor is electrically connected to the source or drain of the fourth transistor. The gate of the third transistor is electrically connected to the fourth wiring. The source or drain of the fourth transistor, the other of which is electrically connected to the gate of the first transistor, The gate of the fourth transistor is electrically connected to the gate of the second transistor. Either the source or the drain of the fifth transistor is electrically connected to the gate of the first transistor. The source or drain of the fifth transistor, the other of which is electrically connected to the fifth wiring, The gate of the fifth transistor is electrically connected to the fifth wiring, Either the source or the drain of the sixth transistor is electrically connected to the gate of the second transistor. The source or drain of the sixth transistor, the other of which is electrically connected to the sixth wiring, The gate of the sixth transistor is electrically connected to the sixth wiring, Either the source or the drain of the seventh transistor is electrically connected to the third wiring. The source or drain of the seventh transistor, the other of which is electrically connected to the gate of the second transistor, The gate of the seventh transistor is electrically connected to the gate of the first transistor. The fourth transistor has a larger ratio of channel width to channel length than the seventh transistor. The first wiring has the function of outputting a first signal, The second wiring is input to the second clock signal. The third wiring is supplied with the first power supply voltage. The fourth wiring is input to the first clock signal. The fifth wiring is input to the second signal. The sixth wiring is to receive the third clock signal. Semiconductor equipment.

5. A device comprising a first transistor to a seventh transistor and a first wiring to a sixth wiring, Either the source or the drain of the first transistor is electrically connected to the first wiring. The source or drain of the first transistor, the other of which is electrically connected to the second wiring, Either the source or the drain of the second transistor is electrically connected to the third wiring. The source or drain of the second transistor, the other of which is electrically connected to the first wiring, Either the source or the drain of the third transistor is electrically connected to the third wiring. The source or drain of the third transistor is electrically connected to the source or drain of the fourth transistor. The gate of the third transistor is electrically connected to the fourth wiring. The source or drain of the fourth transistor, the other of which is electrically connected to the gate of the first transistor, The gate of the fourth transistor is electrically connected to the gate of the second transistor. Either the source or the drain of the fifth transistor is electrically connected to the gate of the first transistor. The source or drain of the fifth transistor, the other of which is electrically connected to the fifth wiring, The gate of the fifth transistor is electrically connected to the fifth wiring, Either the source or the drain of the sixth transistor is electrically connected to the gate of the second transistor. The source or drain of the sixth transistor, the other of which is electrically connected to the sixth wiring, The gate of the sixth transistor is electrically connected to the sixth wiring, Either the source or the drain of the seventh transistor is electrically connected to the third wiring. The source or drain of the seventh transistor, the other of which is electrically connected to the gate of the second transistor, The gate of the seventh transistor is electrically connected to the gate of the first transistor. The fifth transistor has a larger ratio of channel width to channel length than the third transistor. The fifth transistor has a larger ratio of channel width to channel length than the fourth transistor. The fourth wiring is to which the first clock signal is input. Semiconductor equipment.

6. A device comprising a first transistor to a seventh transistor and a first wiring to a sixth wiring, Either the source or the drain of the first transistor is electrically connected to the first wiring. The source or drain of the first transistor, the other of which is electrically connected to the second wiring, Either the source or the drain of the second transistor is electrically connected to the third wiring. The source or drain of the second transistor, the other of which is electrically connected to the first wiring, Either the source or the drain of the third transistor is electrically connected to the third wiring. The source or drain of the third transistor is electrically connected to the source or drain of the fourth transistor. The gate of the third transistor is electrically connected to the fourth wiring. The source or drain of the fourth transistor, the other of which is electrically connected to the gate of the first transistor, The gate of the fourth transistor is electrically connected to the gate of the second transistor. Either the source or the drain of the fifth transistor is electrically connected to the gate of the first transistor. The source or drain of the fifth transistor, the other of which is electrically connected to the fifth wiring, The gate of the fifth transistor is electrically connected to the fifth wiring, Either the source or the drain of the sixth transistor is electrically connected to the gate of the second transistor. The source or drain of the sixth transistor, the other of which is electrically connected to the sixth wiring, The gate of the sixth transistor is electrically connected to the sixth wiring, Either the source or the drain of the seventh transistor is electrically connected to the third wiring. The source or drain of the seventh transistor, the other of which is electrically connected to the gate of the second transistor, The gate of the seventh transistor is electrically connected to the gate of the first transistor. The fifth transistor has a larger ratio of channel width to channel length than the third transistor. The fifth transistor has a larger ratio of channel width to channel length than the fourth transistor. The first wiring has the function of outputting a first signal, The second wiring is input to the second clock signal. The third wiring is supplied with the first power supply voltage. The fourth wiring is input to the first clock signal. The fifth wiring is input to the second signal. The sixth wiring is to receive the third clock signal. Semiconductor equipment.

7. A device comprising a first transistor to a seventh transistor and a first wiring to a sixth wiring, Either the source or the drain of the first transistor is electrically connected to the first wiring. The source or drain of the first transistor, the other of which is electrically connected to the second wiring, Either the source or the drain of the second transistor is electrically connected to the third wiring. The source or drain of the second transistor, the other of which is electrically connected to the first wiring, Either the source or the drain of the third transistor is electrically connected to the third wiring. The source or drain of the third transistor is electrically connected to the source or drain of the fourth transistor. The gate of the third transistor is electrically connected to the fourth wiring. The source or drain of the fourth transistor, the other of which is electrically connected to the gate of the first transistor, The gate of the fourth transistor is electrically connected to the gate of the second transistor. Either the source or the drain of the fifth transistor is electrically connected to the gate of the first transistor. The source or drain of the fifth transistor, the other of which is electrically connected to the fifth wiring, The gate of the fifth transistor is electrically connected to the fifth wiring, Either the source or the drain of the sixth transistor is electrically connected to the gate of the second transistor. The source or drain of the sixth transistor, the other of which is electrically connected to the sixth wiring, The gate of the sixth transistor is electrically connected to the sixth wiring, Either the source or the drain of the seventh transistor is electrically connected to the third wiring. The source or drain of the seventh transistor, the other of which is electrically connected to the gate of the second transistor, The gate of the seventh transistor is electrically connected to the gate of the first transistor. The fifth transistor has a larger ratio of channel width to channel length than the sixth transistor. The fifth transistor has a larger ratio of channel width to channel length than the seventh transistor. The fourth wiring is to which the first clock signal is input. Semiconductor equipment.

8. A device comprising a first transistor to a seventh transistor and a first wiring to a sixth wiring, Either the source or the drain of the first transistor is electrically connected to the first wiring. The source or drain of the first transistor, the other of which is electrically connected to the second wiring, Either the source or the drain of the second transistor is electrically connected to the third wiring. The source or drain of the second transistor, the other of which is electrically connected to the first wiring, Either the source or the drain of the third transistor is electrically connected to the third wiring. The source or drain of the third transistor is electrically connected to the source or drain of the fourth transistor. The gate of the third transistor is electrically connected to the fourth wiring. The source or drain of the fourth transistor, the other of which is electrically connected to the gate of the first transistor, The gate of the fourth transistor is electrically connected to the gate of the second transistor. Either the source or the drain of the fifth transistor is electrically connected to the gate of the first transistor. The source or drain of the fifth transistor, the other of which is electrically connected to the fifth wiring, The gate of the fifth transistor is electrically connected to the fifth wiring, Either the source or the drain of the sixth transistor is electrically connected to the gate of the second transistor. The source or drain of the sixth transistor, the other of which is electrically connected to the sixth wiring, The gate of the sixth transistor is electrically connected to the sixth wiring, Either the source or the drain of the seventh transistor is electrically connected to the third wiring. The source or drain of the seventh transistor, the other of which is electrically connected to the gate of the second transistor, The gate of the seventh transistor is electrically connected to the gate of the first transistor. The fifth transistor has a larger ratio of channel width to channel length than the sixth transistor. The fifth transistor has a larger ratio of channel width to channel length than the seventh transistor. The first wiring has the function of outputting a first signal, The second wiring is input to the second clock signal. The third wiring is supplied with the first power supply voltage. The fourth wiring is input to the first clock signal. The fifth wiring is input to the second signal. The sixth wiring is to receive the third clock signal. Semiconductor equipment.

9. A device comprising a first transistor to a seventh transistor and a first wiring to a sixth wiring, Either the source or the drain of the first transistor is electrically connected to the first wiring. The source or drain of the first transistor, the other of which is electrically connected to the second wiring, Either the source or the drain of the second transistor is electrically connected to the third wiring. The source or drain of the second transistor, the other of which is electrically connected to the first wiring, Either the source or the drain of the third transistor is electrically connected to the third wiring. The source or drain of the third transistor is electrically connected to the source or drain of the fourth transistor. The gate of the third transistor is electrically connected to the fourth wiring. The source or drain of the fourth transistor, the other of which is electrically connected to the gate of the first transistor, The gate of the fourth transistor is electrically connected to the gate of the second transistor. Either the source or the drain of the fifth transistor is electrically connected to the gate of the first transistor. The source or drain of the fifth transistor, the other of which is electrically connected to the fifth wiring, The gate of the fifth transistor is electrically connected to the fifth wiring, Either the source or the drain of the sixth transistor is electrically connected to the gate of the second transistor. The source or drain of the sixth transistor, the other of which is electrically connected to the sixth wiring, The gate of the sixth transistor is electrically connected to the sixth wiring, Either the source or the drain of the seventh transistor is electrically connected to the third wiring. The source or drain of the seventh transistor, the other of which is electrically connected to the gate of the second transistor, The gate of the seventh transistor is electrically connected to the gate of the first transistor. The fourth transistor has a larger ratio of channel width to channel length than the seventh transistor. The fifth transistor has a larger ratio of channel width to channel length than the third transistor. The fifth transistor has a larger ratio of channel width to channel length than the fourth transistor. The fifth transistor has a larger ratio of channel width to channel length than the sixth transistor. The fifth transistor has a larger ratio of channel width to channel length than the seventh transistor. The fourth wiring is to which the first clock signal is input. Semiconductor equipment.

10. A device comprising a first transistor to a seventh transistor and a first wiring to a sixth wiring, Either the source or the drain of the first transistor is electrically connected to the first wiring. The source or drain of the first transistor, the other of which is electrically connected to the second wiring, Either the source or the drain of the second transistor is electrically connected to the third wiring. The source or drain of the second transistor, the other of which is electrically connected to the first wiring, Either the source or the drain of the third transistor is electrically connected to the third wiring. The source or drain of the third transistor is electrically connected to the source or drain of the fourth transistor. The gate of the third transistor is electrically connected to the fourth wiring. The source or drain of the fourth transistor, the other of which is electrically connected to the gate of the first transistor, The gate of the fourth transistor is electrically connected to the gate of the second transistor. Either the source or the drain of the fifth transistor is electrically connected to the gate of the first transistor. The source or drain of the fifth transistor, the other of which is electrically connected to the fifth wiring, The gate of the fifth transistor is electrically connected to the fifth wiring, Either the source or the drain of the sixth transistor is electrically connected to the gate of the second transistor. The source or drain of the sixth transistor, the other of which is electrically connected to the sixth wiring, The gate of the sixth transistor is electrically connected to the sixth wiring, Either the source or the drain of the seventh transistor is electrically connected to the third wiring. The source or drain of the seventh transistor, the other of which is electrically connected to the gate of the second transistor, The gate of the seventh transistor is electrically connected to the gate of the first transistor. The fourth transistor has a larger ratio of channel width to channel length than the seventh transistor. The fifth transistor has a larger ratio of channel width to channel length than the third transistor. The fifth transistor has a larger ratio of channel width to channel length than the fourth transistor. The fifth transistor has a larger ratio of channel width to channel length than the sixth transistor. The fifth transistor has a larger ratio of channel width to channel length than the seventh transistor. The first wiring has the function of outputting a first signal, The second wiring is input to the second clock signal. The third wiring is supplied with the first power supply voltage. The fourth wiring is input to the first clock signal. The fifth wiring is input to the second signal. The sixth wiring is to receive the third clock signal. Semiconductor equipment.

Images