Indication device

Abstract

To provide a display device capable of properly transferring information on an adaptable image format, to an image source.SOLUTION: The display device capable of displaying an image received from an image source comprises: a selection unit which selects either first identification data as identification information on a format receivable from the image source by the display device or second identification data smaller than the first identification data in data size; a detection unit which detects a data transfer amount in transfer of the first identification data from the display device to the image source; and an image source control unit which causes the image source to read the first identification data or the second identification data selected by the selection unit. The selection unit selects the second identification data, in a case where the data transfer amount detected by the detection unit is smaller than the data size of the first identification data.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to a display device.

Background Art

[0002] In recent years, as an interface for connecting between a video transmission device as a video source (hereinafter referred to as a source device) and a video reception device that displays the video received from the source device (hereinafter referred to as a sink device), HDMI (registered trademark, High Definition Multimedia Interface) is widely used. When the source device and the sink device are connected by HDMI, the source device reads EDID (Extended Display Identification Data) from the sink device. By reading this EDID, the source device can transmit a video signal suitable for the performance (e.g., resolution, etc.) of the sink device to the sink device.

[0003] In this regard, Patent Document 1 proposes a configuration in which when the sink device cannot normally reproduce video, audio, etc., the format data regarding video, audio, etc. in the EDID is changed to cause the source device to read the EDID again.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] In HDMI, the size of EDID data that can be read by the source device varies depending on the standard (e.g., version). Therefore, depending on the HDMI standard supported by the source device, it may not be possible to read all of the EDID from the sink device, and only some of the data may be read. In this case, the source device may not be able to transmit a video signal in the optimal format for the sink device. Patent Document 1 describes a method applicable when the source device can read all of the EDID information, and does not solve this problem.

[0006] One embodiment of the present invention provides a display device capable of appropriately transferring information regarding compatible video formats to a video source. [Means for solving the problem]

[0007] A display device according to one embodiment of the present invention is a display device capable of displaying video received from a video source, comprising: a selection unit that selects either first identification data as identification information relating to a format that the display device can accept from the video source, or second identification data having a smaller data size than the first identification data; a detection unit that detects the amount of data transferred when the first identification data is transferred from the display device to the video source; and a video source control unit that causes the video source to read out either the first identification data or the second identification data selected by the selection unit, wherein the selection unit selects the second identification data if the amount of data transferred detected by the detection unit is smaller than the data size of the first identification data. [Brief explanation of the drawing]

[0008] [Figure 1] A block diagram of the video display system according to the first embodiment. [Figure 2] A block diagram of the video display system according to the first embodiment. [Figure 3A] Timing chart of various signals during EDID reading in the video display system according to the first embodiment. [Figure 3B]A sequence diagram showing the operation of the sink device and source device when reading EDID in the video display system according to the first embodiment. [Figure 4A] Timing chart of various signals during EDID reading in the video display system according to the first embodiment. [Figure 4B] A sequence diagram showing the operation of the sink device and source device when reading EDID in the video display system according to the first embodiment. [Figure 5] A flowchart illustrating the operation of the sink device according to the first embodiment. [Figure 6] A conceptual diagram showing the configuration of the basic block of EDID according to the second embodiment. [Figure 7A] A conceptual diagram showing the configuration of the basic and extended blocks of EDID according to the second embodiment. [Figure 7B] A conceptual diagram showing the configuration of the basic and extended blocks of EDID according to the second embodiment. [Figure 8] A flowchart illustrating the operation of the sink device according to the third embodiment. [Figure 9A] A conceptual diagram showing the configuration of the basic and extended blocks of EDID according to the third embodiment. [Figure 9B] A conceptual diagram showing the configuration of the basic block of EDID according to the third embodiment. [Modes for carrying out the invention]

[0009] Embodiments of the present invention will be described below with reference to the drawings. In the drawings, the same or equivalent elements are denoted by the same reference numerals, and redundant explanations are omitted.

[0010] <First Embodiment> A display device according to the first embodiment of this invention will be described. This embodiment relates to a method for transferring EDID to a source device when a sink device and a source device are connected via HDMI.

[0011] Figure 1 is a block diagram of the video display system according to this embodiment, illustrating only the main parts related to this embodiment. As shown in the figure, the video display system 1 comprises a sink device 10 and a source device 20. The sink device 10 is a display device that receives and displays video and audio information from the source device 20, which acts as a video source. Examples of the sink device 10 include, but are not limited to, a television receiver or a display device used in personal computers or digital signage. The source device 20 is the video source for the video displayed by the sink device 10 and is a video transmission device that transmits video and audio information to the sink device 10. Examples of the source device 20 include, but are not limited to, a personal computer, a game console or a recording device such as an HDR (Hard Disk Recorder). The sink device 10 and the source device 20 are connected by HDMI. The details of the sink device 10 and the source device 20 will be described next.

[0012] First, let's describe the sink device 10. As shown in Figure 1, the sink device 10 includes an EDID transmission / reception unit 11, an EDID data selection unit 12, an EDID buffer 13, an EDID communication volume detection unit 14, an HPD control unit 15, and an HDMI control unit 16.

[0013] The EDID data selection unit 12 is a selection unit that selects either first identification data or second identification data as identification information relating to a video format that the sink device 10 can accept from the source device 20. More specifically, the EDID data selection unit 12 comprises a selector 30 and a memory 31.

[0014] Memory 31 holds first identification data and second identification data as the above-mentioned identification data. This identification information is, for example, an EDID which is identification data unique to the device. Memory 31 holds EDID_A as the first identification data and further holds EDID_B as the second identification data. EDID_A as the first identification data includes a basic data block and n extended data blocks, and EDID_B as the second identification data includes a basic data block and m extended data blocks. n is a natural number, and m is zero or a natural number smaller than n. More specifically, the EDID_A according to this embodiment includes a basic block (128 bytes) conforming to the VESA (registered trademark, Video Electronics Standards Association) standard and two (n = 2) CTA (Consumer Technology Association) extended blocks (each 128 bytes), and its data size is 384 bytes. EDID_B includes a basic block (128 bytes) conforming to the same VESA standard and one (m = 1) CTA extended block (128 bytes), and its data size is 256 bytes. That is, the data size of the second identification data EDID_B is smaller than the data size of the first identification data EDID_A. Note that EDID_B is obtained by deleting or replacing some data included in, for example, the CTA extended block of EDID_A, and details thereof will be described later. Also, in this embodiment, the case where n = 2 (EDID_A is 384 bytes) and m = 1 (EDID_B is 256 bytes) is taken as an example for explanation, but it is not limited to this case.

[0015] Selector 30 selects either EDID_A or EDID_B held in memory 31 according to an instruction from HDMI control unit 16.

[0016] EDID buffer 13 temporarily holds either EDID_A or EDID_B selected by selector 30.

[0017] The EDID transmission / reception unit 11 receives an EDID read request from the source device 20. In response to the EDID read request, the EDID transmission / reception unit 11 transfers either EDID_A or EDID_B, which is held in the EDID buffer, to the source device 20 via the HDMI DDC (Display Data Channel) line.

[0018] The EDID communication volume detection unit 14 is a detection unit that detects the amount of data transferred when the first identification data is transferred from the sink device 10 to the source device 20. Specifically, the EDID communication volume detection unit 14 monitors the amount of data transmitted and received on the DDC line and detects the amount of EDID_A data transferred to the source device 20 in response to an EDID read request from the source device 20. It then notifies the HDMI control unit 16 of the detection result (amount of data transferred).

[0019] When the source device 20 is connected to the sink device 10 via HDMI, the HDMI control unit 16 instructs the selector 30 to select EDID_A and then commands the HPD control unit 15 to send an HPD signal (first signal) to the source device 20. Furthermore, if the amount of data transferred during the EDID_A transfer, as detected by the EDID communication volume detection unit 14, is less than the data volume of EDID_A (384 bytes), the HDMI control unit 16 instructs the selector 30 to select EDID_B and then commands the HPD control unit 15 to retransmit the HPD (Hot Plug Detect) signal.

[0020] The HPD control unit 15 is a video source control unit that causes the source device 20 to read out either EDID_A (first identification data) or EDID_B (second identification data) selected in the EDID data selection unit 12. Specifically, the HPD control unit 15, in accordance with the command of the HDMI control unit 16, first sends an HPD signal to the source device 20 prompting it to read EDID_A, and then, if EDID_B is selected in the EDID data selection unit 12, it sends another HPD signal to the source device 20 prompting it to read EDID_B.

[0021] Next, let's describe the source device 20. As mentioned above, the source device 20 is a device (video transmitter) that outputs video and audio to the sink device 10. When the source device 20 is connected to the sink device 10 via HDMI, it supplies a power voltage of, for example, +5V to the sink device 10 via the power line. Furthermore, when the source device 20 receives the HPD signal mentioned above from the sink device 10, it reads the EDID from the sink device 10 and, based on the read EDID, transfers the optimal video and audio signals to the sink device 10 via the TMDS (Transmission Minimized Differential Signaling) line.

[0022] Next, the operation of the video display system 1 with the above configuration will be explained, with particular attention paid to EDID transfer. Figure 2 is a simplified diagram of the video display system 1 shown in Figure 1, and shows the signals transmitted and received between the sink device 10 and the source device 20 when the sink device 10 and the source device 20 are connected by HDMI.

[0023] As shown in Figure 2, when the sink device 10 and the source device 20 are connected via HDMI, a voltage of +5V is transferred from the source device 20 to the sink device 10, for example, via the HDMI power line. In response to the supply of the +5V voltage, the sink device 10, under the command of the HDMI control unit 16, has the HPD control unit 15 output an HPD signal to the source device 20. In response to receiving the HPD signal, the source device 20 reads the EDID held in the EDID buffer 13 from the sink device 10. Subsequently, the source device 20 determines the output video format based on the EDID and transmits the video signal to the sink device 10 in the determined video format.

[0024] The above operation will be explained in more detail below. In this embodiment, the sink device 10 holds, for example, EDID_A of 384 bytes and EDID_B of 256 bytes. In the initial state (immediately after the sink device 10 is connected to the source device 20 via HDMI), the HDMI control unit 16 causes the selector 30 to select EDID_A. As mentioned above, EDID_A is held in the EDID buffer 13. The EDID data format is defined by VESA, with 128 bytes per block, and the performance of the sink device 10 is described in each block. Details of each block of EDID will be explained in the second embodiment, but broadly speaking, they are as follows.

[0025] In other words, the basic blocks (Block0: bytes 1-128) of EDID_A and EDID_B contain the minimum specifications of the sink device 10. These basic blocks include 2K video information but not audio information. EDID_A further includes a first CTA extension block (Block1: bytes 129-256) and a second CTA extension block (Block2: bytes 257-384). EDID_B further includes a first CTA extension block (Block1: bytes 129-256). Details of each of these CTA extension blocks will be described later in the second embodiment using Figures 7A and 7B.

[0026] The first CTA extension block of EDID_A may include 4K compatible format information with a maximum refresh rate of 60Hz or 120Hz, or 8K compatible format information with a maximum refresh rate of 30Hz, depending on the video formats supported by the sink device 10. Similarly, the second CTA extension block of EDID_A and the first CTA extension block of EDID_B may include 4K compatible format information with a maximum refresh rate of 144Hz or 240Hz, or 8K compatible format information with a maximum refresh rate of 60Hz, depending on the video formats supported by the sink device 10. Note that "refresh rate" is a unit representing the number of frames that can be displayed per second on the video displaying side, i.e., the sink device 10, and may be referred to as "frame rate" below, indicating the number of images that can be transmitted to the sink device 10.

[0027] In this example, we will explain the case where the sink device 10 supports 4K video with a refresh rate of 144Hz or 240Hz. Therefore, the second CTA extension block of EDID_A and the first CTA extension block of EDID_B contain 4K-compatible format information with a refresh rate of 144Hz or 240Hz.

[0028] Of the EDID Blocks 0 and 2 described above, the extent to which source device 20 can read is determined by the HDMI standard supported by source device 20. Specifically, if the supported standard is HDMI 1.2 or earlier, source device 20 can only read the basic block, i.e., Block 0 (128 bytes). If the supported standard is HDMI 1.4 or later, it can read the basic block and the first CTA block, i.e., Blocks 0 and 1 (256 bytes). And if the supported standard is HDMI 2.1, it can read all of the basic block and the first and second CTA blocks, i.e., Blocks 0 to 3 (384 bytes).

[0029] First, using Figures 3A and 3B, we will explain the case where the source device 20 supports HDMI 2.1 and can read 384 bytes of EDID_A. Figure 3A is a timing chart of the signals transmitted and received between the sink device 10 and the source device 20. Figure 3B is a sequence diagram showing the processing flow between the sink device 10 and the source device 20.

[0030] As shown in the figure, at time t1, the source device 20 turns on the HDMI power supply, supplying +5V to the sink device 10 via the power line. Then, at time t2, the HPD control unit 15 of the sink device 10 turns on the HPD signal. That is, the HPD control unit 15 outputs an HPD signal, and the HPD signal changes from the "L" level to the "H" level. Triggered by the HPD signal being set to the "H" level, at time t3, the source device 20 begins reading EDID_A from the sink device 10. Note that the DDC line used for transmitting and receiving EDID is also used for transmitting and receiving signals other than EDID. For example, in the example in Figure 3A, at time t1, when +5V is supplied from the source device 20, signal transmission and reception begins via the DDC line. The EDID communication volume detection unit 14 in the sink device 10 detects a read to the beginning address of the area where EDID_A is held in the EDID buffer 13, and begins measuring the amount of EDID_A data read by the source device 20.

[0031] First, source device 20 reads bytes 1-128 of EDID_A, i.e., basic block Block0, from the EDID buffer 13 of sink device 10. This allows source device 20 to obtain the minimum specification information of sink device 10 (e.g., a television receiver). Next, source device 20 reads bytes 129-256 of EDID_A, i.e., CTA extension block Block1, from the EDID buffer 13 of sink device 10. This allows source device 20 to obtain information on 4K compatible formats with a maximum refresh rate of 60Hz or 120Hz, or 8K compatible formats with a maximum refresh rate of 30Hz, which are supported by sink device 10. Furthermore, source device 20 reads bytes 257-384 of EDID_A, i.e., CTA extension block Block2, from the EDID buffer 13 of sink device 10. This allows source device 20 to obtain information on 4K compatible formats with a maximum refresh rate of 144Hz or 240Hz, which are supported by sink device 10. Of course, if the sync device 10 supports 8K video with a refresh rate of 60Hz, it is possible to obtain the relevant format information.

[0032] The source device 20 reads the CTA extension block Block2, which allows the sink device 10 to detect that it supports 4K video with a refresh rate of 144Hz or 240Hz. Therefore, from time t5 onward, the source device 20 transmits 4K video and audio signals with a refresh rate of 144Hz or 240Hz to the sink device 10 via the TMDS line. The sink device 10 then plays back the 4K video and audio signals with a refresh rate of 144Hz or 240Hz.

[0033] Next, we will explain the case where the source device 20 does not support HDMI 2.1, but rather supports, for example, HDMI 1.4 or HDMI 2.0, and can only read up to 256 bytes of EDID. Figure 4A is a timing chart of the signals transmitted and received between the sink device 10 and the source device 20, and Figure 4B is a sequence diagram showing the processing flow between the sink device 10 and the source device 20, corresponding to Figures 3A and 3B described above, respectively.

[0034] As shown in the diagram, the operation from time t1 to t3 is as described in Figures 3A and 3B. The difference from the cases in Figures 3A and 3B is that from time t3, after the source device 20 starts reading EDID_A from the sink device 10, the source device 20 only reads the information from bytes 1 to 256 of the 384 bytes of EDID_A, namely the basic block Block0 and the CTA extension block Block1. Once the source device 20 has read these two blocks, Block0 and Block1, it stops reading the rest of EDID_A. At this point, the EDID communication volume detection unit 14 of the sink device 10 can detect the amount of data transferred when EDID_A is read by the source device 20.

[0035] As mentioned above, in this example, source device 20 can only read Block0 and Block1 of EDID_A. Therefore, source device 20 cannot detect that sink device 10 supports 4K video with a refresh rate of 144Hz or 240Hz. The EDID communication volume detection unit 14 also detects that the amount of data read by source device 20 is 256 bytes and notifies the HDMI control unit 16 of this information.

[0036] The HDMI control unit 16 recognizes that the amount of EDID_A data read by the source device 20 is 256 bytes, which is less than the total amount of EDID_A data, which is 384 bytes. The HDMI control unit 16 then instructs the HPD control unit 15 to stop outputting the HPD signal. Specifically, the HPD control unit 15 changes the HPD signal from "H" level to "L" level at time t7. In other words, the sink device 10 turns off the HPD. Because the HPD signal is set to "L," the source device 20 detects that the connection with the sink device 10 has been disconnected and temporarily stops transmitting and receiving signals with the sink device 10. For example, the source device 20 does not transmit video signals or other data to the sink device 10.

[0037] In the sink device 10, the HDMI control unit 16 determines that the amount of data transferred detected by the EDID communication volume detection unit 14 is less than the data size of EDID_A (384 bytes), and therefore instructs the selector 30 to select EDID_B from memory 31. That is, in the sink device 10, information regarding low-priority functions is excluded, and a 256-byte EDID is selected that includes information indicating support for 144Hz or 240Hz 4K video formats. This EDID_B is held in the EDID buffer 13. Then, at the command of the HDMI control unit 16, the HPD control unit 15 outputs the HPD signal again at time t8. That is, at time t7, the HPD control unit 15 changes the HPD signal from "H" level to "L" level, and then from "L" level to "H" level to retransmit the HPD signal, causing the source device 20 to read EDID_B.

[0038] In response to the output of the HPD signal, the source device 20 detects the reconnection with the sink device 10 and resumes reading the EDID from the sink device 10. That is, the source device 20 reads the EDID from the sink device 10 during the period from time t9 to t10. At this time, the EDID read is EDID_B, which is held in the EDID buffer 13.

[0039] The source device 20 first reads bytes 1 to 128 of EDID_B, i.e., the basic block Block0, from the EDID buffer 13 of the sink device 10. This allows the source device 20 to obtain the minimum specification information of the sink device 10 (e.g., a television receiver). The source device 20 then reads bytes 129 to 256 of EDID_B, i.e., the CTA extension block Block1, from the EDID buffer 13 of the sink device 10. This allows the source device 20 to recognize that the sink device 10 supports 4K video with a refresh rate of 144Hz or 240Hz. Therefore, from time t11 onward, the sink device 10 sends 4K video and audio signals with a refresh rate of 144Hz or 240Hz to the sink device 10, and the sink device 10 plays them back.

[0040] Figure 5 is a flowchart showing the processing flow of the sink device 10 when performing the above operation. As shown in the figure, first in step S10, the selector 30 selects 384 bytes of EDID_A in accordance with the command of the HDMI control unit 16 and sets this as the initial EDID of the sink device 10 in the EDID buffer 13. In step S11, the sink device 10 is connected to the source device 20 via HDMI. More specifically, as described above, a +5V power supply voltage is supplied from the source device 20 to the sink device 10, and the HPD control unit 15 outputs an HPD signal in accordance with the command of the HDMI control unit 16. In step S12, the EDID held in the EDID buffer 13 of the sink device 10 is read to the source device 20 via the DDC line. In step S13, the EDID communication volume detection unit 14 measures the amount of data communication on the DDC line in step S12, more specifically the amount of EDID data communication. As explained in Figure 3A, data transmission and reception via the DDC line begin at time t1, but the processing in step S12 may begin from the moment access is made to the address where the EDID is held in the EDID buffer 13. For example, the EDID communication volume detection unit 14 may hold information about the starting address of the area where the EDID is held in the EDID buffer 13.

[0041] In step S14, if the amount of EDID communication data measured by the EDID communication amount detection unit 14 of the sink device 10 is less than the total amount of EDID data, that is, less than 384 bytes (YES in step S14), in step S20, the HDMI control unit 16 changes the EDID of the sink device 10 from EDID_A (384 bytes) to EDID_B (256 bytes) by having the selector 30 select EDID_B and hold it in the EDID buffer 13. Then, in step S21, the HPD control unit 15 resets the output of the HPD signal, waits for the source device 20 to read the EDID, and returns to step S12. Steps S20 and S21 correspond to the cases described in Figures 4A and 4B above.

[0042] In step S14, if the amount of EDID communication data measured by the EDID communication volume detection unit 14 of the sink device 10 is not less than the total amount of EDID data, that is, if all the EDID data held in the EDID buffer 13 has been transferred to the source device 20 (NO in step S14), then in step S15, the source device 20 completes reading the EDID. In step S16, the source device 20 transmits a video signal according to the EDID. The sink device 10 receives the optimal video signal. In step S17, the sink device 10 displays the video based on the video signal received in step S16.

[0043] Subsequently, in step S18, the connection with the source device 20 is disconnected. In step S19, the HDMI control unit 16 changes the EDID of the sink device 10 back to EDID_A if necessary (if it had been changed to EDID_B).

[0044] As described above, in this embodiment, the memory 31 of the sink device 10 holds two EDIDs (EDID_A and EDID_B) with different data sizes. The EDID communication volume detection unit 14 detects the amount of data transferred when EDID_A is transferred from the sink device 10 to the source device 20. The EDID data selection unit 12 selects EDID_B (an EDID with a smaller data size than EDID_A) held in the memory 31 if the detected amount of data transferred is smaller than EDID_A. The HPD control unit 15 then causes the source device 20 to read the selected EDID_B. As a result, if the detected amount of data transferred when EDID_A is transferred is smaller than EDID_A set in the sink device 10, EDID_B is selected, and the source device 20 can obtain the appropriate EDID from the sink device 10. Since the source device 20 can obtain the appropriate EDID from the sink device 10, it can transmit video information in the appropriate format to the sink device 10.

[0045] Here, for example, in the case of a video display system where the source device 20 does not read EDID_B at times t9 to t10, the source device 20 determines the video formats that the sink device 10 can support based on Block0 and Block1, which are part of the total data of EDID_A. Block1 contains information indicating that it can support 4K video formats with a refresh rate of 60Hz or 120Hz, but it does not contain information indicating that it can support 4K video formats with a refresh rate of 144Hz or 240Hz. Therefore, the source device 20 determines that the sink device 10 does not support 4K video formats with a refresh rate of 144Hz or 240Hz, and sends a video signal to the sink device 10 in 4K video format with a refresh rate of 60Hz or 120Hz. In other words, even though the sink device 10 is capable of displaying higher-definition video, the source device 20 does not recognize this and sends a low-quality video signal with a lower refresh rate to the sink device 10. As a result, the sink device 10 may not be able to display high-definition video that would allow it to perform at its full potential.

[0046] However, in this embodiment, the memory 31 of the EDID data selection unit 12 holds not only EDID_A, but also EDID_B, which has a smaller data size than EDID_A and contains video format information that the sink device 10 can handle. EDID_B is data obtained by removing auxiliary video information from EDID_A, and includes video display information such as the refresh rate and resolution that the sink device 10 can handle. As described above, if the detected data transfer amount is smaller than EDID_A (if the source device 20 could not read all the data of EDID_A), EDID_B is selected. The sink device 10 then outputs an HPD signal again to cause the source device 20 to read EDID_B. As a result, the source device 20 cannot recognize full-spec information about the sink device 10 like EDID_A, but can recognize that the sink device 10 supports 144Hz or 240Hz 4K video formats. The source device 20 then transmits a video signal according to that format to the sink device 10. As a result, it is possible to play high-definition 4K video at 144Hz or 240Hz, fully utilizing the performance of the sink device 10.

[0047] <Second Embodiment> Next, a display device according to a second embodiment of the present invention will be described. This embodiment relates to the details of EDID_A and EDID_B described in the first embodiment above, and to a method for generating EDID_B based on EDID_A.

[0048] Figure 6 shows the configuration of the basic EDID block Block0 in accordance with the VESA standard. As shown in Figure 6, the basic block Block0 is assigned an address to each byte, and of the 128 bytes of data, the first 8 bytes are the Header, and the data from the 9th byte onward is, in order, Vendor / Product ID, EDID Structure Version / Revision, Basic Display Parameters and Features, Phosphor or Filter Chromaticity, Established Timings, Manufacturer's Reserved Timings, Standard Timing Mode, Detailed Timing #2~#4 or Display Descriptor, Extension Flags, and Check Sum. Of these, Detailed Timing #2~#4 indicates the corresponding resolution and maximum refresh rate of the sink device 10. As mentioned above, the resolution and maximum refresh rate that can be included in the basic block Block0 are 4K / 30Hz or 2K / 144Hz. For the sake of simplicity, the relationship between resolution and refresh rate may be expressed as "resolution / refresh rate" below.

[0049] The CTA extension blocks Block1 and Block2 also consist of 128 bytes of data, similar to Figure 6. As mentioned above, if the sink device 10 is compatible, Block1 can contain video format information indicating resolutions of 4K / 60Hz and 4K / 120Hz, and maximum refresh rates, while Block2 can contain video format information indicating resolutions of 4K / 144Hz, 4K / 240Hz, and 8K / 60Hz, and maximum refresh rates.

[0050] Next, we will describe the configuration of the 384-byte EDID (EDID_A in the first embodiment) which includes the basic block Block0 and the CTA extension blocks Block1 and Block2, and the 256-byte EDID (EDID_B in the first embodiment) which includes the basic block Block0 and the CTA extension block Block1.

[0051] First, let's explain the 384-byte EDID using Figure 7A. Figure 7A shows the structure of the three Block0 to Block2 in the 384-byte EDID. The basic block Block0 is as explained in Figure 6; for example, addresses "00h" to "07h" store "00FFFFFFFFFFFF00h" as a header, and address "7Eh" stores information indicating that there are two CTA extension blocks.

[0052] The structure of the first CTA extension block, Block 1, is as follows: The data at addresses "00h" to "03h" is the CTA Extension Header, and the data at "04h" to "06h" is the HF-EEODB. The data at addresses "07h" to "76h" are, in order, the Video Data Block, Audio Data Block, Speaker Allocation Data Block, Colorimetry Data Block, H14b-VSDB, HF-VSDB, Video Capability Data Block, YCbCr 4:2:0 Capability Map Data Block, HDR Static Metadata Data Block, Dolby® VSVDB, and Detailed Timing Descriptor. Addresses "77h" to "7Eh" are filled with "00h", and the data at the final address "7Fh" is the Check Sum.

[0053] The structure of the second CTA extension block, Block 2, is as follows: The data at addresses "00h" to "03h" is the CTA Extension Header, and the data at "04h" to "0Bh" is the VFDB. The data at addresses "0Ch" to "13h" is the HF-SBTMDB, and the data at "14h" to "25h" is the Detailed Timing Descriptor (4th-8th). Finally, addresses "26h" to "7Eh" are filled with "00h", and the data at the last address "7Fh" is the Check Sum.

[0054] Next, we will describe the 256-byte EDID (EDID_B in the first embodiment). The 256-byte EDID can be generated by deleting some of the data from the 384-byte EDID described in Figure 7A, and by moving some of the data in the CTA extension block Block2 to Block1. The video information included in the EDID includes information related to video display, such as resolution, and information related to video assistance, such as color correction. Reducing the information related to video assistance does not cause any problems with the video display itself.

[0055] Specifically, as shown in Figures 7A and 7B, first, the HF-EEODB at addresses "04h" to "06h" of the 384-byte EDID CTA extension block Block 1 is deleted. Then, the Video Data Block, Audio Data Block, Speaker Allocation Data Block, Colorimetry Data Block, H14b-VSDB, HF-VSDB, Video Capability Data Block, YCbCr 4:2:0 Capability Map Data Block, HDR Static Metadata Data Block, Dolby® VSVDB, and Detailed Timing Descriptor are moved from the address range "07h" to "76h" to the range "04h" to "73h". Finally, the VFDB at addresses "0Ch" to "13h" of the CTA extension block Block 2 is moved to the free area ("00h" padding) at addresses "74h" to "7Bh" in Block 1. Furthermore, the HF-SBTMDB entries in the CTA extension block Block2, from address "04h" to "0Bh", will be deleted.

[0056] As described above, the VFDB, which should normally be stored in the CTA extension block Block2, is stored in Block1, making Block2 unnecessary, and as a result, a 256-byte EDID can be generated. The 256-byte EDID may be generated by, for example, the HDMI control unit 16 copying the 384-byte EDID already stored in memory and performing the data replacement and deletion described above, or the manufacturing equipment for the sink device 10 may generate two EDIDs, a 384-byte and a 256-byte, and store them in memory 31 during the manufacturing of the sink device 10.

[0057] Next, we will explain the data that will be deleted in a 384-byte EDID. First, we will explain HF-EEODB (HDMI Forum EDID Extension Override Data Block). HF-EEODB is data that indicates the data size of an EDID when the data size of the EDID exceeds 256 bytes. In this example, since the data size of the EDID is reduced from 384 bytes to 256 bytes, HF-EEODB is unnecessary and can be deleted. Next, we will explain HF-SBTMDB (HDMI Forum Source-Based Tone Mapping Data Block). HF-SBTMDB contains color display capability information of the sink device 10 and is data for the source device 20 to send the color-adjusted video to the sink device 10 based on this information. However, source device 20, which only supports data sizes up to 256 bytes as readable EDIDs, is highly likely to not support this function. Therefore, HF-SBTMDB is unnecessary and can be deleted.

[0058] Next, we will explain the VFDB (Video Format Data Block), which is data copied from a 384-byte EDID to a 256-byte EDID. The VFDB is data stored from byte 257 onwards of the 384-byte EDID and includes 4K-compatible format information with a maximum refresh rate of 144Hz or 240Hz, and 8K-compatible format information with a maximum refresh rate of 60Hz.

[0059] As described above, by deleting unnecessary data and rewriting the video format information to more appropriate data in order to match the EDID data size to the data size that the source device 20 can handle, the sink device 10 can display high-definition video.

[0060] <Third Embodiment> Next, a display device according to the third embodiment of this invention will be described. In this embodiment, EDID_A and EDID_B are set to 256 bytes and 128 bytes, respectively, as in the first and second embodiments described above. Below, only the differences from the first and second embodiments will be described.

[0061] The configuration of the sink device 10 according to this embodiment is the same as that shown in Figure 1 of the first embodiment, but differs from the first embodiment in the following respects. Memory 31 holds EDID_A, a 256-byte first identification data EDID, which includes the basic block Block0 and one (n=1) CTA extension block Block1. Memory 31 further holds EDID_B, a 128-byte second identification data EDID, which includes the basic block Block0 but does not include the CTA extension block (m=0). The basic block Block0 of EDID_B does not contain 2K video information, but it does contain 4K-compatible format information with a maximum refresh rate of 144Hz or 240Hz.

[0062] Next, the operation of the video display system 1 according to this embodiment will be described. First, the case in which the source device 20 can read a 256-byte EDID will be described. This example corresponds to the case in which the source device 20 supports HDMI 1.4 or later standards, such as HDMI 2.0.

[0063] If the source device 20 is capable of reading a 256-byte EDID, the same operation as described in Figures 3A and 3B of the first embodiment is performed. The difference from the first embodiment is that at times t3 to t4 in Figure 3A and in Figure 3B, a 256-byte EDID_A, including the basic block Block0 and the CTA extension block Block1, is read. As a result, the source device 20 detects that the sink device 10 supports 4K / 144Hz or 4K / 240Hz, transmits the video signal to the sink device 10, and the sink device 10 displays the 4K / 144Hz or 4K / 240Hz video.

[0064] Next, we will explain the case where source device 20 cannot read the 256-byte EDID and can only read up to 128 bytes. This example corresponds to the case where source device 20 supports HDMI 1.2 or an earlier standard.

[0065] If the source device 20 can only read up to 128 bytes of EDID, the operation will be almost the same as that described in Figures 4A and 4B in the first embodiment. The difference from the first embodiment is that, at times t3 to t6 in Figure 4A and in Figure 4B, only the basic block Block 1 is read out of the 256 bytes of EDID_A which includes the basic block Block 0 and the CTA extension block Block 1, and at times t9 to t10 in Figure 4A and in Figure 4B, a 128-byte EDID_B which includes the basic block Block 0 but does not include the CTA extension block is read out. As a result, the source device 20 detects that the sink device 10 supports 4K / 144Hz or 4K / 240Hz based on EDID_B, transmits the video signal to the sink device 10, and the sink device 10 displays 4K / 144Hz or 4K / 240Hz video.

[0066] Figure 8 is a flowchart showing the processing flow of the sink device 10 when performing the above operation. The differences from Figure 5 described in the first embodiment are as follows: Instead of step S10, in step S30, the selector 30 selects a 256-byte EDID_A according to the instructions of the HDMI control unit 16 and sets it in the EDID buffer 13 as the initial EDID of the sink device 10. In step S14, if the amount of EDID communication data measured by the EDID communication volume detection unit 14 of the sink device 10 is less than the total amount of EDID data, i.e., less than 256 bytes (YES in step S14), in step S31, the HDMI control unit 16 changes the corresponding format described in EDID_B to 4K resolution. Note that this process in step S31 does not need to be performed every time the sink device 10 is connected to the source device 20; for example, it may be performed during the manufacturing of the sink device 10, and EDID_B containing information about 4K resolution may already be prepared. After step S31, in step S32 instead of step S20, the HDMI control unit 16 causes the selector 30 to select EDID_B and holds it in the EDID buffer 13, changing the EDID of the sink device 10 from 256 bytes EDID_A to 128 bytes EDID_B.

[0067] Other processes are the same as those described in Figure 5 of the first embodiment, so their explanation will be omitted.

[0068] Furthermore, in this embodiment, just as in the first embodiment, a 256-byte EDID_B can be generated based on a 384-byte EDID_A, a 128-byte EDID_B can be generated based on a 256-byte EDID_A. This method will be explained using Figures 9A and 9B. Figure 9A shows the configuration of two Block0 to Block1 in a 256-byte EDID (EDID_A in this embodiment), and Figure 9B schematically shows the configuration of Block0 in a 128-byte EDID (EDID_B in this embodiment).

[0069] First, let's explain the 256-byte EDID using Figure 9A. The configuration of the basic block Block0 and the CTA extension block Block1 is the same as that of the basic block Block0 and CTA extension block Block1 in the 384-byte EDID explained in Figure 7A. That is, the area of ​​addresses "6Ch" to "7Dh" in the basic block Block0 contains 2K resolution information as a Detailed Timing Descriptor, and the area of ​​addresses "62h" to "73h" in the CTA extension block Block1 contains 4K resolution information as a Detailed Timing Descriptor.

[0070] Next, we will explain the 128-byte EDID using Figure 9B. As shown in the figure, the 128-byte EDID only has a basic block, Block0. In the 256-byte EDID explained in Figure 9A, the area from address "6Ch" to "7Dh" of the basic block Block0 contains 4K resolution information, which is held as a Detailed Timing Descriptor in the area from address "62h" to "73h" of the CTA extension block Block1, instead of 2K resolution information. In other words, this is equivalent to replacing the 2K resolution information in the VESA basic block with 4K (or 8K) resolution information that the sink device 10 can handle.

[0071] According to this embodiment, even if the source device 20 can only read a 128-byte EDID, the same effects as in the first embodiment can be obtained. In this embodiment, the case in which the resolution information of EDID_B is replaced from 2K to 4K, which the sink device 10 supports, was used as an example. Of course, if the sink device 10 does not support 4K and only supports 2K, EDID_B will retain 2K resolution information. However, if the sink device 10 supports 4K, as explained in the above embodiment, the source device 20 can be made to recognize that the sink device 10 supports 4K video by replacing the 2K resolution information with 4K resolution information. In this way, even if only a 128-byte EDID can be used, by replacing the resolution information, it is possible to provide the source device 20 with the optimal resolution information for the sink device 10, such as 4K or 8K, and reproduce high-definition video that fully utilizes the performance of the sink device 10.

[0072] <Variations, etc.> The embodiments described above are merely examples, and various modifications are possible. For example, the first embodiment described an example where EDID_A of 384 bytes and EDID_B of 256 bytes are provided. In this example, if the source device 20 can only read EDID of 128 bytes, the source device 20 cannot obtain the 4K information stored in the EDID. In this regard, with recent HDMI standards, HDMI 1.4 or higher is the mainstream, and it is rare for only 128 bytes of EDID to be read, so this is unlikely to be a problem. However, in order to accommodate source devices 20 that can only read EDID of 128 bytes, in the configuration described in the first embodiment, the 128-byte EDID containing 4K information, as described in the third embodiment, may be stored in memory 31. That is, memory 31 may store EDID_A of 384 bytes, EDID_B of 256 bytes, and EDID_C of 128 bytes (EDID having the data structure of EDID_B in the third embodiment). Furthermore, in the operation described using Figure 5, the sink device 10 may determine which EDID to change in step S20 according to the amount of data transferred in step S13. That is, if the amount of data transferred when reading EDID_A is 256 bytes, the HDMI control unit 16 may cause the selector 30 to select EDID_B, and if the amount of data transferred is 128 bytes, it may cause EDID_C to be selected. Alternatively, EDID_B may be selected first, and if not all of the data for EDID_B is transferred, EDID_C may be selected again and an HPD signal may be output. In addition, although the above embodiment was described using the case where EDID_A has two CTA extension blocks as an example, it may have three or more CTA extension blocks. The same applies to EDID_B.

[0073] Furthermore, in the above embodiment, the case in which two EDID_A and EDID_B are pre-stored in memory 31 was described as an example. However, memory 31 may not store EDID_B. In this case, for example, if it becomes necessary to change the EDID in step S20 of Figure 5, the HDMI control unit 16 may read EDID_A from memory 31, generate EDID_B from EDID_A using the method described in the second embodiment, and store it in the EDID buffer 13. In this case, the selector 30 is not necessary. The same applies to the third embodiment.

[0074] Furthermore, in the above embodiment, an example of EDID read by the source device 20 in a case where the sink device 10 and the source device 20 are connected via HDMI has been described. However, the above embodiment is not limited to HDMI EDID. That is, it can be applied to any case in which multiple devices are connected by wire or wireless, and at least one device reads information from the other device, and the data size that can be read by the device is limited. In other words, the device from which the information is read can prepare multiple data to be read in different data sizes, and instruct the device to re-read the smaller data size according to the amount of data transferred at the time of reading.

[0075] Although several embodiments of the present invention have been described above, the invention is not limited to the above-described forms and can be modified as appropriate. Furthermore, the above configurations can be replaced with substantially similar configurations, configurations that produce similar effects, or configurations that can achieve similar objectives. [Explanation of Symbols]

[0076] 1…Video display system, 10…Sink device, 11…EDID transmission / reception unit, 12…EDID data selection unit, 13…EDID buffer, 14…EDID communication volume detection unit, 15…HPD control unit, 16…HDMI control unit, 20…Source device

Claims

1. A display device capable of displaying video received from a video source, A selection unit that selects either first identification data as identification information relating to a format that the display device can accept from the video source, or second identification data with a smaller data size than the first identification data, A detection unit that detects the amount of data transferred when transferring the first identification data from the display device to the video source, A video source control unit causes the video source to read out the first identification data or the second identification data selected in the selection unit. It is equipped with, The selection unit is a display device that selects the second identification data when the amount of data transfer detected by the detection unit is smaller than the data size of the first identification data.

2. The selection unit comprises a memory and a selector, The memory holds the first identification data and the second identification data, The selector selects the first identification data from the memory, and the video source control unit causes the video source to read the first identification data. The detection unit detects the amount of data transferred when the first identification data is read out by the video source. The display device according to claim 1, wherein when the amount of data transfer detected by the detection unit is smaller than the data size of the first identification data, the selector selects the second identification data from the memory, and the video source control unit causes the video source to read the second identification data.

3. The display device according to claim 2, wherein the first identification data and the second identification data are EDID (Extended Display Identification Data), which is device-specific identification data.

4. The first identification data includes a basic data block and n extended data blocks, The second identification data includes the basic data block and m extension data blocks, The display device according to claim 3, wherein n is a natural number and m is zero or a natural number less than n.

5. The first identification data includes the basic data block and two extended data blocks. The second identification data includes the basic data block and one extended data block. The display device according to claim 4, wherein the extended data blocks of the first identification data and the second identification data include 4K video information with a frame rate exceeding 144 Hz.

6. The first identification data includes the basic data block and one extended data block. The second identification data includes the basic data block but does not include the extended data block. The basic data block of the first identification data includes 2K video information as video resolution information, but does not include 4K video information. The display device according to claim 4, wherein the basic data block of the second identification data includes 4K video information as video resolution information, but does not include the 2K video information.

7. The display device according to claim 1, wherein the video source control unit transmits a first signal to the video source prompting it to read the second identification data when the second identification data is selected in the selection unit.

8. The display device according to claim 7, wherein the first signal is an HPD (Hot Plug Detect) signal.

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