Display panel and method for manufacturing the same

Abstract

The present application provides a display panel and a manufacturing method thereof, the manufacturing method including the steps of: providing a first substrate having a plurality of Micro-LED chips spaced apart on one side; providing a second substrate having a plurality of conductive layers on one surface; forming an insulating layer on the second substrate, the insulating layer having a plurality of opening groups, each opening group including a first opening and a second opening exposing the surface of the conductive layer, the width of the first opening being greater than the width of the P-type electrode, and the width of the second opening being greater than the width of the N-type electrode; forming a first bonding layer in the first opening and a second bonding layer in the second opening; supporting the chip body with the insulating layer, bonding the P-type electrode to the first bonding layer and bonding the N-type electrode to the second bonding layer, so that the P-type electrode is embedded in the first bonding layer and the N-type electrode is embedded in the second bonding layer.

Description

[Technical Field] 【0001】 This application claims priority to a Chinese patent application filed with the China National Intellectual Property Office on August 29, 2022, with application number 202211043484.9 and invention title "Display panel and method for manufacturing the same," the entire contents of which are incorporated into this application by reference. 【0002】 This application relates to the field of display technology, and more specifically to display panels and methods for manufacturing the same. [Background technology] 【0003】 Light-emitting diodes (LEDs) are important optoelectronic semiconductor components. LEDs are widely used as light sources due to their advantages such as low power consumption, small size, high brightness, ease of integration with integrated circuits, and high reliability. With technological advancements, Micro-LEDs have found relevant applications in the fields of display, optical communication, indoor positioning, biotechnology, and medicine. Furthermore, they are expected to expand into various fields such as wearable / implantable devices, augmented / virtual reality, automotive displays, ultra-large displays, optical communication / optical interconnects, medical detection, smart car lights, and spatial imaging, demonstrating a promising market outlook. When using Micro-LED chips in display technology, millions or even tens of millions of Micro-LED chips must be accurately and efficiently transferred to the display panel. For example, a single 4K television requires 24 million Micro-LED chips to be transferred (calculated using 4000 x 2000 x R / G / B 3 colors), requiring 2400 transfers even if 10,000 Micro-LED chips are transferred at a time. 【0004】 However, conventional technology has low accuracy in the bonding position between the Micro-LED chip and the substrate, resulting in bonding defects between the Micro-LED chip and the bonding layer. [Overview of the Initiative] [Problems that the invention aims to solve] 【0005】 Therefore, the technical problem that this application aims to solve is to overcome the bonding failure problem between the Micro-LED chip and the bonding layer in the prior art and to provide a display panel and a method for manufacturing the same. [Means for solving the problem] 【0006】 The present invention provides a first substrate having a plurality of Micro-LED chips spaced apart on one side, wherein the Micro-LED chips include a chip body and a P-type electrode and an N-type electrode located on a part of the surface on one side of the chip body; a second substrate having a plurality of conductive layers on the surface on one side; and an insulating layer being formed on the second substrate, wherein the insulating layer has a plurality of groups of openings, each group of openings including a first opening and a second opening spaced apart, and the surfaces of the conductive layers are exposed by the first opening and the second opening, respectively. A method for manufacturing a display panel is provided, comprising the steps of: making the width of the first opening greater than the width of the P-type electrode and the width of the second opening greater than the width of the N-type electrode; forming a first bonding layer in the first opening and forming a second bonding layer in the second opening; and supporting the chip body with the insulating layer, bonding the P-type electrode to the first bonding layer and bonding the N-type electrode to the second bonding layer, so that the P-type electrode is fitted into the first bonding layer and the N-type electrode is fitted into the second bonding layer. 【0007】 Optionally, the chip body includes an N-type semiconductor layer, an active layer located on a portion of one side surface of the N-type semiconductor layer, and a P-type semiconductor layer located on the surface of the active layer away from the N-type semiconductor layer, wherein the P-type electrode is located on a portion of the surface of the P-type semiconductor layer away from the active layer, and the N-type electrode is located on a portion of one side surface of the N-type semiconductor layer on the side of the active layer, the P-type semiconductor layer, and the P-type electrode, and the insulating layer supports the P-type semiconductor layer around the P-type electrode during the bonding of the P-type electrode to a first bonding layer and the bonding of the N-type electrode to a second bonding layer. 【0008】 The method optionally further includes forming a first inclined surface near the boundary between the side wall of the first opening and the top surface of the insulating layer surrounding the first opening before forming a first bonding layer in the first opening, and forming a second inclined surface near the boundary between the side wall of the second opening and the top surface of the insulating layer surrounding the second opening before forming a second bonding layer in the second opening. 【0009】 Optionally, there is a first included angle between the top surface of the insulating layer connected to the first inclined surface and the first inclined surface, where tan(180°-θ1)>μ1, θ1 is the first included angle, and μ1 is the coefficient of friction of the first inclined surface. 【0010】 Optionally, there is a second included angle between the top surface of the insulating layer connected to the second inclined surface and the second inclined surface, where tan(180°-θ2)>μ2, θ2 is the second included angle, and μ2 is the coefficient of friction of the second inclined surface. 【0011】 The method further includes optionally forming a barrier layer in the insulating layer around the aperture group before bonding the P-type electrode to the first bonding layer and the N-type electrode to the second bonding layer, wherein the barrier layer has a third aperture and the width of the third aperture is greater than the width of the Micro-LED chip. 【0012】 Optionally, the width of the third aperture is 1.5 times or less the width of the Micro-LED chip. 【0013】 Optionally, the barrier layer is a light-shielding barrier layer. 【0014】 Optionally, the material of the light-shielding barrier layer is a light-shielding resin. 【0015】 The method further optionally includes the step of making the height of the top surface of the barrier layer away from the second substrate greater than the height of the top surface of the Micro-LED chip away from the second substrate, after bonding the P-type electrode to the first bonding layer and the N-type electrode to the second bonding layer. 【0016】 In the process of optionally bonding the P-type electrode to the first bonding layer and the N-type electrode to the second bonding layer, the binding device employed has a specific alignment accuracy, the width of the first aperture is greater than or equal to the sum of the width of the P-type electrode and twice the specific alignment accuracy, and the width of the second aperture is greater than or equal to the sum of the width of the N-type electrode and twice the specific alignment accuracy. 【0017】 In the step of optionally forming a first bonding layer in a first opening and a second bonding layer in a second opening, the thickness of the first bonding layer is 80% or more of the depth of the first opening and less than or equal to the depth of the first opening, and the thickness of the second bonding layer is 80% or more of the depth of the second opening and less than or equal to the depth of the second opening. 【0018】 Optionally, the thickness of the insulating layer is 50% or less of the difference in thickness between the N-type electrode and the P-type electrode. 【0019】 The thickness of the insulating layer is optionally 500 nm to 1000 nm. 【0020】 Optionally, the materials for the first bonding layer and the second bonding layer are solder, or the materials for the first bonding layer and the second bonding layer are conductive adhesives. 【0021】 This application provides a display panel comprising a first substrate having a plurality of Micro-LED chips provided at intervals on one side, wherein the Micro-LED chips include a chip body, a P-type electrode and an N-type electrode located on a part of the surface on one side of the chip body, a first substrate, a second substrate having a plurality of conductive layers on one side surface, and an insulating layer located on one side of the second substrate, wherein the insulating layer has a plurality of opening groups, each opening group includes a first opening and a second opening provided at intervals, the first opening and the second opening are respectively located in the conductive layer, the width of the first opening is larger than the width of the P-type electrode, the width of the second opening is larger than the width of the N-type electrode, an insulating layer, a first bonding layer located in the first opening, and a second bonding layer located in the second opening, wherein the P-type electrode is fitted into the first bonding layer, the N-type electrode is fitted into the second bonding layer, and the chip body contacts the top surface of a part of the insulating layer. 【0022】 Optionally, the chip body includes an N-type semiconductor layer, an active layer located on a part of the surface on one side of the N-type semiconductor layer, and a P-type semiconductor layer located on the surface of the active layer on the side away from the N-type semiconductor layer, the P-type electrode is located on a part of the surface on the side away from the active layer of the P-type semiconductor layer, the N-type electrode is located on a part of the surface on one side of the N-type semiconductor layer on the side of the active layer, the P-type semiconductor layer, and the side of the P-type electrode, and the P-type semiconductor layer around the P-type electrode contacts the top surface of the insulating layer around the first opening. 【0023】 Optionally, there is a first inclined surface between the side wall of the first opening and the top surface of the insulating layer around the first opening, and a second inclined surface between the side wall of the second opening and the top surface of the insulating layer around the second opening. 【0024】 Optionally, there is a first included angle between the top surface of the insulating layer connected to the first inclined surface and the first inclined surface, and tan(180° - θ1) > μ1, where θ1 is the first included angle and μ1 is the friction coefficient of the first inclined surface. 【0025】 Optionally, there is a second included angle between the top surface of the insulating layer connected to the second inclined surface and the second inclined surface, and tan(180° - θ2) > μ2, where θ2 is the second included angle and μ2 is the friction coefficient of the second inclined surface. 【0026】 Optionally, it further includes a barrier layer located on the insulating layer around the opening group, there is a third opening in the barrier layer, and the width of the third opening is larger than the width of the Micro-LED chip. 【0027】 Optionally, the width of the third opening is 1.5 times or less of the width of the Micro-LED chip. 【0028】 Optionally, the barrier layer is a light-shielding barrier layer. 【0029】 Optionally, the material of the light-shielding barrier layer is a light-shielding resin. 【0030】 Optionally, after bonding the P-type electrode and the first bonding layer, and bonding the N-type electrode and the second bonding layer, the height of the top surface of the side of the barrier layer away from the second substrate is made larger than the height of the top surface of the side of the Micro-LED chip away from the second substrate. 【0031】 Optionally, the width of the first opening is at least the sum of twice the width of the P-type electrode and the specific alignment accuracy, the width of the second opening is at least the sum of twice the width of the N-type electrode and the specific alignment accuracy, and the specific alignment accuracy is 0.5 μm to 2 μm. 【0032】 Optionally, the thickness of the first bonding layer is 80% or more and not more than the depth of the first opening, the thickness of the second bonding layer is 80% or more and not more than the depth of the second opening. 【0033】 Optionally, the thickness of the insulating layer is 50% or less of the difference in thickness between the N-type electrode and the P-type electrode. 【0034】 The thickness of the insulating layer is optionally 500 nm to 1000 nm. 【0035】 Optionally, the materials for the first bonding layer and the second bonding layer are solder, or the materials for the first bonding layer and the second bonding layer are conductive adhesives. [Effects of the Invention] 【0036】 The technical solution of this application has the following beneficial effects. 【0037】 The method for manufacturing a display panel according to the technical solution of the present invention involves supporting the chip body with the insulating layer, bonding the P-type electrode to the first bonding layer, and bonding the N-type electrode to the second bonding layer, such that the P-type electrode is fitted into the first bonding layer and the N-type electrode is fitted into the second bonding layer. The P-type electrode enters the first opening and the N-type electrode enters the second opening, and the insulating layer supports the chip body around the P-type electrode, increasing the self-alignment function, and the lateral offset of the Micro-LED chip is limited to the sidewalls of the first and second openings, ensuring bonding stability. Next, the material of the first bonding layer may be limited to the first opening, and the material of the second bonding layer may be limited to the second opening, reducing the lateral offset of the materials of the first and second bonding layers during bonding and avoiding short circuits between the first and second bonding layers. Based on the above, bonding defects between the Micro-LED chip and the first and second bonding layers are avoided. 【0038】 To more clearly illustrate specific embodiments of the present invention or technical solutions in the prior art, the drawings used to describe specific embodiments or the prior art will be briefly described below. Clearly, the drawings described below are some embodiments of the present invention, and those skilled in the art can obtain other drawings based on these without any creative effort. [Brief explanation of the drawing] 【0039】 [Figure 1] Figure 1 is a schematic diagram of the manufacturing process for the display panel. [Figure 2] Figure 2 is a schematic diagram of the manufacturing process for the display panel. [Figure 3] Figure 3 is a schematic diagram of the manufacturing process for another display panel. [Figure 4] Figure 4 is a schematic diagram of the manufacturing process for another display panel. [Figure 5] Figure 5 is a schematic diagram of the manufacturing process of a display panel according to one embodiment of the present invention. [Figure 6] Figure 6 is a schematic diagram of the manufacturing process of a display panel according to one embodiment of the present invention. [Figure 7] Figure 7 is a schematic diagram of the manufacturing process of a display panel according to one embodiment of the present invention. [Figure 8] Figure 8 is a schematic diagram of the manufacturing process of a display panel according to one embodiment of the present invention. [Figure 9] Figure 9 is a schematic diagram of the manufacturing process of a display panel according to one embodiment of the present invention. [Figure 10] Figure 10 is a schematic diagram of the manufacturing process of a display panel according to one embodiment of the present invention. [Figure 11] Figure 11 is a schematic diagram of the manufacturing process of a display panel according to another embodiment of the present invention. [Figure 12] Figure 12 is a schematic diagram of the manufacturing process of a display panel according to another embodiment of the present invention. [Figure 13] Figure 13 is a schematic diagram of the manufacturing process of a display panel according to another embodiment of the present invention. [Figure 14] Figure 14 is a schematic diagram of the manufacturing process of a display panel according to another embodiment of the present invention. [Figure 15] Figure 15 is a schematic diagram of the manufacturing process of a display panel according to another embodiment of the present invention. [Figure 16] Figure 16 is a schematic diagram of the manufacturing process of a display panel according to another embodiment of the present invention. [Modes for carrying out the invention] 【0040】 As described in the background information, conventional technology suffers from low accuracy in the bonding position between the Micro-LED chip and the substrate, resulting in bonding failures. 【0041】 A method for manufacturing a display panel, referring to Figure 1, comprising the steps of: providing a first substrate 101 having conductive posts 102, wherein solder 103 is applied to the surface of the conductive posts 102 away from the first substrate 101; providing a second substrate 105 having a plurality of Micro-LED chips 104 provided at intervals on one side surface; setting the second substrate 105 and the first substrate 101 facing each other so that the electrodes of the Micro-LED chips 104 face the solder 103; and referring to Figure 2, welding the electrodes of the Micro-LED chips 104 to the solder 103. 【0042】 However, during the process of welding the electrodes of the Micro-LED chip 104 and the solder 103 together, there is a risk of a certain misalignment occurring between the electrodes of the Micro-LED chip 104 and the solder 103, which can lead to cold solder connections and even short circuits. Upon investigation, the causes are as follows: 1. The alignment of the electrodes of the Micro-LED chip 104 and the solder 103 is limited by the alignment accuracy of the alignment device. 2. The electrodes of the Micro-LED chip 104 and the solder 103 are welded by reflow soldering, and during the reflow soldering process, the solder 103 melts, causing an offset in the position of the electrodes of the Micro-LED chip 104 relative to the solder 103. 3. The eutectic vacuum furnace used to weld the electrodes of the Micro-LED chip 104 and the solder 103 together lacks a pressure system, making it impossible to ensure that the relative positions of the Micro-LED chip 104 and the solder 103 remain constant. 【0043】 A method for manufacturing another display panel, referring to Figure 3, comprising the steps of: providing a first substrate 101a having a plurality of electrodes (not shown) on its surface, wherein the electrodes have a conductive colloid 102a on their surface and conductive particles 106 inside the conductive colloid 102a; providing a second substrate 105, referring to Figure 3, wherein the second substrate 105 has a plurality of Micro-LED chips 104 spaced apart on one side of its surface, and the Micro-LED chips 104 include P-type electrodes and N-type electrodes; and, referring to Figure 4, setting the second substrate 105 and the first substrate 101a facing each other, integrally bonding the P-type electrodes of the Micro-LED chips 104 to a portion of the conductive colloid 102a, and integrally bonding the N-type electrodes of the Micro-LED chips 104 to a portion of the conductive colloid 102a. 【0044】 However, during the process of bonding the N-type electrode of the Micro-LED chip 104 to a portion of the conductive colloid 102a, if the pitch between the N-type electrode and the P-type electrode is small, it is easy to cause a short circuit between the N-type electrode and the P-type electrode. 【0045】 The above method carries a high risk of bonding failure between the electrodes of the Micro-LED chip 104 and the bonding layer (solder 103 or conductive colloid 102a). 【0046】 This application provides a display panel and a method for manufacturing the same that can avoid bonding defects between a Micro-LED chip and a bonding layer. 【0047】 The technical solution of this application will be described clearly and completely below with reference to the drawings. As will be obvious, the embodiments described are some, but not all, embodiments of this application. Any other embodiments that a person skilled in the art could obtain without creative effort based on the embodiments of this application are all within the scope of protection of this application. 【0048】 Furthermore, in the description of this application, the directions or positional relationships indicated by terms such as "center," "up," "down," "left," "right," "vertical," "horizontal," "inside," and "outside" are directions or positional relationships based on the illustrations and are merely for the purpose of facilitating or simplifying the description of this application. They do not indicate or imply that the device or element has a specific direction or is configured and operated in a specific direction, and therefore should not be understood as limiting this application. In addition, the terms "first," "second," and "third" are used solely for explanatory purposes and should not be understood as indicating or implying relative importance. 【0049】 In this description, unless otherwise specified and limited, the terms "attachment," "connection," and "connection" should be understood in a broad sense. For example, they may be fixed connections, removable connections, or integral connections; they may be mechanical connections or electrical connections; they may be direct connections or indirect connections via an intermediate medium; or they may be internal communication between two elements. Those skilled in the art will be able to understand the specific meaning of these terms in this application depending on the specific circumstances. 【0050】 Furthermore, the technical features of the various embodiments of the present application described below can be combined with each other, insofar as they do not contradict each other. 【0051】 Example 1 One embodiment of the present application is: Step S1 provides a first substrate having a plurality of Micro-LED chips arranged at intervals on one side, wherein the Micro-LED chips include a chip body and a P-type electrode and an N-type electrode located on a part of the surface on one side of the chip body. Step S2 provides a second substrate having multiple conductive layers on one side surface, Step S3, in which an insulating layer is formed on the second substrate, wherein the insulating layer has a plurality of groups of openings, each group of openings includes a first opening and a second opening provided at intervals, the surface of the conductive layer is exposed by the first opening and the second opening, the width of the first opening is greater than the width of the P-type electrode, and the width of the second opening is greater than the width of the N-type electrode, Step S4 involves forming a first bonding layer in the first opening and a second bonding layer in the second opening. The present invention provides a method for manufacturing a display panel, which includes step S5 of supporting the chip body with the insulating layer, bonding the P-type electrode to the first bonding layer, and bonding the N-type electrode to the second bonding layer, so that the P-type electrode is fitted into the first bonding layer and the N-type electrode is fitted into the second bonding layer. 【0052】 In this embodiment, a P-type electrode is placed in the first opening, an N-type electrode is placed in the second opening, the insulating layer supports the chip body around the P-type electrode, increasing the self-alignment function, and the lateral offset of the Micro-LED chip is limited to the sidewalls of the first and second openings, ensuring bonding stability. Next, the material of the first bonding layer may be limited to the first opening, and the material of the second bonding layer may be limited to the second opening, reducing the lateral offset of the materials of the first and second bonding layers during bonding and avoiding short circuits between the first and second bonding layers. As a result, bonding defects between the Micro-LED chip and the first and second bonding layers are avoided. 【0053】 The following will explain in detail with reference to Figures 5 to 10. 【0054】 Referring to Figure 5, a first substrate 300 is provided having a plurality of Micro-LED chips spaced apart on one side, wherein each Micro-LED chip includes a chip body and a P-type electrode 304 and an N-type electrode 305 located on a part of the surface on one side of the chip body. 【0055】 The chip body includes an N-type semiconductor layer 301, an active layer 302 located on a part of the surface on one side of the N-type semiconductor layer 301, and a P-type semiconductor layer 303 located on the surface of the active layer 302 on the side away from the N-type semiconductor layer 301. The P-type electrode 304 is located on a part of the surface of the P-type semiconductor layer 303 on the side away from the active layer 302, and the N-type electrode 305 is located on a part of the surface on one side of the N-type semiconductor layer 301 at the side of the active layer 302, the P-type semiconductor layer 303 and the P-type electrode 304. 【0056】 In this embodiment, the P-type electrode 304 is located on a part of the surface of the P-type semiconductor layer 303 on the side away from the active layer 302. That is, a part of the surface of the P-type semiconductor layer 303 is not covered by the P-type electrode 304. 【0057】 In one embodiment, the difference between the total area of the surface of the P-type semiconductor layer 303 on the side away from the active layer 302 and the projected area of the P-type electrode 304 on the surface of the P-type semiconductor layer 303 is 50 μm 2 ~200 μm 2 , for example, 50 μm 2 , 80 μm 2 , 100 μm 2 , 120 μm 2 , 150 μm 2 , 180 μm 2 or 200 μm 2 is. 【0058】 In one embodiment, the pitch between the N-type electrode 305 and the P-type electrode 304 in the Micro-LED chip is 5 μm to 6 μm. 【0059】 Referring to FIG. 6, a second substrate 201 having a plurality of conductive layers 206 on one side surface is provided. 【0060】 The second substrate 201 is a driving substrate, and the second substrate 201 includes a substrate body and a driving circuit located on a surface of one side of the substrate body. The conductive layer is located on the surface of the substrate body on the side away from the driving circuit, and the conductive layer 206 is electrically connected to the driving circuit. 【0061】 The conductive layer 206 is a contact electrode, and the conductive layer 206 is formed by film deposition, photoetching, and etching. The material of the conductive layer 206 includes a metal or alloy, and the metal is, for example, Al, Ti, or Mo. 【0062】 Referring to Figure 7, an insulating layer 207 is formed on the second substrate 201, and the insulating layer 207 has a plurality of groups of openings, each of which includes a first opening 2071 and a second opening 2072 provided at intervals, and the surface of the conductive layer 206 is exposed by the first opening 2071 and the second opening 2072, respectively, the width of the first opening 2071 is greater than the width of the P-type electrode 304, and the width of the second opening 2072 is greater than the width of the N-type electrode 305. 【0063】 The step of forming the insulating layer 207 includes forming an initial insulating layer (not shown) covering the conductive layer 206 on the second substrate 201, patterning the initial insulating layer, and forming the insulating layer 207. 【0064】 In one embodiment, the thickness of the insulating layer 207 is 50% or less of the difference in thickness between the N-type electrode 305 and the P-type electrode 304. The thickness of the insulating layer 207 is the dimension in the direction perpendicular to the surface of the second substrate 201, while the thicknesses of the N-type electrode 305 and the P-type electrode 304 are both dimensions in the direction perpendicular to the surface of the first substrate. This setting has the following advantages: the insulating layer 207 is thin, saving costs, and better contact can be ensured between the P-type electrode 304 and the material of the subsequent first bonding layer, and between the N-type electrode 305 and the material of the subsequent second bonding layer. 【0065】 In one specific embodiment, the thickness of the insulating layer 207 is 500 nm to 1000 nm. 【0066】 The material of the insulating layer 207 includes SiO2 or Si3N4. 【0067】 The width of the conductive layer 206 at the bottom of the first opening 2071 is greater than or equal to the width of the first opening 2071, and the width of the conductive layer 206 at the bottom of the second opening 2072 is greater than or equal to the width of the second opening 2072. The width of the conductive layer 206 at the bottom of the first opening 2071 is greater than or equal to the sum of the width of the P-type electrode 304 and twice the specific alignment accuracy, and the width of the conductive layer 206 at the bottom of the second opening 2072 is greater than or equal to the sum of the width of the N-type electrode 305 and twice the specific alignment accuracy. The specific alignment accuracy is the alignment accuracy of the binding device used in the process of bonding the P-type electrode 304 to the first bonding layer 2081 and the N-type electrode 305 to the second bonding layer 2082. 【0068】 Referring to Figure 8, a first bonding layer 2081 is formed in the first opening 2071, and a second bonding layer 2082 is formed in the second opening 2072. 【0069】 In one embodiment, the materials of the first bonding layer 2081 and the second bonding layer 2082 are solder, and the solder includes In solder or tin-containing lead-free solder. 【0070】 In another embodiment, the materials of the first bonding layer 2081 and the second bonding layer 2082 are conductive adhesives, and the conductive adhesive is an anisotropic conductive adhesive. 【0071】 The melting point of the first bonding layer 2081 is less than the melting point of the conductive layer 206 and less than the melting point of the insulating layer 207. The melting point of the second bonding layer 2082 is less than the melting point of the conductive layer 206 and less than the melting point of the insulating layer 207. 【0072】 In the step of forming a first bonding layer 2081 in a first opening 2071 and a second bonding layer 2082 in a second opening 2072, the thickness of the first bonding layer 2081 is 80% or more of the depth of the first opening 2071 and less than or equal to the depth of the first opening 2071, and the thickness of the second bonding layer 2082 is 80% or more of the depth of the second opening 2072 and less than or equal to the depth of the second opening 2072. In this way, during the subsequent bonding process, the material of the first bonding layer 2081 can surround the P-type electrode, the material of the second bonding layer 2082 can surround the N-type electrode, and it is possible to prevent the materials of the first bonding layer 2081 and the second bonding layer 2082 from overflowing and short-circuiting. 【0073】 In one specific example, the thickness of the first bonding layer 2081 is 400nm to 800nm, and the thickness of the second bonding layer 2082 is 400nm to 800nm. 【0074】 Referring to Figure 9, the chip body is supported by the insulating layer 207, the P-type electrode 304 is bonded to the first bonding layer 2081, and the N-type electrode 305 is bonded to the second bonding layer 2082, so that the P-type electrode 304 is fitted into the first bonding layer 2081 and the N-type electrode 305 is fitted into the second bonding layer 2082. 【0075】 During the bonding of the P-type electrode 304 to the first bonding layer 2081 and the N-type electrode 305 to the second bonding layer 2082, the insulating layer 207 supports the P-type semiconductor layer 303 around the P-type electrode 304. 【0076】 In the process of bonding the P-type electrode 304 to the first bonding layer 2081 and the N-type electrode 305 to the second bonding layer 2082, the binding device employed has a specific alignment accuracy, the width of the first aperture 2071 is greater than or equal to the sum of the width of the P-type electrode 304 and twice the specific alignment accuracy, and the width of the second aperture 2072 is greater than or equal to the sum of the width of the N-type electrode 305 and twice the specific alignment accuracy. In one embodiment, the specific alignment accuracy is 0.5 μm to 2 μm. 【0077】 When the materials of the first bonding layer 2081 and the second bonding layer 2082 are solder, reflow soldering is employed to bond the P-type electrode 304 to the first bonding layer 2081 and to bond the N-type electrode 305 to the second bonding layer 2082. 【0078】 If the materials of the first bonding layer 2081 and the second bonding layer 2082 are conductive adhesives, the P-type electrode 304 and the first bonding layer 2081 are extruded to interconnect the P-type electrode 304 with the conductive particles in the first bonding layer 2081, and the N-type electrode 305 and the second bonding layer 2082 are extruded to interconnect the N-type electrode 305 with the conductive particles in the second bonding layer 2082. 【0079】 The P-type electrode 304 is placed in the first opening 2071, the N-type electrode 305 is placed in the second opening 2072, and the insulating layer 207 supports the P-type semiconductor layer 303 around the P-type electrode 304. In this way, not only is the self-alignment function increased, but the flatness of the top surface on the side away from the second substrate of all Micro-LED chips is ensured to some extent, the consistency of the light emission angle of the Micro-LED chips can be improved, and the effective light emission area of ​​the Micro-LED chips can be increased. 【0080】 Referring to Figure 10, the Micro-LED chip and the first substrate 300 are separated. 【0081】 In one specific embodiment, the first substrate 300 and the Micro-LED chip are separated by ultraviolet irradiation. 【0082】 Example 2 Referring to Figure 11, which is a schematic diagram based on Figure 7, a first inclined surface A1 is formed near the boundary between the side wall of the first opening 2071 and the top surface of the insulating layer 207 surrounding the first opening 2071, and a second inclined surface A2 is formed near the boundary between the side wall of the second opening 2072 and the top surface of the insulating layer 207 surrounding the second opening 2072. 【0083】 In one embodiment, there is a first binding angle between the top surface of the insulating layer 207 connected to the first inclined surface A1 and the first inclined surface A1, where tan(180°-θ1)>μ1, θ1 is the first binding angle, and μ1 is the coefficient of friction of the first inclined surface. 【0084】 In one embodiment, there is a second included angle between the top surface of the insulating layer 207 connected to the second inclined surface A2 and the second inclined surface A2, where tan(180°-θ2)>μ2, θ2 is the second included angle, and μ2 is the coefficient of friction of the second inclined surface. 【0085】 The advantage of setting the first and second clamping angles described above is that it ensures that the P-type electrode 304 of the Micro-LED chip automatically enters the first aperture and the N-type electrode 305 of the Micro-LED chip automatically enters the second aperture, thereby reducing yield loss to a certain extent. 【0086】 Referring to Figure 12, after forming the first inclined surface A1, the first bonding layer 2081a is formed in the first opening 2071, and after forming the second inclined surface A2, the second bonding layer 2082a is formed in the second opening 2072. 【0087】 Referring to Figure 13, the chip body is supported by the insulating layer 207, the P-type electrode 304 is bonded to the first bonding layer 2081a, and the N-type electrode 305 is bonded to the second bonding layer 2082a, so that the P-type electrode 304 is fitted into the first bonding layer 2081a and the N-type electrode 305 is fitted into the second bonding layer 2082a, after which the Micro-LED chip and the first substrate 300 are separated. 【0088】 Example 3 Referring to Figure 14, which is a schematic diagram based on Figure 7, a barrier layer 211 is formed on the insulating layer 207 surrounding the group of apertures, and the barrier layer 211 has a third aperture, the width of which the width of the third aperture is greater than the width of the Micro-LED chip. 【0089】 In one embodiment, the material of the barrier layer 211 is a light-shielding resin, which is a resin that has a light-shielding effect. However, the material of the barrier layer 211 is not limited to this material, and the width of the third aperture needs to be slightly larger than the width of the Micro-LED chip so that the Micro-LED chip can fall smoothly into the third aperture. One third aperture corresponds to one Micro-LED chip. 【0090】 The function of the barrier layer 211 includes restricting the position of the Micro-LED chips and causing one Micro-LED chip to fall into one third opening. 【0091】 In one embodiment, the barrier layer 211 is a light-shielding barrier layer. The barrier layer 211 is used to block crosstalk between light emitted by adjacent Micro-LED chips. The material of the light-shielding barrier layer may be, for example, a light-shielding resin. 【0092】 The barrier layer 211 may be made of a non-light-shielding material. 【0093】 In one embodiment, the width of the third aperture is greater than the width of the Micro-LED chip and less than or equal to 1.5 times the width of the Micro-LED chip. 【0094】 In one embodiment, the barrier layer 211 is a light-shielding barrier layer, and after bonding the P-type electrode to the first bonding layer and the N-type electrode to the second bonding layer, the height of the top surface of the barrier layer 211 on the side away from the second substrate is greater than the height of the top surface of the Micro-LED chip on the side away from the second substrate. The advantage of this configuration is that crosstalk between light emitted by adjacent Micro-LED chips can be better avoided. 【0095】 It is necessary to explain that in other embodiments, after bonding the P-type electrode to the first bonding layer and the N-type electrode to the second bonding layer, the height of the top surface of the barrier layer 211 on the side away from the second substrate is less than or equal to the height of the top surface of the Micro-LED chip on the side away from the second substrate. 【0096】 In this embodiment, the first inclined surface is formed near the boundary between the side wall of the first opening 2071 and the top surface of the insulating layer 207 surrounding the first opening 2071, and the second inclined surface is formed near the boundary between the side wall of the second opening 2072 and the top surface of the insulating layer 207 surrounding the second opening 2072. After forming the first and second inclined surfaces, the barrier layer 211 is formed. The first and second inclined surfaces can be described by referring to the above embodiment and will not be described in detail here. 【0097】 It should be explained that in other embodiments, when the barrier layer 211 is formed, the first and second inclined surfaces do not need to be installed. 【0098】 Referring to Figure 15, a first bonding layer 2081b is formed in the first opening 2071, and a second bonding layer 2082b is formed in the second opening 2072. 【0099】 In this embodiment, the first bonding layer 2081b and the second bonding layer 2082b are formed after the barrier layer 211 is formed. In other embodiments, the barrier layer 211 may be formed after the first bonding layer 2081b and the second bonding layer 2082b are formed. 【0100】 Referring to Figure 16, the chip body is supported by the insulating layer 207, the P-type electrode 304 is bonded to the first bonding layer 2081b, and the N-type electrode 305 is bonded to the second bonding layer 2082b, so that the P-type electrode 304 is fitted into the first bonding layer 2081b and the N-type electrode 305 is fitted into the second bonding layer 2082b. 【0101】 Example 4 This embodiment refers to Figure 10, A chip body and a plurality of Micro-LED chips provided at intervals, including a P-type electrode 304 and an N-type electrode 305 located on a part of the surface of one side of the chip body, A second substrate 201 having multiple conductive layers 206 on one side surface, An insulating layer 207 located on one side of the second substrate 201, wherein the insulating layer 207 has a plurality of groups of openings, each group of openings including a first opening and a second opening provided at intervals, the first opening and the second opening each located on the conductive layer 206, the width of the first opening is greater than the width of the P-type electrode 304, and the width of the second opening is greater than the width of the N-type electrode 305, The first bonding layer located within the first opening, Including a second bonding layer located within the second opening, The present invention provides a display panel in which the P-type electrode 304 is embedded in a first bonding layer, the N-type electrode 305 is embedded in a second bonding layer, and the chip body contacts a portion of the top surface of the insulating layer 207. 【0102】 The chip body includes an N-type semiconductor layer 301, an active layer 302 located on a part of one side surface of the N-type semiconductor layer 301, and a P-type semiconductor layer 303 located on the surface of the active layer 302 away from the N-type semiconductor layer 301. The P-type electrode 304 is located on a part of the surface of the P-type semiconductor layer 303 away from the active layer 302, and the N-type electrode 305 is located on a part of one side surface of the N-type semiconductor layer 301 on the side of the active layer 302, the P-type semiconductor layer 303, and the P-type electrode 304. The P-type semiconductor layer 303 around the P-type electrode 304 is in contact with the top surface of the insulating layer 207 around the first opening. 【0103】 In one embodiment, the width of the first aperture is greater than or equal to the sum of the width of the P-type electrode 304 and twice the specific alignment accuracy, the width of the second aperture is greater than or equal to the sum of the width of the N-type electrode 305 and twice the specific alignment accuracy, and the specific alignment accuracy is 0.5 μm to 2 μm. 【0104】 In one embodiment, the thickness of the first bonding layer is 80% or more of the depth of the first opening and less than or equal to the depth of the first opening, and the thickness of the second bonding layer is 80% or more of the depth of the second opening and less than or equal to the depth of the second opening. 【0105】 In one embodiment, the thickness of the insulating layer 207 is 50% or less of the difference in thickness between the N-type electrode and the P-type electrode. 【0106】 In one embodiment, the thickness of the insulating layer 207 is 500 nm to 1000 nm. 【0107】 The materials for the first bonding layer and the second bonding layer are solder, and the materials for the first bonding layer and the second bonding layer are conductive adhesives. 【0108】 Example 5 The difference between this embodiment and Embodiment 4 is, as shown in Figure 13, that there is a first inclined surface A1 (see Figure 12) between the side wall of the first opening and the top surface of the insulating layer 207 surrounding the first opening, and a second inclined surface A2 (see Figure 12) between the side wall of the second opening and the top surface of the insulating layer 207 surrounding the second opening. 【0109】 In one embodiment, there is a first included angle between the top surface of the insulating layer connected to the first inclined surface and the first inclined surface, where tan(180°-θ1)>μ1, θ1 is the first included angle, and μ1 is the coefficient of friction of the first inclined surface. 【0110】 In one embodiment, there is a second included angle between the top surface of the insulating layer connected to the second inclined surface and the second inclined surface, where tan(180°-θ2)>μ2, θ2 is the second included angle, and μ2 is the coefficient of friction of the second inclined surface. 【0111】 Example 6 The difference between this embodiment and Embodiment 5 is, referring to Figure 16, that the display panel further includes a barrier layer 211 located on the insulating layer 207 surrounding the group of apertures, the barrier layer 211 has a third aperture, and the width of the third aperture is greater than the width of the Micro-LED chip. 【0112】 In one embodiment, the width of the third aperture is 1.5 times or less the width of the Micro-LED chip. 【0113】 In one embodiment, the barrier layer 211 is a light-shielding barrier layer. The material of the light-shielding barrier layer is a light-shielding resin. In another embodiment, the material of the barrier layer 211 may further be a non-light-shielding material. 【0114】 In one embodiment, the barrier layer 211 is a light-shielding barrier layer, and the height of the top surface of the barrier layer away from the second substrate is greater than the height of the top surface of the Micro-LED chip away from the second substrate. 【0115】 In another embodiment, the height of the top surface of the barrier layer on the side away from the second substrate is less than or equal to the height of the top surface of the Micro-LED chip on the side away from the second substrate. 【0116】 The details of this embodiment that are similar to those of Embodiment 5 will not be explained in detail here. 【0117】 Example 7 The difference between this embodiment and Embodiment 4 is that the display panel further includes a barrier layer located on the insulating layer surrounding the group of apertures, the barrier layer having a third aperture, and the width of the third aperture being greater than the width of the Micro-LED chip. In one embodiment, the width of the third aperture is 1.5 times or less the width of the Micro-LED chip. 【0118】 In one embodiment, the barrier layer 211 is a light-shielding barrier layer. The material of the light-shielding barrier layer is a light-shielding resin. In another embodiment, the material of the barrier layer 211 may further be a non-light-shielding material. 【0119】 In one embodiment, the barrier layer 211 is a light-shielding barrier layer, and the height of the top surface of the barrier layer away from the second substrate is greater than the height of the top surface of the Micro-LED chip away from the second substrate. In another embodiment, the height of the top surface of the barrier layer away from the second substrate is less than or equal to the height of the top surface of the Micro-LED chip away from the second substrate. 【0120】 The similarities between this embodiment and Embodiment 4 will not be explained in detail here. 【0121】 As is clear, the above embodiments are merely illustrative examples and do not limit the embodiments. Those skilled in the art can make various changes and modifications based on the above description. It is not necessary, nor is it possible, to cover all embodiments. Any obvious changes or modifications arising therefrom remain within the scope of the invention's protection.

Claims

[Claim 1] A method for manufacturing a display panel, A step of providing a first substrate having a plurality of Micro-LED chips arranged at intervals on one side, wherein the Micro-LED chips include a chip body and a P-type electrode and an N-type electrode located on a part of the surface on one side of the chip body, The step of providing a second substrate having multiple conductive layers on one side surface, A step of forming an insulating layer on the second substrate, wherein the insulating layer has a plurality of groups of openings, each group of openings includes a first opening and a second opening provided at intervals, the surface of the conductive layer is exposed by the first opening and the second opening, the width of the first opening is greater than the width of the P-type electrode, and the width of the second opening is greater than the width of the N-type electrode, The steps include forming a first bonding layer in a first opening and forming a second bonding layer in a second opening, The process includes the steps of supporting the chip body with the insulating layer, bonding the P-type electrode to the first bonding layer, bonding the N-type electrode to the second bonding layer, and embedding the P-type electrode within the first bonding layer and the N-type electrode within the second bonding layer, A method for manufacturing a display panel, further comprising the steps of forming a first inclined surface near the boundary between the side wall of the first opening and the top surface of the insulating layer surrounding the first opening before forming a first bonding layer in the first opening, and forming a second inclined surface near the boundary between the side wall of the second opening and the top surface of the insulating layer surrounding the second opening before forming a second bonding layer in the second opening. [Claim 2] The chip body includes an N-type semiconductor layer, an active layer located on a part of one side surface of the N-type semiconductor layer, and a P-type semiconductor layer located on the side surface of the active layer away from the N-type semiconductor layer. The P-type electrode is located on a part of the surface of the P-type semiconductor layer away from the active layer, and the N-type electrode is located on a part of the surface of one side of the N-type semiconductor layer on the side of the active layer, the P-type semiconductor layer, and the P-type electrode. A method for manufacturing a display panel according to claim 1, characterized in that, in the process of bonding the P-type electrode to the first bonding layer and bonding the N-type electrode to the second bonding layer, the insulating layer supports the P-type semiconductor layer around the P-type electrode. [Claim 3] There is a first angle between the top surface of the insulating layer connected to the first inclined surface and the first inclined surface, where tan(180°-θ) １ )>μ １ And θ １ The first included angle is μ １ The method for manufacturing a display panel according to claim 1, characterized in that is the coefficient of friction of the first inclined surface. [Claim 4] There is a second angle between the top surface of the insulating layer connected to the second inclined surface and the second inclined surface, where tan(180°-θ) ２ )>μ ２ And θ ２ The second included angle is μ ２ The method for manufacturing a display panel according to claim 1, characterized in that is the coefficient of friction of the second inclined surface. [Claim 5] A method for manufacturing a display panel according to any one of claims 1 to 4, further comprising the step of forming a barrier layer in the insulating layer surrounding the group of apertures before bonding the P-type electrode and the first bonding layer to the N-type electrode and the second bonding layer, wherein the barrier layer has a third aperture and the width of the third aperture is greater than the width of the Micro-LED chip. [Claim 6] The method for manufacturing a display panel according to claim 5, characterized in that the width of the third aperture is 1.5 times or less the width of the Micro-LED chip. [Claim 7] The method for manufacturing a display panel according to claim 5, characterized in that the barrier layer is a light-shielding barrier layer. [Claim 8] The method for manufacturing a display panel according to claim 7, characterized in that the material of the light-shielding barrier layer is a light-shielding resin. [Claim 9] The binding device used in the process of bonding the P-type electrode to the first bonding layer and the N-type electrode to the second bonding layer has a unique alignment accuracy. The method for manufacturing a display panel according to claim 1, characterized in that the width of the first aperture is greater than or equal to the sum of the width of the P-type electrode and twice the specific alignment accuracy, and the width of the second aperture is greater than or equal to the sum of the width of the N-type electrode and twice the specific alignment accuracy. [Claim 10] A method for manufacturing a display panel according to claim 1, characterized in that, in the step of forming a first bonding layer in a first opening and forming a second bonding layer in a second opening, the thickness of the first bonding layer is 80% or more of the depth of the first opening and less than or equal to the depth of the first opening, and the thickness of the second bonding layer is 80% or more of the depth of the second opening and less than or equal to the depth of the second opening. [Claim 11] The method for manufacturing a display panel according to claim 1, characterized in that the thickness of the insulating layer is 50% or less of the difference in thickness between the N-type electrode and the P-type electrode. [Claim 12] The method for manufacturing a display panel according to claim 11, characterized in that the thickness of the insulating layer is 500 nm to 1000 nm. [Claim 13] The method for manufacturing a display panel according to claim 1, characterized in that the materials of the first bonding layer and the second bonding layer are conductive adhesives. [Claim 14] It is a display panel, A first substrate having a plurality of Micro-LED chips spaced apart on one side, wherein each Micro-LED chip includes a chip body and a P-type electrode and an N-type electrode located on a part of the surface on one side of the chip body, A second substrate having multiple conductive layers on one side surface, An insulating layer located on one side of the second substrate, wherein the insulating layer has a plurality of groups of openings, each group of openings includes a first opening and a second opening provided at intervals, the first opening and the second opening are each located in the conductive layer, the width of the first opening is greater than the width of the P-type electrode, and the width of the second opening is greater than the width of the N-type electrode, The first bonding layer located within the first opening, Including a second bonding layer located within the second opening, The P-type electrode is embedded in the first bonding layer, the N-type electrode is embedded in the second bonding layer, and the chip body is in contact with a portion of the top surface of the insulating layer. A display panel characterized in that there is a first inclined surface between the side wall of the first opening and the top surface of the insulating layer surrounding the first opening, and a second inclined surface between the side wall of the second opening and the top surface of the insulating layer surrounding the second opening. [Claim 15] The chip body includes an N-type semiconductor layer, an active layer located on a part of one side surface of the N-type semiconductor layer, and a P-type semiconductor layer located on the side surface of the active layer away from the N-type semiconductor layer. The display panel according to claim 14, characterized in that the P-type electrode is located on a part of the surface of the P-type semiconductor layer away from the active layer, the N-type electrode is located on a part of the surface of one side of the N-type semiconductor layer on the side of the active layer, the P-type semiconductor layer and the P-type electrode, and the P-type semiconductor layer around the P-type electrode is in contact with the top surface of the insulating layer around the first opening. [Claim 16] There is a first included angle between the top surface of the insulating layer connected to the first inclined surface and the first inclined surface, and tan(180° - θ １ ) > μ １ where θ １ is the first included angle and μ １ is the friction coefficient of the first inclined surface. The display panel according to claim 14, characterized by this. [Claim 17] There is a second angle between the top surface of the insulating layer connected to the second inclined surface and the second inclined surface, where tan(180°-θ) ２ )>μ ２ And θ ２ The second included angle is μ ２ The display panel according to claim 14, characterized in that is the coefficient of friction of the second inclined surface. [Claim 18] The display panel according to claim 14, further comprising a barrier layer located on an insulating layer surrounding the group of apertures, wherein the barrier layer has a third aperture, and the width of the third aperture is greater than the width of the Micro-LED chip. [Claim 19] The display panel according to claim 18, characterized in that the width of the third aperture is 1.5 times or less the width of the Micro-LED chip. [Claim 20] The display panel according to claim 18, characterized in that the barrier layer is a light-shielding barrier layer. [Claim 21] The display panel according to claim 20, characterized in that the material of the light-shielding barrier layer is a light-shielding resin. [Claim 22] The display panel according to claim 18, characterized in that the height of the top surface of the barrier layer on the side away from the second substrate is greater than the height of the top surface of the Micro-LED chip on the side away from the second substrate. [Claim 23] The display panel according to claim 14, characterized in that the width of the first aperture is at least the sum of the width of the P-type electrode and twice the specific alignment accuracy, the width of the second aperture is at least the sum of the width of the N-type electrode and twice the specific alignment accuracy, and the specific alignment accuracy is 0.5 μm to 2 μm. [Claim 24] The display panel according to claim 14, characterized in that the thickness of the first bonding layer is 80% or more of the depth of the first opening and less than or equal to the depth of the first opening, and the thickness of the second bonding layer is 80% or more of the depth of the second opening and less than or equal to the depth of the second opening. [Claim 25] The display panel according to claim 14, characterized in that the thickness of the insulating layer is 50% or less of the difference in thickness between the N-type electrode and the P-type electrode. [Claim 26] The display panel according to claim 25, characterized in that the thickness of the insulating layer is 500 nm to 1000 nm. [Claim 27] ​​The display panel according to claim 14, characterized in that the materials of the first bonding layer and the second bonding layer are conductive adhesives.

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