Semiconductor equipment

Abstract

To provide a semiconductor device in which local corrosion of a front surface electrode and a plating film can be suppressed, which is therefore highly reliable.SOLUTION: A semiconductor device 50 comprises: a semiconductor substrate; a first electrode provided on a surface of the semiconductor substrate; a protection film 24 that covers an end portion of the first electrode; and a second electrode 20 provided on the first electrode at an opening of the protection film 24. An end portion 21 of the protection film where the protection film 24 and the second electrode 20 are overlapped with each other, has a convex portion C and a concave portion B, in a plan view. In the plan view, a curvature radius of the protection film 24 in the convex portion C is larger than the curvature radius of the protection film 24 in the concave portion B.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] This invention relates to a semiconductor device. [Background technology]

[0002] A power semiconductor module is a power semiconductor device that incorporates one or more semiconductor devices to constitute part or all of a DC-AC conversion, DC-to-DC or AC-to-AC voltage and current conversion connection, and has a structure in which the semiconductor device and the laminated substrate or metal substrate are electrically insulated. Power semiconductor modules are used in industrial applications such as motor drive control inverters for elevators. Furthermore, in recent years, they have become widely used in automotive motor drive control inverters. Automotive inverters require miniaturization and weight reduction to improve fuel efficiency, and long-term reliability at high temperatures is required because they are located near the drive motor in the engine compartment.

[0003] Semiconductor devices used in power semiconductor modules often utilize semiconductor elements based on materials such as Si (silicon) or SiC (silicon carbide). Figure 6 is a top view showing the structure of a conventional semiconductor device. As shown in Figure 6, the semiconductor device 150 consists of an active region 140 through which current flows when it is ON, and an edge termination region 141 surrounding the active region 140 to maintain breakdown voltage. The active region 140 is provided with, for example, a front electrode (not shown) and a gate electrode pad 122 made of Al (aluminum). The semiconductor device 150 is, for example, a semiconductor element in which a MOS gate (insulating gate consisting of a metal-oxide-semiconductor film) structure (element structure) is formed on a semiconductor substrate.

[0004] A polyimide film (passivation film) 124 is deposited on the front electrode of a semiconductor device as a protective film to prevent ion diffusion into the semiconductor device and to insulate the semiconductor device. Conventionally, SiN (silicon nitride) films and inorganic materials have been used as protective films, but polyimide films 124, which are organic materials, are more commonly used. Polyimide films 124 are deposited using wet methods such as spin coating and inkjet printing, and the deposition of polyimide films 124 is simpler than that of inorganic materials.

[0005] Furthermore, in order to facilitate the joining of lead frame wiring (not shown) to the front surface electrode with solder (not shown), a plating film 120 of Ni (nickel) or the like is provided at the opening of the polyimide film 124. The polyimide film 124 functions as a mask so that when the plating film 120 is formed by a plating method using Ni or the like, the plating film 120 is selectively deposited on the front surface electrode. At the edge 121 of the polyimide film, a portion of the plating film 120 overlaps the polyimide film 124.

[0006] A known method involves shaping the edge 121 of the polyimide film on the front electrode to include a convex portion that bulges outward in a plan view, and setting the radius of curvature (R) of this portion to 200 μm or more (see, for example, Patent Document 1 below). This relieves stress, improves the adhesion between the plating film 120 formed at the opening of the polyimide film 124 on the front electrode and the polyimide film 124, and suppresses electrode corrosion between the Al front electrode and the Ni plating film 120. [Prior art documents] [Patent Documents]

[0007] [Patent Document 1] Patent No. 6906681 [Overview of the project] [Problems that the invention aims to solve]

[0008] In a conventional semiconductor device 150, in order to further improve the reliability of the semiconductor device, a semiconductor device has been proposed in which high-functional regions such as a current sense section (not shown), a temperature sense section (not shown), and an overvoltage protection section (not shown) are arranged on the same semiconductor substrate as the main semiconductor element. When arranging such high-functional regions, convex shapes are formed not only at the four corners but also at the ends 121 of the polyimide film, and the convex shapes form a plurality of patterns.

[0009] However, in the conventional method described above, the shape of the front surface electrode is substantially rectangular, and the convex shape at the end 121 of the polyimide film corresponds only to a single pattern and does not correspond to a plurality of patterns. For this reason, a portion where the adhesion between the plating film 120 and the polyimide film 124 becomes weak is formed, and a gap occurs at the boundary between the plating film 120 and the polyimide film 124 in this portion. From this gap portion, the front surface electrode made of Al and the plating film 120 made of Ni are locally corroded, and there is a problem that the reliability decreases.

[0010] In order to solve the problems caused by the above-described conventional technology, an object of the present invention is to provide a highly reliable semiconductor device that can suppress local corrosion of the front surface electrode and the plating film.

Means for Solving the Problems

[0011] In order to solve the above-described problems and achieve the object of the present invention, a semiconductor device according to the present invention has the following features. The semiconductor device includes a semiconductor substrate, a first electrode provided on the surface of the semiconductor substrate, a protective film covering an end portion of the first electrode, and a second electrode provided on the first electrode at an opening of the protective film. An end portion of the protective film where the protective film and the second electrode overlap has a convex portion and a concave portion in plan view, and a radius of curvature of the protective film in the convex portion is larger than a radius of curvature of the protective film in the concave portion in plan view. Looking from the opening has a convex portion and a concave portion, and in plan view, a radius of curvature of the protective film in the convex portion is larger than a radius of curvature of the protective film in the concave portion. Furthermore, the semiconductor device according to this invention is characterized in that, in the above-described invention, the convex portion and the concave portion are located along the outer circumference of the opening.

[0012] Furthermore, the semiconductor device according to this invention is characterized in that, in the invention described above, the radius of curvature of the protective film in the convex portion is 500 μm or less, and the radius of curvature of the protective film in the concave portion is 20 μm or more.

[0013] Furthermore, the semiconductor device according to this invention is characterized in that, in the invention described above, the difference between the radius of curvature of the protective film in the convex portion and the radius of curvature of the protective film in the concave portion is 10 μm or more and 40 μm or less.

[0014] Furthermore, the semiconductor device according to this invention is characterized in that, in the invention described above, the ratio of the radius of curvature of the protective film in the convex portion to the radius of curvature of the protective film in the concave portion is 2 times or more and 5 times or less.

[0015] Furthermore, the semiconductor device according to the present invention is characterized in that, in the invention described above, the end of the protective film has a straight portion in a plan view, the length over which the protective film overlaps the first electrode in the straight portion is longer than the length over which the protective film overlaps the first electrode in the concave portion, and the length over which the protective film overlaps the first electrode in the convex portion is shorter than the length over which the protective film overlaps the first electrode.

[0016] Furthermore, the semiconductor device according to this invention is characterized in that, in the invention described above, the difference between the length over which the protective film overlaps the first electrode in the convex portion and the length over which the protective film overlaps the first electrode in the concave portion is the same as the difference between the radius of curvature of the protective film in the convex portion and the radius of curvature of the protective film in the concave portion.

[0017] Furthermore, the semiconductor device according to this invention is characterized in that, in the invention described above, the first electrode is an alloy containing aluminum, the second electrode is an alloy containing nickel, and the protective film is a polyimide film.

[0018] According to the invention described above, the radius of curvature of the convex portion at the edge of the polyimide film is made larger than the radius of curvature of the concave portion at the edge of the polyimide film. This makes it possible to alleviate cracks and stress after the formation of the plating film, and in particular, to suppress voids that occur at the boundary where the adhesion between the plating film and the polyimide film is weak, thereby suppressing localized corrosion of the surface electrode and the plating film, and providing a highly reliable semiconductor device. [Effects of the Invention]

[0019] According to the semiconductor device of the present invention, local corrosion of the front electrode and plating film can be suppressed, resulting in high reliability. [Brief explanation of the drawing]

[0020] [Figure 1] This is a top view showing the structure of a semiconductor device according to an embodiment. [Figure 2] This is a cross-sectional view of a linear portion A in Figure 1, which shows the structure of a semiconductor device according to an embodiment. [Figure 3] This is a cross-sectional view of the concave portion B in Figure 1, which shows the structure of a semiconductor device according to the embodiment. [Figure 4] This is a cross-sectional view of the convex portion C in Figure 1, which shows the structure of the semiconductor device according to the embodiment. [Figure 5] This is a cross-sectional view showing the structure of the semiconductor substrate of a semiconductor device according to an embodiment. [Figure 6] This is a top view showing the structure of a conventional semiconductor device. [Modes for carrying out the invention]

[0021] The present invention relates to the attached drawings below. ru hanPreferred embodiments of the conductive device will be described in detail. In this specification and the accompanying drawings, layers or regions prefixed with n or p indicate that electrons or holes are the majority carriers, respectively. Furthermore, the + and - signs attached to n and p indicate higher and lower impurity concentrations, respectively, compared to layers or regions without these signs. In the following description of embodiments and accompanying drawings, similar components are denoted by the same reference numerals, and redundant explanations are omitted. In this specification, in the notation of Miller indices, "-" indicates a bar attached to the exponent immediately following it, and a "-" before the exponent indicates a negative exponent. Furthermore, it is preferable to include up to 5% variation when describing them as the same or equivalent, taking into account manufacturing variations.

[0022] (Embodiment) Preferred embodiments of the semiconductor device according to this invention will be described in detail below with reference to the attached drawings. Figure 1 is a top view showing the structure of a semiconductor device according to an embodiment. The semiconductor device 50 according to the embodiment shown in Figure 1 may be a vertical semiconductor element in which a drift current flows in the depth direction of the semiconductor substrate when it is turned on.

[0023] The semiconductor device 50 is a semiconductor element such as an IGBT (Insulated Gate Bipolar Transistor), a MOSFET (Metal Oxide Semiconductor Field Effect Transistor: a MOS-type field-effect transistor with an insulated gate consisting of a three-layer structure of metal-oxide-semiconductor), or a diode chip.

[0024] The active region 40 is the region where current flows when the device is ON, and the edge termination region 41 surrounds the active region 40, mitigating the electric field on the front side of the semiconductor device 50 and maintaining the breakdown voltage. A breakdown voltage structure (not shown), such as a field limiting ring (FLR) or a junction termination extension (JTE), is placed in the edge termination region 41. Breakdown voltage is the limit voltage at which the device will not malfunction or be destroyed.

[0025] The active region 40 includes a main active region (not shown) through which the main current flows when the semiconductor device 50 is turned on, and a circuit section (not shown) for protecting and controlling the semiconductor device 50. The main active region has, for example, a roughly rectangular planar shape and occupies most of the surface area of ​​the active region 40. The circuit section is a high-function section such as a current sensing section, a temperature sensing section, an overvoltage protection section, and an arithmetic circuit section.

[0026] A front electrode (first electrode) 12 is provided on the main effective region. The front electrode 12 is covered by a plating film 20 and a polyimide film (protective film) 24, which will be described later, and is therefore not shown in Figure 1 (see Figures 2 to 4). In the case of a MOSFET, the front electrode 12 is the source electrode, and in the case of an IGBT, it is the emitter electrode, and is formed of, for example, AlSi (aluminum silicon alloy). However, the front electrode 12 is not limited to AlSi.

[0027] A polyimide film 24 is formed on the front electrode 12. A plating film (second electrode) 20 is provided within the openings of the polyimide film 24 to facilitate soldering (not shown) the lead frame wiring (not shown) to the front electrode 12. The polyimide film 24 is a resin film that functions as a protective film. The resin film is not limited to a polyimide film; it may be another organic resin film, or an inorganic material such as a SiN (silicon nitride) film.

[0028] The plating film 20 may be Ni or a Ni alloy such as NiP (nickel-phosphorus) or NiB (nickel-boron), or it may be copper, aluminum, or gold. It may also be a multilayer film of these materials. Furthermore, an Au plating film may be formed on top of the Ni plating film. The plating film 20 overlaps the polyimide film 24 at the edges 21 of the polyimide film (see Figures 2-4).

[0029] The front electrode 12 has a larger current capacity than other circuit parts and therefore covers almost the entire main effective area. The front electrode 12 is positioned separately from the other electrode pads. The other electrode pads are, for example, roughly rectangular in shape and have the surface area necessary for joining external terminal electrodes and wires. Examples of the other electrode pads include the gate electrode pad 22, the electrode pads of the current sensing section, the cathode pad and anode pad of the temperature sensing section, the electrode pads of the overvoltage protection section, and the electrode pads of the calculation circuit section.

[0030] Figure 1 shows electrode pads other than the front electrode 12, including a gate electrode pad 22 and a signal electrode pad 23 consisting of a cathode pad and an anode pad for the temperature sensing section. The electrode pads other than the front electrode 12 are not limited to this configuration; the gate electrode pad 22 may have multiple configurations, the signal electrode pad 23 may have multiple configurations, or the electrode pads for the current sensing section, the overvoltage protection section, and the calculation circuit section may also be included.

[0031] Thus, since electrode pads other than the front electrode 12 are provided in the active region 40 of the semiconductor device 50, the edge 21 of the polyimide film is formed in a shape that avoids the electrode pads other than the front electrode 12. For this reason, convex and concave portions are formed on the edge 21 of the polyimide film in a plan view. For example, the linear portion A in Figure 1, the concave portion B in Figure 1, the convex portion C in Figure 1, and the corner portion D in Figure 1 are formed. Here, in Figure 1, the plated film 20 and the edge 21 of the polyimide film are depicted on only one side, but the plated film 20 and the edge 21 of the polyimide film may also be formed on the opposite side, or the plated film 20 and the edge 21 of the polyimide film may be formed on only one side as in Figure 1.

[0032] In this embodiment, the radius of curvature R of the polyimide film is changed in a plan view depending on whether the shape of the end portion 21 of the polyimide film is concave or convex. Specifically, the radius of curvature R2 of the convex portion C of the end portion 21 of the polyimide film is made larger than the radius of curvature R1 of the concave portion B of the end portion 21 of the polyimide film (R2 > R1). For example, the radius of curvature R is changed by optimizing the difference in cross-sectional shape by changing the amount of side etching when forming the polyimide film 24. Furthermore, the radius of curvature R2 of the convex portion C is preferably 500 μm or less, and more preferably 20 μm or more and 180 μm or less, and the radius of curvature R1 of the concave portion B is preferably 20 μm or more, and more preferably 20 μm or more and 200 μm or less. The radius of curvature of the corner portion D is preferably the same as the radius of curvature R1 of the concave portion B.

[0033] Furthermore, the difference between the radius of curvature R2 of the convex portion C and the radius of curvature R1 of the concave portion B (R2-R1) is preferably 10 μm or more and 40 μm or less, or the ratio of the radius of curvature R2 of the convex portion C to the radius of curvature R1 of the concave portion B (R2 / R1) is preferably 2 times or more and 5 times or less.

[0034] The shape of the edges 21 of the polyimide film causes a difference in the stress applied to the polyimide film 24. The convex portion C experiences more stress, resulting in weaker adhesion between the plating film 20 and the polyimide film 24. Therefore, in this embodiment, by increasing the radius of curvature R2 of the convex portion C where more stress is applied, cracks and stress after the formation of the plating film 20 can be alleviated. In particular, voids that occur at the boundary of the portion where the adhesion between the plating film 20 and the polyimide film 24 is weak can be suppressed, preventing localized corrosion of the front electrode 12 and the plating film 20, and providing a highly reliable semiconductor device.

[0035] FIG. 2 is a cross-sectional view of the linear portion A in FIG. 1 showing the structure of the semiconductor device according to the embodiment. FIG. 3 is a cross-sectional view of the concave portion B in FIG. 1 showing the structure of the semiconductor device according to the embodiment. FIG. 4 is a cross-sectional view of the convex portion C in FIG. 1 showing the structure of the semiconductor device according to the embodiment. FIG. 2 is a cross-sectional view of the a-a' portion in FIG. 1, FIG. 3 is a cross-sectional view of the b-b' portion in FIG. 1, and FIG. 4 is a cross-sectional view of the c-c' portion in FIG. 1.

[0036] As shown in FIGS. 2 to 4, a front surface electrode 12 and a polyimide film 24 are provided on the semiconductor substrate 18. The polyimide film 24 covers a part of the front surface electrode 12, and a plating film 20 is provided in an opening that is not covered by the polyimide film 24 on the front surface electrode 12. Both the polyimide film 24 and the plating film 20 have inclined cross-sections, and a part of the plating film 20 overlaps on the end portion 21 of the polyimide film. When the length of the overlapping portion of the polyimide film 24 and the front surface electrode 12 is L1 for the linear portion A, L2 for the concave portion B, and L3 for the convex portion C, the relationship L2 < L1 < L3 holds. That is, the length L1 of the linear portion A is longer than the length L2 of the concave portion B, and the length L3 of the convex portion C is longer than the length L1 of the linear portion A. Also, the difference between the length L3 of the convex portion C and the length L2 of the concave portion B is preferably the same as the difference in the radius of curvature, i.e., R2 - R1 = L3 - L2. By "the same", it means that even if R2 - R1 and L3 - L2 do not exactly match, they may match within an error of 10%.

[0037] The semiconductor substrate 18 is composed of a plurality of semiconductor layers provided on a semiconductor substrate. FIG. 5 is a cross-sectional view showing the structure of the semiconductor substrate of the semiconductor device according to the embodiment. FIG. 5 shows the semiconductor substrate 18 in the case of a trench-type MOSFET 70 fabricated (manufactured) using silicon carbide (SiC).

[0038] As shown in FIG. 5, the semiconductor device according to the embodiment has an n- + type silicon carbide substrate 1 on the first main surface (front surface), for example, the (0001) surface (Si surface), and an n- - type silicon carbide epitaxial layer 2 is deposited.

[0039] n + The n-type silicon carbide substrate 1 is a single crystal silicon carbide substrate. n - The n-type silicon carbide epitaxial layer 2 has n + an impurity concentration lower than that of the n-type silicon carbide substrate 1, and is, for example, a low concentration n-type drift layer. n - On the surface of the n-type silicon carbide epitaxial layer 2 opposite to the side of the n-type silicon carbide substrate 1, an n-type high concentration region 5 may be provided. The n-type high concentration region 5 has n + a high concentration n-type drift layer with an impurity concentration lower than that of the n-type silicon carbide substrate 1 and higher than that of the n-type silicon carbide epitaxial layer 2. + On the surface of the n-type silicon carbide epitaxial layer 2 opposite to the side of the n-type silicon carbide substrate 1, a p-type base layer 6 is provided. Hereinafter, n - the n-type silicon carbide substrate 1, the n-type silicon carbide epitaxial layer 2, the n-type high concentration region 5, and the p-type base layer 6 form a semiconductor substrate (a semiconductor substrate made of silicon carbide) 18.

[0040] n - On the surface of the n-type silicon carbide epitaxial layer 2 opposite to the side of the n-type silicon carbide substrate 1, a drain electrode serving as a back surface electrode 13 is provided. On the surface of the back surface electrode 13, a drain electrode pad (not shown) is provided. + On the surface of the n-type silicon carbide epitaxial layer 2 opposite to the side of the n-type silicon carbide substrate 1, a p-type base layer 6 is provided. Hereinafter, n + the n-type silicon carbide substrate 1 and n - the n-type silicon carbide epitaxial layer 2, the n-type high concentration region 5, and the p-type base layer 6 form a semiconductor substrate (a semiconductor substrate made of silicon carbide) 18.

[0041] n + On the second main surface (the back surface, that is, the back surface of the semiconductor substrate 18) of the n-type silicon carbide substrate 1, a drain electrode serving as a back surface electrode 13 is provided. On the surface of the back surface electrode 13, a drain electrode pad (not shown) is provided.

[0042] A trench structure is formed on the first main surface side (the p-type base layer 6 side) of the silicon carbide semiconductor substrate. Specifically, the trench 16 penetrates the p-type base layer 6 from the surface on the side opposite to the n-type silicon carbide substrate 1 (the first main surface side of the semiconductor substrate) to the n-type high concentration region 5 (when the n-type high concentration region 5 is not provided, n + On the side opposite to the n-type silicon carbide substrate 1 (the first main surface side of the semiconductor substrate) of the p-type base layer 6, and penetrates the p-type base layer 6 to the n-type high concentration region 5 (when the n-type high concentration region 5 is not provided, n -The silicon carbide epitaxial layer 2 (hereinafter simply referred to as (2)) is reached. Along the inner wall of the trench 16, a gate insulating film 9 is formed on the bottom and side walls of the trench 16, and the gate electrode 10 is formed inside the gate insulating film 9 in the trench 16. The gate insulating film 9 insulates the gate electrode 10 from the n-type high-concentration region 5(2) and the p-type base layer 6. A part of the gate electrode 10 may protrude from the top of the trench 16 (the side on which the front surface electrode 12, described later, is provided) toward the front surface electrode 12.

[0043] n-type high-concentration region 5(2) + On the surface layer opposite to the silicon carbide substrate 1 side (the first main surface side of the silicon carbide semiconductor substrate), between the trenches 16, the first p + A type base region 3 is provided. Furthermore, within the n-type high-concentration region 5(2), a second p is located opposite the bottom of the trench 16 in the depth direction (from the front electrode 12 to the back electrode 13). + A type base region 4 is provided. 1p + Type base region 3 is 2p + Lower 1p with the same thickness as the base region 4 of the mold + Type base region 3a and lower 1st p + Upper first p in contact with type base region 3a and p-type base layer 6 + It consists of a base region 3b and the second p + The width of the base region 4 is the same as or wider than the width of the trench 16. The bottom of the trench 16 is the second p + It may reach the p-type base region 4, or the p-type base layer 6 and the second p + It may be located within the n-type high-concentration region 5(2) sandwiched between the type base region 4.

[0044] Also, n - Within the silicon carbide epitaxial layer 2, the first p between the trenches 16 + The peak impurity concentration is higher in the n-type high-concentration region 5(2) at a depth deeper than the n-type base region 3. + A type region 17 is provided. Note that a deep position is the 1st p + This refers to a position closer to the drain electrode 13 than the base region 3.

[0045] Inside the p-type base layer 6, on the first main surface side of the silicon carbide semiconductor substrate 18, n + A type source region 7 is selectively provided. Also, p + A type contact region 8 may be selectively provided. + The impurity concentration in the source region 7 is n - It is higher than the impurity concentration of the silicon carbide epitaxial layer 2. + The impurity concentration in the type contact region 8 is higher than the impurity concentration in the p-type base layer 6.

[0046] The interlayer insulating film 11 is provided over the entire surface of the first main surface side of the semiconductor substrate 18, covering the gate electrode 10 embedded in the trench 16. The front surface electrode 12, which serves as the source electrode, is connected via a contact hole opened in the interlayer insulating film 11. + It is in contact with the p-type source region 7 and the p-type base layer 6. + When a type contact area 8 is provided, the front electrode 12 is n + Type source region 7 and p + It contacts the type contact region 8. The front electrode 12 is electrically insulated from the gate electrode 10 by the interlayer insulating film 11. A source electrode pad (not shown) is provided on the front electrode 12. A barrier metal (not shown) may be provided between the front electrode 12 and the interlayer insulating film 11 to prevent the diffusion of metal atoms from the front electrode 12 to the gate electrode 10 side.

[0047] Furthermore, in the regions where the gate electrode pad 22 and signal electrode pad 23 are provided, a MOS gate structure is not formed, and an interlayer insulating film 11 is provided on the semiconductor substrate 18, insulating the semiconductor substrate 18 from the gate electrode pad 22 and signal electrode pad 23. The signal electrode pad 23 is, for example, an electrode pad connected to a current sensing unit or a temperature sensing unit.

[0048] As described above, according to this embodiment, the radius of curvature of the convex portion at the edge of the polyimide film is made larger than the radius of curvature of the concave portion at the edge of the polyimide film. This makes it possible to alleviate cracks and stress after the formation of the plating film, and in particular, to suppress voids that occur at the boundary where the adhesion between the plating film and the polyimide film is weak, thereby suppressing localized corrosion of the surface electrode and the plating film, and providing a highly reliable semiconductor device.

[0049] As described above, the present invention can be modified in various ways without departing from the spirit of the invention, and in each of the embodiments described above, for example, the dimensions of each part, the impurity concentration, etc., can be set in various ways according to the required specifications. Furthermore, in each of the embodiments described above, the semiconductor can be applied not only to silicon carbide (SiC) but also to semiconductors such as silicon (Si) and gallium nitride (GaN). [Industrial applicability]

[0050] As described above, the semiconductor device according to the present invention is useful as a power semiconductor device used in power conversion devices such as inverters, power supply devices for various industrial machines, and igniters for automobiles. [Explanation of symbols]

[0051] 1 n + Silicon carbide substrate 2 n - Silicon carbide epitaxial layer 3 1st p. + Type-based domain 3a Lower 1st p. + Type-based domain 3b Upper 1st p. + Type-based domain 4 2nd p. + Type-based domain 5 n-type high concentration region 6 p-type base layer 7 n + Type source area 8 p + Type Contact Area 9 Gate insulating film 10 Guard Station 11 Interlayer insulating film 12, 112 Front surface electrodes 13 Backside electrode 16 Trench 17 n + type area 18 Semiconductor substrate 20, 120 Plating film 21, 121 Edge of polyimide film 22, 122 gate electrode pads 23 Signal electrode pads 24, 124 Polyimide film 40, 140 active area 41, 141 Edge Termination Region 50, 150 Semiconductor Equipment 70 Trench-type MOSFETs

Claims

1. Semiconductor substrate and, A first electrode provided on the surface of the semiconductor substrate, A protective film covering the end of the first electrode, In the opening of the protective film, the second electrode provided on the first electrode and Equipped with, The edge of the protective film where the protective film and the second electrode overlap has, in a plan view, a convex portion and a concave portion when viewed from the opening. In a plan view, the radius of curvature of the protective film in the convex portion is greater than the radius of curvature of the protective film in the concave portion. A semiconductor device characterized in that the convex portion and the concave portion are located along the outer circumference of the opening.

2. A semiconductor substrate, A first electrode provided on the surface of the semiconductor substrate, A protective film covering the end of the first electrode, In the opening of the protective film, the second electrode provided on the first electrode and Equipped with, The edge of the protective film where the protective film and the second electrode overlap has, in a plan view, a convex portion and a concave portion when viewed from the opening. In a plan view, the radius of curvature of the protective film in the convex portion is greater than the radius of curvature of the protective film in the concave portion. A semiconductor device characterized in that the difference between the radius of curvature of the protective film in the convex portion and the radius of curvature of the protective film in the concave portion is 10 μm or more and 40 μm or less.

3. A semiconductor substrate and A first electrode provided on the surface of the semiconductor substrate, A protective film covering the end of the first electrode, In the opening of the protective film, the second electrode provided on the first electrode and Equipped with, The edge of the protective film where the protective film and the second electrode overlap has, in a plan view, a convex portion and a concave portion when viewed from the opening. In a plan view, the radius of curvature of the protective film in the convex portion is greater than the radius of curvature of the protective film in the concave portion. A semiconductor device characterized in that the ratio of the radius of curvature of the protective film in the convex portion to the radius of curvature of the protective film in the concave portion is 2 times or more and 5 times or less.

4. A semiconductor substrate and A first electrode provided on the surface of the semiconductor substrate, A protective film covering the end of the first electrode, In the opening of the protective film, the second electrode provided on the first electrode and Equipped with, The edge of the protective film where the protective film and the second electrode overlap has, in a plan view, a convex portion and a concave portion when viewed from the opening. In a plan view, the radius of curvature of the protective film in the convex portion is greater than the radius of curvature of the protective film in the concave portion. The end of the protective film has a straight section in plan view. A semiconductor device characterized in that the length to which the protective film overlaps the first electrode in the straight portion is longer than the length to which the protective film overlaps the first electrode in the concave portion, and the length to which the protective film overlaps the first electrode in the convex portion is shorter than the length to which the protective film overlaps the first electrode.

5. The semiconductor device according to any one of claims 1 to 4, characterized in that the radius of curvature of the protective film in the convex portion is 500 μm or less, and the radius of curvature of the protective film in the concave portion is 20 μm or more.

6. The semiconductor device according to claim 1, characterized in that the difference between the radius of curvature of the protective film in the convex portion and the radius of curvature of the protective film in the concave portion is 10 μm or more and 40 μm or less.

7. The semiconductor device according to Claim 1, characterized in that the ratio of the radius of curvature of the protective film in the convex portion to the radius of curvature of the protective film in the concave portion is 2 times or more and 5 times or less.

8. The end of the protective film has a straight portion in plan view, The semiconductor device according to claim 1, characterized in that the length to which the protective film overlaps the first electrode in the straight portion is longer than the length to which the protective film overlaps the first electrode in the concave portion, and the length to which the protective film overlaps the first electrode in the convex portion is shorter than the length to which the protective film overlaps the first electrode in the convex portion.

9. The semiconductor device according to claim 4 or 8, characterized in that the difference between the length over which the protective film overlaps the first electrode in the convex portion and the length over which the protective film overlaps the first electrode in the concave portion is the same as the difference between the radius of curvature of the protective film in the convex portion and the radius of curvature of the protective film in the concave portion.

10. The first electrode is an alloy containing aluminum, The second electrode is a nickel-containing alloy, The semiconductor device according to any one of claims 1 to 4, characterized in that the protective film is a polyimide film.

Images