Arithmetic processing unit and arithmetic processing method

Abstract

To provide an arithmetic processing apparatus and an arithmetic processing method configured to improve processing performance of arithmetic operation.SOLUTION: A plurality of prefetchers is disposed for each of caches and has different data access prediction algorithms. An accuracy monitoring unit 102 is configured to monitor, for each of the caches, a miss rate of prefetching by each of the prefetchers, and determine a prefetcher to be caused to perform prefetching on the basis of the miss rate. A band monitoring unit 103 is configured to monitor a usage rate of any or all of buses between the caches or between the caches and a main memory in a reading direction, cause the prefetchers corresponding to the caches on a side of a core of a low-usage rate bus in which the usage rate is low to issue a prefetch with a high probability and a prefetch with a low probability, and cause the prefetchers corresponding to the caches on a side of a core of a high-usage rate bus in which the usage rate is high to stop issuing the prefetch with the low probability and to issue the prefetch with the high probability.SELECTED DRAWING: Figure 2

Description

Technical Field

[0001] The present invention relates to an arithmetic processing unit and an arithmetic processing method.

Background Art

[0002] In recent years, the operating frequency of processors has been improving rapidly. On the other hand, the improvement in the operating speed of DRAM (Dynamic Random Access Memory), which is generally used as the main memory, has been slow. Therefore, research on architectures for improving data transfer efficiency to fully utilize the performance of processors has been actively conducted. In an information processing apparatus, a cache memory with a higher data access speed than the main memory is generally arranged in the CPU (Central Processing Unit). Then, by placing the recently referenced data on this cache memory, the reduction of latency due to main memory reference is achieved.

[0003] Furthermore, as a cache management technique, there is a function called hardware prefetch that copies data to be used in the future in a running operation from the main memory to the cache in advance based on the memory access regularity of the program. The entity that performs prefetch is called a prefetcher. By the prefetcher issuing an optimal prefetch, the cost of the core going to read the memory at the timing of using the data can be reduced. Conventionally, one type of prefetcher is arranged for one cache.

[0004] Generally, the distance at which a prefetch is issued is variable. The distance at which a prefetch is issued is the address interval to the data targeted by the next prefetch, and there are various cases, for example, when targeting data in the next line or data 280 bytes ahead.

[0005] In contrast, the algorithm for estimating data access patterns in prefetching is fixed. There are various prefetching algorithms, such as stream prefetching and stride prefetching. Stream prefetching is an algorithm that focuses on access to a contiguous address range and prefetches the value of an address that has traveled a predetermined distance within that contiguous range. Stride prefetching, on the other hand, focuses on access at periodic address intervals and prefetches by adding a predetermined stride to the accessed address. For example, a prefetcher given stride prefetching as the algorithm for estimating data access patterns will perform prefetching using stride prefetching regardless of the type of operation.

[0006] Regarding prefetching techniques, several methods have been proposed to prefetch rows of data from memory to the cache according to one or more prefetching strategies. Other methods include performing prefetching based on prefetch hints indicating that two or more load instructions are likely to request data from the same cache page. Furthermore, a method has been proposed to select one of several selectable prefetch strategies based on access patterns and execute prefetching according to the selected strategy. Finally, a method has been proposed to control the speed of data prefetching from memory to the cache based on bus bandwidth. [Prior art documents] [Patent Documents]

[0007] [Patent Document 1] Special Publication No. 2010-532904 [Patent Document 2] Japanese Patent Publication No. 2008-159057 [Patent Document 3] U.S. Patent Application Publication No. 2015 / 0121038 [Patent Document 4] U.S. Patent Application Publication No. 2019 / 0079871 [Overview of the project] [Problems that the invention aims to solve]

[0008] However, some programs may perform operations with various characteristics. For operations with different characteristics, prefetching accuracy can be improved by using prefetching strategies tailored to each characteristic. In contrast, conventional prefetching strategies are fixed, meaning that programs performing operations with various characteristics may not achieve sufficient prefetching accuracy, potentially leading to a decrease in program execution performance. Furthermore, while actively issuing prefetches can improve the probability of data being present in the cache, issuing numerous prefetches can strain the data bus bandwidth between caches or between main memory and the cache, hindering higher-priority data transfers. This also contributes to a decrease in program execution performance. Therefore, improving the processing performance of operations is difficult.

[0009] Furthermore, in technologies that perform prefetching according to one or more prefetching strategies, the prefetching strategy used is fixed, making it difficult to perform prefetching with an operational policy suited to the characteristics of the computation. Similarly, in technologies that perform prefetching based on prefetch hints, while it is possible to issue prefetches at appropriate times, the prefetching strategy used is fixed, making it difficult to perform prefetching with an operational policy suited to the characteristics of the computation. Moreover, in technologies that select one of several selectable prefetch strategies based on access patterns, it is difficult to appropriately adjust the number of prefetches issued. Furthermore, in technologies that control the prefetching speed based on bus bandwidth, it is difficult to perform prefetching with an operational policy suited to the characteristics of the computation. Therefore, regardless of the technology used, it is difficult to improve the processing performance of the computation.

[0010] The disclosed technology was made in view of the above, and aims to provide an arithmetic processing unit and an arithmetic processing method that improve the processing performance of calculations. [Means for solving the problem]

[0011] In one embodiment of the arithmetic processing unit and arithmetic processing method disclosed herein, a plurality of caches are arranged in a hierarchical manner between the core and the main memory. A plurality of prefetchers are arranged for each cache, and each has a different data access prediction algorithm. The accuracy monitoring unit monitors the prefetch miss rate by each of the prefetchers for each cache, and determines which prefetcher should perform prefetching based on the miss rate. The bandwidth monitoring unit monitors the connections between each of the caches or between the caches and the main memory. of The bandwidth monitoring unit monitors the utilization rate of any or all of the buses in the reading direction between them. Below the threshold The prefetcher corresponding to the cache on the core side of the low-utilization bus First Prefetch and The above first prefetch is Low probability Second The prefetch command is issued. Also, the bandwidth monitoring unit... It is above the aforementioned threshold. The prefetcher corresponding to the cache on the core side of the high-utility bus Second Stop issuing prefetches and the above First Issue a prefetch. [Effects of the Invention]

[0012] In one respect, the present invention can improve the processing performance of calculations. [Brief explanation of the drawing]

[0013] [Figure 1] Figure 1 is a schematic diagram showing the overall configuration of the information processing device. [Figure 2] Figure 2 shows the details of the control mechanism for the L1 cache and L2 cache in the CPU according to Example 1. [Figure 3]FIG. 3 is a diagram showing an example of the calculation result of the miss rate for each prefetcher by the accuracy monitoring unit. [Figure 4] FIG. 4 is a diagram showing an example of the operation of prefetcher selection. [Figure 5] FIG. 5 is a flowchart of arithmetic processing using prefetch in the CPU according to the first embodiment. [Figure 6] FIG. 6 is a diagram showing details of the control mechanism for the L1 cache and the L2 cache in the CPU according to the second embodiment. [Figure 7] FIG. 7 is a diagram showing an example of data obtained by the accuracy monitoring unit and the bandwidth monitoring unit. [Figure 8] FIG. 8 is a diagram showing details of the control mechanism for the L1 cache and the L2 cache in the CPU according to the third embodiment. MODE FOR CARRYING OUT THE INVENTION

[0014] Hereinafter, embodiments of the arithmetic processing device and the arithmetic processing method disclosed in the present application will be described in detail based on the drawings. Note that the arithmetic processing device and the arithmetic processing method disclosed in the present application are not limited by the following embodiments. EXAMPLE

[0015] FIG. 1 is a schematic diagram showing the overall configuration of an information processing device. As shown in FIG. 1, the information processing device 1 includes a core 11, an L1 cache 12, an L2 cache 13, an LLC (Low Level Cache) 14, a main memory 15, an auxiliary storage device 16, a display device 17, and an input device 18. The core 11 is connected to each of the L1 cache 12, the L2 cache 13, the LLC 14, the main memory 15, the auxiliary storage device 16, the display device 17, and the input device 18 via a bus. The core 11, the L1 cache 12, the L2 cache 13, and the LLC 14 are mounted on, for example, a CPU 10 which is an arithmetic processing device.

[0016] The core 11 reads various programs stored in the auxiliary storage device 16, loads them into the main memory 15, and performs calculations using the L1 cache 12, L2 cache 13, LLC 14, and the data stored in the main memory 15.

[0017] The L1 cache 12 is a cache memory that operates quickly and has a smaller capacity compared to the L2 cache 13 and LLC 14, and is the first cache memory read when the core 11 accesses data. The L1 cache 12 is, for example, SRAM (Static Random Access Memory).

[0018] The L2 cache 13 is a cache memory that operates quickly and generally has a larger capacity than the L1 cache 12. It is the next cache memory that is read when a cache miss occurs in the L1 cache 12 during data access by the core 11. The L2 cache 13 is also, for example, SRAM.

[0019] LLC14 is a cache memory that operates quickly and generally has a larger capacity than the L2 cache 13. It is the next cache memory that is read when a cache miss occurs in the L2 cache 13 during data access by the core 11. LLC14 is sometimes called the L3 cache. LLC14 is also, for example, SRAM.

[0020] In this embodiment, the information processing device 1 is described as having three cache memories: L1 cache 12, L2 cache 13, and LLC 14. However, the number of cache memory layers is not limited to these. For example, the information processing device 1 does not need to have L2 cache 13 or LLC 14, and may have four or more layers.

[0021] Main memory 15 is a main memory that operates at a slower speed and has a larger capacity compared to L1 cache 12, L2 cache 13, and LLC 14. Main memory 15 stores data used by core 11 for calculations. Main memory 15 is accessed by core 11 when the data to be accessed is not found in any of L1 cache 12, L2 cache 13, or LLC 14. Main memory 15 is, for example, DRAM (Dynamic Random Access Memory).

[0022] The auxiliary storage device 16 is, for example, an HDD (Hard Disk Drive) or an SSD (Solid State Drive). The auxiliary storage device 16 stores the OS (Operating System) and various programs for performing calculations.

[0023] The display device 17 is, for example, a monitor or display. The display device 17 presents information to the user by displaying the calculation results from the core 11. The input device 18 is, for example, a keyboard or mouse. The user inputs data and commands to the information processing device 1 using the input device 18 while referring to the screen displayed on the display device 17. The display device 17 and the input device 18 may be configured as a single piece of hardware.

[0024] Figure 2 shows the details of the control mechanism for the L1 cache and L2 cache in the CPU according to Embodiment 1. In Figure 2, the hierarchical structure of the L1 cache 12, L2 cache 13, and LLC 14 is shown as being connected in multiple stages for clarity. In reality, they are connected to a bus extending from the core 11, as shown in Figure 1.

[0025] As shown in Figure 2, the CPU 10 has a selector 101, a precision monitoring unit 102, and prefetchers 111-113 for each of the L1 cache 12 and L2 cache 13 as control mechanisms for prefetching. In addition, the CPU 10 has a bandwidth monitoring unit 103 that performs prefetching control for the L1 cache 12 and L2 cache 13 collectively. Here, in this embodiment, as an example, prefetching control mechanisms are provided for the L1 cache 12 and L2 cache 13, but similar control mechanisms may be provided for other caches such as LLC 14.

[0026] Prefetchers 111-113 are hardware prefetchers that perform prefetching using different data access prediction algorithms. When prefetchers 111-113 are not distinguished, they are referred to as prefetcher 110. Prefetcher 110 has a prefetch buffer that stores the prefetched data. Here, Figure 2 shows three prefetchers 110, but there can be any number of prefetchers 110 with different data access prediction algorithms, as long as there are two or more.

[0027] Data access prediction algorithms for estimating data access patterns during prefetching include, for example, Stream prefetching, Stride prefetching, and Temporal prefetching. For example, prefetcher 111 uses Stream prefetching, prefetcher 112 uses Stride prefetching, and prefetcher 113 uses Temporal prefetching. Representative data access prediction algorithms are described below.

[0028] This section describes the operation of the prefetcher 110 when using stream prefetching. When a cache miss is detected in an address block A, the prefetcher 110 prefetches the address block A+1 that follows address block A and saves the data to its own prefetch buffer. Depending on the hardware parameters, the prefetcher 110 may simultaneously save the data of the four address blocks A+1 to A+4 that follow address block A to the prefetch buffer when a miss is detected. Subsequently, when an access to the data in the prefetch buffer occurs, the prefetcher 110 moves the data to, for example, the L1 cache 12, and then prefetches the subsequent address blocks A+2, A+3, ... in order, saving the data to the prefetch buffer.

[0029] Next, we will explain the operation of prefetcher 110 when using Stride prefetching. When consecutive memory accesses are to address block δ, if a cache miss is detected in address block A, prefetcher 110 cannot handle it with Stream prefetching of address block A+1. Therefore, if prefetcher 110 detects that the accesses are at equal intervals, it prefetches address block A+δ and saves the data to the prefetch buffer when a cache miss is detected in address block A. In this case as well, depending on the parameters, prefetcher 110 may prefetch multiple address blocks simultaneously. If data exists in the prefetch buffer for subsequent data accesses, prefetcher 110 moves the data to, for example, L1 cache 12, and then prefetches address block A+δ*2 and saves the data to the prefetch buffer. Here, prefetcher 110 can also perform operation equivalent to Stream prefetching using Stride prefetching by setting δ=1.

[0030] Next, we will explain the operation of the prefetcher 110 when using Temporal prefetching. If the prefetcher 110 can extract a data access pattern that is repeated many times in the access pattern history, which appears random at first glance, it will perform prefetching using that extracted pattern. For example, in the case of an access pattern such as "N,A,B,C,E,G,H,A,B,C,I,J,K,A,B,C,L,M,N,O,A,B,C,...", the prefetcher 110 will determine that A,B,C are repeated and will perform prefetching in the order of address blocks A, B, and C.

[0031] Furthermore, the operation of the prefetcher 110 will be explained using the L1 cache 12 as an example. From among the prefetchers 111 to 113, the selector 101 selects the prefetcher 110 that will actually perform the prefetch.

[0032] Furthermore, the prefetcher 110 receives an instruction from the bandwidth monitoring unit 103 to determine whether to perform prefetching in an active prefetch or a conservative prefetch mode. Each prefetcher 110 then performs prefetching in the mode specified by the bandwidth monitoring unit 103.

[0033] Active prefetching is an operating mode that issues both high-probability and low-probability prefetches. Conversely, conservative prefetching is an operating mode that issues only high-probability prefetches and does not issue low-probability prefetches.

[0034] If stream prefetching is used, for example, if a cache miss occurs for address block A, the data at address block A+1 will be hit. AccuracyAddress block A+1 has the highest cache miss, followed by address blocks A+2, A+3, and so on. Therefore, in the case of conservative prefetching, if a cache miss occurs for address block A, prefetcher 110 will target address block A+1 for prefetching. In contrast, in the case of aggressive prefetching, prefetcher 110 will target address blocks A+1 to A+4 for prefetching.

[0035] Each prefetcher 110 obtains information about data access by the core 11 and information about cache misses in the L1 cache 12 via the selector 101. When a cache miss is detected, each prefetcher 110 calculates the address block to be prefetched according to the data access prediction algorithm it uses. That is, prefetchers 111 to 113 each use different data access prediction algorithms to calculate the address block to be prefetched.

[0036] Subsequently, all prefetchers 110, including both the prefetcher 110 selected by the selector 101 and the prefetchers 110 that are not selected, output the calculated address block information to the accuracy monitoring unit 102.

[0037] Furthermore, the prefetcher 110 selected by selector 101 retrieves data from the calculated address block and stores it in its own prefetch buffer. If the data to be accessed is already stored in its own prefetch buffer, the prefetcher 110 selected by selector 101 moves the data it holds to the L1 cache 12 via selector 101. Subsequently, it prefetches data sequentially according to the data access prediction algorithm used.

[0038] The accuracy monitoring unit 102 stores information on various parameters for calculating the prefetch miss rate of each prefetcher 110 as records. For example, the accuracy monitoring unit 102 stores the prefetched addresses, the number of cache read accesses, and the number of prefetch hits for each prefetcher 110 as parameters. Furthermore, if the system has SMT (Simultaneous Multi-Threading) functionality, the accuracy monitoring unit 102 stores the above parameters for each thread.

[0039] When a data read access occurs to the L1 cache 12, the accuracy monitoring unit 102 receives a notification of the cache read occurrence from the L1 cache 12. The accuracy monitoring unit 102 then increments the cache read access count by one.

[0040] Furthermore, the accuracy monitoring unit 102 obtains the calculation result of the address block to be prefetched for each prefetcher 110 from each prefetcher 110. The accuracy monitoring unit 102 then stores the prefetched address blocks for each prefetcher 110. Here, the number of address blocks stored by the accuracy monitoring unit 102 depends on the size of the memory area that the accuracy monitoring unit 102 has. The accuracy monitoring unit 102 also counts and stores the number of prefetches performed by the prefetcher 110.

[0041] When a cache miss occurs in the L1 cache 12, the accuracy monitoring unit 102 receives information about the cache miss, including the address block being accessed, from the L1 cache 12. The accuracy monitoring unit 102 then determines whether the address block with the cache miss matches any of the address blocks previously prefetched by each prefetcher 110. For prefetchers 110 where the address block matches, the accuracy monitoring unit 102 increments the prefetch hit count by one.

[0042] Furthermore, the accuracy monitoring unit 102 has information in advance about the timing of selecting a prefetcher 110. For example, the timing of selection may be periodic, or it may be when the number of cache misses reaches a predetermined number. When the timing for selecting a prefetcher 110 is reached, the accuracy monitoring unit 102 calculates the number of prefetch misses at that time by subtracting the number of prefetch hits from the number of cache read accesses for each prefetcher 110. Then, the accuracy monitoring unit 102 calculates the miss rate for each prefetcher 110 by dividing the number of prefetch misses for each prefetcher 110 by the number of prefetches to convert it to a percentage. After that, the accuracy monitoring unit 102 notifies the selector 110 of the prefetcher 110 with the lowest miss rate.

[0043] In other words, the accuracy monitoring unit 102 monitors the prefetch miss rate of each prefetcher 110 in the corresponding cache, the L1 cache 12, and determines which prefetcher 110 should perform prefetching based on the miss rate. The accuracy monitoring unit 102 also stores the prefetch results of each prefetcher 110 in the L1 cache 12 for a predetermined period in the past, and calculates the miss rate of each prefetcher 110 based on the information of the data to be accessed during the predetermined period and the prefetch results. The accuracy monitoring unit 102 then decides to have the prefetching performed by the low-miss-rate prefetcher 110, which has the lowest miss rate.

[0044] Figure 3 shows an example of the error rate calculation results for each prefetcher by the accuracy monitoring unit. For example, if the calculation result 130 as shown in Figure 3 is obtained, the accuracy monitoring unit 102 determines that the error rate of prefetcher 111 is the highest and the error rate of prefetcher 113 is the lowest. Subsequently, the accuracy monitoring unit 102 notifies the selector 101 of the information of prefetcher 110, which has the lowest error rate.

[0045] Selector 101 has a pre-defined initial value for the prefetcher 110 that will actually perform prefetching. For example, selector 101 has prefetcher 111 as its initial value. When the information of the prefetcher 110 with the lowest miss rate has not yet been notified by the accuracy monitoring unit 102, such as immediately after the startup of the information processing device 1, selector 101 selects the prefetcher 110 indicated by the initial value as the prefetcher 110 that will actually perform prefetching. As a result, selector 101 causes the prefetcher 110 indicated by the initial value to perform prefetching related to the L1 cache 12.

[0046] When it is time to select a prefetcher 110, the selector 101 receives notification from the accuracy monitoring unit 102 of the prefetcher 110 with the lowest miss rate. The selector 101 then selects the prefetcher 110 that has been notified as the prefetcher 110 to actually perform the prefetch. The selector 101 then has the prefetcher 110 with the lowest miss rate at that time perform the prefetch for the L1 cache 12.

[0047] The bandwidth monitoring unit 103 monitors the usage rate of the read direction, i.e., the upstream bus, of the L1 cache 12 and L2 cache 13, which are subject to prefetch control. Specifically, for the L1 cache 12, the bandwidth monitoring unit 103 monitors the usage rate of the bus 121 between the L1 cache 12 and the L2 cache 13. For the L2 cache 13, the bandwidth monitoring unit 103 obtains the usage rate of the bus 122 between the L2 cache 13 and the LLC 14. In this embodiment, the prefetch operation mode of the LLC 14 is not adjusted, so the bandwidth monitoring unit 103 does not monitor the bus between the LLC 14 and the main memory 15. However, it is possible to monitor that bus and adjust the prefetch operation mode of the LLC 14.

[0048] For example, the bandwidth monitoring unit 103 monitors the amount of data transferred on the bus as the bus utilization rate. The bandwidth monitoring unit 103 performs the same processing for all buses, so the monitoring of the bus 121 between the L1 cache 12 and the L2 cache 13 will be described below.

[0049] The bandwidth monitoring unit 103 has a pre-defined bus utilization threshold for determining whether the utilization rate of bus 121 is high or low. For example, the bandwidth monitoring unit 103 can set the bus utilization threshold to 50% of the maximum transfer rate of bus 121.

[0050] The bandwidth monitoring unit 103 then compares the utilization rate of bus 121 with the bus utilization threshold. If the utilization rate of bus 121 is equal to or greater than the bus utilization threshold, the bandwidth monitoring unit 103 determines that the utilization rate of bus 121 is high, and if the utilization rate of bus 121 is less than the bus utilization threshold, it determines that the utilization rate of bus 121 is low.

[0051] If the bandwidth monitoring unit 103 determines that the bus 121 between the L1 cache 12 and the L2 cache 13 is in high utilization, it decides to perform conservative prefetching in the L1 cache 12, which receives data via that bus. The bandwidth monitoring unit 103 then instructs the L1 cache 12 prefetcher 110 to use conservative prefetching as its operating mode.

[0052] Conversely, if the bandwidth monitoring unit 103 determines that the utilization rate of the bus 121 between the L1 cache 12 and the L2 cache 13 is low, it decides to perform aggressive prefetching in the L1 cache 12. The bandwidth monitoring unit 103 then instructs the L1 cache 12 prefetcher 110 to set the operating mode to aggressive prefetching.

[0053] In other words, the bandwidth monitoring unit 103 monitors the connections between each cache and between the LLC 14 and the main memory 15. ofThe bandwidth monitoring unit 103 monitors the usage rate of each bus in the read direction. The bandwidth monitoring unit 103 then causes the prefetcher 110 corresponding to the cache on the core 11 side of the low-usage bus to issue high-accuracy and low-accuracy prefetches. The bandwidth monitoring unit 103 also causes the prefetcher 110 corresponding to the cache on the core 11 side of the high-usage bus to stop issuing low-accuracy prefetches and issue high-accuracy prefetches. More specifically, the bandwidth monitoring unit 103 determines whether the operating mode of the prefetcher 110 with the lowest miss rate should be to issue high-accuracy and low-accuracy prefetches, or to stop issuing low-accuracy prefetches and issue only high-accuracy prefetches.

[0054] The bandwidth monitoring unit 103 determines the operating mode for buses 121 and 122, respectively. For example, if the utilization rates of both buses 121 and 122 are high, the bandwidth monitoring unit 103 uses conservative prefetching for both the L1 cache 12 and the L2 cache 13. Also, if the utilization rate of bus 121 is high and the utilization rate of bus 122 is low, the bandwidth monitoring unit 103 uses conservative prefetching for the L1 cache 12 and aggressive prefetching for the L2 cache 13. Furthermore, if the utilization rates of both buses 121 and 122 are low, the bandwidth monitoring unit 103 uses aggressive prefetching for both the L1 cache 12 and the L2 cache 13.

[0055] In this embodiment, the operating modes of aggressive prefetching and conservative prefetching were switched within the same data access prediction algorithm. However, it is sufficient to switch the number of prefetches; for example, different data access prediction algorithms could be used to switch between aggressive and conservative prefetching. For example, conservative prefetching would operate a prefetcher 110 using Stream prefetching, while aggressive prefetching would operate both a prefetcher 110 using Stream prefetching and a prefetcher 110 using Stride prefetching. However, since two prefetchers 110 are operating, if both prefetch data from the same address block, it becomes difficult for the L1 cache 12 to determine which data to use. Therefore, in this case, it is assumed that the two prefetchers 110 prefetch data from different address blocks.

[0056] Figure 4 shows an example of the prefetcher selection process. Next, an example of the prefetcher 110 selection process will be explained with reference to Figure 4.

[0057] State 201 represents the state at startup. Here, selector 101 has prefetcher 111 as its initial value. Therefore, selector 101 selects prefetcher 111. As a result, prefetcher 111 performs prefetching to L1 cache 12.

[0058] Subsequently, when it is time to select a prefetcher 110, the accuracy monitoring unit 102 calculates the miss rate of each prefetcher 111 to 113 and obtains the calculation result 131 shown in state 202. In this case, since the miss rate of prefetcher 111 is the lowest, the accuracy monitoring unit 102 notifies the selector 101 of the information about prefetcher 111. The selector 101 maintains the selected state of prefetcher 111 as shown in state 202. In this case, prefetcher 111 proceeds to prefetch the L1 cache 12.

[0059] Subsequently, when the timing for selecting the prefetcher 110 arrives again, the accuracy monitoring unit 102 calculates the miss rate of each prefetcher 111 to 113 and obtains the calculation result 132 shown in state 203. In this case, since the miss rate of prefetcher 113 is the lowest, the accuracy monitoring unit 102 notifies the selector 101 of the information about prefetcher 113. The selector 101 selects prefetcher 113 as shown in state 203. In this case, prefetcher 113 performs prefetching to the L1 cache 12.

[0060] Figure 5 is a flowchart of the prefetching-based arithmetic processing in the CPU according to Example 1. Next, referring to Figure 5, the prefetching-based arithmetic processing in the CPU 10 according to Example 1 will be explained. Here, the prefetching process in the L1 cache 12 will be explained as an example.

[0061] Core 11 performs the arithmetic processing (step S1).

[0062] Core 11 determines whether the calculation has finished (step S2). If the calculation has finished (step S2: affirmative), prefetcher 110 terminates the prefetch process.

[0063] In contrast, if the calculation has not been completed (step S2: negation), the bandwidth monitoring unit 103 monitors the usage rate of the bus 121 between the L1 cache 12 and the L2 cache 13 (step S3).

[0064] Then, the bandwidth monitoring unit 103 determines whether the utilization rate of the bus 121 is equal to or greater than the bus utilization threshold (step S4).

[0065] If the utilization rate of bus 121 is greater than or equal to the bus utilization threshold (step S4: affirmative), the bandwidth monitoring unit 103 instructs the prefetcher 110 to perform conservative prefetching (step S5).

[0066] On the other hand, if the utilization rate of bus 121 is below the bus utilization threshold (step S4: negative), the bandwidth monitoring unit 103 instructs the prefetcher 110 to perform an active prefetch (step S6).

[0067] Each prefetcher 110 performs a prefetch when a cache miss occurs (step S7).

[0068] Each prefetcher 110 notifies the accuracy monitoring unit 102 of the address of the prefetched data. The accuracy monitoring unit 102 stores the address of the prefetched data obtained from each prefetcher 110 in a record for each prefetcher 110 (step S8).

[0069] Furthermore, the accuracy monitoring unit 102 obtains information from the L1 cache 12 about the address to which data access was performed when a cache miss occurred. Then, if there is a prefetcher 110 that has previously prefetched an address matching the address to which data access was performed, the accuracy monitoring unit 102 increments the prefetch hit count of that prefetcher 110 by one. In this way, the accuracy monitoring unit 102 counts the prefetch hit count of each prefetcher 110 (step S9). The accuracy monitoring unit 102 also determines the number of cache read accesses in the L1 cache 12.

[0070] Next, the accuracy monitoring unit 102 determines whether or not the timing for selecting the prefetcher 110 has arrived (step S10). If the timing for selecting the prefetcher 110 has not arrived (step S10: negative), the calculation process using prefetching returns to step S1.

[0071] In response to this, when the time comes to select a prefetcher 110 (step S10: affirmative), the accuracy monitoring unit 102 calculates the miss rate for each prefetcher 110 (step S11). Specifically, the accuracy monitoring unit 102 calculates the miss rate for each prefetcher 110 using the number of cache read accesses and the number of prefetch hits for each prefetcher 110.

[0072] Subsequently, the accuracy monitoring unit 102 notifies the selector 101 of the information of the prefetcher 110 with the lowest error rate. The selector 101 selects the prefetcher 110 notified by the accuracy monitoring unit 102 as the prefetcher 110 to actually perform prefetching (step S12). After that, the calculation process using prefetching returns to step S1.

[0073] Here, the explanation above has used the example of a single core 11 as shown in Figure 2, but the CPU 10 can have other configurations. For example, the CPU 10 may have multiple cores 11. Furthermore, the CPU 10 has an L1 cache 12 and an L2 cache 13 for each core 11. A selector 101, a precision monitoring unit 102, and a prefetcher 110 are provided for each L1 cache 12 and L2 cache 13. In addition, a bandwidth monitoring unit 103 may be provided for each bus extending from each core 11. However, one bandwidth monitoring unit 103 may monitor all the buses extending from each core 11 together.

[0074] As described above, the CPU in this embodiment calculates the prefetch miss rate of each prefetcher and has the prefetcher with the lowest miss rate perform the prefetch. This allows prefetching to be performed using a data access prediction algorithm that is tailored to the characteristics of the data access of the calculations performed by the core, thereby improving the accuracy of prefetching. Consequently, it becomes possible to improve the processing performance of calculations performed by the CPU.

[0075] Furthermore, the CPU calculates the usage rate of the upstream bus for each cache, i.e., the read-direction bus. The CPU then performs aggressive prefetching for the corresponding cache if the bus usage is low, and conservative prefetching if the bus usage is high. This allows for prefetching more data when there is available bus capacity, improving prefetching accuracy. Therefore, it becomes possible to further improve the processing performance of the CPU. [Examples]

[0076] Figure 6 shows the details of the control mechanism for the L1 cache and L2 cache in the CPU according to Embodiment 2. The CPU 10 according to this embodiment detects a decrease in prefetch accuracy caused by threads that access data in different patterns when multiple threads are running on the same core 11. The CPU 10 then issues an instruction to migrate the thread with reduced prefetch accuracy to another OS 105. The details of the thread migration operation by the CPU 10 according to this embodiment will be described below. The CPU 10 according to this embodiment has an integrated monitoring unit 104, as shown in Figure 6. In the following description, the operation of each part, which is the same as in Embodiment 1, will be omitted.

[0077] The CPU 10 in this embodiment has multiple cores 11. Furthermore, each core 11 has SMT functionality and executes multiple threads. In addition, L1 cache 12 and L2 cache 13 are connected to buses extending from each core 11, and a selector 101, prefetchers 111-113, and accuracy monitoring unit 102 are provided to each. A bandwidth monitoring unit 103 is also provided for each core 11. Furthermore, the LLC 14 in this embodiment is shared by the multiple cores 11.

[0078] The accuracy monitoring unit 102 calculates the prefetch hit rate for each prefetcher 110 for each thread in the core 11 using the number of prefetch hits and the number of cache read accesses. The accuracy monitoring unit 102 can calculate the prefetch hit rate by dividing the prefetch hit rate by the number of cache read accesses. For example, the accuracy monitoring unit 102 corresponding to the L1 cache 12 calculates the prefetch hit rate for the L1 cache 12. Similarly, the accuracy monitoring unit 102 corresponding to the L2 cache 13 calculates the prefetch hit rate for the L2 cache 13.

[0079] Then, each accuracy monitoring unit 102 selects the thread with the lowest prefetch hit rate, i.e., the thread with the highest miss rate. Next, each accuracy monitoring unit 102 calculates the average miss rate of the selected thread from the miss rates of each prefetcher 110. Then, each accuracy monitoring unit 102 outputs the average miss rate of the selected thread to the integrated monitoring unit 104.

[0080] Here, the accuracy monitoring unit 102 transmits data in packet format to the integrated monitoring unit 104 via the cache and data path at regular time intervals. Alternatively, if a dedicated path is wired between the accuracy monitoring unit 102 and the integrated monitoring unit 104, the accuracy monitoring unit 102 may transmit data using that dedicated path.

[0081] The bandwidth monitoring unit 103 calculates the bandwidth utilization rate per thread for the bus 121 between the L1 cache 12 and the L2 cache 13, and for the bus 122 between the L2 cache 13 and the LLC 14. The bandwidth monitoring unit 103 also receives information on the amount of data per thread on the bus 123 between the LLC 14 and the main memory 15 from the integrated monitoring unit 104. The bandwidth monitoring unit 103 then calculates the bandwidth utilization rate per thread for the bus 123 between the LLC 14 and the main memory 15. After that, the bandwidth monitoring unit 103 outputs the bandwidth utilization rates for each bus 121 to 123 to the integrated monitoring unit 104.

[0082] The integrated monitoring unit 104 is located at the LLC 14 level. Specifically, the integrated monitoring unit 104 is connected to the bus 123 between the LLC 14 and the main memory 15. The integrated monitoring unit 104 is also connected to the LLC 14. Furthermore, the integrated monitoring unit 104 is connected to each of the bandwidth monitoring units 103 provided for each core 11.

[0083] The integrated monitoring unit 104 periodically receives input from each accuracy monitoring unit 102 regarding the average miss rate of the selected threads. The integrated monitoring unit 104 also acquires information on the amount of data per thread on the bus 123 between the LLC 14 and the main memory 15 and outputs it to the bandwidth monitoring unit 103. The integrated monitoring unit 104 then receives input from each bandwidth monitoring unit 103 regarding the bandwidth utilization rate of each bus 121 to 123 for each thread.

[0084] The integrated monitoring unit 104 has predetermined thresholds for determining whether to move threads based on average miss rate and bandwidth occupancy. The integrated monitoring unit 104 determines which threads to move by prioritizing them in the following order: average miss rate of L1 cache 12, average miss rate of L2 cache 13, and bandwidth occupancy. Here, the integrated monitoring unit 104 may set the number of threads to be moved to one or multiple.

[0085] The integrated monitoring unit 104 identifies threads whose average miss rate in the L1 cache 12 exceeds the move determination threshold, and the core 11 executing those threads. If there are threads whose average miss rate in the L1 cache 12 exceeds the move determination threshold, the integrated monitoring unit 104 selects the threads with the highest average miss rates to be moved.

[0086] After selecting threads to move using the average miss rate of the L1 cache 12, if the number of threads selected for move does not reach the target number of threads, the integrated monitoring unit 104 moves on to determining which threads to move based on the average miss rate of the L2 cache 13. Specifically, the integrated monitoring unit 104 identifies threads whose average miss rate in the L2 cache 13 exceeds the move determination threshold and the core 11 executing those threads. If there are threads whose average miss rate in the L2 cache 13 exceeds the move determination threshold, the integrated monitoring unit 104 selects the remaining threads up to the target number of threads to move, in descending order of average miss rate.

[0087] After selecting threads to move using the average miss rate of the L2 cache 13, if the number of threads selected for move has not yet reached the target number of threads to move, the integrated monitoring unit 104 proceeds to determine which threads to move based on bandwidth utilization. Specifically, the integrated monitoring unit 104 identifies threads whose bandwidth utilization exceeds the move determination threshold and the cores 11 that execute those threads. If there are threads whose bandwidth utilization exceeds the move determination threshold, the integrated monitoring unit 104 selects the remaining threads up to the target number of threads to move, in descending order of bandwidth utilization.

[0088] The integrated monitoring unit 104 terminates the selection process for threads to be moved once it has finished determining which threads to move based on bandwidth utilization, even if the number of threads selected for move has not reached the target number of threads to be moved. For example, if neither the average miss rate nor the bandwidth utilization of any thread exceeds the move determination threshold, the integrated monitoring unit 104 terminates the thread move process without moving any threads.

[0089] Furthermore, if there is a core 11 where the miss rate of the L1 cache 12, the miss rate of the L2 cache 13, and the bandwidth utilization rate of any thread do not exceed the migration determination threshold, the integrated monitoring unit 104 will select that core 11 as the migration destination. If there are multiple cores 11 that can be migration destinations, the integrated monitoring unit 104 will select the cores 11 to be migration destinations in order of lowest miss rate of the L1 cache 12, lowest miss rate of the L2 cache 13, and lowest bandwidth utilization. After that, the integrated monitoring unit 104 will output a migration instruction to the OS 105 to move the threads that have been determined to be moved to the cores 11 that have been selected as migration destinations. For example, the integrated monitoring unit 104 will issue a migration instruction to the OS 105 using a system call or the like. In this way, the integrated monitoring unit 104 determines the threads to be moved and the destination cores 11 based on the miss rate of the prefetcher 110 and the utilization rates of each bus 121 to 123, and moves the threads to be moved to the destination cores 11.

[0090] Figure 7 shows an example of data obtained by the accuracy monitoring unit and the bandwidth monitoring unit. In Figure 7, cells are explained in the case where multiple threads are running on each of the multiple cores 11, including two cores, #0 and #1. Here, we will focus on thread ##0 running on core #0 and thread ##1 running on core #1.

[0091] For example, the accuracy monitoring unit 102 calculates the L1 cache 12 miss rate for thread ##0 of core #0 as 10% at prefetcher 111, 8% at prefetcher 112, and 5% at prefetcher 113, as shown in Table 141 in Figure 7 as the L1 miss rate. In this case, the accuracy monitoring unit 102 calculates the average miss rate for the L1 cache 12 of thread ##0 of core #0 as 7.7%. Similarly, the accuracy monitoring unit 102 calculates the L2 cache 13 miss rate for thread ##0 of core #0 as 5% at prefetcher 111, 4% at prefetcher 112, and 3% at prefetcher 113, as shown in Table 141 as the L2 miss rate. In this case, the accuracy monitoring unit 102 calculates the average miss rate for the L2 cache 13 of thread ##0 of core #0 as 4.0%.

[0092] Furthermore, as shown in Table 141, the accuracy monitoring unit 102 calculates that the miss rate of the L1 cache 12 for thread ##1 of core #1 is 3% at prefetcher 111, 3% at prefetcher 112, and 1% at prefetcher 113. In this case, the accuracy monitoring unit 102 calculates that the average miss rate of the L1 cache 12 for thread ##1 of core #1 is 2.3%. Similarly, as shown in Table 141, the accuracy monitoring unit 102 calculates that the miss rate of the L2 cache 13 for thread ##1 of core #1 is 2% at prefetcher 111, 2% at prefetcher 112, and 0% at prefetcher 113. In this case, the accuracy monitoring unit 102 calculates that the average miss rate of the L2 cache 13 for thread ##1 of core #1 is 1.3%.

[0093] Furthermore, the bandwidth monitoring unit 103 calculates the bandwidth utilization of the bus 121 between the L1 cache 12 and the L2 cache 13 of thread ##0 of core #0 as 60%, as shown in Table 141 as the L1-L2 bandwidth utilization. Also, here, the bandwidth monitoring unit 103 calculates the bandwidth utilization of the bus between the L2 cache 13 and the main memory 15, as shown in Table 141 as the L2-Mem bandwidth utilization. This bus is a combination of buses 122 and 123. Thus, the bandwidth monitoring unit 103 does not need to calculate the range of buses for which it calculates bandwidth utilization separately for each of buses 121-123, but may use a combined range of any of them. In this case, as shown in Table 141, the bandwidth monitoring unit 103 calculates the bandwidth utilization of the bus between the L2 cache 13 and the main memory 15 of thread ##0 of core #0 as 60%.

[0094] Furthermore, as shown in Table 141, the bandwidth monitoring unit 103 calculates the bandwidth utilization of the bus 121 between the L1 cache 12 and the L2 cache 13 of thread ##1 of core #1 as 10%. Furthermore, as shown in Table 141, the bandwidth monitoring unit 103 calculates the bandwidth utilization of the bus between the L2 cache 13 and the main memory 15 of thread ##1 of core #1 as 10%.

[0095] The integrated monitoring unit 104 obtains the miss rate of the L1 cache 12, the miss rate of the L2 cache 13, and the bandwidth occupancy rate of threads ##0 and ##1 based on the values ​​shown in Table 141 in Figure 7. Here, the integrated monitoring unit 104 has a move determination threshold of 5.0% for the miss rate and a move determination threshold of 70% for the bandwidth occupancy rate.

[0096] In this case, the integrated monitoring unit 104 determines that the miss rate of the L1 cache 12 of thread ##0 of core #0 is above the move determination threshold. Then, the integrated monitoring unit 104 designates thread ##0 of core #0 as the target for move.

[0097] The integrated monitoring unit 104 then determines that the miss rate of the L1 cache 12, the miss rate of the L2 cache 13, and the bandwidth utilization of thread ##1 of core #1 do not exceed the move determination threshold. The integrated monitoring unit 104 also confirms that the miss rate of the L1 cache 12, the miss rate of the L2 cache 13, and the bandwidth utilization of other threads of core #1 do not exceed the move determination threshold. After that, the integrated monitoring unit 104 notifies the OS 105 to move thread ##0 of core #0 to core #1.

[0098] OS105 receives migration instructions, along with information about the thread to be moved and the destination core 11, from the integrated monitoring unit 104. Then, OS105 moves the specified thread to the specified core 11.

[0099] As described above, the arithmetic processing unit according to this embodiment, in a multi-core multi-threaded environment, targets threads with high miss rates and bandwidth utilization and moves them to cores that have threads with low miss rates and bandwidth utilization. Threads executed by a given core that have a higher miss rate than other threads are thought to have different data access patterns. Therefore, by moving threads with high miss rates to other cores, disruptions in data access patterns can be eliminated, enabling appropriate prefetching. Furthermore, by moving threads with high bandwidth utilization to cores where the bandwidth utilization of each thread is low, the bandwidth utilization can be made more uniform across cores, increasing the number of proactive prefetching operations.

[0100] (modified version) In Example 3, thread movement was performed using the miss rate and bandwidth utilization, but it is also possible to move threads based on the miss rate without using the bandwidth utilization. The following describes the case where thread movement is performed based on the miss rate.

[0101] In this modified example, the accuracy monitoring unit 102 corresponding to the L1 cache 12 calculates the prefetch hit rate of each prefetcher 110 in the L1 cache 12. The accuracy monitoring unit 102 corresponding to the L2 cache 13 calculates the prefetch hit rate of each prefetcher 110 in the L2 cache 13. Then, each accuracy monitoring unit 102 selects the thread with the minimum prefetch hit rate. Next, each accuracy monitoring unit 102 calculates the average miss rate of the selected thread from the miss rates of each prefetcher 110. Then, each accuracy monitoring unit 102 outputs the average miss rate of the selected thread to the integrated monitoring unit 104.

[0102] The integrated monitoring unit 104 uses the average miss rate of threads transmitted from the accuracy monitoring unit 102 corresponding to the L1 cache 12 to identify threads whose average miss rate in the L1 cache 12 exceeds the move determination threshold, and the core 11 executing those threads. If there are threads whose average miss rate in the L1 cache 12 exceeds the move determination threshold, the integrated monitoring unit 104 selects the threads with the highest average miss rates among those threads to be moved.

[0103] After selecting threads to move using the average miss rate of the L1 cache 12, if the number of threads to be moved does not reach the target number, the integrated monitoring unit 104 identifies threads whose average miss rate in the L2 cache 13 exceeds the move determination threshold and the core 11 executing those threads. If there are threads whose average miss rate in the L2 cache 13 exceeds the move determination threshold, the integrated monitoring unit 104 selects the remaining number of threads up to the target number to move, in descending order of average miss rate among those threads. Thus, in this modified example, the integrated monitoring unit 104 determines which threads to move by prioritizing threads with a high average miss rate in the L1 cache 12, and then threads with a high average miss rate in the L2 cache 13.

[0104] Next, the integrated monitoring unit 104 determines the destination core 11. Then, the integrated monitoring unit 104 outputs a migration instruction to the OS 105 to move the threads that have been determined to be moved to the destination core 11. For example, the integrated monitoring unit 104 gives the migration instruction to the OS 105 using a system call or the like. In other words, the integrated monitoring unit 104 determines the threads to be moved and the destination core 11 based on the error rate, and moves the threads to be moved to the destination core 11.

[0105] As explained above, it is also possible to move threads based on the miss rate rather than using bandwidth utilization. In this case as well, moving threads with high miss rates to other cores can resolve disruptions in data access patterns and enable appropriate prefetching. [Examples]

[0106] Figure 8 shows the details of the control mechanism for the L1 cache and L2 cache in the CPU according to Embodiment 3. The CPU 10 according to this embodiment provides the user with information such as the accuracy of the prefetcher 110 and the utilization rate of the data bus. The CPU 10 according to this embodiment has an information management unit 106. The information processing device 1 also has an output device 107.

[0107] The accuracy monitoring unit 102 outputs the miss rate of each prefetcher 110 to the information management unit 106. The bandwidth monitoring unit 103 also outputs the usage rate of the bus 121 between the L1 cache 12 and the L2 cache 13, and the usage rate of the bus 122 between the L2 cache 13 and the LLC 14 to the information management unit 106.

[0108] The information management unit 106 receives the miss rate input for each prefetcher 110 from the accuracy monitoring unit 102. The information management unit 106 also receives the usage rate of the bus 121 between the L1 cache 12 and the L2 cache 13, and the usage rate of the bus 122 between the L2 cache 13 and the LLC 14 from the bandwidth monitoring unit 103. Furthermore, the information management unit 106 obtains program counter information from the core 11.

[0109] Next, the information management unit 106 identifies the portion of the program counter where the miss rate of the prefetcher 110 in the L1 cache 12 exceeds a predetermined miss rate threshold. The information management unit 106 also identifies the portion of the program counter where the miss rate of the prefetcher 110 in the L2 cache 13 exceeds a predetermined miss rate threshold. Furthermore, the information management unit 106 identifies the portion of the program counter where the utilization rate of the bus 121 between the L1 cache 12 and the L2 cache 13 exceeds a predetermined utilization rate threshold. Finally, the information management unit 106 identifies the portion of the program counter where the utilization rate of the bus 122 between the L2 cache 13 and the LLC 14 exceeds a predetermined utilization rate threshold.

[0110] The information management unit 106 then generates information indicating which part of the program executed by the core 11 corresponds to the identified part. In other words, the information management unit 106 generates information indicating which part of the user-written program experienced a significant decrease in prefetch accuracy or an increase in bus utilization. Subsequently, the information management unit 106 outputs the information indicating which part of the user-written program experienced a significant decrease in prefetch accuracy or an increase in bus utilization to the display device 17. In other words, the information management unit 106 obtains the program counter for the program executed by the core 11. The information management unit 106 then compares the program counter with the error rate monitored by the accuracy monitoring unit 102 and the utilization rate monitored by the bandwidth monitoring unit 103 to generate relationship information between the program and the error rate and utilization rate, and provides the generated relationship information to the user.

[0111] The display device 17 receives input from the information management unit 106 indicating which parts of the user-written program experienced a significant decrease in prefetch accuracy or an increase in bus utilization. The display device 17 then provides the user with this information by displaying it on the screen.

[0112] The user checks the information displayed on the display device 17, which parts of the user-written program showed significant decreases in prefetch accuracy and increases in bus usage. The user then uses this information to tune the program and evaluates its performance by running the tuned program again on the core 11.

[0113] For example, one tuning technique involves rewriting parts of the program that indirectly access an array via an index list to directly access the data array. This can improve the accuracy of access pattern prediction by prefetcher 110.

[0114] As described above, the CPU in this embodiment provides the user with information indicating which parts of the user-written program experienced significant decreases in prefetch accuracy or increases in bus usage. This allows the user to properly tune the program and improve the performance of the computational processing. [Explanation of symbols]

[0115] 1. Information Processing Device 10 CPU 11 cores 12 L1 cache 13 L2 Cache 14 LLC 15 Main Memory 16 Auxiliary storage 17 Display device 18 Input device 101 Selector 102 Precision Monitoring Unit 103 Bandwidth Monitoring Unit 104 Integrated Monitoring Department 105 OS 106 Information Management Department 110-113 Prefetcher

Claims

1. Multiple caches are arranged in a tiered manner between the core and main memory, Each of the aforementioned caches is configured with multiple prefetchers, each with a different data access prediction algorithm. For each of the aforementioned caches, a precision monitoring unit monitors the prefetch miss rate by each of the aforementioned prefetchers and determines which prefetcher to have perform prefetching based on the miss rate. A bandwidth monitoring unit monitors the utilization of any or all of the read buses between each of the caches or between the cache and the main memory, and causes the prefetcher corresponding to the cache on the core side of the low-utility bus where the utilization is below a threshold to issue a first prefetch and a second prefetch with lower accuracy than the first prefetch, and causes the prefetcher corresponding to the cache on the core side of the high-utility bus where the utilization is above the threshold to stop issuing the second prefetch and issue the first prefetch. A processing unit characterized by comprising:

2. The arithmetic processing device according to claim 1, wherein the accuracy monitoring unit maintains the prefetch results for each of the prefetchers for each cache over a predetermined past period, and calculates the miss rate for each of the prefetchers based on the information of the data accessed during the predetermined period and the prefetch results.

3. The accuracy monitoring unit decides to have the low-error rate prefetcher with the lowest error rate perform prefetching. The bandwidth monitoring unit causes the low-miss rate prefetcher corresponding to the cache on the core side of the low-utility bus to issue the first prefetch and the second prefetch, and causes the low-miss rate prefetcher corresponding to the cache on the core side of the high-utility bus to stop issuing the second prefetch and issue the first prefetch. The arithmetic processing device according to feature 1.

4. The aforementioned cores exist in multiple quantities, and each of them runs multiple threads. The system further includes an integrated monitoring unit that determines the thread to be moved and the target core based on the aforementioned error rate, and moves the thread to be moved to the target core. The arithmetic processing device according to feature 1.

5. The arithmetic processing device according to claim 4, characterized in that the integrated monitoring unit determines the thread to be moved and the core to which it will be moved based on the error rate and the utilization rate.

6. The arithmetic processing apparatus according to claim 1, further comprising an information management unit that acquires a program counter for a program executed from the core, compares the program counter with the error rate monitored by the accuracy monitoring unit and the utilization rate monitored by the bandwidth monitoring unit, generates relationship information between the program and the error rate and the utilization rate, and outputs the generated relationship information.

7. A processing unit having multiple caches arranged in a hierarchical structure between the core and main memory, and multiple prefetchers arranged for each cache, each with a different data access prediction algorithm, For each of the aforementioned caches, the prefetch miss rate by each of the aforementioned prefetchers is monitored. Based on the aforementioned error rate, the prefetcher that will perform prefetching is determined. The usage rate of any or all of the read buses between each of the caches or between the cache and the main memory is monitored. The prefetcher corresponding to the cache on the core side of the low-utilization bus, where the utilization rate is below a threshold, is instructed to issue a first prefetch and a second prefetch with a lower accuracy than the first prefetch. If the utilization rate is above the threshold, the prefetcher corresponding to the cache on the core side of the high-utility bus will be instructed to stop issuing the second prefetch and issue the first prefetch. A method for performing calculations characterized by the above.

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