Ceramic electronic components

Abstract

To provide a ceramic electronic component capable of improving electrostatic capacity while suppressing the occurrence of cracks.SOLUTION: A ceramic electronic component has a laminated structure in which each of a plurality of dielectric layers containing ceramic as a main component and each of a plurality of internal electrode layers are alternately laminated. In at least one of the plurality of internal electrode layers, the continuity rate is 80% or less, and the average pore diameter is the thickness of the dielectric layer or less.SELECTED DRAWING: Figure 8

Description

[Technical Field]

[0001] This invention relates to ceramic electronic components. [Background technology]

[0002] In recent years, with the miniaturization and increased performance of electronic devices such as smartphones, there has been a strong demand for miniaturization of ceramic electronic components used in them. However, if the chip size is reduced, for example, the area of ​​the internal electrode layer facing the dielectric layer inevitably decreases, thus reducing capacitance. To reduce chip size while maintaining capacitance, it is necessary to thin the dielectric layer, further thin the internal electrode layer to increase the number of layers for high-density lamination, and improve the material performance of the dielectric layer, such as its dielectric constant. As shown in the following equation, capacitance is inversely proportional to the thickness of the dielectric layer, so generally, thinning the dielectric layer is particularly effective. C = ε × S / d C: capacitance [F], ε: dielectric constant of dielectric material [F / m], S: electrode area [m²] 2 ], electrode spacing (thickness of dielectric layer): d [m] [Prior art documents] [Patent Documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2014-082435 [Patent Document 2] Japanese Patent Publication No. 2016-192477 [Patent Document 3] Japanese Patent Publication No. 2015-131982 [Patent Document 4] Japanese Patent Publication No. 2011-228023 [Patent Document 5] Japanese Patent Publication No. 2013-089944 [Patent Document 6] Japanese Patent Publication No. 2006-332334 [Patent Document 7] Japanese Patent Application Publication No. 11-031633 [Patent Document 8] Japanese Patent Application Publication No. 10-012476 [Patent Document 9] Japanese Patent Publication No. 2018-056433 [Overview of the project] [Problems that the invention aims to solve]

[0004] Multilayer ceramic capacitors are formed by laminating a metal conductive paste containing metal particles such as Ni and Cu with a dielectric green sheet, and then sintering and shrinking the resulting material. However, because the sintering start temperatures of the metal particles and the dielectric differ significantly, a discrepancy in shrinkage behavior occurs between the metal conductive paste and the dielectric green sheet during firing. This can lead to structural defects such as voids in the internal electrode layer, potentially reducing the continuity of the internal electrode layer. A decrease in continuity can result in performance degradation such as a decrease in capacitance and variations, and in more severe cases, it can cause discontinuity in the internal electrode layer, rendering the capacitor unusable.

[0005] To address these challenges, many studies have been conducted with the aim of improving the continuity of the internal electrode layer. For example, many methods have been proposed to add a ceramic co-material to the metal conductive paste in order to reduce the difference in shrinkage behavior during firing between the metal conductive paste and the dielectric green sheet (see, for example, Patent Document 1). Other proposed methods include improving the wettability between the metal conductive paste and the dielectric green sheet by adding metal elements such as Ca, Mg, Ba, and Mn to the metal conductive paste (see, for example, Patent Document 2), adjusting the sinterability of Ni by coating the Ni particles of the metal conductive paste (see, for example, Patent Document 3), and improving the heat resistance of Ni by adding Pt and Au to the metal conductive paste (see, for example, Patent Document 4).

[0006] On the other hand, if the continuity rate of the internal electrode layer is increased, cracks may easily occur because the stress generated from the difference in shrinkage rate during sintering between the internal electrode layer and the dielectric layer cannot be fully absorbed. Methods for restricting the continuity rate from being too high have also been proposed (see, for example, Patent Documents 5 to 8). However, if the continuity rate is restricted, the capacitance will naturally decrease.

[0007] The present invention has been made in view of the above problems, and an object thereof is to provide a ceramic electronic component capable of improving the capacitance while suppressing the occurrence of cracks.

Means for Solving the Problems

[0008] The ceramic electronic component according to the present invention has a laminated structure in which each of a plurality of dielectric layers mainly composed of ceramic and each of a plurality of internal electrode layers are alternately laminated. In at least any one of the plurality of internal electrode layers, the continuity rate is 80% or less, and the average pore diameter is not more than the thickness of the dielectric layer.

[0009] In the above ceramic electronic component, the continuity rate may be 50% or more.

[0010] In the above ceramic electronic component, the average pore diameter may be 5 μm or less.

[0011] In the above ceramic electronic component, the thickness of the plurality of dielectric layers may be 0.1 μm or more and 10 μm or less.

[0012] In the above ceramic electronic component, the thickness of the plurality of internal electrode layers may be 0.1 μm or more and 3 μm or less.

Effects of the Invention

[0013] According to the present invention, it is possible to provide a ceramic electronic component and a method for manufacturing a ceramic electronic component capable of improving the capacitance while suppressing the occurrence of cracks.

Brief Description of the Drawings

[0014] [Figure 1] It is a partial cross-sectional perspective view of a multilayer ceramic capacitor. [Figure 2] It is a cross-sectional view taken along line A-A of FIG. 1. [Figure 3] It is a cross-sectional view taken along line B-B of FIG. 1. [Figure 4] It is a diagram showing the continuity rate of the internal electrode layer. [Figure 5] It is a diagram illustrating a method for calculating the average pore diameter. [Figure 6] (a) to (d) show a part of an example of the model used in the simulation. [Figure 7] (a) to (d) show a part of an example of the model used in the simulation. [Figure 8] It is a graph of capacitance. [Figure 9] It is a graph of capacitance retention rate. [Figure 10] It is a diagram illustrating the flow of a method for manufacturing a multilayer ceramic capacitor.

Mode for Carrying Out the Invention

[0015] Hereinafter, embodiments will be described while referring to the drawings.

[0016] (Embodiment) FIG. 1 is a partial cross-sectional perspective view of a multilayer ceramic capacitor 100 according to an embodiment. FIG. 2 is a cross-sectional view taken along line A-A of FIG. 1. FIG. 3 is a cross-sectional view taken along line B-B of FIG. 1. As illustrated in FIGS. 1 to 3, the multilayer ceramic capacitor 100 includes a multilayer chip 10 having a substantially rectangular parallelepiped shape and external electrodes 20a and 20b provided on two opposing end faces of the multilayer chip 10. Among the four surfaces of the multilayer chip 10 other than the two end faces, the two surfaces other than the upper and lower surfaces in the stacking direction are referred to as side surfaces. The external electrodes 20a and 20b extend on the upper surface, lower surface, and two side surfaces of the multilayer chip 10 in the stacking direction. However, the external electrodes 20a and 20b are spaced apart from each other.

[0017] The multilayer chip 10 has a structure in which dielectric layers 11 containing a ceramic material that functions as a dielectric and internal electrode layers 12 containing a base metal material are alternately stacked. The edges of each internal electrode layer 12 are alternately exposed to the end face of the multilayer chip 10 where the external electrode 20a is provided and the end face where the external electrode 20b is provided. As a result, each internal electrode layer 12 is alternately conductive to the external electrode 20a and the external electrode 20b. Consequently, the multilayer ceramic capacitor 100 has a structure in which multiple dielectric layers 11 are stacked via internal electrode layers 12. Furthermore, in the laminate of dielectric layers 11 and internal electrode layers 12, the outermost layer in the stacking direction is an internal electrode layer 12, and the top and bottom surfaces of the laminate are covered by a cover layer 13. The cover layer 13 is mainly composed of a ceramic material. For example, the main components of the cover layer 13 are the same as those of the dielectric layer 11 and the ceramic material.

[0018] The dimensions of the multilayer ceramic capacitor 100 are, for example, 0.25 mm in length, 0.125 mm in width, and 0.125 mm in height, or 0.4 mm in length, 0.2 mm in width, and 0.2 mm in height, or 0.6 mm in length, 0.3 mm in width, and 0.3 mm in height, or 1.0 mm in length, 0.5 mm in width, and 0.5 mm in height, or 3.2 mm in length, 1.6 mm in width, and 1.6 mm in height, or 4.5 mm in length, 3.2 mm in width, and 2.5 mm in height, but are not limited to these dimensions.

[0019] The internal electrode layer 12 mainly consists of base metals such as Ni (nickel), Cu (copper), and Sn (tin). Precious metals such as Pt (platinum), Pd (palladium), Ag (silver), and Au (gold), or alloys containing these, may also be used as the internal electrode layer 12.

[0020] The dielectric layer 11 mainly consists of a ceramic material having a perovskite structure represented by the general formula ABO3. Note that this perovskite structure is an ABO3 structure that deviates from the stoichiometric composition. 3-αIt includes. For example, as the ceramic material, BaTiO3 (barium titanate), CaZrO3 (calcium zirconate), CaTiO3 (calcium titanate), SrTiO3 (strontium titanate), MgTiO3 (magnesium titanate), Ba forming a perovskite structure 1-x-y Ca x Sr y Ti 1-z Zr z O3 (0 ≤ x ≤ 1, 0 ≤ y ≤ 1, 0 ≤ z ≤ 1), etc., can be selected and used from at least one of them. Ba 1-x-y Ca x Sr y Ti 1-z Zr z O3 includes barium strontium titanate, barium calcium titanate, barium zirconate, barium zirconium titanate, calcium zirconium titanate, and barium calcium zirconium titanate, etc.

[0021] As illustrated in FIG. 2, the region where the internal electrode layer 12 connected to the external electrode 20a and the internal electrode layer 12 connected to the external electrode 20b face each other is the region where capacitance occurs in the multilayer ceramic capacitor 100. Therefore, the region where the capacitance occurs is referred to as the capacitance region 14. That is, the capacitance region 14 is the region where adjacent internal electrode layers 12 connected to different external electrodes face each other.

[0022] The region where the internal electrode layers 12 connected to the external electrode 20a face each other without passing through the internal electrode layer 12 connected to the external electrode 20b is referred to as the end margin 15. Also, the region where the internal electrode layers 12 connected to the external electrode 20b face each other without passing through the internal electrode layer 12 connected to the external electrode 20a is also the end margin 15. That is, the end margin 15 is the region where the internal electrode layers 12 connected to the same external electrode face each other without passing through the internal electrode layer 12 connected to a different external electrode. The end margin 15 is a region where no capacitance occurs.

[0023] As illustrated in Figure 3, in the stacked chip 10, the region extending from the two sides of the stacked chip 10 to the internal electrode layer 12 is called the side margin 16. That is, the side margin 16 is a region provided to cover the ends of the multiple internal electrode layers 12 stacked in the stacked structure that extend to the two sides. The side margin 16 is also a region that does not generate electrical capacitance.

[0024] Figure 4 shows the continuity of the internal electrode layer 12. As illustrated in Figure 4, in an observation area of ​​length L0 in a certain internal electrode layer 12, the lengths L1, L2, ..., Ln of the metal portion can be measured and summed up, and the proportion of the metal portion, ΣLn / L0, can be defined as the continuity of that layer. As an example, an observation area 20 times the thickness of the dielectric layer 11, for example, if the thickness is 1 μm, an observation area with length L0 = 20 μm may be observed.

[0025] By increasing the continuity of the internal electrode layer 12, the decrease and variation in the capacitance of the multilayer ceramic capacitor 100 can be suppressed. However, capacitance is not determined solely by the continuity. Furthermore, if the continuity of the internal electrode layer 12 is made too high, the stress resulting from the difference in shrinkage rates during sintering between the internal electrode layer 12 and the dielectric layer 11 may not be absorbed, making it more prone to cracking.

[0026] Therefore, through diligent research by the present inventors, it has been found that by controlling not only the continuity of the internal electrode layer 12 but also the average value of the diameter of each hole formed in the internal electrode layer 12 (hereinafter referred to as the average hole diameter), it is possible to improve capacitance while suppressing the occurrence of cracks. The details will be explained below. In the following explanation, the internal electrode layer whose continuity and average hole diameter are controlled may be at least one of the internal electrode layers 12 included in the multilayer ceramic capacitor 100, or it may be all of them.

[0027] The average pore diameter in the internal electrode layer 12 can be determined, for example, based on the following measurement. First, as illustrated in Figure 5, the lengths D1, D2, ..., Dm of the parts (pores) where no metal exists are measured in an observation area of ​​length L0 in a certain internal electrode layer 12, and the sum of these lengths is divided by the number of measurements m to obtain the average value ΣDm / m. Here, it is assumed that the pores formed in the internal electrode layer 12 are holes that penetrate the internal electrode layer 12 in the thickness direction and are, for example, cylindrical in shape. The pores may be in a vacuum state, may contain residual air, or may contain residual ceramic components. If the cross-section of the cross-sectional view passes through the center of the pore, Dm is equal to the diameter of the pore. If the cross-section of the cross-sectional view is offset from the center of the pore, Dm will be smaller than the diameter of the pore. The expected value of the pore diameter is 4 / π × Dm, which is Dm multiplied by 4 / π (≒1.27324). Therefore, the average pore diameter can be defined as 4 / π × ΣDm / m. Furthermore, the continuity rate and average pore diameter may be measured using methods such as those described in Patent Document 9, and are not dependent on the measurement method, but it is desirable to measure as many locations as possible to obtain them. In addition, the average pore diameter may be calculated by extracting only the pores where Dm is 1 / 10 or more of the thickness of the dielectric layer 11 in the observation area of ​​length L0.

[0028] A decrease in the continuity of the internal electrode layer 12 leads to a decrease in capacitance, but it is difficult to accurately determine the extent of this decrease experimentally. This is because it is difficult to create a multilayer ceramic capacitor 100 by completely controlling the structure, including the thickness of the dielectric layer 11, the thickness of the internal electrode layer 12, the continuity of the internal electrode layer 12, and the area of ​​the internal electrode layer 12. However, such problems are less likely to occur in computer simulations. Therefore, the capacitance of the multilayer ceramic capacitor 100 was determined by changing the continuity of the internal electrode layer 12 and the average pore diameter using electric field analysis in computer simulations. For the electrolytic analysis, Ansys Maxwell 2020 R1, electromagnetic field analysis software from ANSYS, was used.

[0029] Figures 6(a) to 7(d) show some examples of the models used in the simulation. As illustrated in Figures 6(a) to 7(d), each model is a model of the inside of a multilayer ceramic capacitor 100. In this model, boundary conditions are set so that the same structural pattern is repeated. Therefore, this model is one in which cylindrical holes that penetrate the internal electrode layer 12 are arranged regularly. The capacitance to be calculated is per unit volume or per unit area. As a simulation condition, the dielectric layer 11 was set to have a thickness of 1 μm and a relative permittivity εR of 5,000.

[0030] In the model shown in Figure 6(a), the continuity of the internal electrode layer 12 is set to 100%. Since there are no pores in the internal electrode layer 12, the average pore diameter is 0. In the model shown in Figure 6(b), the continuity of the internal electrode layer 12 is set to 80%. The average pore diameter of the internal electrode layer 12 is set to 1 μm. In the model shown in Figure 6(c), the continuity of the internal electrode layer 12 is set to 50%. The average pore diameter of the internal electrode layer 12 is set to 1 μm. In the model shown in Figure 6(d), the continuity of the internal electrode layer 12 is set to 30%. The average pore diameter of the internal electrode layer 12 is set to 1 μm. As can be seen from these models, even if the average pore diameter is the same, if the continuity is different, the locations where metal components exist in the internal electrode layer 12 will be different.

[0031] In the model shown in Figure 7(a), the continuity of the internal electrode layer 12 is set to 50%. The average pore size of the internal electrode layer 12 is set to 0.25 μm. In the model shown in Figure 7(b), the continuity of the internal electrode layer 12 is set to 50%. The average pore size of the internal electrode layer 12 is set to 0.5 μm. In the model shown in Figure 7(c), the continuity of the internal electrode layer 12 is set to 50%. The average pore size of the internal electrode layer 12 is set to 2 μm. In the model shown in Figure 7(d), the continuity of the internal electrode layer 12 is set to 50%. The average pore size of the internal electrode layer 12 is set to 4 μm. As can be seen from these models, even if the continuity is the same, if the average pore size is different, the locations where metal components are present in the internal electrode layer 12 will be different.

[0032] Table 1 shows the calculated capacitance. Figure 8 shows a graph of the calculated capacitance. Here, capacitance is the capacitance per unit area [mF / m 2 The continuity rates were set to 100%, 95%, 90%, 80%, 70%, 60%, 50%, 40%, and 30%. The average pore size was set to 0.03125μm, 0.0625μm, 0.125μm, 0.25μm, 0.5μm, 1μm, 2μm, 4μm, 8μm, and 16μm. Note that the model with 100% continuity has no pores, so the average pore size of the model with 100% continuity is 0. [Table 1]

[0033] From the results in Table 1 and Figure 8, it was found that in models other than those with 100% continuity, capacitance decreases with decreasing continuity for all average hole diameters, but the degree of decrease varies greatly depending on the average hole diameter. That is, the larger the average hole diameter, the greater the decrease in capacitance, and conversely, the smaller the average hole diameter, the smaller the decrease in capacitance. Therefore, even with the same continuity, capacitance can be increased by reducing the average hole diameter. The reason why the degree of capacitance decrease differs depending on the average hole diameter is presumed to be that as the hole size increases, the proportion of the region within the capacitance region 14 where the electric field cannot wrap around and therefore capacitance does not manifest increases.

[0034] Next, the ratio from the capacitance of the model with 100% continuity is defined as the capacitance retention rate. Table 2 shows the calculated capacitance retention rates. Figure 9 shows a graph of the calculated capacitance retention rates. The capacitance retention rate also shows a similar trend to the capacitance. The degree of decrease in capacitance retention rate with respect to continuity rate varies greatly depending on the average pore diameter. In particular, this difference is significant at continuity rates of 80% or less. Furthermore, by setting the average pore diameter to 1 μm or less, the decrease in capacitance retention rate due to the decrease in continuity rate can be effectively prevented. [Table 2]

[0035] In this calculation, changing the relative permittivity of the dielectric layer 11 changes the capacitance, but the capacitance retention rate remains unchanged. This is because the capacitance of the model with 100% continuity and the capacitance of the model with less than 100% continuity change at the same ratio. Therefore, the above results are independent of the relative permittivity of the dielectric layer 11, that is, independent of the material of the dielectric layer 11.

[0036] On the other hand, changing the thickness of the dielectric layer 11 changes both the capacitance and the capacitance retention rate. Here, the capacitance retention rate is the same for a dielectric layer 11 thickness of 1 μm and an average pore diameter of 1 μm, and for a dielectric layer 11 thickness of 0.5 μm and an average pore diameter of 0.5 μm, because the models are similar. Therefore, with a dielectric layer 11 thickness of 1 μm, the decrease in capacitance retention rate could be effectively prevented by making the average pore diameter 1 μm or less. This can be rephrased as saying that the decrease in capacitance can be effectively prevented by making the average pore diameter less than or equal to the thickness of the dielectric layer 11.

[0037] From the above results, it is possible to design a high-performance multilayer ceramic capacitor 100 by making the average pore diameter of the internal electrode layer 12 less than or equal to the thickness of the dielectric layer 11, provided that the continuity ratio of the internal electrode layer 12 is 80% or less. For example, it is possible to design a multilayer ceramic capacitor 100 that is unprecedented in that it suppresses crack generation by lowering the continuity ratio of the internal electrode layer 12 while maintaining high capacitance by also reducing the average pore diameter.

[0038] To more effectively prevent a decrease in capacitance retention, when the continuity of the internal electrode layer 12 is 80% or less, it is preferable to set the average pore diameter of the internal electrode layer 12 to 0.9 times or less the thickness of the dielectric layer 11, more preferably to 0.8 times or less, and even more preferably to 0.5 times or less.

[0039] If the continuity of the internal electrode layer 12 is too low, sufficient capacitance may not be obtained. Therefore, it is preferable to set a lower limit on the continuity of the internal electrode layer 12. For example, the continuity of the internal electrode layer 12 is preferably 50% or more, more preferably 60% or more, and even more preferably 70% or more.

[0040] The average pore size in the internal electrode layer 12 is preferably small, as explained in Figures 8 and 9. For example, the average pore size in the internal electrode layer 12 is preferably 5 μm or less, more preferably 1 μm or less, and even more preferably 0.5 μm or less.

[0041] The thickness of each dielectric layer 11 is, for example, 0.1 μm to 10 μm, 0.3 μm to 3 μm, or 0.5 μm to 1 μm. The thickness of each dielectric layer 11 can be measured by, for example, exposing the cross-section of the multilayer ceramic capacitor shown in Figure 2 by mechanical polishing, and then taking an image with a microscope such as a scanning transmission electron microscope and calculating the average thickness at 10 points.

[0042] The thickness of each internal electrode layer 12 is, for example, 0.1 μm to 3 μm, 0.5 μm to 2 μm, or 0.8 μm to 1.2 μm. The thickness of each internal electrode layer 12 can be measured by, for example, exposing the cross-section of the multilayer ceramic capacitor shown in Figure 2 by mechanical polishing, and then taking an image with a microscope such as a scanning transmission electron microscope and determining the average thickness at 10 points.

[0043] Next, the manufacturing method of the multilayer ceramic capacitor 100 will be described. Figure 10 is a diagram illustrating the flow of the manufacturing method of the multilayer ceramic capacitor 100.

[0044] (Process for producing raw material powder) First, a dielectric material is prepared to form the dielectric layer 11. The A-site and B-site elements contained in the dielectric layer 11 are usually present in the form of a sintered body of ABO3 particles. For example, BaTiO3 is a tetragonal compound having a perovskite structure and exhibits a high dielectric constant. This BaTiO3 can generally be obtained by synthesizing barium titanate by reacting a titanium raw material such as titanium dioxide with a barium raw material such as barium carbonate. Various methods have been conventionally known for synthesizing the main component ceramic of the dielectric layer 11, such as the solid-phase method, the sol-gel method, and the hydrothermal method. In this embodiment, any of these can be employed.

[0045] A predetermined additive compound is added to the obtained ceramic powder according to the purpose. Examples of additive compounds include oxides of magnesium (Mg), manganese (Mn), vanadium (V), chromium (Cr), rare earth elements (yttrium (Y), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holomium (Ho), erbium (Er), thulium (Tm), and ytterbium (Yb)), or oxides containing cobalt (Co), nickel (Ni), lithium (Li), boron (B), sodium (Na), potassium (K), or silicon (Si), or glass containing cobalt, nickel, lithium, boron, sodium, potassium, or silicon.

[0046] For example, a ceramic material can be prepared by wet-mixing a ceramic raw material powder with a compound containing an additive, followed by drying and pulverization. For example, the ceramic material obtained as described above may be subjected to pulverization as needed to adjust the particle size, or the particle size may be adjusted by combining this with a classification process. A dielectric material can be obtained through the above steps.

[0047] (Lamination process) Next, the obtained dielectric material is wet-mixed with a binder such as polyvinyl butyral (PVB) resin, an organic solvent such as ethanol or toluene, and a plasticizer. Using the resulting slurry, a dielectric green sheet is coated onto a substrate using, for example, a die coater or doctor blade method, and then dried.

[0048] Next, a metal conductive paste containing an organic binder for forming internal electrodes is printed onto the surface of the dielectric green sheet by screen printing, gravure printing, or the like, to arrange an internal electrode layer pattern that alternately leads to a pair of external electrodes with different polarities. Ceramic particles are added to the metal conductive paste as a co-material. The main component of the ceramic particles is not particularly limited, but it is preferable that it is the same as the main component ceramic of the dielectric layer 11. For example, BaTiO3 with an average particle diameter of 50 nm or less may be uniformly dispersed.

[0049] Subsequently, a dielectric green sheet with an internal electrode layer pattern printed on it is punched out to a predetermined size. With the substrate peeled off, the punched dielectric green sheet is stacked for a predetermined number of layers (e.g., 100 to 1000 layers) such that the internal electrode layer 12 and dielectric layer 11 are staggered, and the edges of the internal electrode layer 12 are alternately exposed on both ends of the dielectric layer 11 in the longitudinal direction, alternately leading to a pair of external electrodes 20a and 20b with different polarities. Cover sheets for forming a cover layer 13 are then pressed onto the top and bottom of the stacked dielectric green sheet and cut to a predetermined chip size (e.g., 1.0 mm x 0.5 mm).

[0050] (Firing process) The ceramic laminate thus obtained is subjected to binder removal treatment in an N2 atmosphere, and then a metal paste that will serve as the base layer for the external electrodes 20a and 20b is applied by the dip method, and the oxygen partial pressure is 10 -12 MPa~10 -9 The product is fired in a reducing atmosphere at MPa and 1160°C to 1280°C for 5 to 10 minutes.

[0051] (Re-oxidation process) In order to return oxygen to the partially reduced main phase, barium titanate, of the dielectric layer 11 fired in a reducing atmosphere, heat treatment may be performed at approximately 1000°C in a mixed gas of N2 and water vapor, or at 500°C to 700°C in air, without oxidizing the internal electrode layer 12. This process is called the re-oxidation process.

[0052] (Plating process) Subsequently, a metal coating of Cu, Ni, Sn, etc. is applied to the underlayer of the external electrodes 20a and 20b by plating. Through these steps, the multilayer ceramic capacitor 100 is completed.

[0053] To reduce the average pore size of the internal electrode layer 12, the growth of pores in the internal electrode layer 12 can be suppressed by, for example, reducing the particle size of the main component metal particles in the metal conductive paste used to obtain the internal electrode layer 12, or by increasing the average heating rate from room temperature to the maximum temperature during firing. Alternatively, particles made of a high-melting-point material can be added to the metal conductive paste. For example, the particle size of the main component metal particles in the metal conductive paste used to obtain the internal electrode layer 12 can be set to a particle size of 1 / 2 or less of the thickness of the internal electrode layer 12, for example, metal particles with a particle size of 100 nm or less, more preferably metal particles with a particle size of 50 nm or less. Alternatively, the average heating rate from room temperature to the maximum temperature during firing can be set to 100°C / second or more, more preferably 200°C / second or more. Alternatively, molybdenum (Mo), niobium (Nb), tantalum (Ta), and tungsten (W) can be used as high-melting-point materials added to the metal conductive paste.

[0054] In the embodiments described above, multilayer ceramic capacitors were explained as an example of ceramic electronic components, but the invention is not limited to them. For example, other electronic components such as varistors and thermistors may be used.

[0055] Although embodiments of the present invention have been described in detail above, the present invention is not limited to these specific embodiments, and various modifications and changes are possible within the scope of the gist of the present invention as described in the claims. [Explanation of Symbols]

[0056] 10 stacked chips 11 Dielectric layer 12 Internal electrode layer 13. Cover layer 14 capacity area 15 End margin 16 Side margins 20a,20b external electrode 100 Multilayer Ceramic Capacitors

Claims

1. It has a laminated structure in which multiple dielectric layers, each having a thickness of 3 μm or less and composed mainly of ceramic, and multiple internal electrode layers are alternately stacked. In at least one of the aforementioned plurality of internal electrode layers, the continuity ratio is 80% or less. A ceramic electronic component characterized in that the average pore diameter in the internal electrode layer having a continuity rate of 80% or less is less than or equal to the thickness of the dielectric layer.

2. The ceramic electronic component according to claim 1, characterized in that the continuity rate is 50% or more.

3. The ceramic electronic component according to claim 1 or 2, characterized in that the average pore diameter is 100 μm or less.

4. The ceramic electronic component according to any one of claims 1 to 3, characterized in that the thickness of the plurality of dielectric layers is 0.1 μm or more.

5. The ceramic electronic component according to any one of claims 1 to 4, characterized in that the thickness of the plurality of internal electrode layers is 0.1 μm or more and 3 μm or less.

6. The ceramic electronic component according to any one of claims 1 to 5, characterized in that the thickness of the plurality of dielectric layers is 1 μm or less.

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