Methods for making materials and semiconductor structures porous.

Abstract

To provide a method for making a group III nitride material porous by using a few processing steps.SOLUTION: A method for making a III nitride material in a semiconductor structure porous is provided, and the semiconductor structure includes a subsurface structure of a first III nitride material having charge carrier density exceeding 5×1017 cm-3 under a surface layer of a second III nitride material having charge carrier density between 1×1014 cm-3 and 1×1017 cm-3. The method includes the steps of: exposing the surface structure to an electrolyte; and applying a potential difference between the first III nitride material and the electrolyte so as to make the subsurface structure porous by electrochemical etching, and on the other hand so as not to make the surface layer porous. Further, the semiconductor structure and its use are provided.SELECTED DRAWING: None

Description

[Technical Field]

[0001] The present invention relates to semiconductor materials, particularly group III nitride materials, methods for porous semiconductor structures, the use of semiconductor structures, and devices incorporating or mounted on semiconductor structures. The present invention may be particularly advantageous for the manufacture of porous semiconductor structures for use as distributed Bragg reflectors (DBRs) and substrates in the fabrication of semiconductor devices. [Background technology]

[0002] The class of semiconductor materials known as "Group III nitrides" includes gallium nitride (GaN), indium nitride (InN), and aluminum nitride (AlN), along with their ternary and quaternary alloys. Group III nitrides have not only achieved commercial success in solid-state lighting and power electronics, but also demonstrate particular advantages for quantum light sources and light-matter interactions.

[0003] While various Group III nitride materials are commercially interesting, gallium nitride (GaN) is widely regarded as one of the most important novel semiconductor materials and is of particular interest for several applications.

[0004] It is well known that introducing pores into bulk GaN can significantly affect its material properties, such as its refractive index, without negatively impacting its electrical conductivity. Therefore, the possibility of tuning the optical properties of GaN by changing its porosity makes porous GaN highly interesting for optoelectronic applications.

[0005] WO2011 / 094391A1 discloses the possibility of fabricating nanoporous GaN by electrochemical etching, in which n-type doped GaN is etched to yield porosity by contacting it with an electrolyte and applying an etching potential. WO2011 / 094391A1 (paragraph

[0031] ) describes etching of two types of GaN structures. In the first type, the surface of an exposed layer of n-type doped GaN is etched in contact with an electrolyte to create a porous layer. The etching proceeds perpendicular to the layer surface and is referred to as perpendicular etching in WO2011 / 094391A1. In the second type of structure, a top layer of undoped GaN is formed on top of the n-type doped GaN layer. Thus, the n-type doped GaN forms a sub-surface layer. The layer is then dry-etched or cleaved to form trenches that expose the edges or sidewalls of the layer, which can then be exposed to the electrolyte. The etching then proceeds selectively from the exposed edges through the n-type layer, porous the doped subsurface layer but not the overlying undoped layer. In WO2011 / 094391A1, this is called horizontal or transverse etching.

[0006] Electrochemical etching of n-type GaN has been further described in various academic papers. All of these prior art documents follow the teachings of WO2011 / 094391A1, which state that etching can be performed "perpendicularly" to the exposed n-type GaN surface or "horizontally" to the edge of the n-type GaN layer sandwiched between two layers of undoped GaN and / or an electrically insulating substrate.

[0007] Chen et al, Journal of Applied Physics, 112, 064303 (2012), describes the use of a 500 nm thick undoped underlying GaN layer as an "etch stop" to prevent further etching of n-type GaN during vertical etching. Chen et al further note that vertical etching caused surface pits to form on the surface of the n-type GaN.

[0008] On the other hand, C. Zhang, et al. ACS Photonics 2015, 2, 980 discloses the horizontal etching of a multilayer structure consisting of alternating layers of undoped GaN and n-type GaN. To enable horizontal etching, the multilayer sample was first patterned by lithography using trenches spaced 50 μm apart to expose the edges or sidewalls of the layers, allowing for horizontal transport of the electrolyte into the n-type layer during porosity. An electrically insulating layer of SiO2 was also formed on top of the top layer of undoped GaN as a protective layer.

[0009] Horizontal or transverse etching from the edge of the subsurface layer is limited by factors including the diffusion rate of electrolytes into and out of the layer during etching, which limits the distance from the edge of the layer that can be etched, and therefore means there is a limit to the width of the sample that can be porous by horizontal etching (when etched from the opposite edge).

[0010] The authors of the prior art addressed this sample-side limitation by dry-etching vertical trenches into the sample prior to etching, resulting in the exposure of sample layer edges at regular intervals. This allows the electrolyte to come into contact with the layer edges and etch horizontally through the sample structure. Dry-etching trenches mean that each sample is effectively divided into multiple smaller samples spread between adjacent trenches. The distance between adjacent trenches is naturally limited to twice the distance through which horizontal etching can penetrate the layer (assuming the sample is etched horizontally from both sides). In C. Zhang, et al., for example, the sample width for horizontal etching is limited to a dimension of 50 μm between trenches.

[0011] This additional processing step increases wafer processing costs and also limits the maximum dimensions of the resulting porous structure. Dividing the semiconductor structure into small mesas by dry etching trenches can also make the resulting porous structure unsuitable for use in the fabrication of certain semiconductor devices. Therefore, this technique may limit the feasibility of horizontal etching methods and the resulting structures for large-scale, practical optoelectronic devices.

[0012] Furthermore, prior art horizontal etching methods involve applying a relatively thick dielectric layer to the top of the semiconductor structure prior to etching. This dielectric layer is often formed from silica (SiO2) and covers the surface layer, preventing the electrolyte from coming into contact with the sample's surface layer during etching. This layer acts as a mask to protect the surface layer from damage during dry etching of the trench or during the horizontal etching process. The application of this layer and its subsequent removal, if necessary, introduces further processing steps and constrains material design. [Overview of the project] [Means for solving the problem]

[0013] The present invention relates to methods for porousizing Group III nitride materials and semiconductor structures, the use of semiconductor structures, and devices incorporating or fitted with semiconductor structures, as defined in the appended independent claims which must be referenced herein. Preferred or advantageous features of the present invention are described in the dependent claims.

[0014] The present inventors' publication, Zhu, T. et al. Wafer-scale Fabrication of Non-polar Mesoporous GaN Distributed Bragg Reflectors via Electrochemical Porosification. Sci. Rep. 7, 45344; doi: 10.1038 / srep45344 (2017), is incorporated herein by reference in its entirety.

[0015] According to a first aspect of the present invention, a method for porousizing a group III nitride material in a semiconductor structure is provided. The semiconductor structure is 1 × 10 14 cm -3 From 1 x 10 17 cm -3 Below the surface layer of the second group III nitride material having a charge carrier density between 5 × 10 17 cm -3 The method includes a subsurface structure of a first group III nitride material having a charge carrier density exceeding [a certain value]. The method includes the steps of exposing the surface layer to an electrolyte and applying a potential difference between the subsurface structure and the electrolyte so that the subsurface structure is porous by electrochemical etching, while the surface layer is not porous.

[0016] This method is sometimes referred to separately as a method for making a group III nitride material subsurface porous, or a method for making a group III nitride material subsurface porous. Since a subsurface group III nitride material can be selectively porous depending on its charge carrier density, such a method can be a method for selectively making a group III nitride material porous.

[0017] The subsurface structure can be provided in a desired arrangement or pattern under the surface layer. Preferably, the subsurface structure forms a sub-surface layer under the surface layer. Particularly preferably, the subsurface structure forms a continuous or unbroken sub-surface layer under the surface layer.

[0018] The subsurface structure can advantageously be made porous by electrochemical etching through the surface layer. That is, the method can be a method of making porous through a layer.

[0019] Unlike in the prior art, in the present method, it is not necessary to expose the group III nitride material to be etched to the electrolyte. In WO2011 / 094391A1, for example, both "horizontal" etching and "vertical" etching require the edge or surface of the layer to be etched to be exposed to the electrolyte. When the top surface of n-type doped GaN is exposed, "vertical" etching occurs downward in the layer. When only the sidewalls or edges of the n-type doped layer are exposed to the electrolyte, "horizontal" etching occurs inward in these exposed edges.

[0020] The present method enables etching by exposing the surface layer of a group III nitride material having a charge carrier density between 1×10 14 cm -3 and 1×10 17 cm -3 to the electrolyte. However, it is not necessary to expose the subsurface structure (the material to be etched) to the electrolyte.

[0021] The step of exposing the surface layer to the electrolyte may alternatively be described as bringing the surface layer into contact with the electrolyte. Preferably, the upper surface, top surface or outermost surface of the surface layer is exposed to the electrolyte. Particularly preferably, only the surface layer is exposed to the electrolyte.

[0022] In prior art, when a nominally "undoped" GaN surface layer is masked by a layer of dielectric material such as SiO2, the top surface of the surface layer is not exposed to the electrolyte.

[0023] The surface layer may cover only the top surface of the subsurface structure. In other words, the subsurface structure may be located below or directly beneath the surface layer, or the surface layer may be located above the subsurface structure. The sidewalls or edges of the subsurface structure may be exposed, i.e., not covered by the surface layer.

[0024] Alternatively, the subsurface structure may be completely covered by the surface layer. That is, both the top surface and sidewalls, or edges, of the subsurface structure may be covered by the surface layer. Therefore, when the structure formed from the subsurface structure and surface layer is completely immersed in the electrolyte, the surface layer may be the only material exposed to the electrolyte.

[0025] Prior art discloses the use of undoped GaN as an "etch stop" to halt the progress of electrochemical etching, but the inventors of this invention provide a surface layer of GaN or other group III nitride material that is 1 × 10⁻¹⁶ 14 cm -3 From 1 x 10 17 cm -3 We found that by using a surface layer with a charge carrier density between two values, electrochemical etching through the surface layer of the second group III nitride material becomes possible. In other words, the subsurface structure can be porous by etching through the surface layer without direct contact of the subsurface structure with the electrolyte and without etching the surface layer itself.

[0026] By controlling the charge carrier density of the surface layer and the charge carrier density of the subsurface structure, the inventors have found that the subsurface structure of a first group III nitride material can be porousd through the surface layer without the surface layer itself becoming porous. It is particularly advantageous that the subsurface structure can be electrochemically etched without the surface layer being damaged or roughened during the etching process. Thus, the method of the present invention can advantageously enable the selective porosity of composite (e.g., multilayer) group III nitride structures without applying a protective conductive layer, such as SiO2, on the surface layer. This eliminates the need for the time-consuming and costly extra processing step of applying and then removing a top protective layer, which is required by the prior art, before the porous structure can be used.

[0027] To prevent the surface layer from becoming porous during etching, the surface layer must be at least 5 × 10 14 cm -3 , or 1 x 10 15 cm -3 , or 5 x 10 15 cm -3 The charge carrier density is 7 × 10⁻⁶, and / or 7 × 10⁻⁶. 15 cm -3 , or 1 x 10 16 cm -3 , or 5 x 10 16 cm -3 , or 8 x 10 16 cm -3 It may have a charge carrier density of less than 1.

[0028] The charge carrier density of the surface layer is 1 × 10⁻⁶ 14 cm -3 If the value is less than the minimum, the surface layer may have too high an electrical resistance to allow electrochemical etching through it, because there are not enough charge carriers present to carry the current to the subsurface structure that should be porous.

[0029] However, the charge carrier density of the surface layer is 1 × 10 17 cm -3If the value exceeds 1 × 10⁻¹⁶, the surface layer may be sufficiently conductive that it becomes porous during the electrochemical process. Thus, the surface layer may undergo porosity, surface "pitting," and / or roughening, which makes the surface layer unsuitable for further processing, such as further epitaxial overgrowth. This is because, even if the surface layer is not intentionally doped, the impurity concentration in the surface layer may be too high, causing the surface layer to become porous. 17 cm -3 This can occur when the charge carrier density exceeds a certain value.

[0030] By controlling the charge carrier density of a layer and the contrast in charge carrier density between adjacent layers, it is possible to predetermine which layers will be porous by electrochemical etching.

[0031] The subsurface structure, when porousized by electrochemical etching, has at least 5 × 10 17 cm -3 , or at least 1 × 10 18 cm -3 , or at least 5 × 10 18 cm -3 , or at least 1 × 10 19 cm -3 , or at least 5 × 10 19 cm -3 , or at least 1 × 10 20 cm -3 It has a charge carrier density of and / or 1 × 10 21 cm -3 , or 5 x 10 21 cm -3 , or 1 x 10 22 cm -3 It may have a charge carrier density of less than 1.

[0032] The inventors of the present invention have found that, according to the method of the present invention, 5 × 10 17 cm -3 Subsurface structures with a charge carrier density exceeding 1 × 10 are porous, while on the other hand, 1 × 10⁻¹⁶ structures are porous, while 1 × 10⁻¹⁶ structures are porous. 17 cm -3We found that layers with a charge carrier density of less than 1 × 10⁻¹⁰ do not become porous. 17 cm -3 From 5x10 17 cm -3 While porosity is possible within this range, using charge carrier densities outside this range allows for a contrast in electrical conductivity between the surface layer and the subsurface structure, promoting selective porosity of the subsurface structure.

[0033] To avoid damage to the "undoped" surface layer, the authors of the prior art have found that it is necessary to apply a protective dielectric layer to the top surface of the sample.

[0034] Those skilled in the art will understand that the term "undoped" is relatively inaccurate in semiconductor technology, since virtually all semiconductor materials contain inherent impurities that can be considered "dopant" atoms. Various methods of semiconductor growth can result in varying levels of impurities, and therefore, concentrations of various inherent charge carriers. When impurity levels are high, the resulting semiconductor material may have a concentration of 1 × 10¹⁶ atoms, even if the layer was not intentionally doped. 17 cm -3 It may have a charge carrier density exceeding [a certain value].

[0035] Therefore, the reason the authors of the prior art found it necessary to apply a protective dielectric layer to prevent undesirable etching of the surface layer is that the “undoped” surface layer actually etched 1 × 10⁻¹⁶ times. 17 cm -3 This is because the charge carrier density exceeds a certain level, and as a result, when a potential difference is applied, the surface layer is etched itself or partially etched. By applying a dielectric layer to the top of the surface layer, the surface layer is protected from accidental etching regardless of its charge carrier density.

[0036] The presence of an electrical insulating layer on the outer surface of the surface layer prevents electrical conduction through the surface layer to the (multiple) subsurface structures below, thereby preventing electrochemical etching through the surface layer.

[0037] Coating the outer surface of a surface layer in a dielectric material, as done in prior art, causes etching to proceed horizontally through the exposed edges of the layer. The authors of the prior art found that by doing so, only the n-type doped GaN layer became porous, while the "undoped" GaN layer remained non-porous and acted as an "etch stop."

[0038] The inventors of this invention hypothesize that in the prior art, horizontal etching proceeds selectively through the exposed edges of the "n-type" layer because these layers provide a path with the lowest electrical resistance. Therefore, the nominally "undoped" GaN layer of the prior art is actually 1 × 10⁻¹⁶ 17 cm -3 Even if the charge carrier density exceeds a certain value, horizontal etching will preferentially proceed in the "n-type" layers, as long as these layers have a higher charge carrier density and therefore a higher electrical conductivity than the "undoped" layers.

[0039] This "lowest resistance path" behavior is impossible when the electrolyte is in contact with the exposed top surface of the surface layer. Therefore, the charge carrier concentration of the surface layer must be controlled so that etching through the surface layer can occur, but without causing damage to the surface layer itself or its porosity.

[0040] Therefore, the present invention advantageously provides a method for porousizing a group III nitride material using fewer processing steps than required by prior art methods, and the method can advantageously porous large sample sizes without the need to pre-etch trenches.

[0041] The surface layer and subsurface structure preferably contain a group III nitride material selected from the group consisting of GaN, AlGaN, InGaN, InAlN, and AlInGaN. The surface layer and subsurface structure may be formed from the same group III nitride material having different charge carrier densities in each layer, or each layer may be formed from different group III nitride materials.

[0042] Suitable group III nitride materials may have, for example, any polar or nonpolar crystal orientation. Suitable group III nitride materials may have any crystal structure, for example, wurtzite type or cubic structure, and may have any crystal orientation. For example, suitable group III nitride materials may include polar c-planes, nonpolar a-planes, or even cubic group III nitride materials.

[0043] In a particularly preferred embodiment, the surface layer is 1 × 10 14 cm -3 From 1 x 10 17 cm -3 It is made of GaN having a charge carrier density between 5 × 10, and the subsurface structure is 5 × 10 17 cm -3 It consists of n-type doped GaN having a charge carrier density exceeding [a certain value].

[0044] The subsurface structure is preferably made of an n-type doped group III nitride material. The subsurface structure is particularly preferably doped with silicon (Si), germanium (Ge), and / or oxygen (O).

[0045] The charge carrier density of a given layer can be readily measured by those skilled in the art, for example, by capacitance-voltage profiling or calibrated scanning capacitance microscopy. Depth profiling Hall effect technique may also be suitable. Charge carrier density may also be referred to as carrier density or carrier concentration. In this specification, references to charge carrier density refer to charge carrier density at room temperature.

[0046] In a preferred embodiment, the subsurface structure consists of a planar subsurface layer of a first group III nitride material. The surface layer and the subsurface structure form adjacent planar layers, with the upper surface of the subsurface layer in contact with the lower surface of the surface layer, or separated by an intervening layer of group III nitride material. Preferably, the subsurface layer may be one of several subsurface layers formed from the same group III nitride material or different group III nitride materials.

[0047] The surface layer and subsurface structure may be formed by epitaxial growth. The surface layer and subsurface structure may be formed by molecular beam epitaxy (MBE), metal-organic chemical vapor deposition (MOCVD) (also known as metal-organic vapor phase epitaxy (MOVPE)), hydride vapor phase epitaxy (HVPE), an ammoniacal process, or other conventional processes suitable for growing group III nitride materials with the required charge carrier concentration.

[0048] The surface layer and (multiple) subsurface structures can be grown on an electrically insulating base layer or substrate. The base layer is preferably configured to form the bottom of the multilayer structure, and the surface layer forms the top of the multilayer structure, with the (multiple) subsurface structures positioned between the surface layer and the base layer. The electrically insulating base layer may preferably contain sapphire, silicon, silicon carbide, LiAlO3, glass, or bulk GaN.

[0049] Electrochemical etching can be carried out in various acidic or basic electrolytes. For example, suitable electrolytes include oxalic acid, KOH, NaOH, HF, HCl, and HNO3.

[0050] Preferably, the electrolyte must form a wetting angle or contact angle of 120° or more with the exposed surface of the surface layer.

[0051] To electrochemically etch a sample, an electrochemical cell is arranged so that the sample itself acts as the anode and an inert electrode, such as a platinum foil electrode, acts as the cathode. The sample and platinum electrode are connected to a power source, and the sample is immersed or partially immersed in an electrolyte to form a circuit.

[0052] In order to apply a potential difference between the sample electrolyte and the subsurface structure, the subsurface structure to be porous must be electrically connected to or in contact with the power supply terminals.

[0053] To perform electrochemical etching, the power supply is controlled to apply a potential difference (voltage) between the subsurface structure and the electrolyte, causing current to flow through the electrolyte and the sample. The current flow through the sample is 5 × 10⁻¹⁰ 17 cm -3 This causes electrochemical etching of any subsurface structure with a charge carrier density exceeding a certain value, resulting in increased porosity of these layers.

[0054] In order to selectively porousify the subsurface structure, it is preferable that the potential difference applied between the subsurface structure and the electrolyte is at least 4 volts (V), or 6 V, or 8 V, or 10 V, or 15 V, and / or less than 20 V, 25 V, or 30 V.

[0055] Electrochemical etching may be performed in continuous mode or in pulsed mode, and may be controlled by controlling the voltage or current of the entire cell.

[0056] It is advantageous that the progress of the etching reaction can be monitored by measuring the etching current during the reaction.

[0057] After etching, the sample is cleaned by rinsing with deionized water and drying with N2, ensuring complete dissolution of any remaining etching chemicals and products without affecting the porous structure of the subsurface structure.

[0058] The charge carrier density in the subsurface structure is preferably at least 5 times, or 10 times, or 100 times, or 1000 times, or 10,000 times, or 100,000 times, or 1,000,000 times higher than the charge carrier density in the surface layer. A large difference in charge carrier density between different layers can be considered to have a large "contrast" in charge carrier density, which can advantageously increase the selectivity of the etching process.

[0059] The threading dislocation density in both the surface layer and the subsurface structure is 1×10 4 cm -2 to 1×10 10 cm -2 preferably. Particularly preferably, the threading dislocation density in both the surface layer and the subsurface structure is substantially equal in the surface layer and the subsurface structure. The threading dislocation density in both the surface layer and the subsurface structure is at least 1×10 4 cm -2 、1×10 5 cm -2 、1×10 6 cm -2 、1×10 7 cm -2 or 1×10 8 cm -2 and / or 1×10 9 cm -2 、or 1×10 10 cm -2It is preferable that it be less than [a certain value]. Typically, semiconductor material producers try to minimize the through-dislocation density of the material in their efforts to improve material quality. However, in the present invention, a sufficient through-dislocation density between the surface layer and the subsurface layer may be necessary to enable electrochemical etching through the surface layer. This may be due to increased transport of electrolytes or charge carriers to the subsurface layer.

[0060] The surface layer is preferably a continuous layer of group III nitride material. That is, the surface layer is preferably substantially free of holes or large defects.

[0061] In a preferred embodiment, the subsurface structure may also be a continuous subsurface layer of a group III nitride material.

[0062] The thickness of the surface layer is at least 1 nm, or 10 nm, or 100 nm, and / or preferably less than 1 μm, 5 μm, or 10 μm. In a preferred embodiment, the thickness of the surface layer is 50 nm.

[0063] The thickness of the subsurface structure or subsurface layer is preferably at least 1 nm, 10 nm, or 100 nm, and / or less than 1 μm, 5 μm, or 10 μm.

[0064] Particularly preferably, the outer surface of the continuous surface layer has a minimum lateral dimension of at least 300 μm, or at least 600 μm, or at least 1 mm, or at least 10 mm, or at least 5 cm, or at least 15 cm, or at least 20 cm.

[0065] Particularly preferably, the subsurface structure is a continuous layer having a minimum lateral dimension of at least 300 μm, or at least 600 μm, or at least 1 mm, or at least 10 mm, or at least 5 cm, or at least 15 cm, or at least 20 cm.

[0066] The minimum lateral dimension of a layer refers to the lateral width of the layer at its narrowest point. The layers used in preferred embodiments of the present invention are relatively large and thin. Therefore, the lateral dimension of a layer should be understood to refer to the dimensions of the "top" and "bottom" surfaces of the layer, and the thickness of the layer refers to its "height," i.e., the distance between its top and bottom surfaces. Thus, the top surface of the sample is square, and the minimum lateral dimension of the sample is the distance between the opposite edges of the square. In this case, the "bottom" surface should be understood to be the surface that is first formed during the epitaxial growth of the layer on the substrate, and the "top" surface is the surface formed on the opposite side of the layer from the "bottom" surface.

[0067] The method of the present invention is advantageous in that it is possible to porous semiconductor structures considerably larger than those achievable using prior art horizontal etching techniques. Since the method of the present invention results in electrochemical etching of the subsurface structure through the surface layer rather than horizontally from the exposed edges of each individual layer, the effectiveness of the present invention is not limited to the maximum sample width.

[0068] This method makes it possible to uniformly porous a continuous subsurface layer across an entire 2-inch semiconductor wafer without first forming regular trenches in the wafer to expose the layer edges. This is not possible with prior art etching methods, as horizontal etching cannot etch to the center of such a large wafer. Horizontal etching would be limited to etching distances of tens or hundreds of micrometers from the wafer edge. Furthermore, it is possible to uniformly porous a continuous subsurface layer across an entire 2-inch semiconductor wafer without protecting the surface layer with an electrical insulating layer. This is not possible with prior art etching methods, which require protection of the top surface.

[0069] The characteristics of prior art horizontal etching have been extensively studied and are known to be limited in the etching rate from the sample edge. Limitations such as electrolyte and charge transport mean that beyond a certain sample width, horizontal etching cannot reach the center of the sample, regardless of the time elapsed. Prolonged current concentration at the sample edge leads to non-uniform porosity throughout the layer, concentrating porosity at the sample edge while little to no porosity occurs in the sample center.

[0070] For these reasons, authors of prior art have relied on pre-preparing the sample with dry etching trenches at regular intervals throughout the sample to allow the electrolyte to approach the sample edge every 50 μm or so. This allows the electrolyte to approach the exposed edges of the subsurface layer, which can result in horizontal etching.

[0071] The inventors of this invention have avoided these problems by etching not only from the edges of the layers but also through the surface layer. This method advantageously allows for uniform porosity to occur throughout the entire subsurface layer, rather than just from the edges. This is advantageous because it reduces the time required to etch the sample and increases the uniformity of porosity compared to performing horizontal etching only.

[0072] Particularly advantageous is that approaching the layer edge is not required, so the method of the present invention does not require pre-preparation of the sample by creating trenches in the layer. Therefore, the present invention requires fewer processing steps, does not require dividing the layer using regular trenches, and enables the porosity of large, continuous semiconductor layers.

[0073] Furthermore, since this method does not require approaching the edges of the material to be etched, various subsurface structures can be made porous. Unlike the prior art, the subsurface structure does not need to extend to the edges of the sample, nor does it need to exhibit a large surface area of ​​sidewalls for exposure to the electrolyte during the etching process. Therefore, porous materials with various patterns or structures can be formed as porous subsurface structures beneath the surface layer.

[0074] Preferably, this method can generate pores in the subsurface structure that have an average pore size greater than 1 nm, 2 nm, 10 nm, or 20 nm, and / or have an average pore size less than 50 nm, 60 nm, or 70 nm.

[0075] The pore size and morphology of the subsurface structure, and the resulting porosity percentage, can be advantageously controlled by controlling the charge carrier concentration of the (multiple) subsurface structures and by controlling the potential difference applied between the electrolyte and the (multiple) subsurface structures during etching.

[0076] This method can preferably create a microporous subsurface structure, i.e., the subsurface structure has an average pore size of less than 2 nm. Alternatively, this method can create a mesoporous subsurface structure, i.e., the subsurface structure has an average pore size between 2 nm and 50 nm. Alternatively, this method can create a macroporous subsurface structure, i.e., the subsurface structure has an average pore size greater than 50 nm.

[0077] In a preferred embodiment, the method can be used to porousize multiple subsurface structures. Therefore, the method includes the step of applying a potential difference between the subsurface structure to be porousized and the electrolyte, 5 × 10 17 cm -3 Structures with a charge carrier density exceeding 1 × 10 are porous by electrochemical etching, while on the other hand, 1 × 10 14 cm -3from 1×10 17 cm -3 having a charge carrier density between does not become porous.

[0078] In a particularly preferred embodiment, the subsurface structure may be a subsurface layer, and a plurality of subsurface layers can be made porous using this method. When the semiconductor structure includes a plurality of subsurface layers formed from a group III nitride material, the method includes applying a potential difference between the subsurface layer to be made porous and the electrolyte, and a layer having a charge carrier density exceeding 5×10 17 cm -3 is made porous by electrochemical etching, while a layer having a charge carrier density between 1×10 14 cm -3 and 1×10 17 cm -3 does not become porous.

[0079] A layer having a charge carrier density exceeding 5×10 17 cm -3 can be made porous by electrochemical etching through the layer above it.

[0080] By controlling the charge carrier density of each layer, it is possible to control which of the plurality of subsurface layers are made porous in the electrochemical etching process. Therefore, various multilayer structures can be grown to achieve different porosity characteristics in predetermined layers.

[0081] When the subsurface structure or subsurface layer is made porous by electrochemical etching, its charge carrier density must exceed 5×10 17 cm -3 . When exceeding this threshold, the porosity of the resulting porous structure changes approximately according to the charge carrier density of the original subsurface structure. Therefore, when two subsurface structures having a charge carrier density exceeding 5×10 17 cm -3 are provided, under the condition that the same potential difference is applied to each, the subsurface structure having a higher charge carrier density is made more porous than the other subsurface structure.

[0082] In a preferred embodiment, the subsurface structure forms a plurality of subsurface layers arranged in a stack vertically. The method of the present invention advantageously allows for sequential etching of the subsurface layers downward from the surface layer. That is, the subsurface layer closest to the surface layer is first porous, followed by etching through the subsurface structure downwards to 5 × 10 17 cm -3 The process progresses to the next subsurface layer having a charge carrier density exceeding [a certain value], which is then porous, and this process is repeated.

[0083] Particularly advantageous is that this sequential etching allows the user to control the porosity of a specific subsurface layer by controlling the potential difference between the electrolyte and the subsurface layer during the electrochemical etching of the layer. By monitoring the etching current during etching, it is advantageous that the user can sequentially monitor the progress of etching through the stacking of multiple layers, and as a result, control the potential difference during the electrochemical etching of a specific layer.

[0084] In a particularly preferred embodiment, the subsurface structure is a first subsurface layer, and the semiconductor structure is a second subsurface layer of a group III nitride material, with a total area of ​​1 × 10⁻¹⁶ 14 cm -3 From 1 x 10 17 cm -3 A second subsurface layer having a charge carrier density between 5 × 10, and a third subsurface layer of a group III nitride material, wherein 5 × 10 17 cm -3 The method includes a third subsurface layer having a charge carrier density exceeding a certain value, the second subsurface layer being positioned between the first and third subsurface layers. The method includes an additional step of applying a potential difference between the third subsurface layer and the electrolyte, thereby porousizing the third subsurface layer by electrochemical etching, while the surface layer and the second subsurface layer are not porousized.

[0085] In addition to the porosity of the first subsurface layer, the third subsurface layer can be made porosity by electrochemical etching through the surface layer, the first subsurface layer, and the second subsurface layer.

[0086] Therefore, the method of the present invention is a surface layer, and 1 × 10 14 cm -3 From 1 x 10 17 cm -3 Etching through any subsurface layer having a charge carrier density between 1 × 10⁻¹⁰ allows for the selective porosity of multiple subsurface layers based on their charge carrier density. Particularly advantageous is that this method allows for the porosity of the subsurface of any subsurface layer having a charge carrier density between 1 × 10⁻¹⁰. 14 cm -3 From 1 x 10 17 cm -3 Without damaging, roughening, or porous the layer having a charge carrier density between 5 × 10 17 cm -3 The subsurface layer having a charge carrier density exceeding [a certain value] can be made porous.

[0087] Preferably, the root mean square roughness of the surface layer is not altered during electrochemical etching. Particularly preferably, the root mean square roughness of the outermost surface of the surface layer after etching is less than 10 nm, or less than 5 nm, or less than 2 nm, or less than 1 nm, or less than 0.5 nm over an area of ​​1 square micrometer. That is, the method of the present invention can produce an "epi-ready" surface, and because the root mean square roughness of the surface layer is sufficiently low, further epitaxial growth can be carried out on the surface layer without requiring intermediate processing steps.

[0088] In a preferred embodiment, the surface layer and (multiple) subsurface layers are provided as wafers having a diameter of 1 inch (2.54 cm), 2 inches (5.08 cm), 6 inches (15.24 cm), or 8 inches (20.36 cm).

[0089] This method, 1 × 10 14 cm -3 From 1 x 10 17 cm -3Since it provides electrochemical etching through a layer having charge carrier density between them, it is possible to etch subsurface structures or subsurface layers that are far from any sidewalls or edges of the semiconductor structure.

[0090] Therefore, this method advantageously allows etching of subsurface structures at a distance of at least 300 μm, 500 μm, 750 μm, 1 mm, 1 cm, or 5 cm from the nearest sidewall or edge of the semiconductor structure. This is not possible with horizontal etching, which has limitations on the etchable distance and can etch up to tens of micrometers or at most several hundred micrometers from the layer edge.

[0091] This method is particularly preferably carried out without providing trenches in the surface layer and subsurface structure.

[0092] Preferably, the surface layer is not coated with an electrical insulating layer during electrochemical etching.

[0093] Preferably, the sample is not illuminated with UV light during electrochemical etching.

[0094] According to a second aspect of the present invention, a semiconductor structure formed by the method described above as the first aspect of the present invention is provided.

[0095] According to a third aspect of the present invention, a porous subsurface structure of a first group III nitride material and a surface layer of a second group III nitride material, wherein 1 × 10 14 cm -3 From 1 x 10 17 cm -3 A semiconductor structure is provided which includes a surface layer having a charge carrier density between 550 μm and 550 μm, the subsurface structure having uniform porosity throughout its structure, and both the surface layer and the subsurface structure having a minimum lateral dimension longer than 550 μm.

[0096] According to a preferred embodiment, the semiconductor structure may be a multilayer semiconductor structure.

[0097] As discussed above in relation to the first aspect of the present invention, prior art horizontal etching methods cannot porous subsurface layers having a minimum lateral dimension longer than several hundred micrometers. In pre-patterned structures with vertical trench cuts in the layers, the minimum lateral dimension of the sample may be the distance between adjacent trenches.

[0098] Furthermore, horizontal etching may not produce a porous subsurface layer with uniform porosity throughout the entire layer. In particular, when the minimum lateral dimension of the subsurface layer is relatively large, for example 250 μm, limitations in electrolytes and / or limitations in charge transport from the edge to the layer can produce non-uniform porosity throughout the subsurface layer. In such horizontal etching methods, when the subsurface layer is exposed to the electrolyte, regions of high porosity are created in or near the exposed edge of the subsurface layer, and the porosity decreases as you move away from the edge of the subsurface layer. This effect is particularly pronounced in large structures, and the problems of electrolyte and / or charge transport become more pronounced the further you move away from the edge.

[0099] Preferably, the surface layer and subsurface structure comprise a group III nitride material selected from the group consisting of GaN, AlGaN, InGaN, InAlN, and AlInGaN. The surface layer and subsurface structure may be formed from the same group III nitride material or from different group III nitride materials.

[0100] In a particularly preferred embodiment, the surface layer is 1 × 10 14 cm -3 From 1 x 10 17 cm -3 It consists of GaN having a charge carrier density between [values], and the subsurface structure is made of porous GaN.

[0101] In a preferred embodiment, the subsurface structure is a subsurface layer of a first group III nitride material. The surface layer and the subsurface layer are adjacent layers, with the upper surface of the subsurface layer in contact with the lower surface of the surface layer, or they are separated by an intervening layer of group III nitride material. Preferably, the subsurface layer may be one of a plurality of subsurface layers formed from the group III nitride material.

[0102] Preferably, the penetration dislocation density in both the surface layer and the subsurface structure, or in the subsurface layer, is 1 × 10⁻⁶ 4 cm -2 From 1 x 10 10 cm -2 It is between [a certain range]. The penetration dislocation density in both the surface layer and the subsurface structure, or in the subsurface layer, is at least 1 × 10⁻⁶. 4 cm -2 , 1 x 10 5 cm -2 , 1 x 10 6 cm -2 , 1 x 10 7 cm -2 Or 1 x 10 8 cm -2 and / or 1 × 10 9 cm -2 , or 1 x 10 10 cm -2 It is especially preferable that it be less than [a certain value].

[0103] The thickness of the surface layer is preferably at least 1 nm, or 10 nm, or 100 nm, and / or less than 1 μm, 5 μm, or 10 μm.

[0104] The surface layer is preferably a continuous layer of a second group III nitride material.

[0105] The thickness of the subsurface structure or subsurface layer is preferably at least 1 nm, or 10 nm, or 100 nm, and / or less than 1 μm, or 5 μm, or 10 μm, or 100 μm.

[0106] Particularly preferably, the outer surface of the surface layer has a minimum lateral dimension of at least 600 μm, or at least 1 mm, or at least 10 mm, or at least 5 cm, or at least 15 cm, or at least 20 cm.

[0107] The subsurface structure is preferably a continuous subsurface layer. The subsurface layer preferably has a minimum lateral dimension of at least 600 μm, or at least 1 mm, or at least 10 mm, or at least 5 cm, or at least 15 cm, or at least 20 cm.

[0108] The surface layer may cover only the top surface of the subsurface structure. In other words, the subsurface structure may be located below or directly beneath the surface layer, or the surface layer may be located above the subsurface structure. The sidewalls or edges of the subsurface structure may be exposed, i.e., not covered by the surface layer.

[0109] Alternatively, the subsurface structure may be completely covered by the surface layer. That is, both the top surface and sidewalls or edges of the subsurface structure may be covered by the surface layer.

[0110] Preferably, the porous subsurface structure has an average pore size greater than 1 nm, 2 nm, 10 nm, or 20 nm, and / or an average pore size less than 50 nm, 60 nm, or 70 nm. The porous subsurface structure may be microporous, i.e., it may have an average pore size less than 2 nm. Alternatively, the porous subsurface structure may be mesoporous, i.e., it may have an average pore size between 2 nm and 50 nm. Alternatively, the porous subsurface structure may be macroporous, i.e., it may have an average pore size greater than 50 nm.

[0111] The semiconductor structure may include multiple stacked subsurface layers formed from a group III nitride material, where the odd-numbered subsurface layers are porous with uniform porosity throughout the layer, and the even-numbered subsurface layers are non-porous. In other words, the subsurface layers may consist of multiple alternating porous / non-porous layers.

[0112] Particularly preferably, each of the odd-numbered subsurface layers may be porous and have the same porosity, while each of the even-numbered subsurface layers may be non-porous. Differences in porosity between adjacent layers lead to differences in refractive index, and as a result, the structure can act as a distributed Bragg reflector (DBR). By controlling the thickness of the layers and / or the porosity of the porous layers, the photonic stopband of the DBR can be adjusted to reflect a desired wavelength of light. Particularly preferably, the thickness of each subsurface layer can be equal to one-quarter of the wavelength, or a multiple of one-quarter of the wavelength, in order to be reflected by the DBR.

[0113] The semiconductor structures of the present invention exhibit good electrical conductivity through the layers and offer the possibility of tuning their spectral response by changing the thickness of the surface layer and (multiple) subsurface layers. Therefore, these structures may be usable as microcavity structures for electrically driven VCSELs and quantum light sources.

[0114] In a preferred embodiment, at least two porous subsurface layers have different porosity.

[0115] It is particularly preferable that the semiconductor structure is not patterned using trenches. In other words, the surface layer and (multiple) subsurface structures may be continuous or uninterrupted throughout their entire width.

[0116] Preferably, the top, apex, or outermost surface of the surface layer has a root mean square roughness of less than 10 nm, less than 5 nm, less than 2 nm, less than 1 nm, or less than 0.5 nm over an area of ​​1 square micrometer. On the c-plane of GaN, for example, the root mean square roughness may be less than 1 nm over an area of ​​1 μm × 1 μm.

[0117] Low root mean square roughness is desirable to enable direct epitaxial overgrowth on semiconductor structures.

[0118] Preferably, further group III nitride epitaxial layers and device structures can be directly deposited onto the semiconductor structure after cleaning by techniques such as MBE, MOCVD, or HVPE. After this overgrowth, high-performance optical and electrical devices can be fabricated on the structure. Suitable devices include, for example, light-emitting diodes (LEDs), laser diodes (LDs), high-electron mobility transistors (HEMTs), solar cells, and semiconductor-based sensor devices.

[0119] Preferably, the top surface, outermost surface, or upper surface of the surface layer is not coated with an electrical insulating layer. In other words, the top surface of the surface layer may be exposed.

[0120] According to a fourth aspect of the present invention, the invention comprises a porous subsurface structure of a first group III nitride material and a surface layer of a second group III nitride material, wherein the surface layer is 1 × 10 14 cm -3 From 1 x 10 17 cm -3 A semiconductor structure is provided which has a charge carrier density between and the surface layer covering the subsurface structure.

[0121] The surface layer preferably completely covers the subsurface structure. The subsurface structure may be completely covered by the surface layer such that the top surface and all sidewalls or edges of the subsurface structure are covered by the surface layer.

[0122] The semiconductor structure can be a multilayer semiconductor structure.

[0123] Using prior art etching methods that require the electrolyte to come into contact with the material to be etched, it would not be possible to form semiconductor devices in which the surface layer completely covers the subsurface structure.

[0124] The semiconductor structure is formed on an insulating substrate, such as a sapphire substrate, and the "bottom" or underside (i.e., the surface facing away from the surface layer) of the subsurface structure is adjacent to either the substrate or any further subsurface structure. Therefore, the bottom surface of the subsurface structure is not exposed to its surroundings.

[0125] Since no part of the subsurface structure is exposed, it would not be possible to form such a semiconductor structure using prior art etching methods that require a portion of the material to be etched to be exposed to the electrolyte.

[0126] Preferably, the upper surface of the surface layer has a minimum lateral dimension of at least 1 μm, or 10 μm, or 50 μm, or 100 μm, or 500 μm, or at least 1 mm, or at least 10 mm, or at least 5 cm, or at least 15 cm, or at least 20 cm.

[0127] Since the subsurface structure is completely covered by the surface layer, the lateral width of the subsurface structure will be smaller than the lateral width of the surface layer. However, because the surface layer is extremely thin, the difference can only be a few nanometers or micrometers. The subsurface structure is preferably a continuous subsurface layer.

[0128] Particularly preferred, the subsurface structure has a minimum lateral dimension of at least 500 nm, 1 μm, 5 μm, 45 μm, 95 μm, or 1 mm, or at least 10 mm, or 5 cm, or 15 cm, or 20 cm.

[0129] In an exemplary preferred embodiment, a 20 μm × 20 μm × 20 μm cube of porous GaN is 1 × 10 14 cm -3 From 1 x 10 17 cm -3 The cube is covered by a GaN surface layer having a charge carrier density between the two sides. The bottom surface of the cube is in contact with the sapphire substrate, while the other five faces of the cube are covered by the GaN surface layer.

[0130] Such a structure is 1 × 10 14 cm -3 From 1 x 10 17 cm -3 A surface layer of GaN having a charge carrier density between 1 × 10 14 cm -3 A 20 μm × 20 μm × 20 μm cube of GaN having a charge carrier density exceeding can be formed according to the method of the present invention by etching it. The method of the present invention allows electrochemical etching to proceed through the surface layer of the group III nitride material in order to porousize the material inside the cube. This is not possible using the prior art horizontal etching method, because those methods require the layer to be porousized to be exposed to the electrolyte during etching.

[0131] Further features of the multilayer semiconductor structure according to the fourth aspect are as described above in relation to the third aspect of the present invention.

[0132] According to a fifth aspect of the present invention, a multilayer semiconductor structure is provided to be used as a substrate for the overgrowth of one or more semiconductor devices. The multilayer semiconductor structure is as described above in relation to the second, third, or fourth aspects of the present invention.

[0133] According to a sixth aspect of the present invention, a multilayer semiconductor structure is provided for use as a distributed Bragg reflector (DBR). The multilayer semiconductor structure may be as described above in relation to the second, third, or fourth aspects of the present invention.

[0134] As described above, a multilayer semiconductor structure comprising alternating layers of non-porous group III nitride material and porous group III nitride material can be fabricated using a method according to the first aspect of the present invention. Differences in porosity between adjacent layers can lead to differences in refractive index, and as a result, the structure can act as a distributed Bragg reflector (DBR). By controlling the thickness of the layers and the porosity of the porous layers, the photonic stop band of the DBR can be adjusted to reflect a desired wavelength of light. Particularly preferably, the thickness of each subsurface layer can be equal to one-quarter of the wavelength, or a multiple of one-quarter of the wavelength, in order to be reflected by the DBR.

[0135] In particularly preferred embodiments, non-porous GaN / porous GaN DBRs may offer significant refractive index contrast, making it easier to fabricate DBRs without worrying about strain control, cracking, and dislocation generation issues, which are typical problems in DBR integration. For example, conventional fabrication of epitaxial group III nitride DBRs is extremely difficult in non-polar orientations because there are no available analogues that lattice match non-polar GaN (c-plane GaN can be lattice matched with low refractive index In0.18Al0.82N). However, the present invention can provide crack-free, highly reflective non-polar group III nitride DBRs.

[0136] If the multilayer semiconductor structure of the present invention is used as a DBR (Deep Blocking Receptor) beneath a photonic device, it can reflect light directed downwards, thereby significantly improving the light extraction efficiency of the photonic device.

[0137] According to a seventh aspect of the present invention, a device is provided which incorporates or has a multilayer semiconductor structure attached. The multilayer semiconductor structure may be as described above in relation to the second and third aspects of the present invention.

[0138] Exemplary devices include vertical-cavity surface-emitting lasers (VCSELs) or other quantum light sources in which such multilayer structures can form microcavity structures. Further devices that can incorporate such multilayer semiconductor structures include LEDs for single-photon sources and micropillar cavity structures.

[0139] According to the eighth aspect of the present invention, 1 × 10 14 cm -3 From 1 x 10 17 cm -3 Below the surface layer of a second GaN material having a charge carrier density between 5 × 10 17 cm -3 A method is provided for porousizing GaN in a semiconductor structure including a subsurface structure formed from a first GaN material having a charge carrier density exceeding a certain value. The method includes the steps of exposing the surface layer to an electrolyte and applying a potential difference between the subsurface structure and the electrolyte, thereby porousizing the subsurface structure by electrochemical etching, while the surface layer remains porous.

[0140] Further features of this method are as described above in relation to the first aspect of the present invention. [Brief explanation of the drawing]

[0141] Specific embodiments of the present invention are described herein with reference to the drawings: [Figure 1] Figure 1 shows a schematic diagram of the experimental setup for electrochemical etching. [Figure 2A] Figure 2A is a schematic diagram of a multilayer semiconductor structure forming a distributed Bragg reflector (DBR) according to aspects of the present invention. [Figure 2B] Figure 2B shows a cross-sectional scanning electron microscope (SEM) image of the multilayer semiconductor structure shown in Figure 2A. [Figure 3A]Figure 3A shows the Nomarski optical image of the etched sample from Figure 2B. [Figure 3B] Figure 3B shows an atomic force microscopy (AFM) image of the surface layer of the unetched region of the sample shown in Figure 2B. [Figure 3C] Figure 3C shows an atomic force microscope (AFM) image of the surface layer of the etched region of the sample shown in Figure 2B. [Figure 4] Figure 4 shows the measured reflectance spectrum of a GaN DBR structure according to a preferred embodiment of the present invention. [Figure 5A] Figure 5A shows an AFM image of the top surface of an etched semiconductor wafer on which a DBR is formed. [Figure 5B] Figure 5B shows an AFM image of the top surface of an unetched GaN epitaxial layer. [Figure 6] Figure 6 shows a photograph of an etched 2-inch semiconductor wafer on which a DBR is formed, according to a preferred embodiment of the present invention. [Figure 7A] Figure 7A shows photographs of various GaN DBR structures according to a preferred embodiment of the present invention. [Figure 7B] Figure 7B shows the measured reflectance spectrum of the DBR structure in Figure 7A. [Figure 8A] Figure 8A is a schematic diagram of a GaN-based LED overgrown on a GaN DBR substrate according to a preferred embodiment of the present invention. [Figure 8B] Figure 8B shows a cross-sectional SEM image of the overgrown LED structure shown in Figure 8A. [Figure 8C] Figure 8C is a photograph of a GaN LED structure without the underlying porous GaN DBR. [Figure 8D] Figure 8D is a photograph of a GaN LED structure formed on the top of a porous GaN DBR according to a preferred embodiment of the present invention. [Figure 8E] Figure 8E shows the room-temperature electroluminescence (EL) "internal quantum efficiency" (IQE) of LEDs with and without porous GaN DBR as a pseudo-substrate. [Figure 9A] Figure 9A is a schematic diagram of a multilayer semiconductor structure containing several group III nitride materials according to a preferred embodiment of the present invention. [Figure 9B] Figure 9B shows an SEM image of the multilayer semiconductor structure shown in Figure 9A. [Figure 9C] Figure 9C shows a magnified SEM image of the multilayer semiconductor structure shown in Figure 9B. [Modes for carrying out the invention]

[0142] Figure 1 shows a schematic diagram of an electrochemical (EC) experimental setup arrangement usable in the method of the present invention. As shown in Figure 1, the experimental setup consists of a two-electrode electrochemical cell 100 having a sample 110 connected as the anode and a platinum foil 120 connected as the cathode. The platinum cathode and at least a portion of the surface layer of the sample are exposed to the electrolyte 130 by immersion in the electrolyte. A constant current DC power supply 140 is connected between the anode and the cathode, and an ammeter 150 is used to monitor and record the etching current flowing through the circuit.

[0143] Unless otherwise specified, the EC etching experiments described herein were performed at room temperature using a semiconductor structure as the anode and platinum foil as the counter electrode (cathode). Oxalic acid with a concentration of 0.25 M was used as the electrolyte. The etching process was carried out in constant voltage mode controlled by a Keithley 2400 source meter. After etching, the samples were rinsed with deionized water and blow-dried with N2.

[0144] As discussed above in the summary of this invention, those skilled in the art will understand that the term “undoped” is relatively inaccurate in semiconductor technology. In fact, all semiconductor materials contain inherent impurities that can be considered “dopant” atoms. Various methods of semiconductor growth can result in varying levels of impurities, and therefore, various inherent charge carrier concentrations.

[0145] Therefore, semiconductor materials referred to as "undoped" in the prior art may have high impurity levels, and as a result, they may consist of 1 × 10⁻¹⁰ impurities alone. 17 cm -3 It is possible to have a natural charge carrier density exceeding that.

[0146] Recognizing this, the inventors of this invention prefer to use the term “non-intentionally-doped” (NID) to refer to semiconductor materials that are manufactured without intentional doping. The impurity levels of semiconductor materials naturally vary depending on factors including how they are formed, the environment in which they are formed, and the purity of the reactants used to form the semiconductor material.

[0147] In this application, the term "unintentionally doped" (NID) means 1 × 10 14 cm -3 From 1 x 10 17 cm -3 It should be understood that this refers to a semiconductor material that has been carefully grown to be as pure as possible and has been measured to have a charge carrier density between [a certain value].

[0148] 5 x 10 17 cm -3 Semiconductor materials that are intentionally doped with n-type dopants to obtain a charge carrier density exceeding a certain level are sometimes called "n+" semiconductor materials.

[0149] Figure 2A shows a schematic diagram of an epitaxial nonpolar sample structure consisting of alternating layers of unintentionally doped GaN (NID-GaN) and heavily doped n-type GaN (n+-GaN). The NID-GaN layer is 1 × 10⁻¹⁶ 17 cm -3 It has a charge carrier density of less than 2.3 × 10⁻¹⁶, while the n+-GaN layer has a charge carrier density of 2.3 × 10⁻¹⁶. 19 cm -3 It has a nominal silicon doping concentration. Each of the alternating NID-GaN / n+-GaN layers has a thickness of approximately 136 nm.

[0150] The sample consists of a top surface layer of NID-GaN and 10 pairs of alternating NID-GaN / n+-GaN layers, formed on a sapphire substrate and a sub-layer of lightly doped n-type GaN (n-GaN) and NID-GaN. The n-GaN layer has a thickness of 2 μm and is present for a uniform distribution of anodic oxidation bias throughout the sample.

[0151] Samples were grown on an r-plane sapphire substrate by organometallic vapor phase epitaxy (MOVPE) in a 6 × 2 inch Thomas Swan close-coupled showerhead reactor. Trimethylgallium and ammonia were used as precursors, hydrogen as the carrier gas, and silane for n-type doping. Firstly, approximately 4 × 10 9 cm ―2 The nominal dislocation density and approximately 5 × 10 5 cm ―1 A 4 μm thick a-plane GaN pseudo-substrate with a stacking fault density on the base plane was grown. Here, a single SiNx interlayer was used to reduce defects. After growing another 500 nm undoped GaN layer, 10 pairs of alternating n+-GaN and NID-GaN layers were grown.

[0152] The sample in Figure 2A was electrically connected by soldering an indium wire to the edge of the sample. A portion of the sample, approximately 1 cm × 1 cm in size, was then immersed in the electrolyte. Using the experimental setup shown in Figure 1, the EC etching process was performed on the sample in constant voltage mode with a 6V DC bias, controlled by monitoring and recording the etching current signal at room temperature without UV illumination.

[0153] The EC porosity process begins with the oxidation of alternating n+-GaN layers by local injection of holes under a positive anode bias, followed by local dissolution of the oxide layers in an acid-based electrolyte, resulting in the formation of a mesoporous structure. The end of the anodic oxidation process is typically reached after approximately 30 minutes, when the etching current drops to a baseline level, indicating that all n+-GaN layers have been etched and converted into mesoporous GaN layers.

[0154] The cross-sectional scanning electron microscope (SEM) image in Figure 2B shows the morphology of the porous DBR structure 200. The cross-section in Figure 2B was taken from a cleaved edge after etching, far from the original sample edge. This confirms that the porosity process proceeded very uniformly across the entire sample area immersed in the etching solution. This also confirms that the morphology of the etched layer is indeed mesoporous, as the average pore size is approximately 30 nm. Figure 2B shows that the NID-GaN layers remained almost intact during EC etching and were not porous themselves. Only the n+-GaN layers were selectively etched and converted into mesoporous layers of mesoporous GaN (MP-GaN).

[0155] The 1cm × 1cm sample is considerably larger than the sample porousd by the prior art of horizontal etching, because horizontal etching would not be able to penetrate horizontally into the center of such a large sample without regular trenches on the sample surface. Furthermore, an etching time of 30 minutes would be insufficient for horizontal etching to progress significantly into the bulk material of the sample. Therefore, the porous cross-section in Figure 2B, taken far from the sample edge, is evidence that the n+-GaN layer was etched through the surface layer of NID-GaN, rather than horizontally from the sample edge.

[0156] Figure 3A shows a top view of the Nomarski optical image of the etched sample, where the boundary (indicated by the white arrow) corresponding to the position of the sample immersed in the EC etching solution can be seen. The optical contrast between the porous and non-porous regions arises due to the altered refractive index of the porous layer, leading to a considerably higher reflectivity in the etched region. The distinct boundary between the etched and unetched regions provides evidence that etching is occurring through the surface layer, as uniform reflectivity (and therefore porosity) is achieved far from the edges of the structure.

[0157] To assess the possibility of etching damage at the top of the NID-GaN surface layer, atomic force microscopy (AFM) images were taken from non-porous and porous regions, shown in Figures 3B and 3C, respectively. While some contaminants / small particles present in the porous regions may be related to EC etching products, etching chemicals, and / or inclusions during sample cleaning, apart from these, no changes in surface morphology were observed. The root mean square roughness (RRMS) of the top GaN surface was approximately 1 nm roughness measured over a 1 μm × 1 μm area, and was similar in both etched and unetched regions. Therefore, subsurface EC porosification does not damage the surface of the GaN surface layer, and the RRMS of the post-etched sample appears to be sufficiently low for further semiconductor overgrowth.

[0158] Therefore, such porous DBRs can be used as bottom mirror templates for the regrowth of other heterostructures or for the deposition of high-quality dielectric DBRs to form, for example, planar microcavities.

[0159] The porous DBR structure illustrated in Figures 2B-3C is formed purely by the epitaxial growth of alternating NID-GaN / n+-GaN layers followed by EC porosification. Using the method of the present invention eliminates the need to protect the sample surface with SiO2 or to pattern the sample using regular trenches. Furthermore, UV illumination is not required.

[0160] The reflectance spectra of etched GaN / MP-GaN DBRs were measured using a microreflection setup with indoor light and normalized to a commercially available silver mirror with a spot size of approximately 1 μm. Figure 4 shows the measured reflectance spectra of the GaN / mesoporous-GaN DBR structure, which have a peak reflectance centered at approximately 564 nm and a stopband with a full width at half maximum of 91 nm.

[0161] Peak reflectances greater than 96% were achieved in the nonpolar GaN / MP-GaN DBR structure, exhibiting an extremely large spectral width greater than 80 nm. The inventors note that the measured peak reflectances are slightly lower than the simulated values, which may be due to local heterogeneity in the mesoporous GaN layer and etching paths through the layer, which lead to slight porosity in the NID-GaN. Nevertheless, to the inventors' knowledge, this is the highest reported peak reflectance from a nonpolar group III nitride DBR structure, representing a more than twofold increase in stopband width compared to structures reported to date. This is due to the fact that a considerably large refractive index contrast can be achieved by using a mesoporous GaN layer, provided that significant lattice mismatches are not introduced, leading to large strains and degradation of structural quality (through crack formation and dislocation generation). In contrast, the more common method for fabricating nitride DBRs, which involves the use of Al-containing epitaxial layers on GaN such as Al(Ga)N and InAlN to achieve refractive index contrast, inevitably leads to the introduction of significant strain in at least one in-plane direction for nonpolar structures.

[0162] In another experiment, an equivalent DBR structure was epitaxially grown on a circular semiconductor wafer with a diameter of 2 inches (5.08 cm). A portion of the wafer was then etched by immersion in an electrolyte, as described above in relation to Figures 1-2B. The typical etching time for a 2-inch wafer at 6V was less than 6 hours.

[0163] The wafer-scale fabrication of mesoporous GaN DBRs was found to correlate with the threading dislocation density. The inventors believe these threading dislocations act as through-layer etching pathways, promoting subsurface etching through the surface layer and downward through the multilayer structure. Only complete threading dislocations appear to constitute through-layer etching pathways.

[0164] To achieve 2-inch wafer-scale formation of mesoporous GaN DBR, the surface layer and subsurface layer must be at least 1 × 10⁻¹⁶ 4 cm -2 It may be necessary to have a minimum penetration dislocation density.

[0165] Due to the presence of through-dislocations, the EC process, which starts from the apical NID-GaN surface, is thought to proceed through the through-dislocation sites into the underlying multilayer structure. 17 cm -3 Upon reaching the subsurface layer with a charge carrier density exceeding a certain level, etching proceeds outward from the through dislocations into the n+-GaN layer due to the conductivity-selective properties of the EC process.

[0166] Figures 5A and 5B show AFM images of the top NID-GaN surface of a completed wafer-scale DBR sample and a standard as-grown GaN epitaxial layer. The surface morphology of the porous DBR is almost identical to that of the as-grown GaN epitaxial layer. Surface roughness (root mean square roughness over a 5 μm × 5 μm scan) is remarkably similar and can be maintained at approximately 0.4 nm.

[0167] Figure 6 is a photograph of a 2-inch semiconductor wafer 600 in its as-etched state under indoor lighting, showing the reflection of a card with a printed logo. While the areas near the wafer-flat are transparent and unetched, the strong reflection in the etched DBR areas demonstrates that the EC porosity process is uniform and that high-reflectance nonpolar GaN / MP-GaN DBR has been achieved at the wafer scale. Assuming uniform porosity occurred throughout the entire 2-inch wafer, it is again confirmed that, in addition to any lateral etching occurring at the wafer edge, the subsurface layer of n+-GaN is electrochemically etched downward through the surface layer of NID-GaN and all the intermediate layers of NID-GaN.

[0168] The local refractive index of the NID-GaN layer can be altered by etching through the layer, but the measured reflectance values ​​are very close to the theoretical values, and the density of etching paths through such layers is sufficiently low (approximately 2 × 10⁻¹⁰). 9 cm ―2 ), the overall reflectivity at the wafer scale (approximately 5 cm in diameter) is thought to be only slightly affected.

[0169] Most of the materials exhibit sufficient reflectivity and are unaffected by these factors, enabling the fabrication of devices such as LEDs for single-photon sources and micropillar cavity structures with reasonable yields.

[0170] Improved GaN pseudo-substrates with a fairly low density of perfect dislocations still exhibit porosity, even when typical dislocation spacings are a few microns or larger, and wafer-scale fabrication is still possible, even when the effects of vertical etching paths are further reduced.

[0171] The tunability of the DBR can be easily achieved by changing the thickness of the NID-GaN and n+-GaN layers. Figures 7A and 7B show photographs and measured reflectance spectra of various GaN / porous GaN DBR structures under indoor lighting. By simply changing the epitaxial layer thickness of the NID-GaN and n+-GaN, a widely tunable stopband with high reflectivity (>96%) across the entire visible spectrum is demonstrated. Due to the large refractive index contrast between the GaN and porous GaN layers, the stopband width is also maintained at an extremely wide (>80 nm).

[0172] Particularly preferably, the porous GaN structure of the present invention may be used as a substrate or "pseudo-substrate" for further overgrowth or deposition of additional semiconductor materials. In other words, advantageously, it is possible to deposit or overgrow additional layers of group III nitride material or other semiconductor material on the porous semiconductor structure of the present invention to form various devices. The excellent reflective properties demonstrated by the above examples of DBRs make the DBRs formed by the present invention promising, for example, as pseudo-substrates for overgrowth of optoelectronic devices such as LEDs.

[0173] Particularly advantageous, this method enables the preparation of porous semiconductor structures having an "epiready" surface, i.e., porous semiconductor structures having a surface roughness low enough that additional semiconductor layers can be directly epitaxially grown on its structure.

[0174] For example, a porous GaN-based DBR pseudo-substrate according to an embodiment of the present invention can be used for the manufacture of Group III nitride LEDs, lasers, and single-photon sources, and can also be used for the formation of hybrid cavity structures and devices.

[0175] Figure 8A shows a GaN-based LED structure 800 on a NID-GaN / MP-GaN DBR850, as described above in relation to Figures 2-7. After the formation of the DBR according to the above method, an additional semiconductor layer is epitaxially grown on the DBR according to known epitaxial techniques to form a light-emitting diode (LED). Thus, the DBR acts as a pseudo-substrate for the overgrowth of the LED.

[0176] The overgrown LED structure contains a simple pin structure and includes five periodic 2.5 nm InGaN quantum wells separated by a 7.5 nm thick GaN barrier. The bottom of the active region is 3 × 10⁻⁶ 18 cm -3The active region is coated with a 500 nm thick layer of Si-doped n-type GaN having a charge carrier density, and the upper end of the active region is coated with a 300 nm thick layer of Mg-doped p-type GaN.

[0177] To form the mesa, electro-injected LED devices were fabricated using chlorine-based dielectric-bonded plasma etching. The Ti / Al / Ti / Au metal stack annealed in N2 acts as an n-type junction, while a thin Ni / Au layer annealed in an N2 / O2 mixture acts as a translucent current-diffusing layer on top of the p-type GaN layer and beneath the p-type Ti / Au junction.

[0178] Figure 8B shows a cross-sectional SEM image of an LED structure 800 overgrown on a porous GaN DBR pseudo-substrate 850. The pore morphology of the DBR is preserved during the overgrowth process.

[0179] Figure 8C shows a photograph of a similar LED structure 860 without the underlying porous GaN DBR, while Figure 8D shows the same LED structure 800 formed on the porous GaN DBR 850 as described above. In comparison, the LED overgrown on the porous GaN DBR is considerably brighter than the LED without the GaN DBR as a pseudo-substrate. The intensity of optical emission is found to be extremely uniform throughout the device in Figure 8D, which is only hindered by dislocations and GaN material heterogeneity, which may be due to improper cleaning of the DBR before overgrowth.

[0180] Figure 8E shows the room-temperature electroluminescence (EL) "internal quantum efficiency" (IQE) as a function of current density for LEDs with and without porous GaN DBR as a pseudo-substrate. LEDs formed on non-porous DBRs exhibit low IQE, which decreases at low current densities, while the IQE of LEDs / porous GaN DBRs shows a considerably high peak efficiency and begins to decrease at current densities higher than an order of magnitude.

[0181] Figure 9A is a schematic diagram of a multilayer semiconductor structure forming a GaN HEMT transistor structure according to a preferred embodiment of the present invention. The structure comprises several group III nitride materials.

[0182] The structure shown in Figure 9A was epitaxially grown on a 2-inch sapphire wafer 910 by MOVPE according to a known method. First, 1 × 10 14 cm -3 From 1 x 10 17 cm -3 A layer A of NID-GaN having a charge carrier density between is deposited on a sapphire substrate, and then 5 × 10 17 cm -3 A 5 μm thick layer B of GaN with a charge carrier density exceeding 5 × 10 was deposited. 17 cm -3 A 250 nm thick layer C of GaN having a charge carrier density exceeding 1 × 10⁻¹⁶. The charge carrier density of layer C was made higher than that of layer B by intentionally doping layer C to a higher degree. Then, 1 × 10⁻¹⁶ 14 cm -3 From 1 x 10 17 cm -3 A 500 nm thick layer D of NID-GaN having a charge carrier density between was deposited on top of layer C. A 1 nm thick layer E of NID-AlN was deposited on layer D, followed by a 25 nm thick layer F of NID-Al0.25GaN and a 2 nm thick surface layer G of NID-GaN.

[0183] Electrical contacts were fabricated on the multilayer structure, the wafer was immersed in an electrolyte, and etched as described above in relation to Figure 1.

[0184] Figures 9B and 9C are SEM images of the cross-section of the wafer after etching. By taking the cross-section far from the wafer edge, it was demonstrated that porosity was caused by etching through the surface layer, rather than by horizontal etching from the wafer edge. Due to the limitations of the prior art methods discussed above, horizontal etching of the entire 2-inch wafer is not possible.

[0185] As can be seen from Figures 9B and 9C, layers E, F, and G, as well as the NID-GaN layer D, have a charge carrier density of 1 × 10⁻⁶. 14 cm -3 From 1 x 10 17 cm -3 Because it is between the layers, it is not porous. However, the lower GaN layer C is highly porous due to its high charge carrier density, and it can be seen that relatively large pores are distributed within the layer. GaN layer B is also 5 × 10 before etching. 17 cm -3 It was porous because it had a charge carrier density exceeding [a certain value]. However, the pores formed in layer B are considerably smaller than those in layer C. This is due to the lower charge carrier density of layer B.

[0186] Therefore, Figure 9B shows that electrochemical etching occurred through the unintentionally doped surface layer, as well as through the NID layers of AlGaN and AlN. Thus, it is clear that the method of the present invention makes it possible to porous multiple subsurface layers located at various positions in a multilayer semiconductor structure, and that different porosity can be obtained based on the initial charge carrier density of the group III nitride material.

Claims

1. It is a semiconductor structure, The porous subsurface structure of the first group III nitride material, A nonporous surface layer of a second group III nitride material, 1 × 10 １４ cm －３ from 1 x 10 １７ cm －３ It includes a surface layer having a charge carrier density between the following: A semiconductor structure wherein the porous subsurface structure has uniform porosity throughout the entire porous subsurface structure, the lateral width of the surface layer is longer than 550 μm at its narrowest point, and the lateral width of the porous subsurface structure is longer than 550 μm at its narrowest point.

2. The semiconductor structure according to claim 1, wherein the lateral width at the narrowest point of the surface layer is 1 mm or more.

3. The semiconductor structure according to claim 1 or 2, wherein the surface layer and subsurface structure include a group III nitride material selected from the group consisting of GaN, AlGaN, InGaN, and AlInGaN.

4. The penetration dislocation density in both the surface layer and the subsurface structure is 1 × 10⁻⁶ ４ cm －２ The above is 1 x 10 １０ cm －２ A semiconductor structure according to any one of claims 1 to 3, wherein the semiconductor structure is less than [amount missing].

5. The semiconductor structure according to any one of claims 1 to 4, wherein the thickness of the surface layer is 1 nm or more and less than 10 μm.

6. The semiconductor structure according to any one of claims 1 to 5, wherein the average pore size of the porous subsurface structure is greater than 1 nm and less than 70 nm.

7. A semiconductor structure, The porous subsurface structure of the first group III nitride material, A second nonporous surface layer of a group III nitride material, comprising a surface layer having a charge carrier density between 1 × 10¹⁴ cm⁻³ and 1 × 10¹⁷ cm⁻³, The lateral width of the surface layer is longer than 550 μm at its narrowest point, and the lateral width of the subsurface structure is longer than 550 μm at its narrowest point. The subsurface structure comprises a plurality of subsurface layers formed from a group III nitride material in the form of a stack of layers, and counting away from the surface layer, the odd-numbered subsurface layers are porous and have uniform porosity throughout each layer, while the even-numbered subsurface layers are non-porous and have a charge carrier density between 1 × 10¹⁴ cm⁻³ and 1 × 10¹⁷ cm⁻³, forming a semiconductor structure.

8. The semiconductor structure according to claim 7, wherein, counting from away from the surface layer, the odd-numbered subsurface layers each have the same porosity, and the even-numbered layers each are non-porous, and as a result, it acts as a distributed Bragg reflector (DBR).

9. The semiconductor structure according to any one of claims 1 to 8, wherein the pattern is not formed using trenches.

10. The semiconductor structure according to any one of claims 1 to 9, wherein no pre-patterns separated by trenches of less than 600 μm are formed.

11. The semiconductor structure according to any one of claims 1 to 10, wherein the outermost surface of the surface layer has a root mean square roughness of less than 10 nm over an area exceeding 1 square micrometer.

12. The semiconductor structure according to any one of claims 1 to 11, wherein the surface layer is not coated using an electrical insulating layer.

13. Use of the semiconductor structure according to any one of claims 1 to 12 as a substrate for the overgrowth of one or more semiconductor devices.

14. Use of the semiconductor structure according to claim 13, wherein the semiconductor device is a laser or an LED.

15. Use of the semiconductor structure according to any one of claims 1 to 12 as a mirror or distributed Bragg reflector (DBR).

16. A device incorporating or having attached the semiconductor structure described in any one of claims 1 to 12.

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