Semiconductor device manufacturing method

JP7879255B2Active Publication Date: 2026-06-23KYOCERA CORP

Patent Information

Authority / Receiving Office
JP · JP
Patent Type
Patents
Current Assignee / Owner
KYOCERA CORP
Filing Date
2023-10-19
Publication Date
2026-06-23

AI Technical Summary

Benefits of technology

【0007】 幅広のデバイス層(機能層)を形成することができる。

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Abstract

The present invention comprises: a template substrate including a first seed region and a growth suppression region aligned in a first direction; and a first semiconductor part positioned above the template substrate. The first semiconductor part has a first base section positioned on the first seed region, and a first wing section that is connected to the first base section and that faces the growth suppression region with a first gap therebetween. The first wing section includes a wing edge positioned above the growth suppression region, and with regard to the first gap, the ratio of the width in the first direction to the thickness below the wing edge is 5.0 or more.
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Claims

1. A step of preparing a semiconductor substrate comprising: a template substrate including a first seed region and a non-seed region arranged in a first direction; and a first semiconductor portion located above the template substrate, wherein the first semiconductor portion has a first base portion located on the first seed region and a first wing portion connected to the first base portion and facing the non-seed portion via a first gap, the first wing portion includes a wing end located above the non-seed portion, and the ratio of the width of the first gap in the first direction to the thickness below the wing end is 5.0 or more; The process of forming an upper layer above the first wing portion, A method for manufacturing a semiconductor device, comprising the step of peeling the first wing portion from the template substrate while the first wing portion and the upper layer portion are held on the transfer substrate.

2. A method for manufacturing a semiconductor element according to claim 1, wherein the upper layer is not formed below the first wing portion.

3. A method for manufacturing a semiconductor device according to claim 1, comprising the step of forming an anode and a cathode on the upper layer.

4. The method for manufacturing a semiconductor element according to claim 3, wherein the entire anode is formed above the first wing portion.

5. The method for manufacturing a semiconductor element according to claim 3, wherein the anode and the cathode are formed to be aligned in a second direction perpendicular to the first direction.

6. It comprises a second semiconductor section located above the template substrate, The template substrate has a second seed region adjacent to the first seed region via the non-seed portion in a plan view, The second seed region is located above the non-seed portion. The second semiconductor portion has a second base portion located on the second seed region and a second wing portion connected to the second base portion and facing the non-seed portion via a second gap. The second wing portion includes a wing end located above the non-seed portion, The first wing portion and the second wing portion are aligned in the first direction with a gap between them, The method for manufacturing a semiconductor element according to claim 1, wherein the ratio of the width of the second void in the first direction to the thickness below the wing end is 5.0 or more.

7. The method for manufacturing a semiconductor device according to any one of claims 1 to 6, wherein the template substrate has a mask pattern including a mask portion that functions as the non-seed portion and an opening that overlaps with the first seed region in a plan view.

8. A method for manufacturing a semiconductor element according to any one of claims 1 to 6, comprising the step of separating the first wing portion into a plurality of parts arranged in a second direction perpendicular to the first direction.

9. The method for manufacturing a semiconductor device according to any one of claims 1 to 6, wherein the upper layer includes an active layer and a p-type layer.

10. A method for manufacturing a semiconductor device according to any one of claims 1 to 6, wherein the first semiconductor portion includes a nitride semiconductor.

11. The method for manufacturing a semiconductor device according to claim 10, wherein the first direction is the a-axis direction of the nitride semiconductor.

12. The method for manufacturing a semiconductor element according to any one of claims 1 to 6, wherein the ratio of the width in the first direction to the thickness of the first wing portion is 5.0 or more.

13. The method for manufacturing a semiconductor element according to claim 6, wherein the width of the gap is greater than the thickness of the first void below the wing end.

14. The template substrate has a seed portion including the first seed region, A method for manufacturing a semiconductor device according to any one of claims 1 to 6, wherein the seed portion is formed by a sputtering method.

15. The template substrate has a seed portion including the first seed region, The aforementioned seed section contains argon in 2 × 10 18 / cm 3 A method for manufacturing a semiconductor device according to any one of claims 1 to 6, comprising a nitride semiconductor containing the above.