Image sensors and mobile information terminals

Abstract

To provide an imaging device that can detect a difference and consumes less power.SOLUTION: An imaging device includes a pixel including a photoelectric conversion element and a transistor, an analog processing circuit, and a digital processing circuit. The imaging device operates in a first mode and a second mode. In the first mode, the analog processing circuit detects a difference between first imaging data imaged by the pixel and second imaging data imaged by the pixel and generates a trigger signal on the basis of the value of the difference. In the second mode, the digital processing circuit converts third imaging data imaged by the pixel into digital data. The transition from the first mode to the second mode is performed based on the trigger signal.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] One aspect of the present invention relates to an imaging device, a monitoring device, and an electronic device having an imaging function.

[0002] Note that one aspect of the present invention is not limited to the above technical field. The invention disclosed in this specification etc. The technical field of one aspect relates to an object, a method, or a manufacturing method. Or, one aspect of the present invention relates to a process, a machine, a manufacture, or a composition (composition of matter). Therefore, more specifically, the technical field of one aspect of the present invention disclosed in this specification can include semiconductor devices, display devices, light-emitting devices, power storage devices, storage devices, their driving methods, or their manufacturing methods, as an example.

Background Art

[0003] Imaging devices are standardly incorporated into mobile phones and are becoming widespread (see, for example, Patent Document 1). In particular, CMOS image sensors have characteristics such as low cost, high resolution, and low power consumption compared to CCD image sensors, and most imaging devices are composed of CMOS image sensors.

Prior Art Documents

[0004]

Patent Documents

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] When a CMOS image sensor is used in a security camera, an alarm is issued when an intruder is detected. A system that makes a sound can be considered. Specifically, image processing is performed to compare the imaging data of the captured image in the surveillance area when there is no intruder in the surveillance area captured by the CMOS image sensor with the imaging data of the current captured image, and a trigger signal is generated when there is a difference. Such a configuration can be considered. When performing the above image processing, first, the data of each pixel of the CMOS image sensor is read out and converted into digital data by A / D conversion. Subsequently, the digital data is taken into a computer and the image processing software is executed on the computer. Therefore, in order to generate the above trigger signal, a large amount of power is consumed, such as A / D conversion of the data read from the CMOS image sensor, data transfer for taking a large amount of digital data into the computer, storage of the digital data in the storage device in the computer, reading, and execution of the image processing software.

[0006] This is the procedure. Therefore, in order to generate the above trigger signal, a large amount of power is consumed, such as A / D conversion of the data read from the CMOS image sensor, data transfer for taking a large amount of digital data into the computer, storage of the digital data in the storage device in the computer, reading, and execution of the image processing software.

[0007] Therefore, one aspect of the present invention aims to provide a novel imaging device and the like.

[0008] Alternatively, one aspect of the present invention aims to provide a novel imaging device and the like that enables low-power differential detection.

[0009] The problems of one aspect of the present invention are not limited to the above-listed problems. The above-listed problems do not prevent the existence of other problems. Other problems are the problems not mentioned in this item described below. The problems not mentioned in this item can be derived by those skilled in the art from the descriptions in the specification or drawings, etc., and can be appropriately extracted from these descriptions. ​​​​​​​​​​Furthermore, one aspect of the present invention addresses at least one of the above-listed issues and / or other issues. This solves the following problems. [Means for solving the problem]

[0010] One aspect of the present invention, viewed in view of the above problems, comprises a plurality of pixels and an analog processing circuit In an imaging device having a digital processing circuit, the pixels are, in the first mode, first The difference data between the first imaging data in state A and the second imaging data in state B is stored. The differential data can be read, and in the second mode, the third state is The imaging data is stored and the third data can be read out, and the analog processing circuit is, In the first mode, a difference absolute value sum operation is performed on the difference data read from each pixel. If the result of the calculation is greater than a specified value, a trigger signal is generated, and the digital processing circuit In the second mode, the third imaging data read from each pixel is converted to digital via A / D conversion. Convert to data. Note that this imaging device will enter the first mode when a trigger signal is generated. It then transitions to the second mode. Also, if a certain amount of time has elapsed in the second mode, or If a signal is supplied to return to the first mode, the system will transition from the second mode to the first mode. ru.

[0011] Another aspect of the present invention, taken in view of the above problems, involves a plurality of pixels and an analog In an imaging device having a processing circuit and a digital processing circuit, the pixels operate in a first mode. This is the difference data between the first imaging data in the first state and the second imaging data in the second state. It can store the data and read the differential data, and in the second mode, the third state It can store the third imaging data and read out the said third data, and perform analog processing. In the first mode, the circuit controls the current value corresponding to the difference between the first and second imaging data. The system compares the current value with a reference current value, and if a difference is detected, it generates a trigger signal and performs digital processing. In the second mode, the circuit performs A / D conversion on the third imaging data read from each pixel. It is converted into digital data. Furthermore, when a trigger signal is generated, this imaging device will first It transitions from mode 1 to mode 2. Also, if a certain amount of time has elapsed in mode 2, Alternatively, if a signal is supplied to return to the first mode, the system will switch from the second mode to the first mode. It transitions to [this].

[0012] In the above configuration, the first mode does not perform digital processing that consumes a huge amount of power, Furthermore, since only minimal analog processing is required to generate the trigger signal, power consumption is low. This can reduce the amount of noise. Also, in the second mode, the trigger signal is processed digitally. The cause of the generation, that is, the difference from the imaging data in the first mode, can be examined in detail. can.

[0013] An imaging device according to one aspect of the present invention includes a pixel containing a photoelectric conversion element and a transistor, and analog processing It has a circuit and a digital processing circuit. The imaging device operates in a first mode and a second mode. To perform. In the first mode, the analog processing circuit processes the first imaging data captured by the pixel. Then, the difference between the second image data captured by the pixel and the second image data is detected, and a trigger signal is generated based on the value of the difference. In the second mode, the digital processing circuit processes the third image data captured by the pixel. Converts to digital data. The transition from the first mode to the second mode is triggered by the trigger signal. It will be carried out based on this.

[0014] An analog processing circuit included in an imaging device according to one aspect of the present invention processes the first imaging data and the second The absolute difference sum calculation is performed on the imaging data, and if the result of the calculation is not the same as the specified value, the previous This is a circuit that generates a trigger signal. The analog processing circuits include a subtraction circuit and an absolute value circuit. It also has an adding circuit.

[0015] A digital processing circuit included in an imaging device according to one aspect of the present invention has an A / D conversion circuit.

[0016] An imaging device according to one aspect of the present invention, after a certain period of time has elapsed, switches from the second mode to the Transition to mode 1. [Effects of the Invention]

[0017] One aspect of the present invention can provide a semiconductor device or the like with a novel configuration.

[0018] Alternatively, according to one aspect of the present invention, an imaging device capable of low-power differential detection can be provided. can.

[0019] The effects of one embodiment of the present invention are not limited to those listed above. This does not preclude the existence of other effects. These other effects are described below in this section. This is an effect not mentioned in this section. Effects not mentioned in this section can be found in the specification or by someone skilled in the art. This information can be derived from drawings and other documents, and can be extracted as appropriate from these documents. Furthermore, one aspect of the present invention includes at least one of the effects listed above and / or other effects. It has the following effects. Therefore, in some cases, one aspect of the present invention may have the above-listed effects. It may not always be effective. [Brief explanation of the drawing]

[0020] [Figure 1] A diagram illustrating the configuration of the imaging device. [Figure 2] A diagram illustrating the operation of the imaging device. [Figure 3] A diagram illustrating the operation of the imaging device. [Figure 4] A diagram illustrating the configuration and operation of the imaging device. [Figure 5] A diagram illustrating the operation of the imaging device. [Figure 6] A diagram illustrating the configuration of the imaging device. [Figure 7] A diagram illustrating the configuration of the imaging device. [Figure 8] A diagram illustrating the operation of the imaging device. [Figure 9] A circuit diagram explaining the imaging device. [Figure 10] A circuit diagram explaining the imaging device. [Figure 11] A cross-sectional view illustrating the imaging device. [Figure 12] A cross-sectional view illustrating the imaging device. [Figure 13] A block diagram showing an example of a monitoring system configuration. [Figure 14] A diagram showing an electronic device using an imaging device. [Figure 15] Circuit diagrams and cross-sectional views illustrating the imaging device. [Modes for carrying out the invention]

[0021] The embodiments will be described below with reference to the drawings. However, many of the embodiments differ. It is possible to implement it in any manner, without deviating from its purpose and scope. It will be readily apparent to those skilled in the art that the details can be modified in various ways. Therefore, the present invention The following embodiments are not to be interpreted as being limited to their contents.

[0022] A transistor is a type of semiconductor device that amplifies current and voltage, and controls conduction or non-conductivity. This enables switching operations and the like. The transistors used in this specification are IGFET(Insulated Gate Field Effect Transi) Storr) and Thin Film Transistor (TFT) Includes.

[0023] Note that the position, size, and scope of each component shown in the drawings, etc., are for ease of understanding. The position, size, and range of the edges may not be shown. Therefore, the disclosed invention is not necessarily However, this is not limited to the location, size, and scope disclosed in drawings, etc.

[0024] Furthermore, the ordinal numbers such as "1st," "2nd," and "3rd" used in this specification, etc., are intended to avoid confusion of constituent elements. This is added to avoid any misunderstandings and does not mean that the number is limited.

[0025] Furthermore, in this specification, etc., when it is explicitly stated that X and Y are connected, X When X and Y are electrically connected, and when X and Y are functionally connected, This includes cases where and Y are directly connected. Therefore, a given connection relationship, e.g. For example, not limited to the connection relationships shown in the diagram or text, but the connection relationships shown in the diagram or text This includes things other than those mentioned above.

[0026] Here, X and Y are the object (e.g., device, element, circuit, wiring, electrode, terminal, conductive film, layer). (etc.)

[0027] One example of a case where X and Y are electrically connected is when the electrical connection between X and Y is possible. Elements that perform this function (for example, switches, transistors, capacitive elements, inductors, resistive elements, etc.) One or more elements (such as ions, display elements, light-emitting elements, and loads) are connected between X and Y. This is possible. Furthermore, the switch has a function that allows it to be controlled to be on or off. In other words, A switch can be either conductive (on) or non-conductive (off), allowing current to flow. It has a function to control whether or not current flows. Alternatively, the switch selects the path through which the current flows. It has a function to switch between them.

[0028] One example of a functional connection between X and Y is enabling a functional connection between X and Y. Circuits that perform this function (for example, logic circuits (inverters, NAND gates, NOR gates, etc.), signal transformers) Conversion circuits (DA conversion circuits, AD conversion circuits, gamma correction circuits, etc.), potential level conversion circuits (electric (Source circuits (boost circuits, buck circuits, etc.), level shifter circuits that change the potential level of a signal, etc.) Voltage source, current source, switching circuit, amplification circuit (which can increase signal amplitude or current amount, etc.) Circuits, operational amplifiers, differential amplifier circuits, source follower circuits, buffer circuits, etc., signal generation One or more circuits (such as memory circuits and control circuits) can be connected between X and Y. For example, even if another circuit is placed between X and Y, the signal output from X If the signal is transmitted to Y, then X and Y are assumed to be functionally connected.

[0029] Furthermore, if it is explicitly stated that X and Y are electrically connected, then X and Y are electrically connected. When connected electrically (i.e., connected with another element or circuit in between X and Y) (if such a connection exists) and (if X and Y are functionally connected) (When functionally connected with another circuit in between) and when X and Y are directly connected (That is, the case where X and Y are connected without another element or circuit in between) It shall be assumed that they are electrically connected. In other words, when explicitly stating that they are electrically connected, simply, This is equivalent to the case where it is explicitly stated that it is "continued."

[0030] For example, if the source (or first terminal, etc.) of the transistor is connected via Z1 (or via (In short), electrically connected to X, the drain (or second terminal, etc.) of the transistor is connected to Z. If Y is electrically connected via (or without) 2, or if the transistor source (or the first terminal, etc.) is directly connected to a part of Z1, and another part of Z1 is directly connected to X. They are directly connected, with the transistor's drain (or second terminal, etc.) directly connected to a portion of Z2. If it is connected to and another part of Z2 is directly connected to Y, it can be expressed as follows: It is possible to do so.

[0031] For example, "X and Y and the source (or first terminal, etc.) and drain (or second terminal) of the transistor." The terminals (such as the X terminal) are electrically connected to each other, and X is the source (or the X terminal) of the transistor. The electrical connections are in the following order: terminal 1, the drain of the transistor (or terminal 2, etc.), and Y. It can be expressed as "It is connected." Or, "The source (or the source) of the transistor." Terminal 1 (or terminal 2) is electrically connected to X, and the drain (or terminal 2) of the transistor is connected to X. (d) is electrically connected to Y, X is the source of the transistor (or the first terminal, etc.), and the transistor The drain (or second terminal, etc.) of the converter, Y, is electrically connected in this order. It can be expressed as "X is the source (or first terminal) of the transistor." Alternatively, "X is the source (or first terminal) of the transistor." Y is electrically connected to X via the drain (or second terminal, etc.) and X, the transistor The source of the transistor (or the first terminal, etc.), the drain of the transistor (or the second terminal, etc.) ), Y is provided in this connection order. By using a specific method of expression to define the order of connections in the circuit configuration, Distinguish between the source (or first terminal, etc.) and drain (or second terminal, etc.) of the zista. This allows us to determine the technical scope. Note that these expressions are just examples, and The method of representation is not limited to these. Here, X, Y, Z1, and Z2 are the object (e.g., the device). (This refers to elements, circuits, wiring, electrodes, terminals, conductive films, layers, etc.)

[0032] Note that, in circuit diagrams, independent components are shown as being electrically connected to each other. Even in such cases, one component may possess the functions of multiple components. For example, if part of the wiring also functions as an electrode, one conductive film will perform the function of the wiring, and It possesses the functions of both components of the electrode's function. Therefore, the electrode in this specification A conductive connection is a situation where a single conductive film combines the functions of multiple components. Combined forms are also included in that category.

[0033] Note that the placement of each circuit block in the block diagram is for illustrative purposes only, to indicate the positional relationship. Even though it is shown that different circuit blocks can achieve different functions, the actual circuit In a block, different functions can be implemented within the same circuit block. In some cases, the function of each circuit block in the diagram is to identify its function for explanatory purposes. Therefore, even though it is shown as a single circuit block, in the actual circuit block it is one In some cases, the processing that would normally be done by one circuit block is designed to be performed by multiple circuit blocks.

[0034] In this specification, "parallel" means that two straight lines are positioned at an angle of -10° or more and 10° or less. This refers to a state where something is positioned vertically. Therefore, it also includes cases where the angle is between -5° and 5°. This refers to a state where two straight lines are positioned at an angle of 80° to 100°. Therefore, This also includes cases where the angle is between 85° and 95°.

[0035] Furthermore, in this specification, if a crystal is trigonal or rhombohedral, it will be represented as a hexagonal crystal system. .

[0036] (Embodiment 1) The configuration of an imaging device according to one aspect of the present invention will be described with reference to Figure 1. The image device includes a pixel section 1 containing multiple pixels 100 (PIX100) arranged in a matrix. 05. Analog processing circuit 101 (Analog101), A / D processing circuit Conversion circuit 102 (ADC102), column driver 103 (CDRV103), and row driver It has 104 (RDRV104).

[0037] Pixel 100 has a photodiode that functions as a photoelectric conversion element and at least one The analog processing circuit 101 has the above transistors and outputs from each pixel 100. Analog data processing is performed on the image data, which is analog data. More specifically This performs a difference absolute sum calculation on the imaging data output from each pixel 100. If the calculation result differs from the specified value, a trigger signal (indicated as TRIG) is generated. A / D converter The conversion circuit 102 converts the image data output from each pixel 100 into digital data via A / D conversion. Convert to A / D. The A / D converted digital data is sequentially processed by the column driver 103. The data is extracted externally as data. Column driver 103 and row driver 104 have various functions. Various circuits, such as decoders and shift registers, are used.

[0038] Next, the operation of an imaging device according to one embodiment of the present invention will be explained with reference to Figures 2 and 3.

[0039] First, let's explain the operation of the first mode (see Figure 2). In the first mode, analog In the processing circuit 101, an analog operation called difference absolute sum calculation is performed, and the pixel 100 is imaged. The difference between the first image data and the second image data is detected by this analog processing. If there is no difference between the first imaging data and the second imaging data, that is, if there is no trigger signal, If no image is produced, analog processing will continue. Meanwhile, the first image is obtained through this analog processing. If there is a difference between the data and the second imaging data, that is, if a trigger signal is generated, the second It transitions to this mode.

[0040] In another operation, in the first mode, the analog processing circuit 101 processes the difference in the imaging data. A comparison is made between the current value corresponding to the minute and the reference current value, and the first image captured by pixel 100 is then taken. The difference between the image data and the second imaging data is detected. This analog processing is used to obtain the first imaging data. If the difference between the data and the second imaging data is too small to detect, that is, the trigger signal If no error occurs, analog processing will continue. Meanwhile, the first If there is a difference between the first imaging data and the second imaging data, that is, if a trigger signal is generated, Then, it transitions to the second mode.

[0041] For example, the first imaging data is data of a grove of trees (see Figure 3(A1)), and the second imaging If the image data is also image data of a grove of trees (see Figure 3(A2)), then the difference is zero. Therefore, no trigger signal is generated. On the other hand, the first imaging data is the image data of the grove (Figure (See 3(B1)), and the second imaging data is image data of trees and people (Figure 3(B2)) If this is the case, the difference is not zero, so a trigger signal is generated. Upon the occurrence of the signal, the imaging device's mode transitions from the first mode to the second mode. In the illustrated example, the first and second image data are images of the same landscape. The images were taken at different times. Therefore, the first image data represents the first state of the image data. The first image is sometimes denoted as "data," and the second image data may be referred to as the image data of the second state.

[0042] Next, we will explain the operation of the second mode (see Figure 2). In the second mode, pixel 1 The third image data captured by 00 is converted to digital data through A / D conversion. For example, If the third imaging data is data of a grove of trees and a person (see Figure 3(C)), the third imaging By converting image data into digital data and performing detailed analysis on this data, Detailed information about the person in the data can be obtained. Note that the analysis of the image data requires... Digital processing using computer image processing software can be used.

[0043] Next, we will explain the operation when transitioning from the second mode to the first mode (Figure 2). (See Step 110). This is done by setting conditions in advance. For example Conditions such as the passage of a specific period of time, or the input of a control signal to terminate digital processing. Yes. If this condition is met, the system transitions from the second mode to the first mode.

[0044] In an imaging apparatus according to one embodiment of the present invention having the above configuration, in the first mode, a huge amount of power is used. It does not perform any digital processing that consumes resources, and only the minimum necessary analog processing to generate the trigger signal. Since only the processing needs to be done, power consumption can be reduced. Also, in the second mode, Digital processing reveals the cause of the trigger signal generation, namely the first imaging data and the second The differences from the image data can be examined in detail. (Embodiment 2)

[0045] The configuration of the pixels 100 included in an imaging device according to one aspect of the present invention will be explained with reference to Figure 4(A). Pixel 100 is transistor 111, transistor 112, transistor 113, transistor Transistor 114, transistor 115, capacitor 121, capacitor 122 and photodiode 1 It has 23. Also, pixel 100 has power line VPD, power line VPR, power line VC, power line The potential is supplied from VFR and power line VO, and signal line TX, signal line PR, signal line FR and signal A control signal is supplied from line SEL, and image data of pixel 100 is output to signal line OUT. In addition, charge corresponding to the imaging data is accumulated in the charge holding node FD1. Here, the capacity The capacitance value of 121 is the capacitance value of capacitance 122 and the capacitance value of the gate capacitance of transistor 114. A configuration larger than the sum is preferable.

[0046] Transistor 111 has its gate connected to the signal line TX, and either its source or drain connected to the photodie One terminal of Ode 123 is connected to the source or drain, and the other terminal is connected to the source of transistor 112. Alternatively, it is electrically connected to one of the drains. Transistor 112 has a gate that is connected to the signal line. In PR, the source or drain is electrically connected to the power line VPR. Tube 113 has its gate connected to signal line FR, and either the source or drain connected to one of the capacitors 122. The electrode has either a source or a drain, the other being electrically connected to the power line VFR. STA 114 has its gate connected to one electrode of capacitance 122, and either the source or drain connected to the power line. VO is connected to the source or drain of transistor 115. Electrically connected. Transistor 115 has its gate connected to the signal line SEL, source or The other end of the drain is electrically connected to the signal line OUT. Capacitor 121 has one electrode that The other side of the source or drain of transistor 111 and the source or drain of transistor 112 One electrode is electrically connected to the other electrode, and the other electrode is connected to the transistor 1 of the capacitance 122. It is electrically connected to either the source or drain of 13. The other electrode with capacitance 122 is It is electrically connected to the power line VC. The other terminal of photodiode 123 is connected to the power line V It is electrically connected to the PD.

[0047] The operation of pixel 100 will be explained using Figures 4(B) and 5. Here, for example, the power supply Line VPD is low potential, power line VPR is high potential, power line VC is low potential, power line VFR is high potential The power line VO is set to a high potential. First, regarding the operation in the second mode, see Figure 4(B). I will use it to explain.

[0048] Between time T1 and time T2, signal line PR is "H", signal line FR is "H", signal line TX Let this be "H". At this time, the potential of the charge holding node FD1 is the potential of the power line VFR (V1). The setting is configured to ( ), and the potential of node FD2 is set to the potential of power line VPR (let's call it V2). At times T2 to T3, signal line PR is set to "L", signal line FR is set to "L", signal line T Let X be "H". At this time, depending on the light irradiated onto the photodiode 123, node FD The potential at node 2 decreases. Here, if we let ΔV2 be the voltage drop across node FD2, then node FD The potential of point 2 is V2-ΔV2. Also, capacitance 121 (capacitance value C1) and capacitance 122 (capacitance The combined capacitance of the value C2) and the gate capacitance of transistor 114 (capacitance value Cg), and the capacitive coupling As a result, the potential of the charge-holding node FD1 also decreases. Here, the voltage of the charge-holding node FD1 If the descent is ΔV1, then ΔV1 = ΔV2·C1 / (C1+C2+Cg) = ΔV2·α Yes, the potential of the charge-holding node FD1 is V1-ΔV1. Note that photodiode 12 The stronger the light irradiating node 3, the lower the potential of node FD2. Also, charge-holding node FD1 The potential also decreases. At times T4 to T5, the signal line SEL is set to "H". At that time, depending on the potential of the charge-holding node FD1, a signal corresponding to the imaging data is sent to the signal line OUT. The output is generated. Note that the lower the potential of the charge-holding node FD1, the lower the potential of the signal line OUT. That is, the stronger the light shining on the photodiode 123, the higher the potential of the signal line OUT. It will decrease. The same explanation can be given for times T6 through T10 as for times T1 through T5. Cut.

[0049] Next, the operation in the first mode will be explained using Figure 5.

[0050] Time T01 to time T06 corresponds to the period during which the first imaging data is acquired in the first state. At times T01 to T02, signal line PR is set to "H", signal line FR is set to "H", Let line TX be "H". At this time, the potential of charge-holding node FD1 is the potential of power line VFR ( It is set to V1), and the potential of node FD2 is set to the potential of power line VPR (V2). At time T02 to time T03, signal line PR is set to "L", signal line FR is set to "H", and signal line T Let X be "H". At this time, depending on the light irradiated onto the photodiode 123, node FD The potential at node 2 decreases. Here, if we let ΔV2 be the voltage drop across node FD2, then node FD The potential of point 2 is V2 - ΔV2. Note that the stronger the light irradiated onto photodiode 123, The potential of node FD2 decreases. However, the potential of charge-holding node FD1 remains unchanged. Time Between time T03 and time T04, signal line PR is set to "L", signal line FR is set to "L", and signal line TX Let this be "H". Note that the interval between time T02 and time T03 and the interval between time T03 and time T04 Let the interval be equal to T. At this time, depending on the light irradiated onto the photodiode 123, The potential of FD2 decreases, becoming V2-2·ΔV2. Also, capacitance 121 and capacitance 122 The gate capacitance of transistor 114 and the capacitive coupling between them result in the potential of the charge-holding node FD1. It also decreases. Here, if we let ΔV1 be the voltage drop across the charge holding node FD1, then ΔV1 = Δ V2·α, and the potential of the charge-holding node FD1 is V1-ΔV1. The stronger the light irradiated onto node 123, the lower the potential of node FD2. Also, charge-holding node The potential of FD1 also decreases. Note that here, the interval between time T02 and time T03 and time The interval between time T03 and time T04 was assumed to be equal to T, but the interval between time T02 and time T03 and time Set the voltage drop at node FD2 to be equal between time T03 and time T04. This is the essence of one aspect of the present invention. Therefore, to satisfy the above conditions, at time T02 A configuration that appropriately adjusts the interval between the time T03 and the times T03 to T04 is preferred. Between time 05 and time T06, the signal line SEL is set to "H". At this time, the charge holding node F Depending on the potential of D1, a signal corresponding to the imaging data is output to the signal line OUT. The lower the potential of the load holding node FD1, the lower the potential of the signal line OUT. In other words, The stronger the light shining on the diode 123, the lower the potential of the signal line OUT.

[0051] The period from time T11 to time T15 corresponds to the time during which the second imaging data is acquired in the second state. This is especially true when the difference between the first and second imaging data is zero. Between time T11 and time T12, signal line PR is set to "H", signal line FR is set to "L", and signal line TX Let this be "H". At this time, the potential of node FD2 is set to the potential of power line VPR (V2). That is, the voltage drop (2·ΔV2) between time T02 and time T04, the potential is higher. It rises. On the other hand, capacitance 121, capacitance 122 and the gate capacitance of transistor 114, and the capacitance Due to the coupling, the potential of the charge-holding node FD1 also rises, but the rise (2·ΔV1) is due to time This corresponds to twice the voltage drop at time T03 to T04. In other words, the power line VFR The potential (V1) plus the voltage drop (ΔV1) at time T03 to time T04. (V1 + ΔV1). Between time T12 and time T13, signal line PR is set to "L", signal Let line FR be "L" and signal line TX be "H". At this time, the photodiode 123 is illuminated. Depending on the light, the potential of node FD2 decreases, and capacitance 121 and capacitance 122 and the traction control are also affected. The gate capacitance of transistor 114, coupled with the capacitive coupling, also lowers the potential of the charge-holding node FD1. The stronger the light irradiated onto photodiode 123, the lower the potential of node FD2. In addition, the potential of the charge-holding node FD1 also decreases.

[0052] Here, let T be the interval between time T12 and time T13, and the intensity be the same as between time T02 and time T04. Assuming that the light is shining on photodiode 123, the voltage drop at node FD2 This is equal to the drop ΔV2 at time T03 to time T04. Also, the charge holding node FD1 The voltage drop is also equal to the drop ΔV1 at time T03 to time T04. Therefore, the charge retention The potential of node FD1 becomes V1. This is because the first imaging data and the second imaging data The difference corresponds to zero.

[0053] Between time T14 and time T15, the signal line SEL is set to "H". At this time, the charge holding no Depending on the potential of FD1, a signal corresponding to the imaging data is output to the signal line OUT. Oh, the potential of the signal is the potential when the difference between the first imaging data and the second imaging data is zero. To reach a certain rank.

[0054] The period from time T21 to time T25 corresponds to the time during which the second imaging data is acquired in the second state. In particular, the first imaging data and the second imaging data, as with time T11 to time T15. This corresponds to the case where the difference is zero.

[0055] The period from time T31 to time T35 corresponds to the time during which the second imaging data is acquired in the second state. This is especially true when the difference between the first imaging data and the second imaging data is finite (negative). Between time T31 and time T32, signal line PR is set to "H", signal line FR is set to "L", signal Let line TX be "H". At this time, the potential of node FD2 is set to the potential of power line VPR (V2). It is determined that the voltage drop (ΔV2) at time T12 to time T13 is equal to the potential. It increases. Meanwhile, capacitance 121, capacitance 122 and the gate capacitance of transistor 114, Due to quantitative coupling, the potential of the charge-holding node FD1 also rises, but the rise (ΔV1) occurs at time T This corresponds to the voltage drop between 12 and time T13. That is, the potential of the power line VFR (V 1) Add the voltage drop (ΔV1) at time T03 to time T04 to the potential (V1+ ΔV1) is obtained. Between time T32 and time T33, signal line PR is set to "L" and signal line FR Let be "L" and signal line TX be "H". At this time, the light irradiated onto photodiode 123 is Accordingly, the potential of node FD2 decreases, and the capacitance 121, capacitance 122 and transistor Capacitive coupling with the gate capacitance 114 also lowers the potential of the charge-holding node FD1. The light irradiated onto the photodiode 123 is less than the light irradiated at time T12 to time T13. Assume it is strong. Here, if T is the interval between time T32 and time T33, then the power of node FD2 The pressure drop (ΔV2') is greater than the pressure drop (ΔV2) at time T12 to time T13 (Δ V2'>ΔV2). Also, the voltage drop across the charge-holding node FD1 (ΔV1'=ΔV2'·α) ) is also greater than the descent (ΔV1) at time T12 or time T13 (ΔV1'>ΔV1). Therefore, the potential of the charge-holding node FD1 (V1 + ΔV1 - ΔV1') is the power line VFR This will be lower than the potential (V1) between the first imaging data and the second imaging data. The difference corresponds to a finite (negative) difference.

[0056] Between time T34 and time T35, the signal line SEL is set to "H". At this time, the charge holding no Depending on the potential of FD1, a signal corresponding to the imaging data is output to the signal line OUT. Oh, the potential of the signal is lower than the potential of the signal at time T24 to time T25, This represents the potential when the difference between the first imaging data and the second imaging data is finite (negative).

[0057] The period from time T41 to time T45 corresponds to the time during which the second imaging data is acquired in the second state. This is particularly true when the difference between the first and second imaging data is again zero. Between time T41 and time T42, signal line PR is set to "H", signal line FR is set to "L", signal line Set TX to "H". At this time, the potential of node FD2 is set to the potential of power line VPR (V2). This means that the voltage drop (ΔV2') at time T32 to time T33 is equal to the potential. It increases. Meanwhile, capacitance 121, capacitance 122 and the gate capacitance of transistor 114, Due to quantitative coupling, the potential of the charge-holding node FD1 also rises, but the rise (ΔV1') is due to time This corresponds to the voltage drop at time T32 to T33. That is, the potential of the power line VFR ( The potential (V1) is obtained by adding the voltage drop (ΔV1) at time T03 to time T04. +ΔV1) is the result. Between time T42 and time T43, signal line PR is "L", and signal line F Let R be "L" and signal line TX be "H". At this time, the light shining on photodiode 123 Accordingly, the potential of node FD2 decreases, and the capacitance 121 and capacitance 122 and the transient The gate capacitance of 114 and the capacitive coupling between them also lower the potential of the charge-holding node FD1. Furthermore, the stronger the light irradiated onto photodiode 123, the lower the potential of node FD2. Furthermore, the potential of the charge-holding node FD1 also decreases. This occurs between time T42 and time T43. Let the interval be T, and light of the same intensity as at time T02 to time T04 is shone onto the photodiode 123. Assuming this is the case, the voltage drop at node FD2 is the voltage drop at time T03 to time T04. It is equal to ΔV2. Also, the voltage drop across the charge-holding node FD1 is equal to time T03 to time T04. It is equal to the drop ΔV1. Therefore, the potential of the charge-holding node FD1 is V1. This corresponds to a zero difference between the first and second imaging data. Time T44 At time T45, the signal line SEL is set to "H". At this time, the charge holding node FD1 Depending on the potential, a signal corresponding to the imaging data is output to the signal line OUT. The potential is the potential when the difference between the first imaging data and the second imaging data is zero.

[0058] The period from time T51 to time T55 corresponds to the time during which the second imaging data is acquired in the second state. This is especially true when the difference between the first imaging data and the second imaging data is finite (positive). Between time T51 and time T52, signal line PR is set to "H", signal line FR is set to "L", signal Let line TX be "H". At this time, the potential of node FD2 is set to the potential of power line VPR (V2). It is determined that the voltage drop (ΔV2) at time T42 to time T43 is It increases. Meanwhile, capacitance 121, capacitance 122 and the gate capacitance of transistor 114, Due to quantitative coupling, the potential of the charge-holding node FD1 also rises, but the rise (ΔV1) occurs at time T This corresponds to the voltage drop between time 42 and time T43. That is, the potential of the power line VFR (V 1) Add the voltage drop (ΔV1) at time T03 to time T04 to the potential (V1+ ΔV1)

[0059] Between time T52 and time T53, signal line PR is set to "L", signal line FR is set to "L", signal line Let TX be "H". At this time, node F depends on the light irradiated onto photodiode 123. The potential of D2 decreases, and the gate capacitance of capacitor 121, capacitor 122, and transistor 114 decreases. Due to the capacitive coupling of the quantity and, the potential of the charge-holding node FD1 also decreases. The light irradiated onto code 123 is assumed to be weaker than the light irradiated at time T12 to time T13.

[0060] Here, if we let T be the interval between time T52 and time T53, then the voltage drop at node FD2 is (Δ V2'' is less than the drop (ΔV2) between time T12 and time T13 (ΔV2'' < ΔV2). Also, the voltage drop across the charge-holding node FD1 (ΔV1''=ΔV2''·α) The descent (ΔV1) at time T12 to time T13 is less than (ΔV1'' < ΔV1). Therefore, the potential of the charge-holding node FD1 (V1 + ΔV1 - ΔV1'') is the same as the power line VFR. This will be higher than the potential (V1) between the first imaging data and the second imaging data. The difference corresponds to a finite (positive) difference.

[0061] Between time T54 and time T55, the signal line SEL is set to "H". At this time, the charge holding no Depending on the potential of FD1, a signal corresponding to the imaging data is output to the signal line OUT. Oh, the potential of the signal is higher than the potential of the signal at time T24 to time T25, This represents the potential when the difference between the first imaging data and the second imaging data is finite (positive).

[0062] In this embodiment, the first imaging data is output at times T05 to T06. As explained, the difference data between the first and second imaging data is obtained. If obtaining it is sufficient, that is, if there is no need to output the first imaging data, then time The operations from time T03 to time T06 can be omitted. If the operation is omitted, the operation will be as follows: That is, between time T11 and time T12 When signal line PR is set to "H", signal line FR is set to "L", and signal line TX is set to "H", the node The potential of FD2 is set to potential V2 from the potential V2-ΔV2 at time T03. Also, The potential of the charge-holding node FD1 rises from potential V1 at time T03 to potential V1+ΔV1. Yes. Furthermore, the operation after time T12 can be explained in the same way as above.

[0063] This embodiment can be used in appropriate combination with other embodiments. (Embodiment 3)

[0064] An example of the configuration of an analog processing circuit included in an imaging device according to one aspect of the present invention will be explained with reference to Figure 6. To clarify, the analog processing circuit consists of subtraction circuits SUB[1] to SUB[n] and absolute value circuits AB. It has S[1] to ABS[n] and an adder circuit SUM.

[0065] Subtraction circuits SUB[1] to SUB[n] each connect to the signal line OUT[1] to the signal line OUT[1] of the pixel. The potential of signal line OUT[n] is subtracted from the reference potential VREF. The reference potential VREF is... A dummy circuit equivalent to element 100 is prepared, and the potential of the charge-holding node FD1 is set to VFR. It can be generated by setting the potential of the signal line OUT. Subtraction circuit SUB[1] or subtraction Each calculation circuit SUB[n] has an op-amp OP0 and resistors R01 to R04. Now, for the subtraction circuit SUB[1], the potential of the signal line OUT[1] is set to V10, VREF The potential is set to V20. Also, the resistance values ​​of resistors R01 to R04 are given by the following equations (1) and (2) Set it to satisfy the following conditions.

[0066] R01=R04 (1)

[0067] R04 / R01=R03 / R02 (2)

[0068] Then, the output of the subtraction circuit SUB[1] satisfies equation (3) below.

[0069] V0 = V20 - V10 (3)

[0070] The outputs of subtraction circuits SUB[2] through SUB[n] can be explained similarly. ru.

[0071] The absolute value circuit ABS[1] to the absolute value circuit ABS[n] is a subtraction circuit SUB[1] to the subtraction circuit The absolute values ​​of the outputs of circuit SUB[n] are output. Absolute value circuits ABS[1] to absolute value circuits The circuit ABS[n] consists of op-amp OP11, op-amp OP12, resistor R11, and resistors, respectively. It has R15, diode D11, and diode D12. Here, the absolute value circuit ABS[1 Regarding ], the input signal is set to potential V10', R11=R12, R13×2=R14=R1 When the resistance value is set to 5, the output of the absolute value circuit ABS[1] becomes |V10'|. ru.

[0072] The outputs of absolute value circuits ABS[2] through ABS[n] will be explained similarly. can.

[0073] The SUM adder circuit outputs the sum of the outputs of absolute value circuits ABS[1] through ABS[n]. The summing circuit SUM uses op-amp OP21, op-amp OP22, resistor R21, and so on. It has resistors R2n, R31 to R33. Here, the absolute value circuit ABS[1] to Let the potentials of each output of the absolute value circuit ABS[n] be V10'' to Vn0'', and R21 = (omitted) If you set the resistance values ​​so that R2n=R31 and R32=R33, the summing circuit The output of SUM is V10'' + (omitted) + Vn0''. This is then used as the trigger signal TR. If we consider IG, then TRIG=0 if the first and second imaging data are identical. On the other hand, if the first imaging data and the second imaging data are different, TRIG = 1.

[0074] By adopting the above configuration, we provide an imaging device capable of low-power differential detection. It is possible.

[0075] This embodiment can be used in appropriate combination with other embodiments.

[0076] (Embodiment 4) An example of the configuration of an analog processing circuit included in an imaging device according to one aspect of the present invention will be explained with reference to Figure 7. To clarify, the analog processing circuit consists of transistor 136, transistor 137, and transistor 138, transistor 139, transistor 140, transistor 141, transistor 142, transistor 143, transistor 144, transistor 145, transistor 146, Transistor 147, Transistor 148, Capacitor 149, Comparator CMP+ It consists of a comparator CMP-, a reference potential line Vref+, and a reference potential line Vref The potential of - should be set as appropriate.

[0077] Figure 8 is a timing chart showing the operation of the analog processing circuit.

[0078] Between time T61 and time T62, signal line ABU is set to "H", signal line AOP is set to "L", Let the ATC on line number be "H". Also, let the signal line FR be "H" and the signal line SEL[x] be "H". The signal line SEL[x] is the signal line S of any row (the xth row; x is a natural number less than or equal to m). It is EL. At this time, it is supplied to the signal line OUT[y] (where y is a natural number less than or equal to n) of the yth column. The current is defined as the gate potential VFR of transistor 114 of each pixel PIX in the x-th row. The amount of current at that time, that is, the difference between the imaging data of the initial frame and the imaging data of the current frame. This is the current I0[y] when it is zero. This current I0[y] is the reference current (of the yth column). In some cases, the reference current amounts for each column are I0[1] to I0[ n] is not always the same, but as will be clear from the discussion below, current quantity I0[1] to current quantity The individual values ​​of I0[n] do not directly affect the operation of the circuit. Therefore, from now on, the current I0 [1] All current quantities I0[n] are denoted as current quantity I0.

[0079] The current Ip[1] through Ip[n] flowing through transistor 136 is equal to the current quantity I0. Furthermore, currents Ic[1] through Ic[n] are also equal to the current quantity I0. The current flowing through transistor 137, to which the drain and gate are connected by transistor 138, is also It is equal to the current I0. In particular, the potential required to charge the capacity 149 is necessary to allow the current I0 to flow. It is set to a potential equivalent to the gate voltage.

[0080] Between time T63 and time T64, signal line ABU is set to "H", signal line AOP is set to "H", Let the ATC on line number be "L" and the signal line SEL[1] be "H". In this case, in the first row The current corresponding to the difference data of each pixel is transmitted through signal lines OUT[1] to OUT[n] of each column. It is supplied to ]. Here, assuming that the difference data of each pixel in the first row is zero, then the difference data of each column The current supplied to signal line OUT[1] through signal line OUT[n] is I0, transistor 13 The currents Ip[1] through Ip[n] flowing through 6 are equal to I0, and the current Ic[ 1) The current Ic[n] is also equal to the current I0.

[0081] Between time T64 and time T65, signal line ABU is set to "H", signal line AOP is set to "H", Let the ATC on line number "L" and the signal line SEL[2] "H". In this case, in the second row The current corresponding to the difference data of each pixel is transmitted through signal lines OUT[1] to OUT[n] of each column. It is supplied to ]. Here, the difference data of each pixel in the second row is finite (negative), and the y If the current supplied to the signal line OUT[y] of the column is (I0-ΔIy), then the y-th column transistor The current Ip[y] flowing through Zistor 136 is equal to (I0 - ΔIy), and the current I Since c[y] is equal to the current I0, transistors 139 and 140 in the y-th column A current ΔIy will flow through it.

[0082] Here, in order to pass a current ΔI1 to ΔIn through each of the transistors 140 in each row, Current I, which corresponds to the sum of the two values. - It is necessary to supply the following: Comparator CMP- and Tra Due to the action of inverter 142, the current I - This is supplied. That is, the transitions of each column The sum of the currents flowing through station 140 is I - If less (more), the comparator CMP- The potential at the + terminal will decrease (increase), and the output of the comparator CMP- will decrease (increase). ) In other words, the gate voltage of transistor 142 decreases (increases), and more (less) i) Current I - This will enable the supply of these resources.

[0083] Furthermore, since the same potential as the gate of transistor 142 is applied to transistor 143, Current n1·I obtained by multiplying the W / L ratio (n1) of transistor 143 compared to transistor 142. - This flows to transistor 143. Also, between transistor 148 and transistor 143 The configured buffer causes the signal TRIG to become "H". Note that transistor 148 is... A bias voltage, bias, is applied to the gate.

[0084] Between time T66 and time T67, signal line ABU is set to "H", signal line AOP is set to "H", Let the ATC on line number be "L" and the signal line SEL[m] be "H". In this case, in the mth row The current corresponding to the difference data of each pixel is transmitted through signal lines OUT[1] to OUT[n] of each column. It is supplied to ]. Here, the difference data of each pixel in the mth row is given by the first column being finite (positive) The second column is finite (positive), the nth column is finite (negative), and the other columns are zero, and the signal lines OU of each column The current supplied to T[1], signal line OUT[2], and signal line OUT[n] is (I0 + ΔI1 If we consider (I0 + ΔI2) and (I0 - ΔIn), then the current flows through transistor 136. Currents Ip[1], Ip[2], and Ip[n] are (I0+ΔI1) and (I0+ΔI2) ), is equal to (I0-ΔIn), and current Ic[1] to current Ic[n] is equal to current quantity I0 Because it is equal to, the power is transmitted through transistors 139 and 140 in the first and second columns. Flows ΔI1 and ΔI2 flow through transistors 139 and 141 in the nth column, A current ΔIn will flow.

[0085] Here, in order to pass currents ΔI1 and ΔI2 through the transistors 140 in the first and second columns, a current I - = ΔI1 + ΔI2 needs to be supplied. Here, due to the operation of the comparator CMP- and the transistor 142, this current I - is supplied. That is, when the current flowing through the transistors 140 in each column is less (more) than ΔI, the potential of the + terminal of the comparator CMP- will decrease (increase), and the output of the comparator CMP- will decrease (increase). That is, the gate voltage of the transistor 142 will decrease (increase), and more (less) current I can be supplied. -

[0086] Also, in order to pass a current ΔIn through the transistor 141 in the nth column, a current I + = ΔIn needs to be passed. Here, due to the operation of the comparator CMP+ and the transistor 144, this current I + can flow. That is, when the current flowing through the transistor 141 in the nth column is less (more) than ΔIn, the potential of the + terminal of the comparator CMP+ will increase (decrease), and the output of the comparator CMP+ will increase (decrease). That is, the gate voltage of the transistor 144 will increase (decrease), and more (less) current I + can flow.

[0087] Also, since the same potential as the gate of the transistor 142 is applied to the transistor 143, a current n1·I which is n1 times the W / L ratio (n1) of the transistor 143 with respect to the transistor 142 flows. - This flows to transistor 143.

[0088] Furthermore, since the same potential as the gate of transistor 144 is applied to transistor 145, Current n2·I obtained by multiplying the W / L ratio (n2) of transistor 145 compared to transistor 144. + The current flows through transistor 145. It also flows to 6, and furthermore, the W / L ratio of transistor 147 to transistor 146 (n3 ) The current n3·n2·I multiplied by ) + The current flows to transistor 147. Transistor 148 and The buffer, consisting of transistor 143 and transistor 147, allows the signal TRIG to It becomes "H".

[0089] By adopting the above configuration, we provide an imaging device capable of low-power differential detection. It is possible.

[0090] This embodiment can be used in appropriate combination with other embodiments.

[0091] (Embodiment 5) This embodiment describes a modified version of the pixel described in the above embodiment.

[0092] Figure 9(A) shows the semiconductor layer of the transistor in the circuit diagram of Figure 4(A) as an oxide semiconductor. A modified version of the circuit diagram is shown below. In pixel 100A shown in Figure 9(A), transistor 111 The first 115 has a configuration in which an oxide semiconductor is used as the semiconductor layer.

[0093] In the circuit diagram, a transistor having an oxide semiconductor as its semiconductor layer (OS transistor) is shown. (Also known as) Circuit symbol for an oxide semiconductor transistor The term "OS" is included.

[0094] OS transistors have characteristics such as extremely low off-current characteristics. This allows for an expansion of the dynamic range of imaging. In the circuit diagram shown in Figure 9(A), The potential of the charge-holding node FD1 when the intensity of light incident on photodiode 123 is high. The value becomes smaller. Because OS transistors have extremely low off-current characteristics, the gate potential becomes smaller. Even at extremely low gate potentials, it is possible to accurately output a current corresponding to the gate potential. Therefore, the range of illuminance that can be detected, i.e., the dynamic range, can be widened. It is possible.

[0095] Furthermore, because the OS transistor has extremely low off-current characteristics, the charge-holding node FD1 Because it can hold charge for an extremely long period, the circuit configuration and operating method A global shutter system can be applied without increasing complexity. Therefore, moving objects Even so, it is easy to obtain images with little distortion. Also, for the same reason, exposure time Since it is possible to extend the period during which charge accumulation occurs, it is possible to take photos in low-light environments. It is also suitable for statues.

[0096] Furthermore, OS transistors exhibit less temperature dependence of electrical characteristics than Si transistors. Therefore, it can be used over an extremely wide temperature range. Imaging devices and semiconductor devices with this feature are also suitable for mounting in automobiles, aircraft, spacecraft, etc. It is.

[0097] Figure 9(B) also shows a modified version of the circuit diagram for pixel 100B, which is a further modification of Figure 9(A). 。In pixel 100B shown in FIG. 9(B), transistors 114 and 115 are configured to have a silicon semiconductor layer. 。

[0098] In the circuit diagram, in order to indicate that a transistor has a silicon semiconductor layer (also referred to as a Si transistor), the circuit symbol of the transistor using silicon is labeled with "Si". 。 。

[0099] Si transistors have characteristics such as excellent field-effect mobility compared to OS transistors. Therefore, the amount of current flowing through the transistor functioning as an amplification transistor can be increased. For example, in FIG. 9(B), the amount of current flowing through transistors 114 and 115 can be increased according to the charge stored in charge holding node FD1. 。 。 。

[0100] FIG. 10 shows a circuit diagram of pixel 100C in which photodiode 123 in the circuit diagram of FIG. 4(A) is used as sensor 123A. 。

[0101] Sensor 123A is preferably an element that can convert the given physical quantity into the amount of current flowing through the element. Alternatively, it is preferably an element that can convert the given physical quantity into another physical quantity first and then convert it into the amount of current flowing through the element. 。 。

[0102] Various sensors can be used for sensor 123A. For example, as sensor 123A, a temperature sensor, a light sensor, a gas sensor, a flame sensor, a smoke sensor, a humidity sensor, a pressure sensor, a flow sensor, a vibration sensor, an audio sensor, a magnetic sensor, a radiation sensor, an odor sensor, a pollen sensor, an acceleration sensor, an inclination angle sensor, a gyro sensor, a direction sensor, a power sensor, etc. 。 。 。 can be used.

[0103] For example, when using a photosensor as sensor 123A, a photodiode or a phototransistor can be used.

[0104] Also, when using a gas sensor as sensor 123A, a semiconductor gas sensor that detects a change in resistance due to gas adsorption on a metal oxide semiconductor such as tin oxide, a catalytic combustion type gas sensor, a solid electrolyte type gas sensor, etc. can be used.

[0105] Also, in FIG. 15(A), the photodiode 123 in the circuit diagram of FIG. 4(A), or sensor 123A in the circuit diagram of FIG. 10 is replaced with a selenium-based semiconductor element S S e which is a photoelectric conversion element, and the circuit diagram of pixel PIX_SE is shown.

[0106] The selenium-based semiconductor element S Se is an element capable of photoelectric conversion by utilizing the phenomenon of avalanche multiplication, in which a plurality of electrons can be extracted from a single incident photon by applying a voltage. Therefore, in pixel PIX_SE having the selenium-based semiconductor element S the amplification factor of electrons with respect to the amount of incident light can be increased, and a highly sensitive sensor can be obtained. Se In pixel PIX_SE having the selenium-based semiconductor element S the amplification factor of electrons with respect to the amount of incident light can be increased, and a highly sensitive sensor can be obtained.

[0107] The selenium-based semiconductor element S Se can be a selenium-based semiconductor having amorphous properties or a selenium-based semiconductor having crystalline properties. As an example, a selenium-based semiconductor having crystalline properties can be obtained by heat-treating an amorphous selenium-based semiconductor after film formation. Note that by making the crystal grain size of the crystalline selenium-based semiconductor smaller than the pixel pitch, for each pixel ​​​ This reduces variations in characteristics, resulting in more uniform image quality, which is desirable.

[0108] Among selenoid semiconductors, crystalline selenoid semiconductors have a light absorption coefficient that is wide across a broad wavelength range. It possesses the characteristic of being able to do so across a wide range of light sources. Therefore, in addition to visible light and ultraviolet light, it also possesses X-rays, It can be used as an imaging sensor for a wide wavelength range, including gamma rays, and X-rays and gamma rays. It is used as a so-called direct conversion type element that can directly convert light in the short wavelength range, such as lines, into electric charge. It is possible.

[0109] Figure 15(B) shows a schematic diagram of the cross-sectional structure corresponding to a part of the circuit configuration shown in Figure 15(A). Yes. In Figure 15(B), transistor 111 and electrode E connected to transistor 111 are shown. Pix , selenium-based semiconductor device S Se , electrode E VPD The diagram shows the substrate Sub.

[0110] Electrode E VPD , and from the side where the substrate Sub is provided, the selenium-based semiconductor S Se Shine a light towards it It is incident. Therefore, electrode E VPD The substrate Sub preferably has light-transmitting properties. Extreme E VPD For example, indium tin oxide (ITO) ) can be used, and a glass substrate can be used as the substrate Sub.

[0111] Selenium-based semiconductor device S Se , and selenium-based semiconductor device S Se Electrode E is provided by stacking them. VP D It can be used without processing the shape of each pixel. Since the process can be reduced, the manufacturing cost can be reduced and the manufacturing yield can be improved. This can be achieved.

[0112] As an example, the selenium-based semiconductor can be a chalcopyrite-based semiconductor. As a specific example, CuIn 1-x Ga x Se2(0≦x≦1) (abbreviated as CIGS) can be cited. CIGS can be formed using vapor deposition, sputtering, or the like. This is possible.

[0113] The selenium-based semiconductor, which is a chalcopyrite-based semiconductor, can exhibit avalanche multiplication by applying a voltage of about several volts (5 to 20 V). By applying a voltage to the selenium-based semiconductor, the straightness in the movement of signal charges generated by light irradiation can be enhanced. The film thickness of the selenium-based semiconductor can be reduced to 1 μm or less, thereby reducing the applied voltage. When a voltage is applied to the selenium-based semiconductor, dark current flows. However, in order to prevent dark current from flowing in CIGS, which is the above-mentioned chalcopyrite-based semiconductor, a layer (hole injection barrier layer) can be provided to suppress the flow of dark current. As the hole injection barrier layer, an oxide semiconductor can be used. As an example, gallium oxide can be used. The film thickness of the hole injection barrier layer is preferably smaller than the film thickness of the selenium-based semiconductor. When the film thickness of the selenium-based semiconductor is small, dark current flows when a voltage is applied. However, in order to prevent dark current from flowing in CIGS, which is the above-mentioned chalcopyrite-based semiconductor, a layer (hole injection barrier layer) can be provided to suppress the flow of dark current. As the hole injection barrier layer, an oxide semiconductor can be used. As an example, gallium oxide can be used. The film thickness of the hole injection barrier layer is preferably smaller than the film thickness of the selenium-based semiconductor. When the film thickness of the selenium-based semiconductor is small, dark current flows when a voltage is applied. However, in order to prevent dark current from flowing in CIGS, which is the above-mentioned chalcopyrite-based semiconductor, a layer (hole injection barrier layer) can be provided to suppress the flow of dark current. As the hole injection barrier layer, an oxide semiconductor can be used. As an example, gallium oxide can be used. The film thickness of the hole injection barrier layer is preferably smaller than the film thickness of the selenium-based semiconductor.

[0114] When the film thickness of the selenium-based semiconductor is small, dark current flows when a voltage is applied. However, in order to prevent dark current from flowing in CIGS, which is the above-mentioned chalcopyrite-based semiconductor, a layer (hole injection barrier layer) can be provided to suppress the flow of dark current. As the hole injection barrier layer, an oxide semiconductor can be used. As an example, gallium oxide can be used. The film thickness of the hole injection barrier layer is preferably smaller than the film thickness of the selenium-based semiconductor. When the film thickness of the selenium-based semiconductor is small, dark current flows when a voltage is applied. However, in order to prevent dark current from flowing in CIGS, which is the above-mentioned chalcopyrite-based semiconductor, a layer (hole injection barrier layer) can be provided to suppress the flow of dark current. As the hole injection barrier layer, an oxide semiconductor can be used. As an example, gallium oxide can be used. The film thickness of the hole injection barrier layer is preferably smaller than the film thickness of the selenium-based semiconductor. When the film thickness of the selenium-based semiconductor is small, dark current flows when a voltage is applied. However, in order to prevent dark current from flowing in CIGS, which is the above-mentioned chalcopyrite-based semiconductor, a layer (hole injection barrier layer) can be provided to suppress the flow of dark current. As the hole injection barrier layer, an oxide semiconductor can be used. As an example, gallium oxide can be used. The film thickness of the hole injection barrier layer is preferably smaller than the film thickness of the selenium-based semiconductor. When the film thickness of the selenium-based semiconductor is small, dark current flows when a voltage is applied. However, in order to prevent dark current from flowing in CIGS, which is the above-mentioned chalcopyrite-based semiconductor, a layer (hole injection barrier layer) can be provided to suppress the flow of dark current. As the hole injection barrier layer, an oxide semiconductor can be used. As an example, gallium oxide can be used. The film thickness of the hole injection barrier layer is preferably smaller than the film thickness of the selenium-based semiconductor. When the film thickness of the selenium-based semiconductor is small, dark current flows when a voltage is applied. However, in order to prevent dark current from flowing in CIGS, which is the above-mentioned chalcopyrite-based semiconductor, a layer (hole injection barrier layer) can be provided to suppress the flow of dark current. As the hole injection barrier layer, an oxide semiconductor can be used. As an example, gallium oxide can be used. The film thickness of the hole injection barrier layer is preferably smaller than the film thickness of the selenium-based semiconductor.

[0115] FIG. 15(C) is a schematic diagram of a cross-sectional structure different from FIG. 15(B). In FIG. 15(C), there are transistor 111, electrode E connected to transistor 111 , selenium-based semiconductor Pix S , electrode E Se S VPDIn addition to the substrate Sub, there is also the hole injection barrier layer E OS This is illustrated. .

[0116] As explained above, as a sensor, a selenite semiconductor S Se By using this, the manufacturing cost is reduced. This reduces the number of pixels, improves the production yield, and reduces the variation in characteristics between pixels, resulting in high sensitivity. It can be made into a nsa.

[0117] This embodiment can be used in appropriate combination with other embodiments.

[0118] (Embodiment 6) In this embodiment, the cross-sectional structure of the elements constituting the imaging device will be described with reference to the drawings. In this embodiment, as an example, S is described using Figure 9(B) in Embodiment 4 above. This section describes the cross-sectional structure that constitutes a pixel using i-transistors and OS-transistors. .

[0119] Figure 11 is a cross-sectional view of the elements constituting the imaging device. The imaging device shown in Figure 11 is made of silicon A Si transistor 51 is provided on the substrate 40, and a Si transistor 51 is stacked on top of it. OS transistors 52 and 53 are provided on the silicon substrate 40. Includes a photodiode 60. Each transistor and photodiode 60 is It has electrical connections with various contact plugs 70 and wiring layers 71. The anode 61 of the ion 60 has electrical contact with the contact plug 70 via the low-resistance region 63. It has a connection.

[0120] The imaging device also includes a Si transistor 51 and a photodie provided on the silicon substrate 40. A layer 1100 having an oxide 60, and a layer provided in contact with the layer 1100 and having a wiring layer 71. 1200 and provided in contact with layer 1200, OS transistor 52 and OS transistor A layer 1300 having a ta 53, and a wiring layer 72 and a wiring layer 7 provided in contact with the layer 1300. It comprises a layer 1400 having 3.

[0121] In the example cross-sectional view in Figure 11, the Si transistor 51 is formed on the silicon substrate 40. The configuration has a light-receiving surface for the photodiode 60 on the side opposite to the surface that was formed. This allows for securing an optical path without being affected by various transistors, wiring, etc. Therefore, pixels with a high aperture ratio can be formed. The optical surface can also be the same as the surface on which the Si transistor 51 is formed.

[0122] Furthermore, in the above embodiment 4, the pixels are made using an OS transistor as described with reference to Figure 9(A). When constructing it, layer 1100 should be a layer having an OS transistor. The 1100 can be omitted, and the pixels may be constructed using only OS transistors.

[0123] Note that the silicon substrate 40 is not limited to a bulk silicon substrate, but may also be an SOI substrate. In addition, germanium, silicon germanium, and silicon carbide can be used instead of the silicon substrate 40. Gallium arsenide, aluminum gallium arsenide, indium phosphide, gallium nitride, organic semiconductors It is also possible to use substrates made from human body material.

[0124] Here, although the position is not limited, the Si transistor 51 and photodiode 60 are located A layer 1100 and a layer 130 having OS transistors 52 and 53 An insulating layer 80 is provided between it and 0.

[0125] Hydrogen in the insulating layer near the active region of the Si transistor 51 is in silicon dangly This has the effect of terminating the bonding bond and improving the reliability of the Si transistor 51. On the other hand, The active layer of the OS transistor 52 and OS transistor 53 provided in the layer is an oxidation Hydrogen in the insulating layer placed near the semiconductor layer generates carriers in the oxide semiconductor. Since this is one of the contributing factors, the reliability of OS transistors 52 and 53, etc. Transitions using silicon-based semiconductor materials can sometimes be a factor that causes a decrease. When stacking transistors using oxide semiconductors on top of a stud, water can form between them. It is preferable to provide an insulating layer 80 that has the function of preventing the diffusion of the element. In addition to improving the reliability of the Si transistor 51 by trapping hydrogen in the lower layer, The diffusion of hydrogen from the lower layer to the upper layer is suppressed, which affects the OS transistor 52 and the OS This also allows for simultaneous improvement of the reliability of transistors such as transistor 53.

[0126] Examples of insulating layer 80 include aluminum oxide, aluminum oxide nitride, gallium oxide, Gallium oxide nitride, yttrium oxide, yttrium oxide nitride, hafnium oxide, nitrogen oxide Hafnium oxide, yttria-stabilized zirconia (YSZ), etc., can be used.

[0127] Furthermore, in the cross-sectional view of Figure 11, the photodiode 60 provided in layer 1100 and layer 130 The transistors placed at 0 can be formed to overlap. In this way, the pixel cluster The density can be increased. In other words, the resolution of the imaging device can be increased.

[0128] This embodiment can be used in appropriate combination with other embodiments.

[0129] (Embodiment 7) In this embodiment, the cross-sectional structure of an example of a configuration in which a color filter or the like is added to the imaging device is described below. I will now explain by referring to the drawings.

[0130] Figure 12(A) shows a cross-section of an example of the imaging device shown in Figure 11 with the addition of a color filter, etc. This diagram shows the area occupied by three pixels of circuitry (circuits 91a, 91b, and 91c). An insulating layer 1500 is formed on the photodiode 60 formed in layer 1100. The insulating layer 1500 can be made of a silicon oxide film or the like, which has high light transmittance to visible light. It is possible to use a configuration in which a silicon nitride film is laminated as a passivation film. Alternatively, a dielectric film such as hafnium oxide may be laminated as an anti-reflective coating.

[0131] A light-shielding layer 1510 is formed on the insulating layer 1500. The light-shielding layer 1510 is the upper color It has the effect of preventing the mixing of colors of light passing through the filter. The light-shielding layer 1510 contains aluminum, A metal layer such as tungsten, or a dielectric film having the function of an anti-reflective coating, is attached to the metal layer. It can be configured in layers.

[0132] An organic resin layer 1520 is formed as a planarization film on the insulating layer 1500 and the light-shielding layer 1510. Then, on circuits 91a, 91b, and 91c, the color filter 153 0a, color filter 1530b, and color filter 1530c are formed in pairs. This is done. Color filter 1530a, color filter 1530b and color filter 1 By assigning colors such as R (red), G (green), and B (blue) to each of the 530c units, This allows you to obtain a color image.

[0133] Color filter 1530a, color filter 1530b, and color filter 1530c A microlens array 1540 is positioned above, and light passing through one lens directly below the color The light passes through the filter and is then directed onto the photodiode.

[0134] Furthermore, a support substrate 1600 is provided in contact with the layer 1400. The support substrate 1600 is, Semiconductor substrates such as silicon substrates, hard substrates such as glass substrates, metal substrates, and ceramic substrates. This can be used. Furthermore, an adhesive layer is formed between the layer 1400 and the support substrate 1600. An insulating layer or an organic resin layer may be formed.

[0135] In the configuration of the imaging device described above, color filter 1530a, color filter 1530b Alternatively, an optical conversion layer 1550 may be used instead of the color filter 1530c (Figure 12( (See B). By using the optical conversion layer 1550, images can be obtained in various wavelength ranges. It can be used as an imaging device.

[0136] For example, if a filter that blocks light with wavelengths below visible light is used in the optical conversion layer 1550, infrared light It can be used as a line imaging device. Furthermore, light with a wavelength below near-infrared is applied to the optical conversion layer 1550. By using a blocking filter, it can be made into a far-infrared imaging device. Also, the optical conversion layer 15 If a filter that blocks light with wavelengths greater than visible light is used in 50, it can be made into an ultraviolet imaging device. Cut.

[0137] Furthermore, if a scintillator is used in the optical conversion layer 1550, radiation can be used in medical X-ray imaging devices, etc. It can be used as an imaging device to obtain an image that visualizes the strength of the lines. When radiation enters a scintillator, a phenomenon called photoluminescence occurs. It is converted into light (fluorescence) such as visible light and ultraviolet light. Then, this light is converted into a photodiode 6 Image data is acquired by detecting a value of 0.

[0138] When a scintillator is irradiated with radiation such as X-rays or gamma rays, it absorbs that energy. It consists of a substance that emits visible light or ultraviolet light, or a material containing such a substance, for example, Gd2O 2S:Tb, Gd2O2S:Pr, Gd2O2S:Eu, BaFCl:Eu, NaI, C Materials such as sI, CaF2, BaF2, CeF3, LiF, LiI, ZnO, and those materials It is known to be dispersed in resins and ceramics.

[0139] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments. That is the case.

[0140] (Embodiment 8) This embodiment describes the OS transistor described in the above embodiment.

[0141] OS transistors reduce the impurity concentration in oxide semiconductors, making the oxide semiconductor intrinsic or By making it effectively intrinsic, the off-current can be reduced. Here, effectively intrinsic means The carrier density in the oxide semiconductor is 1 × 10⁻⁶ 17 / cm 3 Preferably less than 1 x 10 15 / cm 3 It is less than 1 × 10⁻¹⁰. 13 / cm3 Less than This refers to the process of adding hydrogen, nitrogen, carbon, silicon, and other components to oxide semiconductors. Metal elements become impurities. For example, hydrogen and nitrogen contribute to the formation of donor levels, This increases the rear density.

[0142] Transistors using intrinsic or substantially intrinsic oxide semiconductors have a low carrier density. Therefore, it is rare for the electrical characteristics to result in a negative threshold voltage. Transistors using oxide semiconductors have fewer carrier traps, resulting in improved electrical characteristics. This results in a transistor with low fluctuation and high reliability. Furthermore, transistors using this oxide semiconductor... The inverter allows for extremely low off-currents.

[0143] Furthermore, with an OS transistor that has a low off-current, the channel width is 1μF at room temperature (around 25°C). The normalized off-current per m is 1 × 10 -18 A or less, preferably 1 × 10 -21 A More preferably 1 × 10 -24 A or less, or 1 x 10 at 85°C -15 A or below, good Mashiku is 1 x 10 -18 A or less, more preferably 1 × 10 -21 It can be set to A or less. ru.

[0144] Off-current refers to the state when an n-channel transistor is not conducting. This refers to the current that flows between the source and drain. The threshold voltage of an n-channel transistor is For example, if the voltage is between 0V and 2V, the voltage applied between the gate and source is a negative voltage. In this case, the current flowing between the source and the drain can be called the off-current.

[0145] Furthermore, the oxide semiconductor used in the semiconductor layer of the OS transistor is at least indium. It is preferable to include (In) or zinc (Zn). It is particularly preferable to include In and Zn. In addition, it is preferable to have a stabilizer that strongly binds to oxygen. Yes. As stabilizers, gallium (Ga), tin (Sn), and zirconium (Zr) are used. It may contain at least one of hafnium (Hf) and aluminum (Al).

[0146] Also, other stabilizers include lanthanides such as lanthanum (La) and cerium ( Ce, praseodymium (Pr), neodymium (Nd), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), hol Mium (Ho), Erbium (Er), Thulium (Tm), Ytterbium (Yb), Lu It may contain one or more types of tecium (Lu).

[0147] Examples of oxide semiconductors used in the semiconductor layer of transistors include indium oxide and oxide Tin, zinc oxide, In-Zn oxides, Sn-Zn oxides, Al-Zn oxides, Zn -Mg oxides, Sn-Mg oxides, In-Mg oxides, In-Ga oxides, In -Ga-Zn oxides (also written as IGZO), In-Al-Zn oxides, In-S n-Zn oxides, Sn-Ga-Zn oxides, Al-Ga-Zn oxides, Sn-Al -Zn oxides, In-Hf-Zn oxides, In-Zr-Zn oxides, In-Ti- Zn oxides, In-Sc-Zn oxides, In-Y-Zn oxides, In-La-Zn In-Ce-Zn oxides, In-Pr-Zn oxides, In-Nd-Zn oxides Oxides, In-Sm-Zn oxides, In-Eu-Zn oxides, In-Gd-Zn acids In-Tb-Zn oxides, In-Dy-Zn oxides, In-Ho-Zn oxides Materials, In-Er-Zn oxides, In-Tm-Zn oxides, In-Yb-Zn oxides In-Lu-Zn ​​oxides, In-Sn-Ga-Zn oxides, In-Hf-Ga-Z n-based oxides, In-Al-Ga-Zn-based oxides, In-Sn-Al-Zn-based oxides, In Examples include Sn-Hf-Zn oxides and In-Hf-Al-Zn oxides.

[0148] For example, In:Ga:Zn=1:1:1, In:Ga:Zn=3:1:2, or In In-Ga-Zn oxides with an atomic ratio of :Ga:Zn=2:1:3 and acids with a similar composition. It would be good to use monsters.

[0149] When a large amount of hydrogen is present in the oxide semiconductor film that makes up the semiconductor layer, it bonds with the oxide semiconductor. As a result, some of the hydrogen becomes a donor, generating electrons, which act as carriers. Therefore, the transistor's threshold voltage shifts in the negative direction. After the conductive film is formed, a dehydration treatment (dehydrogenation treatment) is performed to remove hydrogen from the oxide semiconductor film. Alternatively, it is preferable to remove moisture and purify the product to minimize the amount of impurities it contains.

[0150] Furthermore, by dehydrating (dehydrogenating) the oxide semiconductor film, Oxygen levels may decrease. Therefore, dehydration treatment (dehydrogenation treatment) of oxide semiconductor films is necessary. The oxygen that has been reduced by (the process) is added to the oxide semiconductor, or oxygen is supplied to the oxide semiconductor. It is preferable to fill in the oxygen deficiencies in the conductive film.

[0151] Thus, oxide semiconductor films undergo dehydration treatment (dehydrogenation treatment) to remove hydrogen or water. It is removed and the oxygen deficiency is compensated for by oxygenation treatment, resulting in type i (true) or i It is possible to create an oxide semiconductor film that is very close to the type and is essentially type i (intrinsic). In essence, true means that there are very few donor-derived carriers in the oxide semiconductor film ( (close to the letter B), carrier density is 1 × 10 17 / cm 3 Below, 1 x 10 16 / cm 3 The following, 1 ×10 15 / cm 3 Below, 1 x 10 14 / cm 3 Below, 1 x 10 13 / cm 3 The following is To say that.

[0152] Thus, transistors having an oxide semiconductor film that is type i or substantially type i are extremely This enables the achievement of excellent off-current characteristics.

[0153] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments. That is the case.

[0154] (Embodiment 9) In this embodiment, the imaging device described in the above embodiment is used as a monitoring device (also called a monitoring system). This section explains how to use it for (u).

[0155] Figure 13 is a block diagram showing an example of the configuration of the monitoring device according to this embodiment. The monitoring device is a turtle It has a 200, a storage device 211, a display device 212, and an alarm device 213. Camera 2 00 has an imaging device 220. Images captured by the camera 200 are stored in the storage device 211. The data is recorded and displayed on the display device 212. Additionally, the alarm device 213 is activated when the camera 200 moves. If a threat is detected, an alert will be sent to the administrator.

[0156] The imaging device 220 generates a trigger signal when the camera 200 detects differential data. If no trigger signal is generated, analog processing will continue; if a trigger signal is generated, digital processing will continue. This involves barrel processing. Therefore, it does not require continuous digital processing that consumes a huge amount of power. Therefore, power consumption can be reduced.

[0157] For example, state 1 is a state where there are definitely no intruders in the monitored area, and state 2 is the current state. Let's assume that there is no intruder when the imaging device 220 is operating in the first mode. Since the first and second imaging data are identical, the difference data is zero. Therefore, the difference data read from each pixel by the analog processing circuit is summed by the absolute difference value. The result of the calculation is zero, and no trigger signal is generated. On the other hand, if there is an intruder, the first Since the initial imaging data and the second imaging data are different, the difference data is finite. Therefore, The analog processing circuit performs a difference absolute value sum operation on the difference data read from each pixel. The result is finite, and a trigger signal is generated. Upon generation of the trigger signal, the imaging device 220 The system transitions to mode 2, and the third imaging data is converted into digital data by the digital processing circuit. Detailed analysis of the captured images is performed using digital processing on a PC or similar device. As a result, Detailed information about the intruder can be obtained.

[0158] Therefore, during periods when no motion is detected in the image, the imaging device 220 does not perform digital processing. As a result, power consumption in the camera 200 can be reduced. In addition, the memory device 211 is This allows for saving storage capacity in the storage device 211 by utilizing image data from periods when no motion is detected. Therefore, longer recording times become possible.

[0159] Furthermore, the alarm device 213 only needs to issue an alarm to the surrounding area when a trigger signal is generated. Alternatively, the system may determine whether or not to issue an alarm based on verification in the authentication system. .

[0160] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments. That is the case.

[0161] (Embodiment 10) This embodiment describes an example of an electronic device using an imaging device according to one aspect of the present invention. do.

[0162] An electronic device using an imaging device according to one aspect of the present invention includes a display device such as a television or monitor. Lighting fixtures, desktop or notebook personal computers, word processors It is stored on recording media such as DVDs (Digital Versatile Discs). Image playback devices that play still images or videos, portable CD players, radios, tape recorders Coda, headphone stereo, stereo, navigation system, desk clock, wall clock Totals, cordless phone handsets, transceivers, mobile phones, car phones, portable game consoles, tablets Let-type terminals, large game machines such as pachinko machines, calculators, personal digital assistants, electronic organizers, and e-books. Registered terminals, electronic translators, voice input devices, video cameras, digital still cameras, electric shading devices. High-frequency heating devices such as microwave ovens, electric rice cookers, electric washing machines, electric vacuum cleaners, water heaters, and electric fans. Air conditioning equipment such as fans, hair dryers, air conditioners, humidifiers, dehumidifiers, and dishwashers. Dish dryer, clothes dryer, futon dryer, electric refrigerator, electric freezer, electric refrigerator-freezer, D NA storage freezers, flashlights, tools such as chainsaws, smoke detectors, medical equipment such as dialysis machines fax machines, printers, multifunction printers, automated teller machines (ATMs), automatic Examples include vending machines. Furthermore, guide lights, traffic lights, conveyor belts, elevators, etc. For calators, industrial robots, power storage systems, power leveling, and smart grids. Examples include industrial equipment such as energy storage devices. Also, fuel-powered engines and non-aqueous secondary batteries. Mobile devices propelled by electric motors using electricity from the source are also included in the category of electronic equipment. As such, the above-mentioned mobile devices include, for example, electric vehicles (EVs), and vehicles that combine internal combustion engines and electric motors. Hybrid electric vehicles (HEVs), plug-in hybrid electric vehicles (PHEVs), and these tires Tracked vehicles with wheels replaced by tracks, motorized bicycles including electric assist bicycles, and motorcycles Cars, electric wheelchairs, golf carts, small or large vessels, submarines, helicopters, aircraft, Examples include rockets, artificial satellites, space probes and planetary probes, and spacecraft.

[0163] Figure 14(A) shows a video camera, consisting of a housing 941, a housing 942, a display unit 943, and operation keys. It has 944, lens 945, connecting part 946, etc. Operation key 944 and lens 945 The housing 941 is located on the casing, and the display unit 943 is located on the casing 942. Body 941 and housing 942 are connected by a connecting part 946, and housing 941 and housing 94 The angle between 2 can be changed by the connecting part 946. The image on the display unit 943 is The configuration is such that the connection part 946 switches according to the angle between housing 941 and housing 942. It is also acceptable to provide an imaging device according to one embodiment of the present invention at the focal point of lens 945. can.

[0164] Figure 14(B) is a mobile phone, and the casing 951 contains a display unit 952, a microphone 957, and a speaker. It has -954, camera 959, input / output terminal 956, operation buttons 955, etc. Camera An imaging device according to one aspect of the present invention can be used for 959.

[0165] Figure 14(C) shows a digital camera, consisting of a housing 921, a shutter button 922, and a microphone 9 23. It has a light-emitting part 927, a lens 925, etc. The light-emitting part is located at the focal point of the lens 925. An imaging device of one aspect can be provided.

[0166] Figure 14(D) shows a portable game console, consisting of a casing 901, casing 902, display unit 903, and display unit. 904, Microphone 905, Speaker 906, Control keys 907, Stylus 908, Camera It has 909, etc. Note that the portable game console shown in Figure 14(A) has two display units 903 It has a display unit 904, but the number of display units that a portable game console has is not limited to this. It is not possible. Camera 909 can use an imaging device according to one aspect of the present invention.

[0167] Figure 14(E) shows a wristwatch-type information terminal, comprising a housing 931, a display unit 932, and a wristband 9 33. It has a camera 939, etc. The display unit 932 may be a touch panel. An imaging device according to one embodiment of the present invention can be used in Ra939.

[0168] Figure 14(F) shows a portable data terminal, which includes a housing 911, a display unit 912, a camera 919, etc. The display unit 912 has a touch panel function that allows for the input and output of information. Camera 919 can use an imaging device according to one embodiment of the present invention.

[0169] Furthermore, the present invention is not limited to the electronic devices described above, as long as it includes an imaging device according to one embodiment of the present invention. Needless to say, that's not possible.

[0170] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments. That is the case. [Explanation of symbols]

[0171] 40 silicon substrates 51 Si transistors 52 OS transistors 53 OS Transistors 60 Photodiodes 61 Anodes 63 Low resistance region 70 Contact Plugs 71 Wiring layer 72 wiring layer 73 Wiring layer 80 Insulating layer 91a Circuit 91b circuit 91c circuit 100 pixels 100A pixels 100B pixels 100C pixels 101 Analog Processing Circuit 102 A / D conversion circuit 103-column driver 104-line driver 105 pixel section 111 transistors 112 transistors 113 Transistors 114 transistors 115 transistors 121 capacity 122 capacity 123 Photodiode 123A sensor 136 transistors 137 transistors 138 transistors 139 transistors 140 transistors 141 Transistors 142 transistors 143 transistors 144 transistors 145 transistors 146 transistors 147 transistors 148 transistors 149 capacity FD1 Charge-holding node FD2 node SUB Subtraction Circuit ABS Absolute Value Circuit SUM Adder Circuit 200 Cameras 211 Storage device 212 Display device 213 Alarm device 220 Imaging device 901 cabinet 902 cabinet 903 Display section 904 Display section 905 Microphone 906 Speakers 907 Operation Keys 908 Stylus 909 Camera 911 cabinet 912 Display section 919 Camera 921 cabinet 922 Shutter button 923 Mike 925 lens 927 Light-emitting part 931 cabinet 932 Display section 933 Wristband 939 Camera 941 cabinet 942 cabinets 943 Display section 944 Operation Keys 945 lens 946 Connection part 951 cabinet 952 Display section 954 Speakers 955 Buttons 956 Input / output terminal 957 Mike 959 Camera 1100 layers 1200 layers 1300 layers 1400 layers 1500 Insulating layer 1510 Light blocking layer 1520 Organic resin layer 1530a color filter 1530b color filter 1530c color filter 1540 Microlens Array 1550 Optical conversion layer 1600 Support board

Claims

1. A pixel having the function of acquiring a first image data which is analog data, and acquiring a second image data which is analog data after acquiring the first image data, An analog processing circuit having a function to compare a current value corresponding to the difference between the first image data and the second image data acquired at the pixel with a reference current value, and a function to generate a trigger signal according to the result of the comparison, The system includes an A / D conversion circuit that converts third image data, which is analog data acquired at the pixel, into digital data after the generation of the trigger signal. Before the generation of the trigger signal, the second image data is not converted to digital data. The aforementioned pixel has a transistor, The transistor is an image sensor having an oxide semiconductor in the channel formation region.

2. A pixel having the function of acquiring a first image data which is analog data, and acquiring a second image data which is analog data after acquiring the first image data, An analog processing circuit having a function to compare a current value corresponding to the difference between the first image data and the second image data acquired at the pixel with a reference current value, and a function to generate a trigger signal according to the result of the comparison, The system includes an A / D conversion circuit that converts third image data, which is analog data acquired at the pixel, into digital data after the generation of the trigger signal. Before the generation of the trigger signal, the second image data is not converted to digital data. The aforementioned pixel has a transistor, The transistor has an oxide semiconductor in the channel formation region. The aforementioned oxide semiconductor is indium oxide, in the image sensor.

3. In claim 1 or claim 2, The result of the comparison is the difference between the first image data and the second image data, as determined by the image sensor.

4. A portable information terminal including an image sensor according to any one of claims 1 to 3.

Images