Page remapping and rotation increase the randomization entropy of address space arrangement.

Abstract

Various embodiments include methods and devices for generating a memory map configured to map virtual addresses of pages to physical addresses, where pages of the same size are grouped into regions. Embodiments may include adding a first entry for a first additional page to a first region of the memory map, shifting the virtual address of the first region by a sub-page granularity shift amount to correspond to a shift of the virtual address of the first region allocated to code, mapping the shifted virtual address of the first entry for the first additional page to a physical address mapped to a first lowest shifted virtual address page of the first region, and shifting the virtual address of the first region allocated to code by a sub-page granularity shift amount, where the virtual address of the first region allocated to code is partially shifted into the first entry for the first additional page.

Description

Technical Field

[0001] Related Applications This application claims the benefit of priority of U.S. Non-Provisional Application No. 17 / 201,247, filed Mar. 15, 2021, the entire content of which is incorporated herein by reference.

Background Art

[0002] Code reuse attacks are increasingly becoming a more common attack vector on systems with baseline countermeasures implemented, such as W^X. Code reuse attacks reuse existing code in a binary for the attacker's purposes. One form of code reuse is when the attacker can call a function of their choice. For example, the attacker may use an overwrite vulnerability to change a pointer in a function pointer table or jump table to a different function that exists in the binary but not in the table originally. One common characteristic of all code reuse attacks is that the attacker must know the address of the binary's code or function in advance for the binary's code or function to be reusable.

[0003] One way to defend against such attacks is by address space layout randomization (ASLR) of the binary's code segment. In this scheme, the loader will load the binary's code segment at a random offset in the virtual address space of the process on every load. As a result, the code of interest to the attacker is now at a random address on each load. A measure of the effectiveness of ASLR is sometimes referred to as the entropy of ASLR. Various system factors can limit the entropy of ASLR.

Summary of the Invention

Means for Solving the Problems

[0004] Various embodiments of the disclosure may include apparatus and methods for generating a memory map configured to map virtual addresses of pages to physical addresses, where pages of the same size are grouped into regions. Various embodiments may include the steps of adding a first entry for a first additional page to a first region of the memory map; shifting the virtual address of the first region by a subpage granularity shift to accommodate the shift of the virtual address of the first region allocated to the code; mapping the shifted virtual address of the first entry for the first additional page to a physical address mapped to the first lowest shifted virtually addressed page of the first region; and shifting the virtual address of the first region allocated to the code by a subpage granularity shift, such that the virtual address of the first region allocated to the code is partially shifted to the first entry for the first additional page.

[0005] Some embodiments may include the steps of adding a second entry for a second append page to a second region of a memory map, wherein the second region is virtually addressed higher than the first region; shifting the virtual address of the second region by a subpage granularity shift to accommodate a shift in the virtual address of the second region allocated to the code; mapping the shifted virtual address of the second entry for the second append page to a physical address mapped to the second lowest shifted virtual address page of the second region; and shifting the virtual address of the second region allocated to the code by a subpage granularity shift, wherein the virtual address of the second region allocated to the code is partially shifted to the second entry for the second append page.

[0006] Some embodiments may include the steps of shifting the virtual address of a second region to correspond to a first entry added to a first region of a memory map, and shifting the virtual address of the second region to align the pages of the second region, including a second additional page, with the page boundaries of the pages of the second region.

[0007] Some embodiments may include the step of rotating the code for a shifted virtual address in a first region allocated to the code in physical memory.

[0008] In some embodiments, the step of rotating the code in physical memory for a shifted virtual address in a first region allocated to the code may include the steps of loading the code to a physical address mapped from a first lowest virtual address page for the shifted virtual address in the first region allocated to the code, and loading the code to a physical address mapped from a first additional page for the shifted virtual address in the first region allocated to the code, wherein the physical address mapped from the first additional page for the shifted virtual address in the first region allocated to the code is a lower physical address than the physical address mapped from the first lowest virtual address page for the shifted virtual address in the first region allocated to the code.

[0009] Some embodiments may include the step of adjusting the pointer for the binary code containing the code by the amount of the shift in the virtual address of the second area allocated to the code, in order to correspond to the shift in the virtual address of the second area allocated to the code by the amount of the shift in the granularity of the subpage.

[0010] Some embodiments may include the steps of generating program counter relative code and generating binary code from program counter relative code.

[0011] Further embodiments include a computing device having a processor configured to perform any of the operations summarized above. Further embodiments include a computing device having means for performing any of the functions summarized above. Further embodiments include a non-temporary processor-readable medium storing processor-executable instructions configured to cause the processor and other components of the computing device to perform any of the operations summarized above.

[0012] The accompanying drawings incorporated herein and constituting part of this specification illustrate exemplary embodiments among various embodiments and, together with the above general description and the modes for carrying out the invention below, are useful in illustrating the features of the claims. [Brief explanation of the drawing]

[0013] [Figure 1] This is a component block diagram illustrating an exemplary computing device suitable for implementing various embodiments. [Figure 2] This is a component block diagram illustrating an exemplary memory system suitable for implementing various embodiments. [Figure 3A] This block diagram shows an example of memory mapping and rotation for subpage granularity shifts, suitable for implementing various embodiments. [Figure 3B] This block diagram shows an example of memory mapping and rotation for subpage granularity shifts, suitable for implementing various embodiments. [Figure 3C] This block diagram shows an example of memory mapping and rotation for subpage granularity shifts, suitable for implementing various embodiments. [Figure 3D] This block diagram shows an example of memory mapping and rotation for subpage granularity shifts, suitable for implementing various embodiments. [Figure 4A]This table shows an example of memory mapping and rotation for subpage granularity shifts, suitable for implementing various embodiments. [Figure 4B] This table shows an example of memory mapping and rotation for subpage granularity shifts, suitable for implementing various embodiments. [Figure 5] This component block and flowchart demonstrate an example of memory mapping and rotation for subpage granularity shifts, suitable for implementing various embodiments. [Figure 6] This is a process flow diagram illustrating a method for memory mapping of subpage granularity shifts according to one embodiment. [Figure 7] This is a process flow diagram illustrating a method for memory mapping of subpage granularity shifts according to one embodiment. [Figure 8] This is a process flow diagram illustrating a method for memory rotation according to one embodiment. [Figure 9] This is a process flow diagram illustrating a method for memory rotation according to one embodiment. [Figure 10] This is a component block diagram illustrating an exemplary mobile computing device suitable for implementing various embodiments. [Figure 11] This is a component block diagram illustrating an exemplary mobile computing device suitable for implementing various embodiments. [Figure 12] This is a component block diagram showing an exemplary server suitable for implementing various embodiments. [Modes for carrying out the invention]

[0014] Various embodiments will be described in detail with reference to the accompanying drawings. Where possible, the same reference numerals will be used throughout the drawings to refer to the same or similar parts. References made to specific examples and implementations are illustrative and not intended to limit the scope of the claims.

[0015] Various embodiments include a method for increasing the address space layout randomization (ASLR) entropy by page remapping and rotation, and a computing device implementing such a method. Various embodiments may include generating a page map of a sub-page granularity shift from a page map using a shift amount of the sub-page granularity. In some embodiments, a page virtual address range may be shifted to correspond to a shift amount of the sub-page granularity and mapped to a physical address of the page map. In some embodiments, a page virtual address range of a region of a page may be shifted to align with a page boundary of the page size of that region. In some embodiments, additional page map entries may be added for each region of a page of the same size. Some embodiments may include rotating code, data, and / or information stored in physical memory based on the mapping of virtual addresses to physical addresses in a page map of a sub-page shift granularity. In some embodiments, the virtual address ranges for the first page entry and the additional page entries of a region may be mapped to the same range of physical addresses.

[0016] The terms "computing device" and "mobile computing device" are used interchangeably herein to refer to any one or all of cellular phones, smartphones, personal or mobile multimedia players, personal digital assistants (PDAs), laptop computers, tablet computers, convertible laptop / tablet (2-in-1 computers), smartbooks, ultrabooks, netbooks, palmtop computers, wireless email receivers, multimedia Internet-enabled cellular phones, mobile game consoles, wireless game controllers, and similar personal electronic devices that include memory and programmable processors. The term "computing device" may further refer to stationary computing devices including personal computers, desktop computers, all-in-one computers, workstations, supercomputers, mainframe computers, embedded computers (such as in vehicles and other larger systems), servers, multimedia computers, and game consoles.

[0017] For ease and clarity of explanation, various embodiments are described with respect to code, such as processor-executable instructions, but may equally apply to any data, such as code, program data, or other information stored in memory. The terms "code", "data", and "information" are used interchangeably herein and are not intended to limit the scope of the claims and description to the types of code, data, information used as examples in describing various embodiments.

[0018] ASLR is a technique used to defend against malicious attacks such as code reuse attacks. The measure of ASLR effectiveness is sometimes called ASLR entropy. One way to interpret this measure is that it represents the success rate of an attacker if they make multiple code reuse attack attempts assuming a specific address. This could be multiple attempts on a specific device of interest, or a broader attack on an entire group of devices. The higher the ASLR entropy, the more attempts are needed for an attack to succeed, or the lower the success rate of the attack.

[0019] The greater the number of locations where a loader can legally place the start of code, the more difficult it becomes for an attacker to exploit. The entropy achievable in ASLR is typically limited by the amount of virtual address (VA) space available to the loader. Available entropy is also closely related to how virtual memory is managed through the memory management unit (MMU) and operating system (OS), such as by using a limited-sized translation lookaside buffer (TLB) or page table, which can impose significant constraints. Some systems support multiple page sizes and have a statically determined memory map between virtual and physical addresses. This introduces alignment constraints that can further reduce available entropy.

[0020] Various embodiments provide ASLR schemes that can increase entropy by overcoming the limitations on entropy imposed by the above memory, mapping, and alignment constraints. The ASLR scheme may include implementing subpage granularity shifts of virtual addresses in virtual memory, corresponding code rotations in physical memory, and mapping the changed virtual memory addresses to code addresses in physical memory.

[0021] A shift in subpage granularity may be a shift in virtual addresses in a memory map configured to map virtual addresses of code in virtual memory to physical addresses in physical memory. The term “memory map” is used herein to refer to data or memory structures configured to map virtual addresses of virtual memory to physical addresses in physical memory. For example, a memory map may include a TLB, a page table, an address array, a linked list, and the like. In some embodiments, a memory map may map virtual addresses of pages in virtual memory of any number and combinations of page sizes to physical addresses in physical memory representing the corresponding portions of physical memory.

[0022] A subpage granularity shift may result in a shift of code virtual addresses by any amount of virtual addresses that are not multiples of the page size for virtual memory. For example, a subpage granularity shift may result in a shift of virtual addresses in virtual memory by any amount of virtual addresses that are not multiples of the minimum page size for virtual memory. Therefore, virtual addresses shifted to the subpage granularity of code may not align with the virtual address boundaries of pages in virtual memory. A subpage granularity shift of code virtual addresses may result in virtual addresses shifted across regions of the memory map. The term “region” is used herein to refer to the mapping of virtual addresses of pages of the same size in a memory map. New entries for mapping the virtual addresses of additional pages may be added to a memory map, such as a region, to accommodate code virtual addresses that are shifted across a region. The new entries may map the virtual addresses of additional pages to physical addresses to which virtual addresses of pages of the same size are mapped. For example, the new entries may map the virtual addresses of additional pages to physical addresses to which virtual addresses of first pages in the same region are mapped.

[0023] A memory map may have multiple regions. Different regions may map virtual addresses of pages of different sizes to physical addresses. A subpage granularity shift, including additional entries into a first region, may cause the virtual addresses of pages in the second region to be unaligned with the virtual address page boundaries of pages of the second region's size. A virtual address hole may be introduced into the memory map to align the virtual addresses of pages in the second region with the virtual addresses of the page boundaries of the size pages. A virtual address hole may be introduced by shifting the virtual addresses of pages in the second region by an amount equal to the amount of the additional virtual address shift to the subpage granularity shift of the virtual address, the amount of the virtual address, and any number and combination of additional entries that may cause the virtual addresses of pages in the second region to be aligned with the virtual addresses of the page boundaries of the size pages.

[0024] In some embodiments, a subpage granularity shift may leave memory-mapped entries for the page's virtual addresses uncoded, and such entries may be omitted from the memory map. In some embodiments, virtual address holes may result in discontinuous virtual addresses between regions, leaving some virtual addresses between regions unmapped. In either or both cases, a subpage granularity shift may require one entry for each region added to the memory map. Therefore, the increase in the memory map may be small compared to other ASLR schemes that may require the addition of more memory-mapped entries.

[0025] The code for the virtual address of an additional entry in the memory map, added in response to a subpage granularity shift, may be rotated in physical memory. As described above, a subpage granularity shift may cause the shifted virtual address of the code to not align with the virtual address of the page boundary. Therefore, a subpage granularity shift may cause the mapping of the virtual address of the code on the page to the physical address to be shifted by the same amount, leaving the corresponding empty portion of the page's virtual and physical addresses untouched. A subpage granularity shift may also cause the mapping of the additional entry to a region in memory, the mapping from the virtual address of the code on the page to the physical address of the additional entry, to not align with the corresponding virtual address of the page boundary. The virtual address of the page may be mapped to the same physical address, but the virtual address of the code on the page may be mapped to a different portion of the physical address. The virtual address of the code in the additional entry may be mapped to fill the empty portion of the physical address created by the subpage granularity shift. Therefore, when code is loaded, the code may be rotated in physical memory, moving the code for additional entries into the memory map from one end of the physical address range to the other end of the physical address range, corresponding to the region in the memory map.

[0026] In some embodiments, the linker may use a memory map as input and adjust the code pointer accordingly. The code pointer may be adjusted to point to a virtual address by the amount by which the virtual address is shifted in the memory map. In some embodiments, the code pointer may be adjusted by the amount of the virtual address shift at the subpage granularity. In some embodiments, the code pointer may be adjusted by the amount of the virtual address shift at the subpage granularity, and the amount of the virtual address for any number and combination of virtual address holes. Adjusting the code pointer may allow the loader to have flexibility for any code rotation in physical memory without having to consider code changes or page alignment.

[0027] Figure 1 shows a system including a computing device 100 suitable for use with various embodiments. The computing device 100 may include a SoC 102 having a central processing unit 104, memory 106, a communication interface 108, a memory interface 110, a peripheral device interface 120, and a processing device 124. The computing device 100 may further include a communication component 112 such as a wired or wireless modem, memory 114, an antenna 116 for establishing a wireless communication link, and / or peripheral devices 122. The processor 124 may include any of the various processing devices, for example, several processor cores.

[0028] The term “system on a chip” or “SoC” is used herein to refer to a set of interconnected electronic circuits, including, but not limited to, processing devices, memory, and communication interfaces. Processing devices may include various different types of processors and / or processor cores, such as general-purpose processors, central processing units (CPUs)104, digital signal processors (DSPs), graphics processing units (GPUs), accelerated processing units (APUs), secure processing units (SPUs), intellectual property units (IPUs), subsystem processors, auxiliary processors, peripheral device processors, single-core processors, multi-core processors, controllers, and / or microcontrollers, which are specific components of computing devices. Processing devices may further incorporate other hardware and combinations of hardware, such as field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), other programmable logic devices, discrete gate logic, transistor logic, performance monitoring hardware, watchdog hardware, and / or time references. Integrated circuits may be configured such that the components of the integrated circuit reside on a single semiconductor material such as silicon.

[0029] An SoC 102 may include one or more CPUs 104 and processors 124. A computing device 100 may include two or more SoCs 102, thereby increasing the number of CPUs 104, processors 124, and processor cores. A computing device 100 may also include CPUs 104 and processors 124 that are not associated with an SoC 102. Each individual CPU 104 and processor 124 may be a multi-core processor. Each CPU 104 and processor 124 may be configured for a specific purpose, which may be the same as or different from the other CPUs 104 and processors 124 in the computing device 100. One or more CPUs 104, processors 124, and processor cores with the same or different configurations may be grouped together. A group of CPUs 104, processors 124, or processor cores may be called a multiprocessor cluster.

[0030] The memory 106 of the SoC 102 may be volatile or non-volatile memory configured to store data and processor-executable code for access by the CPU 104, processor 124, or other components of the SoC 102. The computing device 100 and / or SoC 102 may include one or more memories 106 configured for various purposes. One or more memories 106 may include volatile memory such as random access memory (RAM) or main memory, or cache memory. These memories 106 may be configured to temporarily hold data received from data sensors or subsystems, data and / or processor-executable code instructions requested from non-volatile memory and loaded from non-volatile memory into memory 106 in anticipation of future access based on various factors, and / or a limited amount of intermediate processing data and / or processor-executable code instructions generated by the CPU 104 and / or processor 124 and temporarily stored for quick future access without being stored in non-volatile memory. In some embodiments, any number and combination of memories 106 may include one-time programmable or read-only memory.

[0031] Memory 106 may be configured to at least temporarily store data and processor-executable code that are loaded into memory 106 from another memory device, such as another memory 106 or memory 114, for access by one or more of the CPU 104, processor 124, or other components of the SoC 102. The data or processor-executable code loaded into memory 106 may be loaded in response to the execution of a function by the CPU 104, processor 124, or other components of the SoC 102. Loading data or processor-executable code into memory 106 in response to the execution of a function may result from a memory access request to memory 106 that fails or "misses" because the requested data or processor-executable code is not in memory 106. In response to the miss, a memory access request to another memory 106 or memory 114 may be made to load the requested data or processor-executable code into memory 106 from that other memory 106 or memory 114. Loading data or processor-executable code into memory 106 in response to the execution of a function may result from a memory access request to another memory 106 or memory 114, and the data or processor-executable code may be loaded into memory 106 for later access.

[0032] The memory interface 110 and memory 114 may operate simultaneously to enable the computing device 100 to store data and processor executable code in volatile and / or non-volatile storage media and to retrieve data and processor executable code from volatile and / or non-volatile storage media. Memory 114 may be configured much like an embodiment of memory 106, in which memory 114 may store data or processor executable code for access by one or more of the CPU 104, processor 124, or other components of the SoC 102. In some embodiments, non-volatile memory 114 may retain information after the computing device 100 is powered off. When power is restored and the computing device 100 restarts, the information stored on memory 114 may be available to the computing device 100. In some embodiments, volatile memory 114 may not retain information after the computing device 100 is powered off. The memory interface 110 may control access to the memory 114 and allow the CPU 104, processor 124, or other components of the SoC 102 to read data from and write data to the memory 114.

[0033] Some or all of the components of computing device 100 and / or SoC 102 may be arranged and / or combined in different ways, while still performing the functions of various embodiments. Computing device 100 is not limited to one of each of the components, and multiple instances of each component may be included in various configurations of computing device 100.

[0034] Figure 2 shows the components of a memory system 200 in a computing device (for example, computing device 100 in Figure 1) suitable for implementing several embodiments. Referring to Figures 1 and 2, the memory system 200 may include components configured to implement virtual memory 202 (for example, on SoC 102, CPU 104, processor 124), a memory map 204 (for example, on SoC 102, CPU 104, processor 124), a memory management unit (MMU) 206 (for example, on SoC 102, CPU 104, processor 124), and physical memory 208 (for example, memory 106).

[0035] The memory management unit 206 may be configured to manage access to physical memory 208 by the processor (e.g., CPU 104, processor 124) to implement memory access requests, such as read and / or write memory access requests. The processor may implement virtual memory 202 and execute code based on the virtual address of virtual memory 202. The processor may issue memory access requests to physical memory 208 based on the virtual address of virtual memory 202. To implement a memory access request, physical memory 208 may request its physical address to identify the location of physical memory 208 where the memory access request is being made. Virtual addresses and physical addresses may not be the same, and a virtual address may need to be translated to a physical address for physical memory 208 to implement a memory access request. Furthermore, the processor may request any return from physical memory 208 to implement a memory access request that indicates a virtual memory address. The physical address used by physical memory 208 may need to be translated to a virtual address for the processor to accept the return of the memory access request.

[0036] The memory management unit 206 may generate and / or maintain a memory map 204 configured to map virtual addresses of virtual memory 202 to physical addresses of physical memory 206, as further described herein. The memory management unit 206 may use the memory map 204 to translate between virtual addresses and physical addresses in order to enable the physical memory 208 to perform memory access requests and the processor to accept returns of memory access requests.

[0037] In addition, the memory management unit 206 may be configured to implement an ASLR scheme that may increase ASLR entropy through page remapping and rotation, as further described herein. In some embodiments, the memory management unit 206 may shift the virtual addresses in the memory map 204 by the amount of the subpage granularity shift, and may add and / or omit entries in the memory map 204 that map virtual addresses to physical addresses. In some embodiments, the memory management unit 206 may shift the virtual addresses in the memory map 204 to align the virtual addresses of pages to page boundaries for any number and combination of page sizes.

[0038] Figures 3A to 3D show examples of memory mapping and rotation of subpage granularity shifts suitable for implementing various embodiments. Referring to Figures 1 to 3D, memory mapping and rotation of subpage granularity shifts may be implemented on a computing device (e.g., computing device 100 in Figure 1) via a memory system (e.g., memory system 200) for virtual memory 300 (e.g., on SoC 102, CPU 104, processor 124 in Figure 1, and virtual memory 202 in Figure 2) and physical memory 320 (e.g., memory 106 in Figure 1, physical memory 208 in Figure 2).

[0039] Virtual memory 300 may include pages 302a, 302b, 302c, 304a, and 304b of any number and combination of page sizes. The virtual addresses of pages 302a, 302b, 302c, 304a, and 304b may be assigned to codes 306 and 308 of any number and combination of code sizes.

[0040] Physical memory 320 may include the range of physical addresses 326a, 326b, and 328a, which are mapped to pages 302a, 302b, 302c, 304a, and 304b of virtual memory 300. Codes 306 and 308, to which virtual addresses are assigned, may be loaded into and stored in physical memory 320 within the range of physical addresses 326a, 326b, and 328a.

[0041] Figure 3A shows an exemplary mapping of virtual memory 300 and physical memory 320 before implementing memory mapping and rotation for subpage granularity shifts. Virtual addresses assigned to codes 306 and 308 may be located in pages 302a, 302b, and 304a of virtual memory 300. For example, the virtual address assigned to code 306 may be located in pages 302a and 302b. The virtual address assigned to code 308 may be located in page 304a. Any portion or combination of virtual addresses in pages 302a, 302b, and 304a may be assigned to codes 306 and 308.

[0042] The virtual addresses of pages 302a, 302b, and 304a may be mapped to physical addresses within the range of physical addresses 326a, 326b, and 328a. The codes 306 and 308 to which the virtual addresses are assigned may be loaded into physical memory 320 and stored at physical addresses within the range of physical addresses 326a, 326b, and 328a to which the virtual addresses are mapped. For example, the virtual address of page 302a may be mapped to physical addresses within the range of physical address 326a. The portion of code 306 to which the virtual address of page 302a may be assigned may be loaded into physical addresses within the range of physical address 326a and stored. The virtual address of page 302b may be mapped to physical addresses within the range of physical address 326b. The portion of code 306 to which the virtual address of page 302b may be assigned may be loaded into physical addresses within the range of physical address 326b and stored. The virtual address of page 304a may be mapped to a physical address within the range of physical address 328a. The code 308 to which the virtual address of page 304a may be assigned may be loaded and stored in a physical address within the range of physical address 328a. Codes 306 and 308 may be loaded and stored in any part or combination of physical addresses within the range of physical addresses 326a, 326b, and 328a.

[0043] Figure 3B shows an example of virtual memory 300 implementing memory mapping and rotation of subpage granularity shifts. A subpage granularity shift may shift the virtual addresses allocated to codes 306 and 308 by an amount of subpage granularity shift of virtual addresses that is not a multiple of the page size for virtual memory 300. For example, a subpage granularity shift may shift virtual addresses in virtual memory 300 by any amount of virtual addresses that is not a multiple of the minimum page size for virtual memory. For example, the amount of virtual addresses shifted by a subpage granularity shift may be greater than or less than a page. Therefore, virtual addresses shifted to the granularity of subpages allocated to codes 306 and 308 may not align with the virtual address boundaries for pages 302a, 302b, and 304a in virtual memory 300.

[0044] Subpage granularity shifts may shift the virtual addresses assigned to codes 306 and 308 across the boundaries of pages 302a, 302b, and 304a. For the lowest address region of a page, adjacent pages of the same size as the pages in the region may be assigned to correspond to the virtual addresses shifted across page boundaries. For example, for a region containing pages 302a and 302b, adjacent page 302c of the same size as pages 302a and 302b may be assigned to correspond to the virtual addresses shifted across the boundaries of pages 302a and 302b. In some embodiments where the virtual address assigned to code 306 is shifted completely across any of pages 302a, 302b, or 302c, the virtual addresses of pages 302a, 302b, and 302c may be shifted accordingly while maintaining alignment with page boundaries. In some embodiments, the virtual addresses of pages 302a, 302b, and 302c may be shifted by an amount equal to the nearest multiple of the page size, which is smaller than the amount of shift in the granularity of the subpages of the virtual addresses. Page 302c may be allocated such that the shifted virtual addresses assigned to code 306 may be encompassed by pages 302a, 302b, and 302c. In some embodiments, page 302c may be allocated before assigning code 306 to the virtual addresses allocated to page 302c, and may include an empty address space 310a.

[0045] The upper address region of a page may contain pages of different sizes from the lower address region. Similarly, for the lower address region of a page, the upper address region of the page may allocate adjacent pages of the same size as the pages in the region to correspond to virtual addresses shifted across page boundaries. For example, for a region containing page 304a, an adjacent page 304b of the same size as page 304a may be allocated to correspond to virtual addresses shifted across the boundary of page 304a. In some embodiments, page 304b may be allocated before assigning code 308 to the virtual address of page 304b, and may contain an empty address space 312a.

[0046] In some embodiments, the shift of the virtual address of a page in the lower address region may also be applied to the virtual address of a page in the upper address region. In some embodiments, the shift of the virtual address of a page in the upper address region may include an amount of virtual address to account for adding a page to the lower address region. The shift may be such that the virtual address of a page in the upper address region is not aligned with the virtual address page boundary of a page of size for the upper address region. A virtual address hole may be introduced in virtual memory 300 to align the virtual address of a page in the upper address region with the virtual address of the page boundary of a page of size. The virtual address hole may be introduced by shifting the virtual address of a page in the upper address region by an amount of additional virtual address that may align the virtual address of a page in the upper address region with the virtual address of the page boundary of a page of size. The amount of additional virtual address may be added to the amount of the shift of the page's virtual address and / or the amount of virtual address of an additional page in the lower address region. For example, page 304a may be an independent region and may be larger in size than each of pages 302a and 302b. Page 304b may be added to the upper address region that has page 304a. The virtual addresses of the region containing pages 304a and 304b may be shifted by the amount by which the virtual addresses of pages in the lower address region are shifted. The virtual addresses of the region containing pages 304a and 304b may also be shifted to accommodate the addition of another page. However, any construction of a shift may not align pages 304a and 304b with the page boundaries of the page 304a and 304b-sized page. In order to align pages 304a and 304b with the page boundaries of the page 304a and 304b-sized page, the virtual addresses of the region containing pages 304a and 304b may be shifted by an additional amount that may align pages 304a and 304b with the page boundaries for the page 304a and 304b-sized page.

[0047] Figure 3C shows an example of virtual memory 300 implementing subpage granularity shift memory mapping and rotation. Subpage granularity shift may shift the virtual addresses assigned to codes 306 and 308 by the amount of the subpage granularity shift of the virtual address. The amount of the subpage granularity shift of the virtual address may be the same for all regions of virtual memory 300. In the lowest address region pages, the virtual address of the page may be shifted by the amount of the subpage granularity shift of the virtual address. For example, the virtual address of the region containing pages 302a and 302b may be shifted by the amount of the subpage granularity shift of the virtual address so that the virtual address assigned to code 306 spans pages 302a, 302b, and 302c, and a portion of codes 306 and 314 is assigned to an additional page 302. The subpage granularity shift may involve creating an empty address space 310b at the lowest address of the area within page 302a, and reducing the amount of the empty address space 310c at the highest address of the area within page 302c by the amount of the virtual address subpage granularity shift.

[0048] In the upper address region of a page, the virtual address of a page may be shifted by the amount of the subpage granularity shift of the virtual address, in order to accommodate additional pages with lower addresses such as page 302a, and to align the virtual address of the page in the upper address region with the virtual address of the page boundary for the size page. For example, as illustrated with reference to Figure 3B, the virtual address of a region having page 304a may be shifted by the amount of the subpage granularity shift of the virtual address, such that the virtual address assigned to code 308 spans pages 304a and 304b, and a portion of code 308 and code 316 is assigned to the additional page 304b. The subpage granularity shift may create an empty address space 312b at the lowest address of the region in page 304a, and reduce the amount of empty address space 312c at the highest address of the region in page 304b by the amount of the subpage granularity shift of the virtual address.

[0049] Figure 3D shows an example of virtual memory 300 and physical memory 320 during the implementation of subpage granularity shift memory mapping and rotation. Virtual addresses shifted to the subpage granularity of virtual memory 300 may be remapped to physical addresses in physical memory 320. The original pages 302a, 302b, and 304a may be mapped to the same range of physical addresses 326a, 326b, and 328a as before the subpage granularity shift was performed, regardless of whether their virtual addresses were shifted. Address pages 302c and 304b may be mapped to the same range of physical addresses 326a and 328a as the lowest address pages 302a and 304a in the same region.

[0050] The shifted virtual addresses of codes 306 and 308 may be mapped so that code rotation is implemented in physical memory 320. The shifted virtual addresses of codes 306 and 308 may be mapped so that the physical addresses of codes 306 and 308 are shifted by the same amount of addresses as the virtual addresses of codes 306 and 308 are shifted within the original pages 302a, 302b, and 304a. The shifted virtual addresses of codes 314 and 316 may be mapped so that the physical addresses of codes 314 and 316 fill the empty portion of the range of physical addresses 326a, 326b, and 328a created by shifting the physical addresses of codes 306 and 308 by the same amount of addresses as the virtual addresses of codes 306 and 308 are shifted within the original pages 302a, 302b, and 304a. Therefore, codes 314 and 316 are loaded and rotated to physical memory 320 at a lower address range of physical addresses 326a, 326b, and 328a than at a higher address range of physical addresses 326a, 326b, and 328a where codes 314 and 316 are stored without the implementation of memory mapping and rotation of subpage granularity shifts.

[0051] The examples shown in Figures 3A to 3D are used for clarity and simplicity of explanation and do not represent all possible embodiments. These examples do not limit the scope of the claims and specification. The examples do not limit the number and size of regions, the number and size of pages, the amount of code allocated to any number and combination of pages, including fully and partially allocated pages, the number and size of physical address ranges, the size of subpage granularity shifts, etc.

[0052] Figures 4A to 4B show examples of memory mapping and rotation for subpage granular shifts that are suitable for implementing various embodiments. Referring to Figures 1 to 4B, memory mapping and rotation for subpage granular shifts may be implemented on a computing device (e.g., computing device 100 in Figure 1) via a memory system (e.g., memory system 200) using any number and combination of memory maps 400a, 400b (e.g., memory map 204 in Figure 2). Figure 4A shows an exemplary memory map 400a showing a memory map before implementing memory mapping for subpage granular shifts. Figure 4B shows an exemplary memory map 400b showing a memory map with memory mapping for subpage granular shifts implemented.

[0053] The memory map 400a may include two memory areas: the lowest address area of ​​the page and the upper address area of ​​the page. The lowest address area of ​​the page may include four pages, each 4K in size. The upper address area of ​​the page may include one page, 16K in size. Each page may include the page size and the virtual address corresponding to the page, ensuring that the virtual addresses of different pages do not overlap. All virtual addresses of a page may be contiguous. The virtual addresses of a page may be mapped to the corresponding range of physical addresses of the same size as the page. In other words, a 4K page may be mapped to a 4K range of physical addresses, and a 16K page may be mapped to a 16K range of physical addresses.

[0054] Memory map 400b may be generated from memory map 400a by implementing a memory mapping of shifts with a granularity of several subpages. In the example shown in Figure 4B, memory map 400b may be generated using a shift with a granularity of subpages that is larger than 8K virtual addresses but smaller than 12K virtual addresses, such as 10K virtual addresses.

[0055] To accommodate the granularity shift of subpages in a 10K virtual address, a 4K-sized page may be added to the lowest address area of ​​the page. This additional page may contain virtual addresses shifted beyond the boundaries of the original 4 pages in the lowest address area of ​​the page. A 16K-sized page may be added to the upper address area of ​​the page. This additional page may contain virtual addresses shifted beyond the boundaries of the original 1 page in the upper address area of ​​the page.

[0056] The virtual addresses of a 4K-sized page in its lowest address region may be shifted to encompass all of the virtual addresses of the original 4K-sized page that were shifted by a granularity shift of 10K virtual address subpages, while still aligning with the 4K-sized page boundaries. For example, an 8K virtual address shift allows five 4K-sized pages in their lowest address region to encompass all of the virtual addresses of the original 4K-sized page that were shifted by a granularity shift of 10K virtual address subpages, while still aligning with the 4K-sized page boundaries.

[0057] The virtual addresses of a 16K-sized page in the upper address region of a page may be shifted to encompass all of the virtual addresses of the original 16K-sized page that were shifted by a granularity shift of 10K virtual address subpages, while still aligning with the 16K-sized page boundary and not overlapping with the lower address region of the page. For example, an 8K virtual address shift allows two 16K-sized pages in the lower address region of the page to encompass all of the virtual addresses of the original 16K-sized page that were shifted by a granularity shift of 10K virtual address subpages. However, an 8K virtual address shift is insufficient to avoid overlapping with the lower address region of the page due to an added fifth page in the lower address region of the page. Therefore, the virtual address shift of the virtual addresses in the upper address region of the page may include an additional 4K virtual addresses, the size of the added fifth page in the lower address region of the page. However, a 12K virtual address shift (8K + 4K) may not align two 16K pages in the upper address region of the page with the 16K page boundary. Therefore, the virtual address shift of the virtual addresses in the upper address region of a page may include an additional amount of virtual addresses to align the page in the upper address region of the page with the page boundary of the page size. The virtual address shift of the virtual addresses in the upper address region of a page may be 16K (8K + 4K + 4K), so as not to overlap with the lowest address region of the page, and still to align with the 16K-sized page boundary, while encompassing all of the virtual addresses of the original 16K-sized page that were shifted by the granularity shift of 10K virtual address subpages.

[0058] The shifted virtual addresses of the original pages in the region may be mapped to the same range of physical addresses as before the shift. The added 4K pages may be mapped to the same range of physical addresses as the lowest address page of the 4K-sized page region. The added 16K pages may be mapped to the same range of physical addresses as the lowest address page of the 16K-sized page region.

[0059] The examples shown in Figures 4A and 4B are used for clarity and ease of explanation and do not represent all possible embodiments. These examples are not intended to limit the scope of the claims and specification. The examples do not limit the number and size of regions, the number and size of pages, the amount of code allocated to any number and combination of pages, including fully and partially allocated pages, the number and size of physical address ranges, the size of subpage granularity shifts, etc.

[0060] Figure 5 shows an example of a subpage granularity shift memory mapping and rotation system 500 flow suitable for implementing various embodiments. Referring to Figures 1 to 5, the subpage granularity shift memory mapping and rotation system 500 may be implemented on a computing device (e.g., computing device 100) by a processor (e.g., CPU 104, processor 124) running the compiler 504, linker 510, and loader 516, as well as by physical memory.

[0061] Source code 502 may be received by a memory mapping and rotation system 500 for subpage granularity shifts. The compiler may generate program counter (PC) relative code 508 from source code 502. The compiler 504 may also generate a memory map 506 (e.g., memory map 204, memory 400b). Memory map 506 may be configured to map virtual addresses of virtual memory (e.g., virtual memory 202, virtual memory 300 in Figure 2) and physical addresses of physical memory 522 (e.g., memory 106, physical memory 208, physical memory 320). Memory map 506 may be generated to accommodate memory mapping for subpage granularity shifts. For example, memory map 506 may be generated with extra entries per region of memory map 506 (e.g., mapping of virtual addresses of pages to physical addresses) compared to a memory map commonly used to execute PC relative code 508 (e.g., memory map 400a). In another example, the virtual addresses of the pages of a region may be shifted to add extra entries for each region and may not be aligned with the page boundaries of the corresponding size page. Memory map 506 may be generated by shifting the virtual addresses of any number and combinations of pages of a region to align the pages of the region with the page boundaries of the size page of the region.

[0062] The linker 510 may receive a memory map 506 and PC-relative code 508 as input. The linker 510 may use shifts in virtual addresses from the memory map 506 and PC-relative code 508 to generate binary code 514 having subpage granularity shift adjustment pointers. The linker may adjust PC-relative offsets using region-specific shifts in the memory map 506 to correctly link between PC-relative instructions. The linker can convert the adjusted PC-relative code into binary code 514 having subpage granularity shift valid pointers, which may be configured to work regardless of the value of the subpage granularity shift amount of the virtual address applied to the virtual address in the memory map 506.

[0063] The loader 516 may receive as input a memory map 506 and binary code 514 having subpage-granularity shift-valid pointers. The loader 516 may apply subpage-granularity shifts to the virtual addresses of the memory map 506. In some embodiments, the subpage-granularity shifts may be predetermined by a random number generator algorithm or the like, or algorithmically derived. The subpage-granularity shift to the virtual addresses of the memory map 506 may shift the virtual addresses of the memory map 506 by the amount of the subpage-granularity shift of the virtual addresses, and generate a memory map 518 of the subpage-granularity shifts (e.g., memory map 204, memory 400b). The loader 516 may retrieve the code required to execute the binary code 514 having subpage-granularity shift-valid pointers from memory (e.g., memories 106, 114). The loader 516 may use the memory map 518 of the subpage-granularity shifts to load and store the code in physical memory 522. For example, the loader 516 may implement memory rotation of subpage-granularity shifts of code in physical memory 522 according to a virtual-to-physical-memory mapping of subpage-granularity shifts in memory map 518. The loader may shift and rotate the code retrieved from memory to generate rotated binary code 520 having subpage-granularity shift valid pointers. The loader 516 may load and store the rotated binary code 520 having subpage-granularity shift valid pointers in physical memory 522.

[0064] Figure 6 shows Method 600 for memory mapping of subpage granularity shifts according to one embodiment. Referring to Figures 1 to 6, Method 600 may be implemented in a computing device (e.g., computing device 100), in hardware (e.g., SoC 102, CPU 104, memory 106, processor 124, memory management unit 206), in software running on the processor (e.g., memory management unit 206, compiler 504, linker 510, loader 516), or in a combination of a software-configured processor and dedicated hardware including various memory / cache controllers (e.g., memory system 200, memory management unit 206, subpage granularity shift memory mapping and rotation system 500). To encompass alternative configurations possible in various embodiments, the hardware implementing Method 600 is referred to herein as a “memory control device”.

[0065] In block 602, the memory control device may set the subpage granularity shift amount. In some embodiments, the subpage granularity shift amount for any number and combination of subpages may be predetermined by a random number generator algorithm or the like, or be algorithmically derived. In some embodiments, the subpage granularity shift amount may be the amount of virtual addresses in the virtual address space or virtual memory (e.g., virtual memory 202, virtual memory 300). In some embodiments, the memory control device that sets the subpage granularity shift amount in block 602 may be a processor, CPU, memory management unit, and / or loader.

[0066] In block 604, the memory control device may generate memory maps of subpage granular shifts (e.g., memory map 204, e.g., memory map 400b, memory map 518 of subpage granular shifts). The memory control device may apply subpage granular shifts to memory maps (e.g., memory map 400b, memory map 506). Applying subpage granular shifts to memory maps may shift the virtual addresses allocated to code in the memory maps by the amount of the subpage granular shift. The memory maps to which subpage granular shifts are applied may be memory maps generated in method 700, which is described with reference to Figure 7. In some embodiments, the memory control device that generates the subpage granular shift memory maps in block 604 may be a processor, a CPU, a memory management unit, and / or a loader.

[0067] In block 606, the memory control device may rotate code (e.g., codes 306, 308, 314, 316) in physical memory (e.g., memory 106, physical memory 208, physical memory 320, physical memory 522) according to a memory map of subpage granular shifts. The memory control device may rotate code in physical memory by loading and storing code retrieved from memory (e.g., memories 106, 114) according to the execution of code (e.g., binary code 514 having a subpage granular shift valid pointer). Code retrieved from memory may be loaded and stored in physical memory according to the mapping of subpage granular shifts to a memory map in method 900, which will be further described with reference to Figure 9. In some embodiments, the memory control device that rotates code in physical memory according to a memory map of subpage granular shifts in block 606 may be a processor, CPU, memory management unit, and / or loader.

[0068] Figure 7 shows a method for memory mapping of subpage granularity shifts in memory according to one embodiment. Referring to Figures 1 to 7, Method 700 may be implemented in a computing device (e.g., computing device 100), in hardware (e.g., SoC 102, CPU 104, memory 106, processor 124, memory management unit 206), in software running on the processor (e.g., memory management unit 206, compiler 504, linker 510, loader 516), or in a combination of a software-configured processor and dedicated hardware (memory system 200, memory management unit 206, subpage granularity shift memory mapping and rotation system 500), including various memory / cache controllers. To encompass alternative configurations possible in various embodiments, the hardware implementing Method 700 is referred to herein as a “memory control device”.

[0069] In block 702, the memory control device may add memory map entries to regions of a memory map (e.g., memory map 400a). The memory map may contain regions of virtual addresses for pages of the same size. In other words, each region may contain virtual addresses for a single size of page. The memory map may be generated based on the received source code (e.g., source code 502) to use virtual memory (e.g., virtual memory 202, virtual memory 300) mapped to physical memory (e.g., memory 106, physical memory 208, physical memory 320, physical memory 522) to execute the source code. The memory control device may add entries for pages to each region of the memory map with an appropriate page size for the region. The entries for a region may contain virtual addresses for pages adjacent to the region. The virtual addresses for pages in the entries for a region may be mapped to the same range of physical addresses for the lowest virtual address pages of the entries for a region. In some embodiments, the memory control device that adds memory-mapped entries to the memory-mapped region in block 702 may be a processor, CPU, memory management unit, and / or compiler.

[0070] In block 704, the memory control device may shift the virtual address range of the memory map pages to accommodate one or more additional entries to the memory map. When an entry is added to a region of the memory map, the virtual address of the added entry may overlap with the virtual address of another region of the memory map. The memory control device may shift any number and combinations of regions of the memory map to avoid overlapping virtual addresses between regions of the memory map. In some embodiments, the memory control device that shifts the virtual address range of the memory map pages to accommodate one or more additional entries to the memory map in block 704 may be a processor, CPU, memory management unit, and / or compiler.

[0071] In decision block 706, the memory control device may determine whether the virtual address range of a page in a region aligns with a page boundary of the corresponding page size. Different regions of the memory map may have different page sizes, and the pages of a region may align with page size boundaries recognized by various software, firmware, and / or hardware. To maintain functionality after shifting the virtual address range of a page in the memory map to accommodate one or more additional entries to the memory map in block 704, the memory control device may ensure that the virtual address range of a page in a region aligns with a page boundary of the corresponding page size. For example, the memory control device may compare the virtual addresses of a region and / or a page with known page boundaries of the corresponding page size. In another example, the memory control device may compare the virtual addresses of a region and / or a page with several known or calculated page boundaries of the corresponding page size, such as page boundaries prior to the shift in block 704. In some embodiments, the memory control device that determines whether the virtual address range of a page in a region aligns with a page boundary of the corresponding page size in decision block 706 may be a processor, CPU, memory management unit, and / or compiler.

[0072] Depending on whether the virtual address range of a page in a region is determined not to align with the page boundary of the corresponding page size (i.e., determination block 706 "No"), the memory control device may shift the virtual address range of the page in the region by an amount that aligns the virtual address range with the page boundary of the corresponding page size in block 708. The comparison in determination block 706 may result in the virtual address range of the page in the region not aligning with the page boundary of the corresponding page size. The memory control device may shift the virtual address range of the page in the region by an amount that aligns the virtual address range with the page boundary of the corresponding page size. In some embodiments, the memory control device that shifts the virtual address range of the page in the region by an amount that aligns the virtual address range with the page boundary of the corresponding page size in block 708 may be a processor, CPU, memory management unit, and / or compiler.

[0073] In some embodiments, decision blocks 706 and 708 may be implemented recursively in contiguous regions of the memory map. For example, each contiguous region of the memory map may be shifted when the previous region is shifted. Once the previous region is aligned to the boundary of the corresponding page size, the memory control device may implement decision blocks 706 and 708 for the contiguous region. The recursive implementation of decision blocks 706 and 708 may continue until the last region of the memory map is aligned to the boundary of the corresponding page size.

[0074] Depending on whether the memory control device determines that the virtual address range of a page in a region aligns with a page boundary of the corresponding page size (i.e., determination block 706 "Yes"), or whether it shifts the virtual address range of a page in a region by an amount that aligns it with a page boundary of the corresponding page size in block 708, the memory control device may map the shifted virtual address range of a page in a region to a range of physical addresses the same size as the page in block 710. Mapping the shifted virtual address range of a page in a region to a range of physical addresses the same size as the page may include mapping the lowest and highest virtual address pages in the region to the same range of physical addresses. In some embodiments, the memory control device that maps the shifted virtual address range of a page in a region to a range of physical addresses the same size as the page in block 710 may be a processor, CPU, memory management unit, and / or compiler.

[0075] Figure 8 shows a method 800 for memory rotation according to one embodiment. Referring to Figures 1 to 8, the method 800 may be implemented in a computing device (e.g., computing device 100), in hardware (e.g., SoC 102, CPU 104, memory 106, processor 124, memory management unit 206), in software running on the processor (e.g., memory management unit 206, compiler 504, linker 510, loader 516), or in a combination of software-configured processor and dedicated hardware (memory system 200, memory management unit 206, memory mapping and rotation system 500 for subpage granularity shifts), including various memory / cache controllers. To encompass alternative configurations possible in various embodiments, the hardware implementing the method 800 is referred to herein as a “memory control device”.

[0076] In block 802, the memory control device may generate PC-relative code (e.g., PC-relative code 508) from source code (e.g., source code 502). In some embodiments, the memory control device that generates PC-relative code from source code in block 802 may be a processor, CPU, memory management unit, and / or compiler.

[0077] In block 804, the memory control device may use a memory map (e.g., memory map 400b, memory map 506) to generate binary code with subpage granularity shift-enabled pointers (e.g., binary code 514 with subpage granularity shift adjustment pointers). The memory map may be the memory map generated in method 700 as described with reference to Figure 7. The memory control device may receive a memory map and PC-relative code generated in block 802 as input. The memory control device may use shifts in the virtual addresses from the memory map and PC-relative code to generate binary code with subpage granularity shift adjustment pointers. The memory control device may use region-specific shifts in the memory map to adjust the PC-relative offsets to correctly link between PC-relative instructions. The memory control device may convert the adjusted PC-relative code into binary code with subpage granularity shift-enabled pointers, which may be configured to function regardless of the value of the subpage granularity shift amount of the virtual address applied to the virtual address in block 604 of method 600 as described with reference to Figure 6. In some embodiments, the memory control device that generates binary code with subpage-granular shift-valid pointers using a memory map in block 804 may be a processor, CPU, memory management unit, and / or linker.

[0078] In block 806, the memory control device may generate rotated binary code having subpage-granularity shift-valid pointers (e.g., rotated binary code 520 having subpage-granularity shift-valid pointers). The memory control device may receive a memory map and the binary code having subpage-granularity shift-valid pointers generated in block 804 as input. The memory control device may generate memory maps of subpage-granularity shifts (e.g., memory map 204, memory map 400b, memory map 518 of subpage-granularity shifts) similar to the operation of block 604 of method 600 described with reference to Figure 6. The memory control device may retrieve the code required to execute the binary code having subpage-granularity shift-valid pointers from memory (e.g., memories 106, 114). The memory control device may use the memory maps of subpage-granularity shifts to load and store the code in physical memory (e.g., memory 106, physical memory 208, physical memory 320, physical memory 522). For example, a memory control device may implement memory rotation of subpage-granular shifts of code in physical memory according to a mapping of subpage-granular shift memory maps from virtual memory to physical memory, similar to block 606 of method 600 described with reference to Figure 6, and method 900 described with reference to Figure 9. In some embodiments, the memory control device that generates the rotated binary code with subpage-granular shift valid pointers in block 806 may be a processor, CPU, memory management unit, and / or loader.

[0079] Figure 9 shows a method 900 for memory rotation described in one embodiment. Referring to Figures 1 to 9, the method 900 may be implemented in a computing device (e.g., computing device 100), in hardware (e.g., SoC 102, CPU 104, memory 106, processor 124, memory management unit 206), in software running on the processor (e.g., memory management unit 206, compiler 504, linker 510, loader 516), or in a combination of a software-configured processor and dedicated hardware (memory system 200, memory management unit 206, memory mapping and rotation system 500 for subpage granularity shifts). To encompass alternative configurations possible in various embodiments, the hardware implementing the method 900 is referred to herein as a “memory control device”.

[0080] In block 902, the memory control device may load the code of the virtual address of the original page in the region into a physical address according to the mapping of the memory maps of subpage granular shifts (e.g., memory map 204, memory map 400b, memory map 518 of subpage granular shifts). The memory control device may interpret the mapping of the memory maps of subpage granular shifts for rotated binary code with subpage granular shift valid pointers (e.g., rotated binary code 520 with subpage granular shift valid pointers), such as the one generated in block 806 of method 800 described with reference to Figure 8. For example, the memory control device may interpret the mapping from virtual addresses to physical addresses for pages in the region other than the page added to the region in block 702 of method 700 described with reference to Figure 7. The pages may have virtual addresses that are shifted and mapped to contiguous, increasing physical addresses. The physical address to which the virtual address of the original page is mapped may be shifted by the amount of the subpage granular shift address or address space. In block 902, the memory control device that loads the code of the virtual address of the original page of the region into a physical address according to the memory map mapping of the subpage granularity shift may be a processor, CPU, memory management unit, and / or loader.

[0081] In block 904, the memory control device loads the code of the virtual address of the added page into the region into a physical address according to the memory map mapping of the subpage granularity shift. The memory control device may further interpret the memory map mapping of the subpage granularity shift for rotated binary code that has a subpage granularity shift valid pointer. For example, the memory control device may interpret the mapping from the virtual address to the physical address of the added page in the region in block 702 of method 700 as described with reference to Figure 7. The page may have a virtual address that is shifted to a physical address that overlaps with the physical address of the lowest virtual address page of the region and mapped thereto. The physical address to which the virtual address of the added page is mapped may be a physical address that is left empty by a physical address shift of the amount of the subpage granularity shift or by the amount of the address space. The memory control device that loads the code of the virtual address of the added page into the region into a physical address according to the memory map mapping of the subpage granularity shift in block 904 may be a processor, CPU, memory management unit, and / or loader.

[0082] The systems according to various embodiments (including, but not limited to, the embodiments described above with reference to Figures 1 to 9) may be implemented in a wide variety of computing systems, including mobile computing devices, and an example of a mobile computing device suitable for use with various embodiments is shown in Figure 10. The mobile computing device 1000 may include a processor 1002 coupled to a touchscreen controller 1004 and internal memory 1006. The processor 1002 may be one or more multicore integrated circuits designated for general-purpose or specific processing tasks. The internal memory 1006 may be volatile memory or non-volatile memory, and may be secure memory and / or encrypted memory or non-secure memory and / or unencrypted memory, or any combination thereof. Examples of memory types that may be utilized include, but are not limited to, DDR, LPDDR, GDDR, WIDEIO, RAM, SRAM, DRAM, P-RAM, R-RAM, M-RAM, STT-RAM, and embedded DRAM. The touchscreen controller 1004 and processor 1002 may also be coupled to a touchscreen panel 1012 such as a resistive touchscreen, capacitive touchscreen, or infrared touchscreen. Furthermore, the display of the mobile computing device 1000 does not need to have touchscreen functionality.

[0083] The mobile computing device 1000 may have one or more radio signal transceivers 1008 (e.g., Peanut, Bluetooth, ZigBee, Wi-Fi, RF radio, etc.) and antennas 1010 coupled to each other and / or to the processor 1002 for transmitting and receiving communications. The transceivers 1008 and antennas 1010 may be used together with the circuits described above to implement various wireless transmission protocol stacks and interfaces. The mobile computing device 1000 may also include a cellular network wireless modem chip 1016 that enables communication over a cellular network and is coupled to the processor.

[0084] The mobile computing device 1000 may include a peripheral device connection interface 1018 coupled to the processor 1002. The peripheral device connection interface 1018 may be configured to accept one type of connection on its own, or it may be configured to accept various common or proprietary types of physical and communication connections, such as Universal Serial Bus (USB), FireWire, Thunderbolt, or PCIe. The peripheral device connection interface 1018 may also be coupled to a similarly configured peripheral device connection port (not shown).

[0085] The mobile computing device 1000 may also include a speaker 1014 for providing audio output. The mobile computing device 1000 may also include a housing 1020 made of plastic, metal, or a combination of materials for housing all or some of the components described herein. The mobile computing device 1000 may also include a power supply 1022 coupled to the processor 1002, such as a disposable or rechargeable battery. The rechargeable battery may be coupled to a peripheral device connection port to receive charging current from a power supply outside the mobile computing device 1000. The mobile computing device 1000 may also include a physical button 1024 for receiving user input. The mobile computing device 1000 may also include a power button 1024 for turning the mobile computing device 1000 on and off.

[0086] Systems according to various embodiments (including, but not limited to, the embodiments described above with reference to Figures 1 to 9) may be implemented in a wide variety of computing systems, including a laptop computer 1100, one example of which is shown in Figure 11. Many laptop computers include a touch surface 1117 of a touchpad that acts as the computer's pointing device and may therefore receive drag, scroll, and flick gestures similar to those implemented on the aforementioned computing devices equipped with touchscreen displays. The laptop computer 1100 typically includes a processor 1102 coupled with volatile memory 1112 and large-capacity non-volatile memory such as a flash memory disk drive 1113. In addition, the computer 1100 may have one or more antennas 1108 for sending and receiving electromagnetic radiation, which may be connected to a wireless data link and / or cellular telephone transceiver 1116 coupled to the processor 1102. The computer 1100 may also include a floppy disk drive 1114 and a compact disk (CD) drive 1115 coupled to the processor 1102. In a notebook configuration, the computer housing includes a touchpad 1117, a keyboard 1118, and a display 1119, all coupled to the processor 1102. Other configurations of the computing device, as is well known, may include a computer mouse or trackball coupled to the processor (for example, via a USB input), which may also be used in various embodiments.

[0087] Systems according to various embodiments (including, but not limited to, the embodiments described above with reference to Figures 1 to 9) may be implemented in a fixed computing system, such as any of the various commercially available servers. An exemplary server 1200 is shown in Figure 12. Such a server 1200 typically includes one or more multicore processor assemblies 1201 coupled to large-capacity non-volatile memory such as volatile memory 1202 and disk drives 1204. As shown in Figure 12, the multicore processor assemblies 1201 may be added to the server 1200 by inserting them into a rack of assemblies. The server 1200 may also include a floppy disk drive, compact disk (CD), or digital versatile disk (DVD) disk drive 1206 coupled to the processor 1201. Server 1200 may also include a network access port 1203 coupled to a multicore processor assembly 1201 for establishing network interface connections with network 1205, such as local area networks, the Internet, public switched telephone networks, and / or cellular data networks (e.g., CDMA, TDMA, GSM, PCS, 3G, 4G, LTE, or any other type of cellular data network) coupled to other broadcast system computers and servers.

[0088] Implementation examples are described in the following paragraphs. While some of the following implementation examples are described in terms of exemplary methods, further exemplary implementations may include exemplary methods described in the following paragraphs, which are implemented by a computing device having a processor configured to execute processor-executable instructions for the operation of the exemplary method; exemplary methods described in the following paragraphs, which are implemented by a computing device including means for performing the functionality of the exemplary method; and exemplary methods described in the following paragraphs, which are implemented as a non-temporary processor-readable storage medium storing processor-executable instructions configured to cause the processor of a computing device to perform the operation of the exemplary method.

[0089] Example 1. A method for generating a memory map configured to map virtual addresses of pages to physical addresses, comprising the steps of: adding a first entry for a first additional page to a first region of the memory map, wherein pages of the same size are grouped into regions; shifting the virtual addresses of the first region allocated to the code by a subpage granularity shift amount to accommodate a shift in the first region; mapping the shifted virtual addresses of the first entry for the first additional page to a physical address mapped to a first lowest shifted virtual address page of the first region; and shifting the virtual addresses of the first region allocated to the code by a subpage granularity shift amount, such that the virtual addresses of the first region allocated to the code are partially shifted to the first entry for the first additional page.

[0090] Example 2. The method of Example 1, further comprising the steps of: adding a second entry for a second additional page to a second region of a memory map, wherein the second region is virtually addressed higher than the first region; shifting the virtual address of the second region by a subpage granularity shift amount to accommodate a shift in the virtual address of the second region allocated to the code; mapping the shifted virtual address of the second entry for the second additional page to a physical address mapped to a second lowest shift virtual address page of the second region; and shifting the virtual address of the second region allocated to the code by a subpage granularity shift amount, wherein the virtual address of the second region allocated to the code is partially shifted to the second entry for the second additional page.

[0091] Example 3. Either method of Example 1 or 2, further comprising the steps of shifting the virtual address of a second region to accommodate a first entry added to a first region of the memory map, and shifting the virtual address of the second region to align the pages of the second region, including the second additional page, with the page boundaries of the pages of the second region.

[0092] Example 4. Any method of Examples 1 to 3, further comprising the step of rotating the code for a shifted virtual address in a first region allocated to the code in physical memory.

[0093] Example 5. The method of Example 4, wherein the step of rotating the code in physical memory for a shifted virtual address in a first region allocated to the code includes loading the code to a physical address mapped from a first lowest virtual address page for the shifted virtual address in the first region allocated to the code, and loading the code to a physical address mapped from a first additional page for the shifted virtual address in the first region allocated to the code, wherein the physical address mapped from the first additional page for the shifted virtual address in the first region allocated to the code is a lower physical address than the physical address mapped from the first lowest virtual address page for the shifted virtual address in the first region allocated to the code.

[0094] Example 6. Any method of Examples 1 through 5, further comprising the step of adjusting the pointer for the binary code containing the code by the amount of the shift in the virtual address of the second area to correspond to the shift in the virtual address of the second area allocated to the code, by the amount of the subpage granularity shift.

[0095] Example 7. The method of Example 6, further comprising the steps of generating program counter relative code and generating binary code from program counter relative code.

[0096] Computer program code for execution on a programmable processor to perform the operations of various embodiments, or “program code,” may be written in high-level programming languages ​​such as C, C++, C#, Smalltalk, Java, JavaScript, Visual Basic, Structured Query Language (e.g., Transact-SQL), Perl, or various other programming languages. Program code or programs stored on computer-readable storage media as used in this application may refer to machine code (such as object code) whose format is understandable by a processor.

[0097] The above description of the method and process flow diagram are provided merely as illustrative examples and do not require or imply that the operations of the various embodiments must be performed in the order presented. As will be understood by those skilled in the art, the order of operations in the above embodiments may be performed in any order. Words such as “then,” “next,” and “then” do not limit the order of operations, and these words are simply used to guide the reader through the description of the method. Furthermore, any reference to a claim element in the singular form, for example using the articles “a,” “an,” or “the,” should not be interpreted as limiting that element to the singular form.

[0098] The various exemplary logic blocks, modules, circuits, and algorithmic operations described in relation to various embodiments may be implemented as electronic hardware, computer software, or a combination of both. To clearly demonstrate this hardware- and software compatibility, the various exemplary components, blocks, modules, circuits, and operations have generally been described above in terms of their functions. Whether such functions are implemented as hardware or software depends on the specific application and the design constraints imposed on the overall system. A person skilled in the art may implement the described functions in various ways for each specific application, but such implementation decisions should not be construed as causing a departure from the claims.

[0099] The hardware used to implement the various exemplary logics, logic blocks, modules, and circuits described in relation to the embodiments disclosed herein may be implemented or run using general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs) or other programmable logic devices, discrete gate logic or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. The general-purpose processor may be a microprocessor, but alternatively, the processor may be any conventional processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices, for example, a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors working with a DSP core, or any other such configuration. Alternatively, some operations or methods may be performed by circuits specific to a given function.

[0100] In one or more embodiments, the functions described may be implemented in hardware, software, firmware, or any combination thereof. If implemented in software, the functions may be stored as one or more instructions or codes on a non-temporary computer-readable medium or a non-temporary processor-readable medium. The operation of the methods or algorithms disclosed herein may be embodied in a processor-executable software module that may reside on a non-temporary computer-readable storage medium or a non-temporary processor-readable storage medium. The non-temporary computer-readable storage medium or a non-temporary processor-readable storage medium may be any storage medium that may be accessed by a computer or processor. Such non-temporary computer-readable or processor-readable medium may include, but are not limited to, RAM, ROM, EEPROM, FLASH memory, CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other medium that may be used to store desired program code in the form of instructions or data structures and may be accessed by a computer. The terms "disk" and "disc" as used herein include compact discs (CDs), laser discs, optical discs, digital multipurpose discs (DVDs), floppy disks, and Blu-ray® discs, where a disk typically reproduces data magnetically, and a disc reproduces data optically using a laser. The above combinations also fall within the scope of non-temporary computer-readable media and non-temporary processor-readable media. Additionally, the operation of a method or algorithm may exist as one of the codes and / or instructions on a non-temporary processor-readable medium and / or non-temporary computer-readable medium, or any combination or set thereof, which may be incorporated into a computer program product.

[0101] The foregoing description of the embodiments disclosed is provided to enable any person skilled in the art to construct or use the claims. Various modifications to these embodiments will be readily apparent to a person skilled in the art, and the general principles defined herein may be applied to other embodiments and implementations without departing from the claims. Accordingly, this disclosure is not intended to be limited to the embodiments and implementations described herein, but should be given the broadest scope that is consistent with the claims and principles disclosed herein, as well as novel features. [Explanation of symbols]

[0102] 100 Computing Devices 102 SoC 104 Central Processing Unit (CPU) 106 memory 108 Communication Interfaces 110 Memory Interface 112 Communication Components 114 memory 116 Antenna 120 Peripheral Device Interfaces 122 Peripheral Devices 124 Processing Devices / Processors 200 memory system 202 virtual memory 204 Memory Map 206 Memory Management Unit (MMU) 208 physical memory 300 virtual memory Page 302 Page 304 306 Code 308 Code 320 physical memory 326 physical address 328 physical address 400 memory map 502 Source Code 522 physical memory 1000 mobile computing devices 1002 Processor 1004 Touchscreen Controller 1006 Internal Memory 1008 Transceiver 1010 Antenna 1012 Touchscreen Panel 1014 Speaker 1016 Cellular Network Wireless Modem Chip 1018 Peripheral device connection interface 1020 Housing 1022 Power supply 1024 Physical Buttons / Power Button 1102 Processor 1108 Antenna 1100 Laptop Computer 1112 Volatile memory 1113 Disk drive 1114 Floppy disk drive 1115 Compact Disc (CD) Drive 1116 Wireless data link and / or cellular telephone transceiver 1117 Touchpad 1118 keyboard 1119 Display 1200 servers 1201 Multicore Processor Assembly 1202 Volatile memory 1203 Network Access Port 1204 Disk Drive 1205 Network 1206 Digital Multipurpose Disc (DVD) Disc Drive

Claims

1. A method for generating a memory map which is performed by a computing device and is configured to map the virtual addresses of pages to physical addresses, wherein pages of the same size are grouped into regions, and the method The steps include adding a first entry for a first additional page to a first area of ​​the memory map, To accommodate the shift of the virtual address of the first region allocated to the code, the steps include shifting the virtual address of the first region by the amount of the subpage granularity shift, The steps of mapping the shifted virtual address of the first entry for the first additional page to a physical address mapped to the first least shifted virtual address page of the first region, A step of shifting the virtual address of the first region allocated to the code by the amount of the subpage granularity shift, wherein the virtual address of the first region allocated to the code is partially shifted to the first entry for the first additional page. Methods that include...

2. A step of adding a second entry for a second additional page to a second region of the memory map, wherein the second region is virtually addressed higher than the first region. To accommodate the shift of the virtual address of the second region allocated to the code, the steps include shifting the virtual address of the second region by the amount of the subpage granularity shift, The steps of mapping the shifted virtual address of the second entry for the second additional page to the physical address mapped to the second lowest shifted virtual address page of the second area, A step of shifting the virtual address of the second area allocated to the code by the amount of the granularity shift of the subpage, wherein the virtual address of the second area allocated to the code is partially shifted to the second entry for the second additional page. The method according to claim 1, further comprising:

3. The steps include shifting the virtual address of the second region to correspond to the first entry added to the first region of the memory map, The steps include shifting the virtual address of the second region to align the page of the second region, including the second additional page, with the page boundary of the size page of the page in the second region, and The method according to claim 2, further comprising:

4. The method according to claim 1, further comprising the step of rotating the code for the shifted virtual address of the first region allocated to the code in physical memory.

5. The step of rotating the code in the physical memory for the shifted virtual address of the first region allocated to the code is: The steps include loading the code from the first lowest shifted virtual address page to the mapped physical address for the shifted virtual address in the first region allocated to the code, A step of loading code from the first additional page to the mapped physical address for the shifted virtual address of the first region allocated to the code, wherein the mapped physical address for the shifted virtual address of the first region allocated to the code from the first additional page is a physical address lower than the mapped physical address for the shifted virtual address of the first region allocated to the code from the first lowest shifted virtual address page. The method according to claim 4, including the method described in claim 4.

6. The method according to claim 1, further comprising the step of adjusting a pointer for the binary code containing the code by the amount of the shift in the virtual address of the first region to the code by the amount of the shift in the granularity of the subpage.

7. A computing device, Adding a first entry for a first additional page to a first region of a memory map, wherein the memory map is configured to map the virtual addresses of pages to physical addresses, and pages of the same size are grouped into a region containing the first region. To accommodate the shift in the virtual address of the first region allocated to the code by the amount of the subpage granularity shift, the virtual address of the first region is shifted, Mapping the shifted virtual address of the first entry for the first additional page to the physical address mapped to the first least shifted virtual address page of the first region, Shifting the virtual address of the first region allocated to the code by the amount of the subpage granularity shift, such that the virtual address of the first region allocated to the code is partially shifted to the first entry for the first additional page. A computing device comprising a processing device configured to perform the following actions.

8. The computing device according to claim 7, wherein the processing device is configured to rotate the code for the shifted virtual address of the first region allocated to the code in physical memory.

9. The aforementioned processing device For the shifted virtual address of the first region allocated to the code in the physical memory, Loading the code from the first lowest shifted virtual address page to the mapped physical address for the shifted virtual address in the first region allocated to the code, Loading code from the first additional page to the mapped physical address for the shifted virtual address of the first region allocated to the code, wherein the mapped physical address for the shifted virtual address of the first region allocated to the code from the first additional page is a lower physical address than the mapped physical address for the shifted virtual address of the first region allocated to the code from the first lowest shifted virtual address page. The computing device according to claim 8, configured to rotate the code by means of the said code.

10. A computing device, Means for adding a first entry for a first additional page to a first region of a memory map, wherein the memory map is configured to map the virtual addresses of pages to physical addresses, and pages of the same size are grouped into a region containing the first region. A means for shifting the virtual address of the first region allocated to the code, in order to correspond to a shift in the virtual address of the first region allocated to the code by the amount of the subpage granularity shift, Means for mapping the shifted virtual address of the first entry for the first additional page to a physical address mapped to the first least shifted virtual address page of the first area, Means for shifting the virtual address of the first region allocated to the code by the amount of the subpage granularity shift, wherein the virtual address of the first region allocated to the code is partially shifted to the first entry for the first additional page. A computing device equipped with [a certain feature].

11. The computing device according to claim 10, further comprising means for rotating the code for the shifted virtual address of the first region allocated to the code in physical memory.

12. Means for rotating the code in the physical memory for the shifted virtual address of the first region allocated to the code, Means for loading code from the first lowest shifted virtual address page to the mapped physical address for the shifted virtual address in the first region allocated to the code, Means for loading code from the first additional page to the mapped physical address for the shifted virtual address of the first region allocated to the code, wherein the mapped physical address for the shifted virtual address of the first region allocated to the code from the first additional page is a physical address lower than the mapped physical address for the shifted virtual address of the first region allocated to the code from the first lowest shifted virtual address page. The computing device according to claim 11, comprising:

13. A non-temporary processor-readable storage medium storing processor-executable instructions configured to cause a processing device to perform an operation, wherein the operation is Adding a first entry for a first additional page to a first region of a memory map, wherein the memory map is configured to map the virtual addresses of pages to physical addresses, and pages of the same size are grouped into a region containing the first region. To accommodate the shift of the virtual address of the first region allocated to the code, the virtual address of the first region is shifted by the amount of the subpage granularity shift, Mapping the shifted virtual address of the first entry for the first additional page to the physical address mapped to the first least shifted virtual address page of the first region, Shifting the virtual address of the first region allocated to the code by the amount of the subpage granularity shift, such that the virtual address of the first region allocated to the code is partially shifted to the first entry for the first additional page. A non-temporary processor-readable storage medium, including [the specified element].

14. The non-temporary processor-readable storage medium according to claim 13, wherein the stored processor-executable instructions are configured to cause the processing device to perform an operation that further includes rotating the code for the shifted virtual address of the first region allocated to the code in physical memory.

15. The stored processor-executable instructions are transmitted to the processing device. Loading the code from the first lowest shifted virtual address page to the mapped physical address for the shifted virtual address in the first region allocated to the code, Loading code from the first additional page to the mapped physical address for the shifted virtual address of the first region allocated to the code, wherein the mapped physical address for the shifted virtual address of the first region allocated to the code from the first additional page is a lower physical address than the mapped physical address for the shifted virtual address of the first region allocated to the code from the first lowest shifted virtual address page. A non-temporary processor-readable storage medium according to claim 14, configured to operate to rotate the code for the shifted virtual address of the first region allocated to the code in the physical memory, including the above.

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