Silicon carbide semiconductor wafer, silicon carbide semiconductor device, and method for manufacturing silicon carbide single crystal
A boron-doped SiC substrate with a specific concentration and structured layers in the SiC semiconductor device suppresses BPD expansion into SSFs, enhancing diode current degradation characteristics and reducing electrical property degradation, particularly in high-current applications.
Patent Information
- Authority / Receiving Office
- JP · JP
- Patent Type
- Patents
- Current Assignee / Owner
- DENSO CORP
- Filing Date
- 2023-07-24
- Publication Date
- 2026-06-30
AI Technical Summary
Existing methods of introducing p-type impurities in SiC single crystal substrates to suppress the expansion of basal plane dislocations (BPDs) into Shockley stacking faults (SSFs) are insufficient when considering the current flowing through built-in diodes in SiC semiconductor devices, particularly in high-current applications.
A SiC substrate doped with n-type impurities, specifically boron (B) at a concentration of 9.0 × 10⁶/cm³, combined with a structured n-type low-concentration layer and p-type deep layer, forms a SiC semiconductor device with a trench gate structure that suppresses BPD expansion into SSFs, even under high current densities.
The proposed solution effectively reduces SSF area occupancy to 3% or less, maintaining excellent diode current degradation characteristics and preventing electrical property degradation in SiC semiconductor devices, while minimizing wafer warpage and hole injection.
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