Manufacturing method of wiring boards

Abstract

This method for manufacturing a wiring board includes: a step (I) of forming an insulation material layer on a surface of a support substrate; a step (II) of forming, by electroless copper plating, a first electrically-conductive layer on a surface of the insulation material layer; a step (III) of forming a first opening through which the first electrically-conductive layer and the insulation material layer pass through; a step (IV) of forming, by electroless copper plating, a second electrically-conductive layer on a bottom face and side faces of the first opening; a step (V) of forming, on a surface of the second electrically-conductive layer, a resist pattern having a second opening in communication with the first opening; and a step (VI) of filling, by copper electroplating, the first opening and the second opening with an electrically-conductive material including copper.

Description

Technical Field

[0001] The present disclosure relates to a method for manufacturing a wiring board and a laminated board.

Background Art

[0002] For the purpose of high density and high performance of semiconductor packages, an implementation form in which semiconductor elements with different performances (hereinafter, sometimes referred to as "chips") are mixed and mounted in one package has been proposed. From the perspective of cost, the importance of high-density interconnect technology between chips has been increasing (see Patent Document 1).

[0003] In smartphones and tablet terminals, a connection method called package-on-package is widely adopted. Package-on-package is a method of connecting different packages on a package by flip-chip mounting (see Non-Patent Documents 1 and 2). Further, as a form for more high-density mounting, package technologies using an organic substrate having high-density wiring (organic interposer), fan-out type package technology (FO-WLP) having through-mold vias (TMV), package technologies using a silicon or glass interposer, package technologies using through-silicon vias (TSV), package technologies using chips embedded in a substrate for inter-chip transmission, etc. have been proposed. Particularly in the case of organic interposers and FO-WLP, when chips are mounted in parallel, a fine wiring layer is required for high-density conduction (see Patent Document 2).

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Patent Document 2

Non-Patent Documents

[0005] [Non-Patent Document 1] Application of Through Mold Via(TMV) as PoP Base Package, Electronic Components and Technology Conference(ECTC),2008 [Non-Patent Document 2] Advanced Low Profile PoP Solution with Embedded Wafer Level PoP(eWLB-PoP)Technology,ECTC,2012 [Overview of the Initiative] [Problems that the invention aims to solve]

[0006] Incidentally, the inventors of this invention manufactured a wiring board having vias using a laminate comprising a prepreg and an ultra-thin copper foil (thickness of about 1.5 to 5 μm) provided on its surface, and found the following problems with the miniaturization of vias in recent years. Specifically, when openings penetrating the copper foil and prepreg were formed using a carbon dioxide laser, which is widely used in this field, a phenomenon of delamination of the copper foil from the prepreg around the openings was observed. Although the delamination of the copper foil around the via openings was previously at a level that could be ignored, since miniaturization of via openings is required (for example, opening diameter of about 10 to 100 μm), it is expected that this will affect the reliability of the vias.

[0007] This disclosure has been made in view of the above problems, and provides a method for manufacturing a wiring board that can sufficiently suppress peeling of the conductive layer around an opening, even when an opening for via formation is formed by a carbon dioxide laser. This disclosure provides a laminate used in the manufacture of a wiring board that can sufficiently suppress peeling of the conductive layer around an opening, even when an opening for via formation is formed by a carbon dioxide laser, and is useful for manufacturing a wiring board with excellent reliability and a sufficiently high yield. [Means for solving the problem]

[0008] The method for manufacturing a wiring board according to this disclosure includes the steps of: (I) forming an insulating material layer on the surface of a support substrate; (II) forming a first conductive layer on the surface of the insulating material layer by electroless copper plating; (III) forming a first opening that penetrates the first conductive layer and the insulating material layer; (IV) forming a second conductive layer on the surface of the first conductive layer, on the bottom surface and on the side surface of the first opening by electroless copper plating; (V) forming a resist pattern on the surface of the second conductive layer having a second opening that communicates with the first opening; and (VI) filling the first opening and the second opening with a conductive material containing copper by electrolytic copper plating.

[0009] The inventors have found that the above problem can be solved by providing an insulating material layer on the surface of a support substrate and forming a first conductive layer on the surface of this insulating material layer by electroless copper plating. That is, even if a first opening is formed through the first conductive layer and the insulating material layer using a carbon dioxide laser after the formation of the first conductive layer, peeling of the first conductive layer from the insulating material layer around the opening can be sufficiently suppressed. The main reason for this effect is presumed to be that the first conductive layer formed by electroless copper plating is thinner than copper foil. That is, the thickness of the first conductive layer formed in step (II) is, for example, 20 to 590 nm. Because the first conductive layer is sufficiently thin, the heat generated during the processing of the opening with the carbon dioxide laser in step (III) is easily dissipated, and an opening can be formed in the first conductive layer in a relatively short time. From these points, it is presumed that peeling of the first conductive layer from the insulating material layer around the opening is unlikely to occur. In other words, according to this disclosure, vias (first and second openings) of a predetermined shape can be stably formed, and wiring boards can be manufactured with a good yield. In contrast, the thickness of ultra-thin copper foil conventionally used in the field of wiring boards is, for example, 1.5 to 5 μm. When openings are formed by a carbon dioxide laser on a laminate having copper foil of this thickness on the outermost surface, the radiation of heat generated during processing tends to be obstructed by the copper foil. As a result, it is presumed that heat accumulates in the insulating material layer around the opening, and this heat causes the insulating material to deteriorate, leading to delamination of the copper foil. Furthermore, since carbon dioxide lasers emit light in the infrared region, the temperature of the area irradiated by the carbon dioxide laser and its vicinity tends to rise. If delamination does not occur around the opening when using a carbon dioxide laser, it can be said that delamination will not occur even when using other lasers (e.g., YAG laser, UV-YAG laser, green laser, deep ultraviolet laser, excimer laser).

[0010] The resist pattern in step (V) may further have a plurality of grooves that extend to the surface of the second conductive layer and are provided parallel to each other. In this case, in step (VI), wiring is formed by filling the plurality of grooves with conductive material by electrolytic copper plating. The width of the grooves is, for example, 1 to 100 μm. The distance between two adjacent grooves is, for example, 1 to 100 μm. Note that "width of the grooves" and "distance between two adjacent grooves" can be rephrased as "width of the wiring" and "distance between two adjacent wirings," respectively.

[0011] The process from step (VI) to finally obtaining the printed circuit board is not particularly limited, but for example, the printed circuit board may be manufactured through the following steps: • Step of removing the resist pattern (VII) (VIII) Steps to remove the second conductive layer exposed by peeling off the resist pattern and the first conductive layer in contact with it.

[0012] The wiring layer formed on the support substrate may be single-layer or multi-layer. A wiring substrate having a multi-layer wiring layer on a support substrate is manufactured, for example, through the following process. • After step (VIII), step (IX) further forms an insulating material layer to cover the wiring provided on the insulating material layer. • After process (IX), process (X) executes the series of processes from process (II) to process (IX).

[0013] The laminate according to the present disclosure includes a support substrate, an insulating material layer provided on the surface of the support substrate, and a conductive layer with a thickness of 20 to 590 nm provided on the surface of the insulating material layer. This laminate is used for manufacturing a wiring substrate, can sufficiently suppress the peeling of the conductive layer around the opening for via formation, and is useful for manufacturing a wiring substrate with excellent reliability at a sufficiently high yield. The above conductive layer is formed by electroless copper plating. Instead of electroless copper plating, the conductive layer with the above thickness may be formed by other methods (for example, sputtering or vapor deposition). According to sputtering or vapor deposition, a conductive layer that adheres firmly enough to the insulating material layer can be formed, similar to electroless copper plating.

[0014] The support substrate in the present disclosure has, for example, a prepreg containing a cloth (for example, a glass cloth) and a copper layer formed on the surface of the prepreg. The insulating material layer in the present disclosure is, for example, a prepreg containing a cloth (for example, a glass cloth).

Advantages of the Invention

[0015] According to the present disclosure, even when an opening for via formation is formed by a carbon dioxide laser, a method for manufacturing a wiring substrate capable of sufficiently suppressing the peeling of the conductive layer around this opening is provided. According to the present disclosure, even when an opening for via formation is formed by a carbon dioxide laser in a laminate used for manufacturing a wiring substrate, the peeling of the conductive layer around this opening can be sufficiently suppressed, and a laminate useful for manufacturing a wiring substrate with excellent reliability at a sufficiently high yield is provided.

Brief Description of the Drawings

[0016] [Figure 1] Figures 1(a) to 1(c) are cross-sectional views schematically showing the manufacturing process of a wiring substrate. [Figure 2] Figures 2(a) to 2(c) are cross-sectional views schematically showing the manufacturing process of a wiring substrate. [Figure 3] Figures 3(a) to 3(c) are cross-sectional views schematically showing the manufacturing process of a wiring substrate. [Figure 4]FIG. 4 is a cross-sectional view schematically showing a wiring board including a wiring layer formed on the surface of an insulating material layer. [Figure 5] FIG. 5 is a cross-sectional view schematically showing an embodiment of a laminate according to the present disclosure.

Mode for Carrying Out the Invention

[0017] Hereinafter, embodiments of the present disclosure will be described with appropriate reference to the drawings. However, the present disclosure is not limited to the following embodiments. In the following embodiments, the constituent elements (including steps, etc.) are not essential unless otherwise specified. The sizes of the constituent elements in each drawing are conceptual, and the relative size relationships between the constituent elements are not limited to those shown in each drawing.

[0018] The same applies to the numerical values and ranges thereof in this specification, and they do not limit the present disclosure. The numerical range indicated by "~" in this specification indicates a range including the numerical values described before and after "~" as the minimum value and the maximum value, respectively. In the numerical ranges described stepwise in this specification, the upper limit value or the lower limit value described in one numerical range may be replaced with the upper limit value or the lower limit value of another numerically described range. Also, in the numerical ranges described in this specification, the upper limit value or the lower limit value of the numerical range may be replaced with the value shown in the examples.

[0019] [Method for Manufacturing a Wiring Board] The method for manufacturing a wiring board according to this embodiment at least includes the following steps. (I) A step of forming an insulating material layer 3 on the surface 7F of a support substrate 7. (II) A step of forming a first conductive layer ʟ on the surface 3F of the insulating material layer 3 by electroless copper plating. (III) A step of forming a first opening H1 that penetrates the insulating material layer 3 from the surface 1F of the first conductive layer 1 to reach the surface 7F of the support substrate 7 by a carbon dioxide laser. (IV) A step of forming a second conductive layer 2 on the surface 1F of the first conductive layer 1, and on the bottom surface H1a and side surface H1b of the first opening H1 by electroless copper plating. (V) A step of forming a resist pattern 11 on the surface of the second conductive layer 2, having a second opening H2 that communicates with the first opening H1. (VI) A step of filling the first opening H1 and the second opening H2 with a copper-containing conductive material 9a by electrolytic copper plating. (VII) Step of peeling off the resist pattern 11. (VIII) A step of removing the second conductive layer 2 exposed by peeling off the resist pattern 11 and the first conductive layer 1 in contact with it.

[0020] One of the features of the above manufacturing method is that the first conductive layer 1 formed in process (II) is formed by electroless copper plating. The first conductive layer 1 formed by electroless copper plating is thinner than copper foil. The thickness of the first conductive layer 1 is, for example, 20 to 590 nm, and may be 20 to 200 nm or 210 to 590 nm. In contrast, the thickness of copper foil used in the field of wiring boards is, for example, 1.5 to 5 μm. Due to the sufficiently thin first conductive layer 1, the heat generated during carbon dioxide laser processing in process (III) is easily dissipated, and delamination is less likely to occur at the interface between the insulating material layer 3 and the first conductive layer 1. As a result, vias (first and second openings) of a predetermined shape can be stably formed, and wiring boards can be manufactured with a good yield. The following describes each process.

[0021] <Process (I)> This step involves forming an insulating material layer 3 on the surface 7F of the support substrate 7 (Figure 1(a)). The support substrate 7 has a copper layer 7a on its surface. The copper layer 7a is formed on the surface of the substrate body 7b. For example, a copper-clad laminate (CCL) can be used as the support substrate 7. The copper-clad laminate has a prepreg containing cloth (e.g., glass cloth) and a copper layer formed on the surface of the prepreg. The cloth included in the prepreg may be woven or nonwoven. From the viewpoint of the strength of the prepreg, it is preferable that the cloth is woven. On the other hand, from the viewpoint of the flatness of the surface of the prepreg, it is preferable that at least the cloth placed near the surface of the prepreg is nonwoven.

[0022] The thickness of the support substrate 7 is, for example, 0.2 to 2.0 mm. If the thickness is 0.2 mm or more, the handling of the support substrate 7 tends to be good, while if it is 2.0 mm or less, the material cost tends to be kept low. The shape of the support substrate 7 can be wafer-shaped or panel-shaped. The diameter of the wafer-shaped substrate is, for example, 200 mm, but may also be 300 mm or 450 mm. The length of one side of a rectangular panel is, for example, 300 to 700 mm.

[0023] Methods for forming the insulating material layer 3 on the surface 7F of the support substrate 7 include atmospheric pressure pressing, vacuum pressing, vacuum lamination, roll lamination, and vacuum roll lamination. Vacuum pressing, which can bond a large area at once, is preferred. The material constituting the insulating material layer 3 is, for example, a thermosetting insulating material. Examples of thermosetting insulating materials include liquid or film-type materials, and film-type thermosetting insulating materials are preferred from the viewpoint of film thickness flatness and cost. In terms of forming fine wiring, it is preferable that the thermosetting insulating material contains fillers (fillers) with an average particle size of 500 nm or less (more preferably 50 to 200 nm). The filler content is preferably 0 to 70 parts by mass, and more preferably 0 to 50 parts by mass, per 100 parts by mass of the thermosetting insulating material excluding the fillers.

[0024] When using a film-type thermosetting insulating material, it is preferable to use a thermosetting insulating film that can be pressed at temperatures between 40°C and 250°C. Thermosetting insulating films that can be pressed at temperatures above 40°C tend to have moderate tack at room temperature (approximately 25°C) and are easy to handle, while thermosetting insulating films that can be pressed at temperatures below 250°C tend to suppress warping after lamination.

[0025] The thermal expansion coefficient of the insulating material layer 3 after curing is 80 × 10 from the viewpoint of suppressing warping. -6 It is preferable to have a K value of 70 × 10, which is the value at which high reliability can be obtained. -6 It is more preferable that the temperature is less than or equal to / K. Also, 50 × 10 is preferable in terms of stress relaxation and obtaining a high-resolution pattern. -6 It is preferable that the value is 1 / K or higher.

[0026] The thickness of the insulating material layer 3 is preferably 50 μm or less, more preferably 40 μm or less, and even more preferably 30 μm or less. When the thickness of the insulating material layer 3 is within the above range, for example, it is easier to form fine first openings H1 (opening shape: circular or elliptical) in step (III). From the viewpoint of insulation reliability, the thickness of the insulating material layer 3 is preferably 1 μm or more.

[0027] As the insulating material layer 3, for example, a prepreg can be used. The prepreg comprises a cloth (e.g., glass cloth) and a thermosetting resin composition impregnated with the cloth. The cloth included in the prepreg may be woven or nonwoven. From the viewpoint of the strength of the prepreg, it is preferable that the cloth is woven. On the other hand, from the viewpoint of the flatness of the surface of the prepreg, it is preferable that at least the cloth placed near the surface of the prepreg is nonwoven.

[0028] <Process (II)> This step involves forming a first conductive layer 1 on the surface 3F of the insulating material layer 3 by electroless copper plating (Figure 1(b)). To adsorb palladium, which acts as a catalyst for electroless copper plating, onto the surface of the insulating material layer 3, the surface of the insulating material layer 3 is washed with a pretreatment solution. The pretreatment solution may be a commercially available alkaline pretreatment solution containing sodium hydroxide or potassium hydroxide. The concentration of sodium hydroxide or potassium hydroxide is, for example, 1 to 30%. The immersion time in the pretreatment solution is, for example, 1 to 60 minutes. The immersion temperature is, for example, 25 to 80°C. After pretreatment, the surface may be washed with tap water, pure water, ultrapure water, or an organic solvent to remove excess pretreatment solution.

[0029] After removing the pretreatment solution, the insulating material layer 3 is immersed in an acidic aqueous solution to remove alkaline ions from its surface. The acidic aqueous solution may be a sulfuric acid solution, with a concentration of, for example, 1% to 20%, and an immersion time of, for example, 1 to 60 minutes. To remove the acidic aqueous solution, the material may be washed with tap water, pure water, ultrapure water, or an organic solvent.

[0030] Next, palladium is attached to the surface of the insulating material layer 3. The palladium can be a commercially available palladium-tin colloid solution, an aqueous solution containing palladium ions, or a palladium ion suspension. Of these, an aqueous solution containing palladium ions is preferred because the palladium ions are effectively adsorbed onto the region modified by the pretreatment.

[0031] When immersing in an aqueous solution containing palladium ions, the temperature of the aqueous solution containing palladium ions is, for example, 25 to 80°C, and the immersion time is, for example, 1 to 60 minutes. After adsorbing the palladium ions, the material may be washed with tap water, pure water, ultrapure water, or an organic solvent to remove any excess palladium ions.

[0032] After palladium ion adsorption, the palladium ions are activated to act as a catalyst. A commercially available activator (activation solution) can be used as the reagent to activate the palladium ions. The temperature of the activator is, for example, 25-80°C, and the immersion time is, for example, 1-60 minutes. After activating the palladium ions, the material may be washed with tap water, pure water, ultrapure water, or an organic solvent to remove any excess activator.

[0033] Next, electroless copper plating is applied to the surface of the insulating material layer 3 to form the first conductive layer 1. The copper content of the first conductive layer 1 is, for example, 90-99.9% by mass. The first conductive layer 1 serves to protect the surface of the insulating material layer 3.

[0034] Examples of electroless copper plating include electroless pure copper plating (purity of 99% by mass or higher) and electroless copper nickel phosphorus plating (nickel content: 1-10% by mass, phosphorus content: 1-13% by mass). However, non-magnetic electroless copper plating is preferred because it ensures good signal integrity. The electroless copper plating solution can be a commercially available plating solution; for example, an electroless copper plating solution (manufactured by Uemura Kogyo, product name "Surupap") can be used. The temperature of the electroless copper plating solution is, for example, 25-60°C. After electroless copper plating, the surface may be washed with tap water, pure water, ultrapure water, or an organic solvent to remove excess plating solution. If it is difficult to form a film on the surface of the insulating material layer 3 by electroless plating, the surface of the insulating material layer 3 may be surface-treated. Examples of surface treatment methods include oxygen plasma, argon plasma, nitrogen plasma, and ultraviolet-ozone modification.

[0035] The thickness of the first conductive layer 1 is, for example, 20 to 200 nm, and may be 40 to 200 nm or 60 to 200 nm. The thickness of the first conductive layer 1 may be, for example, 20 to 590 nm, and may be 210 to 590 nm, 250 to 520 nm, 320 to 480 nm or 350 to 440 nm. By making the first conductive layer 1 sufficiently thin, the heat generated during processing with a carbon dioxide laser in step (III) can be dissipated. According to the inventors' research, if the thickness of the first conductive layer 1 is 590 nm or less, peeling at the interface between the first conductive layer 1 and the insulating material layer 3 can be suppressed to a higher degree. If the thickness of the first conductive layer 1 is 210 nm or more, the effect is achieved that the electroless plating thickness within the substrate surface can be easily controlled.

[0036] <Process (III)> This step is to form a first opening H1 that penetrates the first conductive layer 1 and the insulating material layer 3 (Figure 1(c)). The first opening H1 extends from the surface 1F of the first conductive layer 1, through the insulating material layer 3, to the surface 7F of the support substrate 7. The first opening H1 is composed of a bottom surface H1a, which is made of the surface of the support substrate 7 (the surface of the copper layer 7a), and a side surface H1b. The bottom surface H1a is made of the surface of the support substrate 7 (the surface of the copper layer 7a). The side surface H1b is made of the first conductive layer 1 and the insulating material layer 3. The shape of the opening of the first opening H1 is preferably circular or elliptical, and in this case the opening size may correspond to the area of ​​a circle with a diameter of 10 to 100 μm (or 10 to 50 μm in the case of finer openings).

[0037] From a cost standpoint, carbon dioxide laser processing is preferred for forming the first opening H1. If the insulating material layer 3 is made of a thermosetting material, the insulating material layer 3 may be further hardened by heating after the formation of the first opening H1. The heating temperature is, for example, 100°C to 200°C, and the heating time is, for example, 30 minutes to 3 hours. If there is residue of the insulating material layer 3 around the processed area after the formation of the first opening H1, the residue can be removed by oxygen plasma treatment, argon plasma treatment, nitrogen plasma treatment, or treatment with desmear solution. Note that treatment to remove residue may roughen the surface of the object being treated. This tends to reduce the transmission characteristics of high-frequency signals, for example. In this embodiment, since a laminate in which the insulating material layer 3 is covered with the first conductive layer 1 can be used as the object to be processed, roughening of the surface of the insulating material layer 3 can be suppressed even when this treatment is performed. In other words, the first conductive layer 1 can be said to play a role in protecting the surface of the insulating material layer 3 during the process of manufacturing the wiring board.

[0038] <Process (IV)> This step involves forming a second conductive layer 2 on the surface 1F of the first conductive layer 1, the bottom surface H1a of the first opening H1, and the side surface H1b of the first opening H1 by electroless copper plating (Figure 2(a)). The electroless plating method may be the same as in step (II). The second conductive layer 2 serves as a seed layer (power supply layer) for the electrolytic copper plating performed in step (VI). The thickness of the second conductive layer 2 may be, for example, 20-200 nm, 40-200 nm, or 60-200 nm. A thickness of 20 nm or more for the second conductive layer 2 tends to result in lower electrical resistance during electrolytic plating, thereby suppressing variations in the plating thickness of the entire panel. On the other hand, a thickness of 200 nm or less tends to result in easier seed etching. From the viewpoint of seed etching, it is preferable that the second conductive layer 2 is thinner than the first conductive layer 1. The ratio (T2 / T1) of the thickness T2 of the second conductive layer 2 to the thickness T1 of the first conductive layer 1 is, for example, 0.2 to 0.8, and may also be 0.4 to 0.8 or 0.6 to 0.8. A ratio of 0.2 or higher tends to result in good electroplating adhesion to the openings, while a ratio of 0.8 or lower tends to result in easier seed etching.

[0039] <Process (V)> This step involves forming a resist pattern 11 on the surface of the second conductive layer 2, having a second opening H2 that communicates with the first opening H1 (Figure 2(b)). The second opening H2 is formed at the same location where the first opening H1 is formed. The shape of the second opening H2 may be, for example, circular or elliptical, and the opening size may correspond to the area of ​​a circle with a diameter of 15 to 120 μm (or 15 to 60 μm in the case of finer openings).

[0040] As shown in Figure 2(b), the resist pattern 11 may have a plurality of grooves G for forming fine wiring. The plurality of grooves G are provided so as to extend to the surface of the second conductive layer H2 and to be parallel to each other. The grooves G are preferably trench structures. Conductive material is filled into the plurality of grooves G by electrolytic copper plating in step (VI). This conductive material constitutes the wiring. The width of the grooves G is, for example, 1 to 100 μm. The distance between two adjacent grooves G is, for example, 1 to 100 μm.

[0041] The resist pattern 11 can be formed using a commercially available resist. An example of a commercially available resist is a negative-type film-type photosensitive resist (Photec RY-5107UT, manufactured by Showa Denko Materials Co., Ltd.). The resist pattern 11 can be formed by the following steps: First, the resist is deposited using a roll laminator. Next, the phototool with the pattern formed on it is placed in close contact and exposed using an exposure machine. After that, spray development is performed with an aqueous sodium carbonate solution. Note that a positive-type photosensitive resist may be used instead of a negative-type resist.

[0042] <Process (VI)> This step involves filling the first opening H1 and the second opening H2 with a copper-containing conductive material 9a by electrolytic copper plating (Figure 2(c)). In this step, conductive material 9b is filled into multiple grooves G by electrolytic copper plating. Specifically, by performing electrolytic copper plating using the second conductive layer 2 formed in step (IV) as a seed layer, conductive material 9a is filled into the first opening H1 and the second opening H2, and conductive material 9b is filled into the multiple grooves G. The thickness of the conductive material 9b (wiring thickness) filled into the multiple grooves G is, for example, 1 to 30 μm, and may be 3 to 30 μm or 5 to 30 μm.

[0043] <Process (VII)> This step involves removing the resist pattern 11 (Figure 3(a)). The resist can be removed using a commercially available stripping solution.

[0044] <Process (VIII)> This process involves removing the second conductive layer 2 exposed by the peeling off of the resist pattern 11, and the first conductive layer 1 in contact with it (Figure 3(b)). More specifically, it involves removing the second conductive layer 2 and the first conductive layer 1 in the areas of the second conductive layer 2 that are not covered by the conductive materials 9a and 9b (areas exposed by the peeling off of the resist pattern 11), as well as removing the catalyst for electroless plating that remains beneath them. This removal can be carried out using a commercially available removal solution (etching solution), and specific examples include acidic etching solutions (JCU Corporation products, BB-20, PJ-10, SAC-700W3C).

[0045] By removing the unnecessary portions of the first conductive layer 1 and the second conductive layer 2, fine wiring is formed from the conductive material 9b, the remaining portion 2a of the second conductive layer 2, and the remaining portion 1a of the first conductive layer 1. Subsequently, an insulating material layer 13 is formed to cover the surface of the insulating material layer 3, the fine wiring, and the conductive material 9a (step (IX)). This forms a wiring layer 15 comprising the insulating material layer 13 and the fine wiring embedded therein (see Figure 3(c)). Subsequently, openings H3 extending to the conductive material 9a are formed in the insulating material layer 13 (see Figure 4). Via holes are formed by the openings H1, H2, and H3. The wiring board is completed by filling the via holes with conductive material and performing surface finishing processes.

[0046] Although the method for manufacturing a wiring board has been described above, the present invention is not necessarily limited to the embodiments described above, and modifications may be made as appropriate without departing from the spirit of the invention.

[0047] For example, the above embodiment illustrates a method for manufacturing a wiring board having a single wiring layer, but a wiring board having multiple wiring layers may also be manufactured. A wiring board having multiple wiring layers on a support substrate can be manufactured by performing a series of steps from (II) to (IX) on a laminate in the state after step (IX) shown in Figure 4.

[0048] In the above embodiment, an example was given in which step (II) of forming the first conductive layer 1 on the surface of the insulating material layer 3 by electroless copper plating is carried out. However, a laminate having a similar configuration to the laminate shown in Figure 1(b) may be prepared in advance and used to manufacture the wiring board.

[0049] The laminate 20 shown in Figure 5 comprises a support substrate 7, an insulating material layer 3 provided on the surface 7F of the support substrate 7, and a conductive layer 21 with a thickness of 20 to 590 nm provided on the surface 3F of the insulating material layer 3. The conductive layer 21 may be formed by electroless copper plating or by other methods (e.g., sputtering or vapor deposition). Sputtering or vapor deposition, similar to electroless copper plating, can form a conductive layer that adheres sufficiently firmly to the insulating material layer. The thickness of the conductive layer 21 is, for example, 20 to 590 nm, and may be 20 to 200 nm, 40 to 200 nm, or 60 to 200 nm. The thickness of the conductive layer 21 may also be, for example, 210 to 590 nm, and may be 250 to 520 nm, 320 to 480 nm, or 350 to 440 nm.

[0050] This disclosure relates to the following matters. [1] A step (I) of forming an insulating material layer on the surface of the support substrate, Step (II) of forming a first conductive layer on the surface of the insulating material layer by electroless copper plating, Step (III) of forming a first opening that penetrates the first conductive layer and the insulating material layer, (IV) A step of forming a second conductive layer on the surface of the first conductive layer, on the bottom surface and on the side surface of the first opening by electroless copper plating, Step (V) of forming a resist pattern on the surface of the second conductive layer having a second opening that communicates with the first opening, (VI) A step of filling the first opening and the second opening with a conductive material containing copper by electrolytic copper plating, A method for manufacturing a wiring board, including the method described above. [2] The method for manufacturing a wiring substrate according to [1], wherein the thickness of the first conductive layer is 20 to 590 nm. [3] The method for manufacturing a wiring substrate according to [1], wherein the thickness of the first conductive layer is 210 to 590 nm. [4] A method for manufacturing a wiring board according to any one of [1] to [3], wherein in step (III), the first opening is formed by a carbon dioxide laser. [5] The resist pattern in step (V) further has a plurality of grooves that extend to and are parallel to the surface of the second conductive layer, A method for manufacturing a wiring board according to any one of [1] to [4], wherein in step (VI) above, wiring is formed by filling the plurality of grooves with a conductive material containing copper by electrolytic copper plating. [6] The method for manufacturing a wiring board according to [5], wherein the width of the groove is 1 to 100 μm and the distance between two adjacent grooves is 1 to 100 μm. [7] Step (VII) of peeling off the resist pattern, (VIII) A step of removing the second conductive layer exposed by peeling off the resist pattern and the first conductive layer in contact therewith, A method for manufacturing a wiring board according to any one of [1] to [6], further comprising: [8] After step (VIII), a further step (IX) is taken to form an insulating material layer so as to cover the wiring provided on the insulating material layer, After step (IX), step (X) is performed, which is a series of steps from step (II) to step (IX). A method for manufacturing a wiring substrate according to [7], wherein a multilayer wiring layer is formed on the support substrate by going through the above process. [9] Support substrate and, An insulating material layer provided on the surface of the support substrate, A conductive layer with a thickness of 20 to 590 nm is provided on the surface of the insulating material layer, A laminated board equipped with the following features.

[10] The laminate according to [9], wherein the thickness of the conductive layer is 210 to 590 nm.

[11] The laminate according to [9] or

[10] , wherein the support substrate comprises a prepreg including cloth and a copper layer formed on the surface of the prepreg.

[12] The laminate according to any one of [9] to

[11] , wherein the insulating material layer is a prepreg containing cloth. [Examples]

[0051] The present invention will be described in more detail by examples and comparative examples, but the present invention is not limited to the following examples.

[0052] (Example 1) <Process (I)> A support substrate was prepared, comprising a glass cloth-reinforced substrate (size: 200 mm square, thickness: 1.5 mm) and a copper layer (thickness: 20 μm) provided on its surface. Prepreg 1 (E-705G, manufactured by Showa Denko Materials Co., Ltd.) was placed on the copper layer side surface of this support substrate and pressed using a press-type vacuum laminator (MVLP-500, manufactured by Meiki Seisakusho Co., Ltd.). The pressing conditions were as follows. • Pressing plate temperature: 70°C • Vacuuming time: 20 seconds • Press time: 40 seconds • Press pressure: 0.5 MPa • Atmospheric pressure below 4kPa Next, additional pressing was performed using a press machine. The pressing conditions were as follows: • Pressing time: Heat up to 220°C during 0-60 minutes. • Maintain a temperature of 220°C during a pressing time of 60 to 190 minutes. • Cool to 25°C during the pressing time of 190-220 minutes. • Press pressure: 2.0 MPa • Atmospheric pressure 4kPa

[0053] <Process (II)> An electroless copper plating layer (first conductive layer) was formed on the surface of prepreg 1 (insulating material layer) in the laminate obtained through process (I) by electroless copper plating as follows: First, the laminate was immersed in a 110 mL / L aqueous solution of alkaline cleaner (manufactured by JCU Corporation, product name: EC-B) at 50°C for 5 minutes, and then immersed in pure water for 1 minute. Next, the laminate was immersed in a mixture of conditioning solution (manufactured by JCU Corporation, product name: PB-200) and EC-B (PB-200 concentration: 70 mL / L, EC-B concentration: 2 mL / L) at 50°C for 5 minutes, and then immersed in pure water for 1 minute. Next, the laminate was immersed in a mixture of soft etching solution (manufactured by JCU Corporation, product name: PB-228) and 98% sulfuric acid (PB-228 concentration: 100 g / L, sulfuric acid concentration: 50 mL / L) at 30°C for 2 minutes, and then immersed in pure water for 1 minute. Next, as a desmat, the laminate was immersed in 10% sulfuric acid at room temperature for 1 minute. Then, the laminate was immersed in a mixture of catalyst reagent 1 (manufactured by JCU Corporation, product name: PC-BA), catalyst reagent 2 (manufactured by JCU Corporation, product name: PB-333), and EC-B (PC-BA concentration: 5 g / L, PB-333 concentration: 40 mL / L, EC-B concentration: 9 mL / L) at 60°C for 5 minutes, and then immersed in pure water for 1 minute. Next, the laminate was immersed in a mixture of accelerator reagent (manufactured by JCU Corporation, product name: PC-66H) and PC-BA (PC-66H concentration: 10 mL / L, PC-BA concentration: 5 g / L) at 30°C for 5 minutes, and then immersed in pure water for 1 minute.

[0054] Next, the laminate was immersed in a mixture of electroless copper-nickel-phosphorus plating solution (manufactured by JCU Corporation, product names: AISL-570B, AISL-570C, AISL-570MU) and PC-BA (AISL-570B concentration: 70 mL / L, AISL-570C concentration: 24 mL / L, AISL-570MU concentration: 50 mL / L, PC-BA concentration: 13 g / L) at 60°C for 7 minutes, and then immersed in pure water for 1 minute. After that, the laminate was dried on a hot plate at 85°C for 5 minutes. Next, it was heat-annealed in an oven at 180°C for 1 hour. This resulted in a laminate comprising a support substrate, prepreg 1, and an electroless copper plating layer (thickness: approximately 90 nm, copper content: 94 mass%, nickel content: 6 mass%) in this order.

[0055] <Process (III)> Next, a carbon dioxide laser processing machine (LUC-2K21, manufactured by Via Mechanics Co., Ltd., laser wavelength 9.4 μm) was used to form multiple openings (first openings) that penetrated the electroless copper plating layer and prepreg 1 and reached the surface of the copper layer of the support substrate. The laser pulse width was set to 4 μm. The multiple openings had different diameters, resulting in four types with diameters of 10 μm, 50 μm, 80 μm, and 100 μm.

[0056] After the opening was formed, a residue removal process (desmear treatment) was performed. A swelling solution (manufactured by Atotech Japan Co., Ltd., product name: Sweeling Dip Securigant) was used as the pretreatment solution. A roughening solution (manufactured by Atotech Japan Co., Ltd., product name: Concentrate Compact CP) was used as the desmear solution. A neutralizing solution (manufactured by Atotech Japan Co., Ltd., product name: Reduction Securigant) was used as the chemical solution for neutralization after the desmear treatment.

[0057] <Process (IV)> After desmearing, an electroless copper plating layer (second conductive layer) was formed on the surface of the electroless copper plating layer, as well as on the bottom and sides of the openings, by electroless copper plating. The conditions for forming this electroless copper plating layer were the same as those for process (II).

[0058] <Process (V)> On the surface of the electroless copper plating layer formed in process (IV), a wiring resist (RY-5107UT, manufactured by Showa Denko Materials Co., Ltd.) was vacuum-laminated using a vacuum laminator (V-160, manufactured by Nichigo Morton Co., Ltd.). The lamination temperature was 110°C, the lamination time was 60 seconds, and the lamination pressure was 0.5 MPa.

[0059] After vacuum lamination, the material was left for one day, and then the resist for wiring formation was exposed using an i-line stepper exposure machine (product name: S6CK type exposure machine, lens: ASC3(Ck), manufactured by Therma Precision Co., Ltd.). The exposure dose was 140 mJ / cm². 2 The focus was set to -15 μm. After exposure, the image was left for 1 hour, the protective film of the resist for wiring formation was peeled off, and the image was developed using a spray developer (Mikasa Corporation, AD-3000). The developer was a 1.0% sodium carbonate aqueous solution, the development temperature was 30°C, and the spray pressure was 0.14 MPa.

[0060] <Process (VI)> The openings were filled with conductive material by electrolytic copper plating. First, the laminate was immersed in a 100 mL / L aqueous solution of cleaner (Okuno Pharmaceutical Co., Ltd., product name: ICP Clean S-135) at 50°C for 1 minute, then immersed in pure water at 50°C for 1 minute, then in pure water at 25°C for 1 minute, and finally immersed in a 10% sulfuric acid aqueous solution at 25°C for 1 minute. Next, in a 7.3 L aqueous solution of 120 g / L copper sulfate pentahydrate and 220 g / L 96% sulfuric acid, 0.25 mL of hydrochloric acid, 10 mL of Okuno Pharmaceutical Co., Ltd.'s product name: Toplutina GT-3, and 1 mL of Okuno Pharmaceutical Co., Ltd.'s product name: Toplutina GT-2 were added, and the current density was set to 1.5 A / dm² at 25°C. 2 Electroplating was performed under conditions of 10 minutes. After that, the laminate was immersed in pure water at 25°C for 5 minutes, and then dried on a hot plate at 80°C for 5 minutes.

[0061] <Process (VII)> The resist pattern was removed using a spray developer (Mikasa Corporation, AD-3000). A 2.38% TMAH aqueous solution was used as the stripping solution. The stripping temperature was 40°C and the spray pressure was 0.2 MPa.

[0062] <Process (VIII)> The electroless copper plating layer and palladium catalyst were removed. To remove the electroless copper plating layer, the laminate was immersed in an etching solution (manufactured by JCU Corporation, SAC-700W3C) and an aqueous solution of 98% sulfuric acid, 35% hydrogen peroxide, and copper sulfate pentahydrate (SAC-700W3C concentration: 5% by volume, sulfuric acid concentration: 4% by volume, hydrogen peroxide concentration: 5% by volume, copper sulfate pentahydrate concentration: 30 g / L) at 35°C for 1 minute. Next, to remove the palladium catalyst, the laminate was immersed in an FL aqueous solution (manufactured by JCU Corporation, FL-A 500 mL / L, FL-B 40 mL / L) at 50°C for 1 minute. After that, the laminate was immersed in pure water at 25°C for 5 minutes, and then dried on a hot plate at 80°C for 5 minutes.

[0063] (Examples 2-4) Each step was carried out in the same manner as in Example 1, except that the following prepregs were used instead of prepreg 1. • Prepreg 2 (E-770G, manufactured by Showa Denko Materials Co., Ltd.) • Prepreg 3 (HS-200, manufactured by Showa Denko Materials Co., Ltd.) • Prepreg 4 (LW-910G, manufactured by Showa Denko Materials Co., Ltd.)

[0064] (Example 5) Each step was carried out in the same manner as in Example 1, except that the thickness of the electroless copper plating layer (first conductive layer) formed in step (II) was set to approximately 180 nm instead of approximately 90 nm.

[0065] (Example 6) Each step was carried out in the same manner as in Example 1, except that the thickness of the electroless copper plating layer (first conductive layer) formed in step (II) was set to approximately 500 nm instead of approximately 90 nm.

[0066] (Example 7) Each step was carried out in the same manner as in Example 1, except that the thickness of the electroless copper plating layer (first conductive layer) formed in step (II) was set to approximately 600 nm instead of approximately 90 nm.

[0067] (Comparative Example 1) <Fabrication of support substrates with copper foil> Prepreg 1 and copper foil (Furukawa Electric Co., Ltd., GTS-MP, 12 μm thick) were placed on the surface of a glass cloth-reinforced substrate (size: 200 mm square, thickness: 1.5 mm) in that order. This was then pressed using a press-type vacuum laminator (MVLP-500, Meiki Seisakusho Co., Ltd.). The pressing conditions were as follows: • Pressing plate temperature: 70°C • Vacuuming time: 20 seconds • Laminating press time: 40 seconds • Press pressure: 0.5 MPa • Atmospheric pressure below 4kPa Next, additional pressing was performed using a press machine. The pressing conditions were as follows: • Pressing time: Heat up to 220°C during 0-60 minutes. • Maintain a temperature of 220°C during a pressing time of 60 to 190 minutes. • Cool to 25°C during the pressing time of 190-220 minutes. • Press pressure: 2.0 MPa • Atmospheric pressure 4kPa

[0068] <Half-etching and blackening treatment> The copper foil surface was half-etched to reduce its thickness from 12 μm to 4 μm. Subsequently, the copper foil thickness was reduced to 3 μm by a blackening treatment, and the surface of the copper foil was blackened. Each of the subsequent steps (steps (III) to (VIII)) was carried out in the same manner as in Example 1.

[0069] (Comparative Examples 2-4) Each step was carried out in the same manner as in Comparative Example 1, except that the above prepregs were used instead of prepreg 1.

[0070] [evaluation] <Regarding the presence or absence of peeling around the opening> Cross-sectional analysis was performed on the area around the opening after process (VIII) using a FIB apparatus (Hitachi High-Tech, MI-4050). For Examples 1 to 7, the presence or absence of delamination at the interface between the electroless copper plating layer (first conductive layer) and the prepreg was investigated. For Comparative Examples 1 to 4, the presence or absence of delamination at the interface between the copper foil and the prepreg was investigated. In addition, for Examples 1 to 7, the presence or absence of delamination at the interface between the electroless plating and the prepreg after the reliability test was investigated. The reliability test was conducted under the following conditions. First, the laminates for each example were placed in a constant temperature and humidity chamber (product name: PR-2KP, manufactured by ESPEC Corporation) at 85°C and 60% relative humidity for 168 hours to perform a moisture absorption test. Subsequently, a nitrogen atmosphere reflow apparatus (product name: SNR-1065GT, manufactured by Senju Metal Industry Co., Ltd.) was used to perform three reflow tests at a maximum temperature of 275°C. For openings with diameters of 10 μm, 50 μm, 80 μm, and 100 μm, those without delamination were classified as "none," and those with delamination were classified as "present." The results are shown in Tables 1 and 2.

[0071] [Table 1]

[0072] [Table 2] [Industrial applicability]

[0073] According to this disclosure, a method for manufacturing a wiring substrate is provided that can sufficiently suppress the peeling of the conductive layer around an opening, even when an opening for via formation is formed by a carbon dioxide laser. According to this disclosure, a laminate used in the manufacture of a wiring substrate is provided that can sufficiently suppress the peeling of the conductive layer around an opening, even when an opening for via formation is formed by a carbon dioxide laser, and is useful for manufacturing a wiring substrate with excellent reliability and a sufficiently high yield. [Explanation of Symbols]

[0074] 1...First conductive layer, 1a...Remaining portion, 1F...Surface, 2...Second conductive layer, 2a...Remaining portion, 3,13...Insulating material layer, 3F...Surface, 7...Support substrate, 7a...Copper layer, 7b...Substrate body, 7F...Surface, 9a,9b...Conductive material, 11...Resist pattern, 15...Wiring layer, 20...Laminate, 21...Conductive layer, H1...First opening, H1a...Bottom surface, H1b...Side surface, H2...Second opening, H3...Opening, G...Groove

Claims

1. Step (I) of forming an insulating material layer on the surface of the support substrate, Step (II) of forming a first conductive layer on the surface of the insulating material layer by electroless copper plating, Step (III) of forming a first opening that penetrates the first conductive layer and the insulating material layer, Step (IV) of forming a second conductive layer on the surface of the first conductive layer, on the bottom surface and on the side surface of the first opening by electroless copper plating, Step (V) of forming a resist pattern having a second opening that communicates with the first opening on the surface of the second conductive layer, Step (VI) of filling the first opening and the second opening with a conductive material containing copper by electrolytic copper plating, The process of removing the resist pattern (VII), Step (VIII): Remove the second conductive layer exposed by peeling off the resist pattern and the first conductive layer in contact therewith. A method for manufacturing a wiring board, including the method described above.

2. The method for manufacturing a wiring substrate according to claim 1, wherein the thickness of the first conductive layer is 20 to 590 nm.

3. The method for manufacturing a wiring substrate according to claim 1, wherein the thickness of the first conductive layer is 210 to 590 nm.

4. A method for manufacturing a wiring board according to any one of claims 1 to 3, wherein in step (III), the first opening is formed by a carbon dioxide laser.

5. The resist pattern in step (V) further has a plurality of grooves that extend to and are parallel to the surface of the second conductive layer, A method for manufacturing a wiring substrate according to any one of claims 1 to 3, wherein in the step (VI) above, wiring is formed by filling the plurality of grooves with a conductive material containing copper by electrolytic copper plating.

6. The method for manufacturing a wiring board according to claim 5, wherein the width of the groove is 1 to 100 μm, and the distance between two adjacent grooves is 1 to 100 μm.

7. After step (VIII), a further step (IX) is taken to form an insulating material layer so as to cover the wiring provided on the insulating material layer, After the aforementioned step (IX), a step (X) is performed which is a series of steps from the aforementioned step (II) to the aforementioned step (IX), A method for manufacturing a wiring substrate according to claim 5, wherein a multilayer wiring layer is formed on the support substrate by going through the above process.

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