Multilayer ceramic capacitor

Abstract

The present invention provides a multilayer ceramic capacitor (1) which is capable of achieving a good balance between contactability of an internal electrode layer (5) and an external electrode (3) and interlayer adhesion between the internal electrode layer (5) and a dielectric layer (7). The multilayer ceramic capacitor (1) is provided with: a multilayer body (2) which comprises a plurality of dielectric layers (7) and a plurality of internal electrode layers (5) stacked upon each other, and which has a first main surface (M1) and a second main surface (M2) that are opposite to each other in the stacking direction (T), a first lateral surface (S1) and a second lateral surface (S2) that are opposite to each other in the width direction (W) which is perpendicular to the stacking direction (T), and a first end face (E1) and a second end face (E2) that are opposite to each other in the longitudinal direction which is perpendicular to the stacking direction (T) and the width direction (W); and external electrodes (3) which are arranged on the first end face (E1) and the second end face (E2) and are connected to the internal electrode layers (5). The internal electrode layers (5) each have a first region (A1) and a second region (A2) which have different coverages from each other; the first region (A1) has a higher coverage than the second region (A2); and the first region (A1) is connected to an external electrode (3).

Description

Technical Field

[0001] The present invention relates to a multilayer ceramic capacitor.

Background Art

[0002] In a multilayer ceramic capacitor, a technique for improving the coverage (coating rate) of an internal electrode layer is known. For example, Patent Document 1 describes that by setting the average crystal grain size of the internal electrode layer to 0.1 μm or less, structural defects in the internal electrode layer are suppressed. As a result of suppressing the structural defects in the internal electrode layer, the coverage of the internal electrode layer is improved. When the coverage of the internal electrode layer is improved, the area connected to the external electrode increases, and the ESR (Equivalent Series Resistance) is suppressed.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] In a multilayer ceramic capacitor, there are locations where the internal electrode layer and the dielectric layer are adhered, and locations where the dielectric layer and the dielectric layer are adhered. The location where the internal electrode layer and the dielectric layer are adhered tends to be more likely to peel compared to the location where the dielectric layer and the dielectric layer are adhered. Here, when the coverage of the internal electrode layer increases, generally the adhesion between the internal electrode layer and the dielectric layer decreases. [[IDID=38]] Therefore, when the coverage of the internal electrode layer is improved and the coverage becomes high, the reliability of the multilayer ceramic capacitor may decrease. Therefore, the present invention aims to provide a multilayer ceramic capacitor that can achieve both good contact between the internal electrode layer and the external electrode, and good interlayer adhesion between the internal electrode layer and the dielectric layer. [Means for solving the problem]

[0005] The multilayer ceramic capacitor includes a plurality of stacked dielectric layers and a plurality of internal electrode layers, and comprises a laminate having a first main surface and a second main surface facing each other in the stacking direction, a first side surface and a second side surface facing each other in the width direction perpendicular to the stacking direction, and a first end surface and a second end surface facing each other in the length direction perpendicular to the stacking direction and the width direction, and an external electrode disposed on the first end surface and the second end surface and connected to the internal electrode layer, wherein the internal electrode layer has a first region and a second region with different coverage from each other, the first region having greater coverage than the second region, and the first region is connected to the external electrode. [Effects of the Invention]

[0006] According to the present invention, it is possible to provide a multilayer ceramic capacitor that can achieve both good contact between the internal electrode layer and the external electrode, and good interlayer adhesion between the internal electrode layer and the dielectric layer. [Brief explanation of the drawing]

[0007] [Figure 1] This is a perspective view of the multilayer ceramic capacitor of the present invention. [Figure 2] This is a cross-sectional view taken along line II in Figure 1. [Figure 3] This is a cross-sectional view taken along line II-II in Figure 1. [Figure 4] This is a cross-sectional view taken along line III-III in Figure 1. [Figure 5] This is a diagram showing the LT cross-section of the internal electrode layer. [Figure 6] This diagram shows a state in which an internal electrode layer is formed on a dielectric layer. [Figure 7] This is a diagram showing the sheet after cutting. [Figure 8]This is a diagram showing the LT cross-section of a multilayer ceramic capacitor. [Figure 9] This is a diagram showing the LT cross-section of a multilayer ceramic capacitor. [Modes for carrying out the invention]

[0008] An example of an embodiment of the present invention will be described below with reference to the attached drawings. In each drawing, the same or corresponding parts will be denoted by the same reference numerals.

[0009] <Outer dimensions of a multilayer ceramic capacitor> The external appearance of the multilayer ceramic capacitor 1 will be described based on Figure 1. Figure 1 is a perspective view showing the multilayer ceramic capacitor 1 of this embodiment. As shown in Figure 1, the multilayer ceramic capacitor 1 comprises a laminate 2 and an external electrode 3.

[0010] <Definition of Direction> Figures 1 to 9 show the L, W, and T directions. The L direction is the length L of the multilayer ceramic capacitor 1. The W direction is the width W of the multilayer ceramic capacitor 1. The T direction is the stacking direction T of the multilayer ceramic capacitor 1. As a result, the cross-section shown in Figure 2 is called the LT cross-section, the cross-section shown in Figure 3 is called the WT cross-section, and the cross-section shown in Figure 4 is called the LW cross-section. The length direction L, the width direction W, and the stacking direction T do not necessarily have to be orthogonal to each other. They may also intersect each other.

[0011] <Outer shape of the laminate> As shown in Figure 1, the laminate 2 has a roughly rectangular parallelepiped shape. The laminate has two main faces, two end faces, and two side faces. The main faces are the faces facing the lamination direction T. The end faces are the faces facing the length direction L. The side faces are the faces facing the width direction W. Let the two main surfaces be the first main surface M1 and the second main surface M2. Let the two end surfaces be the first end surface E1 and the second end surface E2. Let the two side surfaces be the first side surface S1 and the second side surface S2.

[0012] It is preferable that the ridge lines and corners of the laminate 2 are rounded. A ridge line is a portion where two surfaces of the laminate 2 intersect. A corner is a portion where three surfaces of the laminate 2 intersect.

[0013] <Size of the laminate> The size of the laminate 2 can be, for example, as follows. That is, the length in the length direction L of the laminate 2 can be 200 μm or more and 3500 μm or less. The length in the stacking direction T of the laminate 2 can be 100 μm or more and 2800 μm or less. The length in the width direction W of the laminate 2 can be 100 μm or more and 2800 μm or less. The length of each part of the laminate 2 can be measured with a micrometer or an optical microscope.

[0014] <Internal structure of the laminate (LT cross-section)> Based on FIG. 2, the internal structure of the laminate 2 will be described. FIG. 2 is a cross-sectional view taken along the line I-I of the multilayer ceramic capacitor shown in FIG. 1. As shown in FIG. 2, the laminate 2 has a plurality of dielectric layers 7 and a plurality of internal electrode layers 5. The plurality of dielectric layers 7 and the plurality of internal electrode layers 5 are laminated in the stacking direction T with respect to each other.

[0015] <Inner layer part and outer layer part> In the stacking direction T, the laminate 2 has an inner layer part IL and a first outer layer part OL1 and a second outer layer part OL2 which are two outer layer parts arranged so as to sandwich the inner layer part IL.

[0016] The inner layer part IL includes a part of the plurality of dielectric layers 7 and the plurality of internal electrode layers 5. In the inner layer part IL, the plurality of internal electrode layers 5 are arranged to face each other through the dielectric layers 7. The inner layer IL is the part that forms capacitance and therefore functions as a capacitor in effect. Thus, the inner layer IL can also be considered the effective region in the stacking direction T.

[0017] The first outer layer OL1 is positioned on the first main surface M1 side of the laminate 2, and the second outer layer OL2 is positioned on the second main surface M2 side of the laminate 2. Specifically, the first outer layer OL1 is positioned between the internal electrode layer 5 closest to the first main surface M1 and the first main surface M1. The second outer layer OL2 is positioned between the internal electrode layer 5 closest to the second main surface M2 and the second main surface M2. The first outer layer OL1 and the second outer layer OL2 do not include the internal electrode layer 5, and include the remaining dielectric layers 7 of the plurality of dielectric layers 7, excluding the dielectric layer 7 for the inner layer IL. The first outer layer OL1 and the second outer layer OL2 function as protective layers for the inner layer IL.

[0018] <Dielectric layer> The dielectric layer 7 includes an outer dielectric layer 7a and an inner dielectric layer 7b. <Outer dielectric layer> The outer dielectric layer 7a is a dielectric layer 7 that constitutes the first outer layer portion OL1 and the second outer layer portion OL2 of the dielectric layer 7. The outer dielectric layer 7a is located between the first main surface M1 and the internal electrode layer 5 closest to the first main surface M1, and between the second main surface M2 and the internal electrode layer 5 closest to the second main surface M2.

[0019] <Inner dielectric layer> The inner dielectric layer 7b is located between the inner electrode layers 5 and, together with the inner electrode layers 5, constitutes the inner layer IL. The inner dielectric layer 7b is located between the first internal electrode layer 5a and the second internal electrode layer 5b, which are described below.

[0020] <Number of dielectric layers> The number of dielectric layers 7 stacked on the laminate 2 can be, for example, 10 to 1800. This number of dielectric layers 7 includes the number of outer dielectric layers 7a and inner dielectric layers 7b.

[0021] <Thickness of the dielectric layer> Of the dielectric layers 7, the thickness of the outer dielectric layer 7a can be, for example, 10 μm or more and 200 μm or less. The thickness of the inner dielectric layer 7b can be, for example, 0.3 μm or more and 5.0 μm or less.

[0022] <Materials for the dielectric layer> The material of the dielectric layer 7 is, for example, BaTiO3, CaTiO3, SrTiO 3、 This can be a dielectric ceramic containing CaZrO3 or TiO2, etc. The material of the dielectric layer 7 may be the aforementioned dielectric ceramic to which Mn compounds, Fe compounds, Cr compounds, Co compounds, Ni compounds, etc., have been added.

[0023] <Internal electrode layer> The internal electrode layer 5 includes a first internal electrode layer 5a and a second internal electrode layer 5b. The first internal electrode layer 5a is an internal electrode layer 5 connected to the first external electrode 3a. The second internal electrode layer 5b is an internal electrode layer 5 connected to the second external electrode 3b. The first internal electrode layer 5a extends from the first end face E1 toward the second end face E2. The second internal electrode layer 5b extends from the second end face E2 toward the first end face E1.

[0024] <Opposite section and drawer section> The first internal electrode layer 5a and the second internal electrode layer 5b each have a counter electrode portion and a lead electrode portion. The opposing electrode portion is the part of the internal electrode layer 5 where the first internal electrode layer 5a and the second internal electrode layer 5b face each other in the stacking direction T. The drawn-out electrode portion is the part of the internal electrode layer 5 that is drawn out from the opposing electrode portion to the end face E1 or end face E2 of the laminate 2.

[0025] The opposing electrode portion of the first internal electrode layer 5a is designated as the first opposing electrode portion 5af, and the drawn-out electrode portion of the first internal electrode layer 5a is designated as the first drawn-out electrode portion 5ad. The first drawn-out electrode portion 5ad is the portion drawn out from the first opposing electrode portion 5af to the first end face E1 of the laminate 2. Similarly, the opposing electrode portion of the second internal electrode layer 5b is designated as the second opposing electrode portion 5bf, and the drawn-out electrode portion of the second internal electrode layer 5b is designated as the second drawn-out electrode portion 5bd. The second drawn-out electrode portion 5bd is the portion drawn out from the second opposing electrode portion 5bf to the second end face E2 of the laminate 2.

[0026] <Number of internal electrode layers> The number of internal electrode layers 5 can be, for example, 10 to 1800. This number of internal electrode layers 5 includes the number of first internal electrode layers 5a and the number of second internal electrode layers 5b.

[0027] <Thickness of the internal electrode layer> The thickness of the internal electrode layer 5 can be, for example, 0.3 μm or more and 5.0 μm or less.

[0028] <Materials for the internal electrode layer> The material of the internal electrode layer 5 can be, for example, metals such as Ni, Cu, Ag, Pd, and Au, or alloys of Ni and Cu or Ag and Pd. In addition, the material of the internal electrode layer 5 may also contain dielectric particles of the same composition as the ceramic contained in the dielectric layer 7.

[0029] <Electrode facing part> The division along the length L of the laminate 2 will be explained. The laminate 2 has, in the longitudinal direction L, an electrode-facing portion LF and two end gap portions EG, a first end gap portion EG1 and a second end gap portion EG2. The electrode opposing portion LF is the portion where the first internal electrode layer 5a and the second internal electrode layer 5b face each other in the stacking direction T. That is, the electrode opposing portion LF is the portion where the first opposing electrode portion 5af and the second opposing electrode portion 5bf face each other in the stacking direction T. The electrode-facing portion LF is located in the central part of the length L of the laminate 2. Capacitance is formed when the first opposing electrode portion 5af and the second opposing electrode portion 5bf face each other via the inner dielectric layer 7b. Thus, the electrode opposing portion LF can also be said to be an effective region in the length direction L.

[0030] <End gap section> The end gap is the portion where the first internal electrode layer 5a and the second internal electrode layer 5b do not face each other in the stacking direction T. Specifically, in the stacking direction T, the portion where the first internal electrode layer 5a is located and the second internal electrode layer 5b is not located is the first end gap portion EG1. Similarly, the portion where the second internal electrode layer 5b is located and the first internal electrode layer 5a is not located is the second end gap portion EG2.

[0031] The first end gap portion EG1 corresponds to the portion where the first lead-out electrode portion 5ad is located, and the second end gap portion EG2 corresponds to the portion where the second lead-out electrode portion 5bd is located. The first end gap EG1 functions as a lead-out electrode to the first end face E1 of the first internal electrode layer 5a, and the second end gap EG2 functions as a lead-out electrode to the second end face E2 of the second internal electrode layer 5b. The end gap EG is a section along the length L, and is therefore also called the L gap.

[0032] The length L in the longitudinal direction of the end gap EG can be, for example, 5 μm or more and 30 μm or less.

[0033] <External electrode> The external electrodes include a first external electrode 3a and a second external electrode 3b. The first external electrode 3a is an external electrode positioned on the first end face E1 of the laminate 2. The first external electrode 3a is electrically connected to the first internal electrode layer 5a. The first external electrode 3a extends from the first end face E1 to portions of the two main faces and portions of the two side faces. Of the first external electrode 3a, the portion located on the first end face E1 of the laminate 2 is designated as the end face external electrode 3aE. Of the first external electrode 3a, the portion located on a part of the first main surface M1 or a part of the second main surface M2 is designated as the main surface external electrode 3aM. Of the first external electrode 3a, the portion located on a part of the first side surface S1 or a part of the second side surface S2 is designated as the side surface external electrode 3aS.

[0034] The second external electrode 3b is an external electrode positioned on the second end face E2 of the laminate 2. The second external electrode 3b is electrically connected to the second internal electrode layer 5b. The second external electrode 3b has the same configuration as the first external electrode 3a. In other words, the second external electrode 3b extends from the second end face E2 to parts of the two main faces and parts of the two side faces. Of the second external electrode 3b, the portion positioned on the second end face E2 of the laminate 2 is designated as the end face external electrode 3bE. Of the second external electrode 3b, the portion positioned on a part of the first main surface M1 or a part of the second main surface M2 is designated as the main surface external electrode 3bM. Of the second external electrode 3b, the portion positioned on a part of the first side surface S1 or a part of the second side surface S2 is designated as the side surface external electrode 3bS.

[0035] <Layer structure of external electrodes> The layer configuration of the external electrode 3 will be explained based on Figure 2. The first external electrode 3a includes a first underlay electrode layer 3a1, a first inner plating layer 3a2, and a first surface plating layer 3a3; similarly, the second external electrode 3b includes a second underlay electrode layer 3b1, a second inner plating layer 3b2, and a second surface plating layer 3b3. The layer configuration of the external electrode 3 will be explained below based on the first external electrode 3a. This explanation based on the first external electrode 3a is also valid for the second external electrode 3b. This is because, although the surfaces on which the first external electrode 3a and the second external electrode 3b are provided are different, their configurations are similar.

[0036] The first base electrode layer 3a1 is positioned on the first end face E1 of the laminate 2 and covers the first end face E1 of the laminate 2. The first base electrode layer 3a1 may extend from the first end face E1 to a part of the first main surface M1, a part of the second main surface M2, a part of the first side surface S1, and a part of the second side surface S2.

[0037] The first underlay electrode layer 3a1 may be a fired layer containing metal and glass. Examples of glass include glass components containing at least one selected from B, Si, Ba, Mg, Al, or Li. Borosilicate glass can be used as a specific example. The metal mainly contains Cu. The metal may also mainly contain at least one selected from metals such as Ni, Ag, Pd, or Au, or alloys such as Ag-Pd alloys, or may be included as a component other than the main component.

[0038] The fired layer is a layer obtained by applying a conductive paste containing metal and glass to the laminate using a dip method and then firing it. It may be fired after the firing of the internal electrode layer, or it may be fired simultaneously with the internal electrode layer. Furthermore, there may be multiple fired layers.

[0039] Furthermore, the first base electrode layer 3a1 may be a resin layer containing conductive particles and a thermosetting resin. The resin layer may be formed on the above-described firing layer, or it may be formed directly on the laminate without forming a firing layer.

[0040] The resin layer is a layer obtained by coating a laminate with a conductive paste containing conductive particles and a thermosetting resin using a coating method and then firing it. It may be fired after the firing of the internal electrode layer, or it may be fired simultaneously with the internal electrode layer. Furthermore, the resin layer may consist of multiple layers.

[0041] The thickness of each layer of the first base electrode layer 3a1 and the second base electrode layer 425, which are fired layers or resin layers, is not particularly limited and may be 1 μm or more and 10 μm or less.

[0042] Furthermore, the first underlay electrode layer 3a1 may be a thin film layer of 1 μm or less in thickness, formed by a thin film formation method such as sputtering or vapor deposition, and in which metal particles are deposited.

[0043] The first inner plating layer 3a2 is positioned on the first base electrode layer 3a1 and covers at least a portion of the first base electrode layer 3a1. The first inner plating layer 3a2 includes, for example, at least one selected from metals such as Cu, Ni, Ag, Pd, or Au, or alloys such as Ag-Pd alloys.

[0044] The first surface plating layer 3a3 is positioned on the first inner plating layer 3a2 and covers at least a portion of the first inner plating layer 3a2. The first surface plating layer 3a3 includes, for example, a metal such as Sn.

[0045] Preferably, the first inner plating layer 3a2 is a Ni plating layer, and the first outer plating layer 3a3 is a Sn plating layer. The Ni plating layer can prevent the underlying electrode layer from being corroded by the solder when mounting ceramic electronic components, and the Sn plating layer improves the solder wettability when mounting ceramic electronic components, making mounting easier. In other words, the first inner plating layer 3a2 has lower solder wettability than the first outer plating layer 3a3.

[0046] <Internal structure of the laminate (WT cross-section)> Based on Figure 3, the internal structure of the laminate 2 will be explained based on its appearance from the second end face E2. Figure 3 is a cross-sectional view of the multilayer ceramic capacitor shown in Figure 1, taken along line II-II. As shown in Figure 3, the laminate 2 has, in the width direction W, an electrode facing portion WF on which the internal electrode layer 5 faces, and two side gap portions SG, a first side gap portion SG1 and a second side gap portion SG2, which are arranged to sandwich the electrode facing portion WF. The first side gap portion SG1 is located between the electrode-facing portion WF and the first side surface S1, and the second side gap portion SG2 is located between the electrode-facing portion WF and the second side surface S2.

[0047] Specifically, the first side gap portion SG1 is located between the end of the internal electrode layer 5 on the first side surface S1 side and the first side surface S1, and the second side gap portion SG2 is located between the end of the internal electrode layer 5 on the second side surface S2 side and the second side surface S2. The first side gap portion SG1 and the second side gap portion SG2 do not include the internal electrode layer 5, and include only the dielectric layer 7. The first side gap portion SG1 and the second side gap portion SG2 function as protective layers for the internal electrode layer 5. The side gap SG is a section in the width direction W, and is therefore also called the W gap.

[0048] The widthwise length W of the side gap portion SG can be, for example, 5 μm or more and 30 μm or less.

[0049] <Size of multilayer ceramic capacitors> The length L of the entire multilayer ceramic capacitor 1, including the laminated body 2 and the external electrodes 3, can be, for example, 0.2 mm or more and 3.5 mm or less. The length T of the entire multilayer ceramic capacitor 1 in the stacking direction can be, for example, 0.1 mm or more and 2.8 mm or less. The length W of the entire multilayer ceramic capacitor 1 in the width direction can be, for example, 0.1 mm or more and 2.8 mm or less.

[0050] In this embodiment, the multilayer ceramic capacitor 1 is a two-terminal capacitor. However, the multilayer ceramic capacitor 1 is not limited to two terminals and can also be a multi-terminal capacitor with three or more terminals.

[0051] <Internal electrode layer coverage> The multilayer ceramic capacitor 1 of this embodiment is characterized by the coverage of the internal electrode layer 5. The distribution of in-plane coverage of the internal electrode layer 5 will be explained based on Figure 4. Figure 4 is a cross-sectional view of the laminate 2 corresponding to the cross-sectional view along line III-III of the multilayer ceramic capacitor shown in Figure 1. In other words, Figure 4 shows the LW cross-section of the laminate 2 at the location where the first internal electrode layer 5a exists. Since Figure 4 is a cross-sectional view of the laminate 2, the external electrode 3 is not shown in Figure 1. In the following explanation, we will focus on the first internal electrode layer 5a as the internal electrode layer 5. The first internal electrode layer 5a extends from the first end face E1 to the second end face E2. The first internal electrode layer 5a is located in the first end gap EG1 and the electrode-facing portion LF in the longitudinal direction L of the laminate 2.

[0052] The first internal electrode layer 5a has multiple regions with different coverage within its plane. Specifically, the first internal electrode layer 5a has four regions, from the first region A1 to the fourth region A4, and these four regions have different coverage.

[0053] <Coverage> The internal electrode layer 5 is formed of the aforementioned metallic material. However, the internal electrode layer 5 is not completely filled with this metallic material. The internal electrode layer 5 contains voids where the metallic material is not present. Therefore, the proportion of the internal electrode layer 5 occupied by the metal material is defined as the coverage. Coverage is also called the coating rate. The method for measuring coverage will be explained later.

[0054] <Regions 1 to 4> As described above, the first internal electrode layer 5a has four regions with different coverage, from the first region A1 to the fourth region A4. The order of coverage size from area 1 A1 to area 4 A4 is area 1 A1 > area 2 A2 > area 3 A3 > area 4 A4.

[0055] The arrangement of each region in the first internal electrode layer 5a is as follows. From the first end face E1 toward the second end face E2, the regions are arranged in the order of first region A1, third region A3, second region A2, and fourth region A4. Specifically, the first region A1 and third region A3 are located in the first end gap EG1, and the second region A2 and fourth region are located in the electrode-facing portion LF. In other words, the first region A1 and the third region A3 occupy the first end gap EG1, and the second region A2 and the fourth region occupy the electrode-facing region LF.

[0056] In the multilayer ceramic capacitor 1 of this embodiment, the internal electrode layer 5 has multiple regions with different coverage, thereby achieving both connectivity between the internal electrode layer 5 and the external electrode 3 and suppression of delamination between the internal electrode layer 5 and the dielectric layer 7. The following describes the characteristics of the region arrangement in order.

[0057] <Feature 1> The internal electrode layer 5 has multiple regions with different coverage. The first region A1, which has high coverage, is located facing the first end face E1. Regions with low coverage are located at the other positions.

[0058] <Connectivity> A first region A1 with high coverage is positioned in the first internal electrode layer 5a at a location where it connects to the first external electrode 3a. Therefore, good connectivity can be achieved between the first internal electrode layer 5a and the first external electrode 3a.

[0059] <Peel-inhibiting> The first internal electrode layer 5a has a second region and a third region, which are areas with low coverage. The areas with low coverage can improve the adhesion between the first internal electrode layer 5a and the inner dielectric layer 7b. As a result, delamination between the first internal electrode layer 5a and the inner dielectric layer 7b can be suppressed. The reason for the improved adhesion is as follows: The first internal electrode layer 5a in the region with low coverage has more voids, through holes, and depressions than the first internal electrode layer 5a in the region with high coverage. The dielectric of the inner dielectric layer 7b can easily penetrate into these voids, through holes, and depressions. As the dielectric of the inner dielectric layer 7b penetrates into the interior of the first internal electrode layer 5a, the adhesion between the first internal electrode layer 5a and the inner dielectric layer 7b is improved.

[0060] As described above, a region with high coverage is located in the first internal electrode layer 5a at a position connected to the first external electrode 3a, while a region with low coverage is located at a position not directly involved in the connection with the first external electrode 3a. Therefore, it is possible to achieve both improved connectivity between the first external electrode 3a and suppression of delamination between the first internal electrode layer 5a and the inner dielectric layer 7b.

[0061] <Feature 2> The first internal electrode layer 5a has a second region A2 and a third region A3, which have less coverage than the first region A1. The third region A3 is located between the first region A1 and the second region A2 and is positioned in the end gap EG1. The coverage of the third region A3 is smaller than the coverage of the second region A2.

[0062] By arranging the first region A1 to the third region A3 as described above, the adhesion between the first internal electrode layer 5a and the inner dielectric layer 7b can be improved without sacrificing either the connectivity between the first internal electrode layer 5a and the first external electrode 3a, or the formation of capacitance.

[0063] Of the three regions A3, the third region A3, which has the smallest coverage, is located in the first end gap EG1 rather than in the electrode-facing portion LF.

[0064] Therefore, even if the coverage of the third region A3 is small, it does not hinder volume formation.

[0065] Furthermore, the third region A3 is located on the electrode-facing portion LF side of the first end gap portion EG1, rather than on the side of the first end face E1. Therefore, although the third region A3 is located in the first end gap portion EG1, it does not face the first end face E1. Therefore, even if the coverage of the third region A3 is small, the connectivity with the external electrode 3 does not decrease.

[0066] On the other hand, since the third region A3 has low coverage, as mentioned above, the adhesion between the first internal electrode layer 5a and the inner dielectric layer 7b can be improved.

[0067] As described above, since the third region A3 with low coverage is located on the side of the electrode-facing portion LF in the first end gap portion EG, the adhesion between the first internal electrode layer 5a and the inner dielectric layer 7b can be improved without sacrificing either capacitance formation or connectivity between the first internal electrode layer 5a and the first external electrode 3a.

[0068] <Feature 3> The fourth region A4 is located at the end of the second region A2 opposite to the first end gap EG1. The fourth region A4 has the smallest coverage among the first to fourth regions A4. Furthermore, as will be explained later, the length L of the fourth region A4 is significantly shorter than the length of the second region A2.

[0069] By arranging the fourth region A4 as described above, the adhesion between the first internal electrode layer 5a and the inner dielectric layer 7b can be improved without sacrificing capacitance formation.

[0070] As will be explained later, the fourth region A4 is located at the edge of the internal electrode layer 5 formed on the dielectric layer 7 by coating or other means. Therefore, the thickness of the first internal electrode layer 5a in the fourth region A4 gradually decreases towards its edge. In other words, its cross-section is inclined at an angle. Therefore, the edge of the first internal electrode layer 5a where the fourth region A4 is located can be said to be a region that does not contribute much to capacitance formation. Thus, even if the coverage of the fourth region A4 is small, the effect on capacitance formation is not significant.

[0071] On the other hand, the edges of the internal electrode layer 5 are prone to delamination from the dielectric layer 7. Therefore, by placing the fourth region A4 at the edge of the first internal electrode layer 5a, delamination between the first internal electrode layer 5a and the inner dielectric layer 7b can be effectively suppressed.

[0072] As described above, by positioning the fourth region A4, which has the smallest coverage, at the end of the first internal electrode layer 5a on the side of the second end face E2, the adhesion between the first internal electrode layer 5a and the inner dielectric layer 7b can be improved without sacrificing capacitance formation.

[0073] The arrangement of each region in the first internal electrode layer 5a has been explained above. The same applies to the second internal electrode layer 5b. The arrangement of each region in the second internal electrode layer 5b will be explained later with reference to Figure 7.

[0074] <Length of each region> The preferred length L in the longitudinal direction of each region and the preferred ratio of each region to the length L in the longitudinal direction of the end gap EG1, i.e., the L gap, will be explained. First, the first region A1 and the third region A3 located in the end gap EG1 are as follows. The length of the first region A1 is preferably 5 μm or more and 15 μm or less, and its ratio to the L gap is preferably 8% or more and 25% or less. The length of the third region A3 is preferably 16 μm or more and 45 μm or less, and its ratio to the L gap is preferably 26% or more and 75% or less. Next, the second region A2 and the fourth region A4 located in the electrode-facing portion LF are as follows. The length of the second region A2 is preferably 1840 μm or more and 1880 μm or less, and the ratio to the L gap is preferably 3067% or more and 3133% or less. The length of the fourth region A4 is preferably 1 μm or more and 30 μm or less, and its ratio to the L gap is preferably 2% or more and 50% or less. Note that the aforementioned values ​​are examples and can be changed as appropriate depending on the size of the multilayer ceramic capacitor 1, etc.

[0075] Next, we will explain the method for measuring coverage and determining the area. <Method for measuring coverage> Coverage is measured as follows: As mentioned above, the internal electrode layer 5 contains voids where no metal exists. Therefore, the proportion of metal in the internal electrode layer 5 is defined as coverage.

[0076] However, when the internal electrode layer 5 and the dielectric layer 7 are stacked, some of the cavities in the internal electrode layer 5 may be filled with dielectric material. Therefore, the definition of coverage is metal / (metal + (cavity or dielectric)). In other words, the entire internal electrode layer 5 is defined as the sum of (i) metal, (ii) a portion that exists as a cavity without being filled with dielectric, and (iii) a portion where the cavity is filled with dielectric. The proportion of (i) metal to the entire internal electrode layer 5 is defined as coverage.

[0077] Coverage can be determined specifically through the following steps 1 and 2. Step 1: For the laminate 2, the surface including the length direction L and the lamination direction T, i.e., the LT surface, is polished up to the center in the width direction W, exposing the LT cross-section of the internal electrode layer 5. Step 2: The LT cross-section of the exposed internal electrode layer 5 is divided into regions of a predetermined length L, and the proportion of metal in each divided region relative to the whole is determined. This determined proportion is the coverage. The predetermined length is set to, for example, 2% to 3% of the total length L of the internal electrode layer 5. Note that this length is merely an example and can be changed as appropriate depending on the size of the multilayer ceramic capacitor 1, the size of the end gap, etc. For example, the predetermined length may be 50 μm.

[0078] The following describes an example of coverage measurement based on Figure 5. Figure 5 shows the LT cross-section of the internal electrode layer 5. Specifically, Figure 5 shows the LT cross-section of the first internal electrode layer 5a shown in Figure 4. Figure 5 shows four frames R1 to R4 as the outer frame for measuring coverage. The proportion of metal to the whole is determined within these frames. In Figure 5, the dielectric material of the dielectric layer 7 that has entered the cavity of the internal electrode layer 5 is shown as the cavity dielectric 7c.

[0079] <Procedure for measuring coverage> The procedure for measuring coverage is as follows: First, the area within the frame is brought into the field of view and observed using an optical microscope. Next, determine the total length L2 of the internal electrode layer as captured by the optical microscope. Determine the length L1 of the length L in the length direction where the metal is substantially observed within the range captured by the optical microscope. L1 is the remaining length after subtracting the length of the region where the metal of the internal electrode layer is "not observed" from the total length. By dividing length L1 by length L2, we can find the ratio, and this ratio represents the coverage.

[0080] <Determining the area based on coverage> Next, we will explain how to determine the region based on the coverage value obtained as described above. Areas with a coverage of 95% or more are classified as Area 1 A1, indicating high coverage. Areas with coverage between 80% and 95% are classified as Area 2A2 within the coverage area. Areas with coverage between 70% and 80% are classified as area A3, which indicates low coverage. Areas with coverage between 50% and 70% are classified as Area 4, A4, which has the lowest coverage.

[0081] <First internal electrode layer and second internal electrode layer> The relationship between the first internal electrode layer 5a and the second internal electrode layer 5b will be explained based on Figures 6 and 7. Figure 6 shows the state in which the first internal electrode layer 5a and the second internal electrode layer 5b are formed on the upper surface of the dielectric layer 7. Part 601 of Figure 6 shows the LW cross-section of the laminate 2, and part 602 shows the LT cross-section corresponding to part 601. As shown in section 601, a first internal electrode layer 5a and a second internal electrode layer 5b are formed on the dielectric layer 7. This is referred to as the sheet 10 before cutting. The sheet 10 before cutting is cut in two along the cutting line CL. One of the resulting pieces is designated as the first sheet after cutting 10a, and the other as the second sheet after cutting 10b.

[0082] Figure 7 shows the first cut sheet 10a and the second cut sheet 10b. Part 701 of Figure 7 shows the LW cross section of the first cut sheet 10a, and part 702 shows the LW cross section of the second cut sheet 10b. The inner layer IL of the laminate 2 can be formed by sequentially stacking multiple sheets of the first cut sheet 10a shown in section 701 and the second cut sheet 10b shown in section 702.

[0083] <Sheet before cutting> Based on Figure 6, the sheet 10 before cutting will be described in detail. As described above, the dielectric layer 7 is provided with an internal electrode layer 5 corresponding to the first internal electrode layer 5a and an internal electrode layer 5 corresponding to the second internal electrode layer 5b. When cut along the cutting line CL, the internal electrode layer 5 is separated into the first internal electrode layer 5a and the second internal electrode layer 5b. Furthermore, the dielectric layer 7 has portions at both ends in its length L where the internal electrode layer 5 is not formed. These portions become the end gap portions EG in the laminate 2. Due to the aforementioned positional relationship between the dielectric layer 7 and the internal electrode layer 5 in the sheet 10 before cutting, the portion of the internal electrode layer 5 facing the cutting line CL in the sheet 10 before cutting becomes the portion connected to the external electrode 3. Therefore, it is preferable that the portion facing the cutting line CL is the first region A1, which has high coverage.

[0084] Furthermore, as shown in Figure 7, when the first cut sheet 10a and the second cut sheet 10b are stacked, the portion where the first internal electrode layer 5a and the second internal electrode layer 5b overlap becomes the electrode-facing portion LF. The electrode-facing portion LF is the portion where capacitance is formed. Therefore, the region following the first region A1 located on both sides of the cutting line CL can also be a second region A2, which has the second largest coverage after the first region A1. However, in the end gap EG, it is not necessary to make the portion following the first region A1 of the internal electrode layer 5 a region with high coverage. This is because no capacitance is formed in the end gap EG.

[0085] Therefore, as shown in Figure 6, a third region A3 is placed in the end gap EG following the first region A1, with coverage smaller than that of the first region A1 and the second region A2. As a result, as shown in Figure 7, it is possible to suppress delamination between the internal electrode layer 5 and the dielectric layer 7 by using a portion that has little involvement in capacitance formation, while maintaining connectivity between the internal electrode layer 5 and the external electrode 3.

[0086] Then, as a region following the third region A3 of the internal electrode layer 5, a second region A2 with greater coverage than the third region A3 is placed at a position corresponding to the electrode-facing portion LF. This ensures that the capacitance formed in the electrode-facing portion LF is secured.

[0087] (4th area) Next, we will explain area 4A4. As shown in Figure 6, the fourth region A4 is located at both ends in the longitudinal direction L of the internal electrode layer 5 in the sheet 10 before cutting. As shown in section 602 as region LE, both ends of the internal electrode layer 5 in the longitudinal direction L have their end faces inclined obliquely. That is, the LT cross-section of the internal electrode layer 5 has a trapezoidal shape.

[0088] When the internal electrode layer 5 is formed on the dielectric layer 7 by screen printing or the like, this end face of the internal electrode layer 5 inevitably becomes slanted. When forming the internal electrode layer 5 by printing, a paste of the electrode material is wetted and spread onto the dielectric layer 7 to form a coating. The aforementioned end face of the internal electrode layer 5 corresponds to the tip of this printed coating. Therefore, the end face of the internal electrode layer 5 is inclined.

[0089] In this inclined portion, the thickness of the internal electrode layer 5 is thinner. Therefore, this portion of the internal electrode layer 5 does not contribute well to capacitance formation. Furthermore, the end face of the internal electrode layer 5 is a region where delamination from the dielectric layer 7 is likely to occur. Therefore, a fourth region A4 with low coverage is placed in the region LE of the internal electrode layer 5. This makes it possible to improve the adhesion between the internal electrode layer 5 and the dielectric layer 7 without impairing capacitance formation.

[0090] <Coverage adjustment> This section explains one example of how to adjust coverage. In this example, an auxiliary dielectric layer 7d is used to adjust coverage. First, let's explain the auxiliary dielectric layer 7d. It is preferable that the length of the laminate 2 in the stacking direction T differs only slightly between the electrode-facing portion LF and the end gap portion EG. However, in the inner layer IL, the length of the stacking direction T tends to differ between the electrode-facing portion LF and the end gap portion EG. This is because, in the electrode-facing portion LF, multiple dielectric layers 7 and internal electrode layers 5 are stacked, whereas in the end gap portion EG, only the dielectric layer 7 is stacked, and the internal electrode layer 5 is not stacked. Therefore, in order to reduce the difference in length T in the stacking direction between the end gap portion EG and the electrode opposing portion LF, an auxiliary dielectric layer 7d, which is an additional dielectric layer 7, may be placed in the end gap portion EG.

[0091] <Auxiliary dielectric layer> The auxiliary dielectric layer 7d will be described based on Figures 8 and 9. Figures 8 and 9 show the LT cross-section of the multilayer ceramic capacitor 1. Figures 8 and 9 simulate the state of region R5 in Figure 2. Figures 8 and 9 also show examples of different configurations near the auxiliary dielectric layer 7d. As shown in Figure 8, in the first end gap EG1, an auxiliary dielectric layer 7d is placed between the two inner dielectric layers 7b. Since the auxiliary dielectric layer 7d compensates for the thickness of the second internal electrode layer 5b, the difference in length T in the stacking direction between the end gap EG and the electrode facing portion LF becomes smaller.

[0092] Note that the configuration in Figure 8 and the configuration in Figure 9 differ in the configuration at which the auxiliary dielectric layer 7d and the second internal electrode layer 5b are in contact. In the configuration in Figure 8, the auxiliary dielectric layer 7d overlaps the second internal electrode layer 5b, whereas in the configuration in Figure 9, the second internal electrode layer 5b overlaps the auxiliary dielectric layer 7d. Here, overlap refers to covering from above in the stacking direction T. Note that the side of the second main surface M2 is considered the upper side relative to the first main surface M1. Therefore, overlap means covering from the side of the second main surface M.

[0093] The auxiliary dielectric layer 7d and the internal electrode layer 5 may or may not overlap, as described above. In other words, instead of one covering the other, their end faces may be in contact with each other.

[0094] The coverage can be adjusted by changing the composition of the auxiliary dielectric layer 7d, thereby altering the degree of shrinkage of the auxiliary dielectric layer 7d during firing. In the internal electrode layer 5, a break in the metal occurs when it follows the contraction of the auxiliary dielectric layer 7d. Therefore, the coverage of the internal electrode layer 5 can be adjusted by changing the degree of contraction of the auxiliary dielectric layer 7d.

[0095] <Other ways to adjust coverage> This section explains other ways to adjust coverage. When forming the internal electrode layer 5 on the dielectric layer 7 by screen printing, the coverage can be adjusted by adjusting the depth of the openings in the mesh used for screen printing. Specifically, adjust the mesh openings as follows: Opening corresponding to area A1: Large depth (deepest) Opening corresponding to area 2A2: Medium depth (depth between the deepest and shallowest points) Opening corresponding to area 3A3: Small depth (shallowest) Furthermore, the fourth region A4 can be created by adjusting the viscosity of the conductive paste to be printed to form a gradient region (region LE shown in Figure 6).

[0096] The internal electrode layer 5 can also be formed using gravure printing. When forming the internal electrode layer 5 using gravure printing, the coverage of each region can be adjusted by adjusting the area and volume of the openings in the gravure plate corresponding to each region. The area and volume of the aperture can also be adjusted, for example, using laser drawing.

[0097] Furthermore, whether or not to provide the aforementioned auxiliary dielectric layer 7d can be arbitrarily selected. When an auxiliary dielectric layer 7d is provided, the Ni paste may be printed first, followed by the paste for the auxiliary dielectric layer 7d, or conversely, the paste for the auxiliary dielectric layer 7d may be printed first, followed by the Ni paste. The composition of the auxiliary dielectric layer 7d may be the same as or different from the composition of the dielectric layers 7 in the other parts. Here, "composition" refers to the elements that make up the dielectric layer 7 and their quantities. Furthermore, the grain size may differ between the auxiliary dielectric layer 7d and the other dielectric layers 7. The grain size of the auxiliary dielectric layer 7d may be less than the grain size of the other dielectric layers 7, or vice versa.

[0098] Sn may be present at the interface between the internal electrode layer 5 and the dielectric layer 7. Furthermore, as a method for forming the laminate 2, a method can be used in which the first side gap portion SG1 and the second side gap portion SG2 are added to the opposing electrode portion WF in a so-called retrofitting manner.

[0099] Although embodiments of the present invention have been described above, the present invention is not limited to the embodiments described above, and various modifications and variations are possible.

[0100] <1> It includes multiple stacked dielectric layers and multiple internal electrode layers, A laminate having a first main surface and a second main surface facing each other in the stacking direction, a first side surface and a second side surface facing each other in the width direction perpendicular to the stacking direction, and a first end surface and a second end surface facing each other in the length direction perpendicular to the stacking direction and the width direction, The device comprises an external electrode positioned on the first end face and the second end face and connected to the internal electrode layer, The internal electrode layer has a first region and a second region with different coverage from each other. The first region has greater coverage than the second region. The first region is connected to the external electrode, Multilayer ceramic capacitor.

[0101] <2> Between the first and second regions, there is a third region. The coverage of the third region is less than the coverage of either the first region or the second region. <1> The multilayer ceramic capacitor described above.

[0102] <3> When the region where the internal electrode layers face each other is defined as the effective region, the second region includes at least a portion of the effective region where the internal electrode layers face each other. <1> or <2> The multilayer ceramic capacitor described above.

[0103] <4> The coverage of the aforementioned first region is 95% or more. The coverage of the second domain is between 80% and 95%. <1> from <3> A multilayer ceramic capacitor as described in one of the following:

[0104] <5> The coverage of the third domain is between 70% and 80%. <2> The multilayer ceramic capacitor described above.

[0105] <6> At the end of the second region opposite to the first region, there is a fourth region. The coverage of the fourth region is smaller than that of the first, second, and third regions. <3> The multilayer ceramic capacitor described above.

[0106] <7> The coverage of the aforementioned fourth domain is between 50% and 70%. <6> The multilayer ceramic capacitor described above. [Explanation of Symbols]

[0107] 1. Multilayer ceramic capacitor 2 Laminate 3 External electrode 3a First external electrode 3b Second external electrode 5 Internal electrode layer 5a First internal electrode layer 5ad First extraction electrode section 5af First counter electrode section 5b Second internal electrode layer 5bd First extraction electrode section 5bf Second counter electrode section 7. Dielectric layer 7a Outer dielectric layer 7b Inner Dielectric Layer 7c Intracavity dielectric 7d auxiliary dielectric layer 10 Sheet before cutting 10a First cut sheet 10b Second sheet after cutting IL inner layer OL1 First outer layer OL2 Second outer layer LF electrode opposing part EG1 First end gap section EG2 Second end gap section WF electrode facing part SG1 First side gap section SG2 Second side gap section M1 First main surface M2 Second main surface E1 First end face E2 Second end face S1 First Aspect S2 Second Aspect T Stacking direction L (Length direction) W (width direction) A1 1st area A2 2nd area A3 3rd area A4 4th area CL cutting line

Claims

1. It includes multiple stacked dielectric layers and multiple internal electrode layers, A laminate having a first main surface and a second main surface facing each other in the stacking direction, a first side surface and a second side surface facing each other in the width direction perpendicular to the stacking direction, and a first end surface and a second end surface facing each other in the length direction perpendicular to the stacking direction and the width direction, The system comprises an external electrode connected to the internal electrode layer, The internal electrode layer has a first region, a second region, and a third region, each having different coverage from the others. The first region has greater coverage than the second region. The third region has less coverage than the first and second regions. The first region is connected to the external electrode, The third region is a multilayer ceramic capacitor located between the first region and the second region.

2. When the region where the internal electrode layers face each other is defined as the effective region, the second region includes at least a part of the effective region where the internal electrode layers face each other. The multilayer ceramic capacitor according to claim 1.

3. The coverage of the first region is 95% or more. The coverage of the second area mentioned above is between 80% and 95%. The multilayer ceramic capacitor according to claim 1.

4. The coverage of the aforementioned third domain is between 70% and 80%. The multilayer ceramic capacitor according to claim 1.

5. At the end of the second region opposite to the first region, there is a fourth region. The coverage of the fourth region is smaller than that of the first, second, and third regions. The multilayer ceramic capacitor according to claim 1.

6. The coverage of the aforementioned fourth domain is 50% or more but less than 70%. The multilayer ceramic capacitor according to claim 5.

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